diff options
author | Thi Tran <thi@us.ibm.com> | 2014-02-06 15:25:19 -0600 |
---|---|---|
committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-02-14 15:21:34 -0600 |
commit | 9ea4a28823a5c17d8adc448635fdec1e18c5ce5d (patch) | |
tree | 5332b389deb70163f026ce3056f07db3c6935a61 /src/usr/hwpf | |
parent | 687aff211d6a018a3361124f8213ff102c9ef121 (diff) | |
download | talos-hostboot-9ea4a28823a5c17d8adc448635fdec1e18c5ce5d.tar.gz talos-hostboot-9ea4a28823a5c17d8adc448635fdec1e18c5ce5d.zip |
INITPROC: Hostboot SW244672 RAS Review updates
Change-Id: I57642650e977d106a5078d5a8bc1ec4d9aec2f96
CQ:SW244672
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/8633
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf')
7 files changed, 239 insertions, 42 deletions
diff --git a/src/usr/hwpf/hwp/dram_training/cen_stopclocks/cen_stopclocks.H b/src/usr/hwpf/hwp/dram_training/cen_stopclocks/cen_stopclocks.H index 937210cd7..c4f3f4fa5 100644 --- a/src/usr/hwpf/hwp/dram_training/cen_stopclocks/cen_stopclocks.H +++ b/src/usr/hwpf/hwp/dram_training/cen_stopclocks/cen_stopclocks.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013 */ +/* COPYRIGHT International Business Machines Corp. 2013,2014 */ /* */ /* p1 */ /* */ diff --git a/src/usr/hwpf/hwp/dram_training/mem_startclocks/memory_cen_stopclocks.xml b/src/usr/hwpf/hwp/dram_training/mem_startclocks/memory_cen_stopclocks.xml index 8a4e20bfb..b81549147 100644 --- a/src/usr/hwpf/hwp/dram_training/mem_startclocks/memory_cen_stopclocks.xml +++ b/src/usr/hwpf/hwp/dram_training/mem_startclocks/memory_cen_stopclocks.xml @@ -20,19 +20,35 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> + <hwpErrors> -<!-- $Id: memory_cen_stopclocks.xml,v 1.2 2014/01/16 17:50:23 mfred Exp $ --> +<!-- $Id: memory_cen_stopclocks.xml,v 1.3 2014/01/31 22:05:42 mfred Exp $ --> <!-- For file ../../ipl/fapi/cen_stopclocks.C --> <!-- // *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com --> <!-- // *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com --> +<registerFfdc> + <id>REG_FFDC_CLOCK_STOP_BAD_STATUS_REGS</id> + <cfamRegister>CFAM_FSI_GP3_0x00002812</cfamRegister> + <cfamRegister>CFAM_FSI_GP4_0x00002813</cfamRegister> + <cfamRegister>CFAM_FSI_GP3_MIRROR_0x0000101B</cfamRegister> + <scomRegister>MEM_GP3_0x030F0012</scomRegister> + <scomRegister>NEST_GP3_0x020F0012</scomRegister> +</registerFfdc> + <hwpError> <rc>RC_MSS_UNEXPECTED_MEM_CLOCK_STATUS</rc> <description> cen_stopclocks got unexpected clock status in MEM_CLK_STATUS_0x03030008 + This error could happen for a number of reasons and probably not on the + IPL path, so callout the memory buffer chip, but do not deconfigure/GARD. </description> <ffdc>EXPECTED_STATUS</ffdc> <ffdc>ACTUAL_STATUS</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_CLOCK_STOP_BAD_STATUS_REGS</id> + <target>MEMBUF_CHIP_IN_ERROR</target> + </collectRegisterFfdc> <callout> <target>MEMBUF_CHIP_IN_ERROR</target> <priority>HIGH</priority> @@ -43,9 +59,15 @@ <rc>RC_MSS_UNEXPECTED_NEST_CLOCK_STATUS</rc> <description> cen_stopclocks got unexpected clock status in NEST_CLK_STATUS_0x02030008 + This error could happen for a number of reasons and probably not on the + IPL path, so callout the memory buffer chip, but do not deconfigure/GARD. </description> <ffdc>EXPECTED_STATUS</ffdc> <ffdc>ACTUAL_STATUS</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_CLOCK_STOP_BAD_STATUS_REGS</id> + <target>MEMBUF_CHIP_IN_ERROR</target> + </collectRegisterFfdc> <callout> <target>MEMBUF_CHIP_IN_ERROR</target> <priority>HIGH</priority> @@ -56,9 +78,15 @@ <rc>RC_MSS_UNEXPECTED_TP_CLOCK_STATUS</rc> <description> cen_stopclocks got unexpected clock status in TP_CLK_STATUS_0x01030008 + This error could happen for a number of reasons and probably not on the + IPL path, so callout the memory buffer chip, but do not deconfigure/GARD. </description> <ffdc>EXPECTED_STATUS</ffdc> <ffdc>ACTUAL_STATUS</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_CLOCK_STOP_BAD_STATUS_REGS</id> + <target>MEMBUF_CHIP_IN_ERROR</target> + </collectRegisterFfdc> <callout> <target>MEMBUF_CHIP_IN_ERROR</target> <priority>HIGH</priority> diff --git a/src/usr/hwpf/hwp/dram_training/memory_mss_termination_control.xml b/src/usr/hwpf/hwp/dram_training/memory_mss_termination_control.xml index 98979f9e1..58552cfdf 100644 --- a/src/usr/hwpf/hwp/dram_training/memory_mss_termination_control.xml +++ b/src/usr/hwpf/hwp/dram_training/memory_mss_termination_control.xml @@ -20,8 +20,9 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> + <hwpErrors> -<!-- $Id: memory_mss_termination_control.xml,v 1.3 2014/01/22 15:39:32 mjjones Exp $ --> +<!-- $Id: memory_mss_termination_control.xml,v 1.4 2014/01/31 13:42:23 sasethur Exp $ --> <!-- For file ../../ipl/fapi/mss_termination_control.C --> <!-- // *! OWNER NAME : Saravanan Sethuraman email ID:saravanans@in.ibm.com --> <!-- // *! BACKUP NAME: Menlo Wuu email ID:menlowuu@us.ibm.com --> @@ -112,14 +113,120 @@ </callout> </hwpError> +<registerFfdc> + <id>REG_FFDC_MSS_SLEW_CAL_FAILURE_PORT0</id> + <scomRegister>DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0_0x8000401A0301143F</scomRegister> + <scomRegister>DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR1_0x8000441A0301143F</scomRegister> + <scomRegister>DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR2_0x8000481A0301143F</scomRegister> + <scomRegister>DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR3_0x80004C1A0301143F</scomRegister> + <scomRegister>DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_0_0x800000750301143F</scomRegister> + <scomRegister>DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_1_0x800004750301143F</scomRegister> + <scomRegister>DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_2_0x800008750301143F</scomRegister> + <scomRegister>DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_3_0x80000C750301143F</scomRegister> + <scomRegister>DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_4_0x800010750301143F</scomRegister> +</registerFfdc> + +<registerFfdc> + <id>REG_FFDC_MSS_SLEW_CAL_FAILURE_PORT1</id> + <scomRegister>DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR0_0x8001401A0301143F</scomRegister> + <scomRegister>DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR1_0x8001441A0301143F</scomRegister> + <scomRegister>DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR2_0x8001481A0301143F</scomRegister> + <scomRegister>DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR3_0x80014C1A0301143F</scomRegister> + <scomRegister>DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_0_0x800100750301143F</scomRegister> + <scomRegister>DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_1_0x800104750301143F</scomRegister> + <scomRegister>DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_2_0x800108750301143F</scomRegister> + <scomRegister>DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_3_0x80010C750301143F</scomRegister> + <scomRegister>DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_4_0x800110750301143F</scomRegister> +</registerFfdc> + <hwpError> - <rc>RC_MSS_SLEW_CAL_ERROR</rc> + <rc>RC_MSS_SLEW_CAL_TIMEOUT_PORT0</rc> <description> - mss_slew_cal for slew calibration error + mss_slew_cal found slew calibration timeout on MBA port 0 </description> <ffdc>DATA_ADR</ffdc> <ffdc>IMP</ffdc> <ffdc>SLEW</ffdc> + <ffdc>STAT_REG</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_MSS_SLEW_CAL_FAILURE_PORT0</id> + <target>MBA_IN_ERROR</target> + </collectRegisterFfdc> + <callout> + <target>MBA_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>MBA_IN_ERROR</target> + </deconfigure> + <gard> + <target>MBA_IN_ERROR</target> + </gard> +</hwpError> + +<hwpError> + <rc>RC_MSS_SLEW_CAL_TIMEOUT_PORT1</rc> + <description> + mss_slew_cal found slew calibration timeout on MBA port 1 + </description> + <ffdc>DATA_ADR</ffdc> + <ffdc>IMP</ffdc> + <ffdc>SLEW</ffdc> + <ffdc>STAT_REG</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_MSS_SLEW_CAL_FAILURE_PORT1</id> + <target>MBA_IN_ERROR</target> + </collectRegisterFfdc> + <callout> + <target>MBA_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>MBA_IN_ERROR</target> + </deconfigure> + <gard> + <target>MBA_IN_ERROR</target> + </gard> +</hwpError> + +<hwpError> + <rc>RC_MSS_SLEW_CAL_ERROR_PORT0</rc> + <description> + mss_slew_cal found slew calibration error on MBA port 0 + </description> + <ffdc>DATA_ADR</ffdc> + <ffdc>IMP</ffdc> + <ffdc>SLEW</ffdc> + <ffdc>STAT_REG</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_MSS_SLEW_CAL_FAILURE_PORT0</id> + <target>MBA_IN_ERROR</target> + </collectRegisterFfdc> + <callout> + <target>MBA_IN_ERROR</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>MBA_IN_ERROR</target> + </deconfigure> + <gard> + <target>MBA_IN_ERROR</target> + </gard> +</hwpError> + +<hwpError> + <rc>RC_MSS_SLEW_CAL_ERROR_PORT1</rc> + <description> + mss_slew_cal found slew calibration error on MBA port 1 + </description> + <ffdc>DATA_ADR</ffdc> + <ffdc>IMP</ffdc> + <ffdc>SLEW</ffdc> + <ffdc>STAT_REG</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_MSS_SLEW_CAL_FAILURE_PORT1</id> + <target>MBA_IN_ERROR</target> + </collectRegisterFfdc> <callout> <target>MBA_IN_ERROR</target> <priority>HIGH</priority> diff --git a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/memory_mss_ddr_phy_reset.xml b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/memory_mss_ddr_phy_reset.xml index 9fd61dc8b..df9156550 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/memory_mss_ddr_phy_reset.xml +++ b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/memory_mss_ddr_phy_reset.xml @@ -20,8 +20,9 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> + <hwpErrors> -<!-- $Id: memory_mss_ddr_phy_reset.xml,v 1.2 2014/01/16 20:55:42 mfred Exp $ --> +<!-- $Id: memory_mss_ddr_phy_reset.xml,v 1.3 2014/01/31 15:08:07 mfred Exp $ --> <!-- For file ../../ipl/fapi/mss_ddr_phy_reset.C --> <!-- // *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com --> <!-- // *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com --> @@ -39,6 +40,13 @@ <target>MBA_IN_ERROR</target> <priority>HIGH</priority> </callout> + <callout> + <hw> + <hwid>MEM_REF_CLOCK</hwid> + <refTarget>MEMBUF_CHIP_IN_ERROR</refTarget> + </hw> + <priority>MEDIUM</priority> + </callout> <deconfigure> <target>MBA_IN_ERROR</target> </deconfigure> @@ -60,6 +68,13 @@ <target>MBA_IN_ERROR</target> <priority>HIGH</priority> </callout> + <callout> + <hw> + <hwid>MEM_REF_CLOCK</hwid> + <refTarget>MEMBUF_CHIP_IN_ERROR</refTarget> + </hw> + <priority>MEDIUM</priority> + </callout> <deconfigure> <target>MBA_IN_ERROR</target> </deconfigure> @@ -81,6 +96,13 @@ <target>MBA_IN_ERROR</target> <priority>HIGH</priority> </callout> + <callout> + <hw> + <hwid>MEM_REF_CLOCK</hwid> + <refTarget>MEMBUF_CHIP_IN_ERROR</refTarget> + </hw> + <priority>MEDIUM</priority> + </callout> <deconfigure> <target>MBA_IN_ERROR</target> </deconfigure> @@ -102,6 +124,13 @@ <target>MBA_IN_ERROR</target> <priority>HIGH</priority> </callout> + <callout> + <hw> + <hwid>MEM_REF_CLOCK</hwid> + <refTarget>MEMBUF_CHIP_IN_ERROR</refTarget> + </hw> + <priority>MEDIUM</priority> + </callout> <deconfigure> <target>MBA_IN_ERROR</target> </deconfigure> diff --git a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C index 30ef0fb7e..052c10ff9 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C +++ b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C @@ -20,7 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_ddr_phy_reset.C,v 1.27 2014/01/16 20:54:48 mfred Exp $ + +// $Id: mss_ddr_phy_reset.C,v 1.28 2014/01/31 15:09:03 mfred Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_ddr_phy_reset.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -430,6 +431,7 @@ fapi::ReturnCode mss_ddr_phy_reset_cloned(const fapi::Target & i_target) const uint16_t & EXPECTED_STATUS = DP18_PLL_EXP_LOCK_STATUS; const uint16_t ACTUAL_STATUS = dp_p0_lock_data.getHalfWord(3); const fapi::Target & MBA_IN_ERROR = i_target; + const fapi::Target & MEMBUF_CHIP_IN_ERROR = l_centaurTarget; FAPI_SET_HWP_ERROR(rc, RC_MSS_DP18_0_PLL_FAILED_TO_LOCK); break; } @@ -453,6 +455,7 @@ fapi::ReturnCode mss_ddr_phy_reset_cloned(const fapi::Target & i_target) const uint16_t & EXPECTED_STATUS = DP18_PLL_EXP_LOCK_STATUS; const uint16_t ACTUAL_STATUS = dp_p1_lock_data.getHalfWord(3); const fapi::Target & MBA_IN_ERROR = i_target; + const fapi::Target & MEMBUF_CHIP_IN_ERROR = l_centaurTarget; FAPI_SET_HWP_ERROR(rc, RC_MSS_DP18_1_PLL_FAILED_TO_LOCK); break; } @@ -468,6 +471,7 @@ fapi::ReturnCode mss_ddr_phy_reset_cloned(const fapi::Target & i_target) const uint16_t & EXPECTED_STATUS = AD32S_PLL_EXP_LOCK_STATUS; const uint16_t ACTUAL_STATUS = ad_p0_lock_data.getHalfWord(3); const fapi::Target & MBA_IN_ERROR = i_target; + const fapi::Target & MEMBUF_CHIP_IN_ERROR = l_centaurTarget; FAPI_SET_HWP_ERROR(rc, RC_MSS_AD32S_0_PLL_FAILED_TO_LOCK); break; } @@ -479,6 +483,7 @@ fapi::ReturnCode mss_ddr_phy_reset_cloned(const fapi::Target & i_target) const uint16_t & EXPECTED_STATUS = AD32S_PLL_EXP_LOCK_STATUS; const uint16_t ACTUAL_STATUS = ad_p1_lock_data.getHalfWord(3); const fapi::Target & MBA_IN_ERROR = i_target; + const fapi::Target & MEMBUF_CHIP_IN_ERROR = l_centaurTarget; FAPI_SET_HWP_ERROR(rc, RC_MSS_AD32S_1_PLL_FAILED_TO_LOCK); break; } @@ -1174,6 +1179,9 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: mss_ddr_phy_reset.C,v $ +Revision 1.28 2014/01/31 15:09:03 mfred +Mike Jones added statements to pass target into XML for callouts. + Revision 1.27 2014/01/16 20:54:48 mfred Updates for passing more data to error handler. From Mike Jones. diff --git a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.H b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.H index 9ef643a3c..4a96fa503 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.H +++ b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.H @@ -1,26 +1,25 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.H $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ // $Id: mss_ddr_phy_reset.H,v 1.2 2012/03/21 18:12:28 mfred Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_ddr_phy_reset.H,v $ //------------------------------------------------------------------------------ diff --git a/src/usr/hwpf/hwp/dram_training/mss_termination_control.C b/src/usr/hwpf/hwp/dram_training/mss_termination_control.C index c237d0d5b..39dd60f11 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_termination_control.C +++ b/src/usr/hwpf/hwp/dram_training/mss_termination_control.C @@ -20,7 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_termination_control.C,v 1.25 2014/01/22 15:39:18 mjjones Exp $ + +// $Id: mss_termination_control.C,v 1.26 2014/01/31 13:41:28 sasethur Exp $ /* File is created by SARAVANAN SETHURAMAN on Thur 29 Sept 2011. */ //------------------------------------------------------------------------------ @@ -43,6 +44,7 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.26 | mjjones |31-Jan-14| RAS Reviewed // 1.25 | mjjones |22-Jan-14| Removed firmware header // 1.24 | abhijsau |21-Jan-14| mike and menlo fixed ras review comments // 1.23 | bellows |02-Dec-13| VPD attribute update @@ -1344,16 +1346,6 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba) } else { - if (cal_status == 1) - { - FAPI_ERR("Error occurred during slew " - "calibration"); - } - else - { - FAPI_ERR("Slew calibration timed out, loop=%i", - poll_count); - } FAPI_ERR("Slew calibration failed on %s slew: " "imp_idx=%d(%i ohms)", (data_adr ? "ADR" : "DATA"), imp, @@ -1370,7 +1362,41 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba) const uint8_t & IMP = imp; const uint8_t & SLEW = slew; const fapi::Target & MBA_IN_ERROR = i_target_mba; - FAPI_SET_HWP_ERROR(rc, RC_MSS_SLEW_CAL_ERROR); + const ecmdDataBufferBase & STAT_REG = stat_reg; + + if (cal_status == 1) + { + if (l_port == 0) + { + FAPI_ERR("Error occurred during slew calibration on port 0"); + FAPI_SET_HWP_ERROR(rc, + RC_MSS_SLEW_CAL_ERROR_PORT0); + } + else + { + FAPI_ERR("Error occurred during slew calibration on port 1"); + FAPI_SET_HWP_ERROR(rc, + RC_MSS_SLEW_CAL_ERROR_PORT1); + } + } + else + { + if (l_port == 0) + { + FAPI_ERR("Slew calibration timed out on port 0, loop=%i", + poll_count); + FAPI_SET_HWP_ERROR(rc, + RC_MSS_SLEW_CAL_TIMEOUT_PORT0); + } + else + { + FAPI_ERR("Slew calibration timed out on port 1, loop=%i", + poll_count); + FAPI_SET_HWP_ERROR(rc, + RC_MSS_SLEW_CAL_TIMEOUT_PORT1); + } + } + array_rcs[l_port]=rc; continue; } |