TULETA Bring Up - HW procedure update 04/29/2013

SW199915

Change-Id: I5d9bcd80bd014d5c07f85f8f181394fd10202c71
Tested-by: Jenkins Server
Reviewed-by: Van H. Lee <vanlee@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

12 files changed, 2615 insertions, 532 deletions

diff --git a/src/usr/hwpf/hwp/core_activate/switch_rec_attn/proc_switch_rec_attn.C b/src/usr/hwpf/hwp/core_activate/switch_rec_attn/proc_switch_rec_attn.C
index c2f483adc..a1cce3d25 100644
--- a/src/usr/hwpf/hwp/core_activate/switch_rec_attn/proc_switch_rec_attn.C
+++ b/src/usr/hwpf/hwp/core_activate/switch_rec_attn/proc_switch_rec_attn.C
@@ -21,7 +21,7 @@
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
 // -*- mode: C++; c-file-style: "linux";  -*-
-// $Id: proc_switch_rec_attn.C,v 1.1 2012/12/10 20:38:04 mfred Exp $
+// $Id: proc_switch_rec_attn.C,v 1.2 2013/04/12 19:23:36 mfred Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_switch_rec_attn.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -94,7 +94,12 @@ extern "C"
             // The FIR bits are in the MCS MCIFIR register (02011840 is the first instance)
             // The FIR masks are in the MCS MCIFIRMASK reg (02011843 is the first instance)
             FAPI_INF("Mask OFF the MCI FIR bits 12,15,16,17 coming from Centaur.\n");
-            rc_ecmd |= scom_data.flushTo0();
+            rc = fapiGetScom(i_target, MCS_MCIFIRMASK_0x02011843, scom_data);
+            if (rc)
+            {
+                FAPI_ERR("fapiGetScom error (MCS_MCIFIRMASK_0x02011843)");
+                break;
+            }
             rc_ecmd |= scom_data.setBit(MCI_CENTAUR_CHECKSTOP_BIT);
             rc_ecmd |= scom_data.setBit(MCI_CENTAUR_RECOV_ERR_BIT);
             rc_ecmd |= scom_data.setBit(MCI_CENTAUR_SPEC_ATTN_BIT);
@@ -179,6 +184,9 @@ extern "C"
 This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 $Log: proc_switch_rec_attn.C,v $
+Revision 1.2  2013/04/12 19:23:36  mfred
+Avoid clearing bit 18 of the MCIFIRMASK by reading the reg first. (Fix for SW197032).
+
 Revision 1.1  2012/12/10 20:38:04  mfred
 Committing new procedure proc_switch_rec_attn.
 
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C
index 7993f87df..bf2740375 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit_training_advanced.C,v 1.29 2013/04/23 14:26:07 sasethur Exp $
+// $Id: mss_draminit_training_advanced.C,v 1.30 2013/04/24 13:41:57 sasethur Exp $
 /* File is created by SARAVANAN SETHURAMAN on Thur 29 Sept 2011. */
 
 //------------------------------------------------------------------------------
@@ -69,6 +69,7 @@
 //  1.27   | sasethur |09-Apr-13| Updated for port in parallel and pass shmoo param
 //  1.28   | sasethur |22-Apr-13| Fixed fw comment 
 //  1.29   | sasethur |23-Apr-13| Fixed fw comment 
+//  1.30   | sasethur |24-Apr-13| Fixed fw comment 
 
 // This procedure Schmoo's DRV_IMP, SLEW, VREF (DDR, CEN), RCV_IMP based on attribute from effective config procedure
 // DQ & DQS Driver impedance, Slew rate, WR_Vref shmoo would call only write_eye shmoo for margin calculation
@@ -1013,9 +1014,9 @@ void find_best_margin(shmoo_param i_shmoo_param_valid,
     uint32_t right_margin = 0;
     uint32_t left_margin_nom = 0;
     uint32_t right_margin_nom = 0;
-    uint32_t __attribute__((unused)) diff_margin_nom = 0; // SW198827
+    uint32_t diff_margin_nom = 0;
     //uint32_t total_margin = 0;
-    uint32_t __attribute__((unused)) diff_margin = 0; // SW198827
+    uint32_t diff_margin = 0;
     uint8_t index = 0;
     uint8_t index2 = 0;
    
@@ -1087,8 +1088,7 @@ void find_best_margin(shmoo_param i_shmoo_param_valid,
 	diff_margin = (i_left[index2] >= i_right[index2]) ? (i_left[index2] - i_right[index2]) : (i_right[index2] - i_left[index2]);
 	if ((left_margin > 0 && right_margin > 0))
 	{
-	   // if((left_margin >= left_margin_nom) && (right_margin >= right_margin_nom) && (diff_margin <= diff_margin_nom))
-	    if((left_margin >= left_margin_nom) && (right_margin >= right_margin_nom))
+	    if((left_margin >= left_margin_nom) && (right_margin >= right_margin_nom) && (diff_margin <= diff_margin_nom))
 	    {
  	        o_index = index2;
 		//wont break this loop, since the purpose is to find the best parameter value & best timing margin The enum is constructed to do that
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C
index 7ade47d33..4e1a00b51 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C
@@ -21,7 +21,7 @@
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
 
-// $Id: mss_generic_shmoo.C,v 1.44 2013/04/22 17:03:34 sasethur Exp $
+// $Id: mss_generic_shmoo.C,v 1.47 2013/04/25 12:14:00 sasethur Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -40,17 +40,15 @@
 //------------------------------------------------------------------------------
 // Version:|Author: | Date:   | Comment:
 // --------|--------|---------|--------------------------------------------------
-//   1.44  |bellows |04/22/13 |  fixed fw comments  
-//   1.43  |bellows |04/11/13 |  quick fix for firmware delivery.  Uninitialized varialbles: i_mcbtest, i_mcbpatt 
-//   1.42  |abhijit |04/09/13 |  added shmoo param 
-//   1.40  |abhijit |03/22/13 |  Fixed boundary checks  
-//   1.38  |abhijit |03/19/13 |  included spare byte and ECC and fixed printing for RD_EYE 
-//   1.36  |abhijit |03/19/13 |  changed mcbist call position   
-//   1.35  |abhijit |03/16/13 | fixed clearing of error map regs for mba23  
-//   1.32  |abhijit |03/12/13 | new parallel schmoo under dev 
-//   1.27  |abhijit |01/21/13 | fixed ISDIMM mapping need some workaround 
-//   1.26  |abhijit |01/21/13 | fixed fw comments  
-//   1.25  |abhijit |01/21/13 | fixed the constructor definition 
+//   1.45  |abhijit	|04/25/13 | added test type SIMPLE_FIX_RF and SHMOO_STRESS  
+//   1.40  |abhijit	|03/22/13 | Fixed boundary checks  
+//   1.38  |abhijit	|03/19/13 | included spare byte and ECC and fixed printing for RD_EYE 
+//   1.36  |abhijit	|03/19/13 | changed mcbist call position   
+//   1.35  |abhijit	|03/16/13 | fixed clearing of error map regs for mba23  
+//   1.32  |abhijit	|03/12/13 | new parallel schmoo under dev 
+//   1.27  |abhijit	|01/21/13 | fixed ISDIMM mapping need some workaround 
+//   1.26  |abhijit	|01/21/13 | fixed fw comments  
+//   1.25  |abhijit	|01/21/13 | fixed the constructor definition 
 //   1.21  |sasethur|01/17/13 | Updated for sanity mcbist function
 //   1.20  |abhijit |01/11/13 | Updated for change in setup_mcbist function
 //   1.19  |aditya  |01/07/13 | Updated for change in setup_mcbist function
@@ -61,8 +59,8 @@
 //   1.12  |abhijit |15-Nov-12| Fixed FW review comments
 //   1.11  |abhijit |29-Oct-12| added change for ISDIMM checker DQS.
 //   1.9   |abhijit |22-Oct-12| added Write and read DQS.  
-//   1.8   |abhijit |15-Oct-12|Updated multiple changes 
-//   1.0   |varkeykv|27-Sep-11|Initial check in
+//   1.8   |abhijit |15-Oct-12| Updated multiple changes 
+//   1.0   |varkeykv|27-Sep-11| Initial check in
 //------------------------------------------------------------------------------
 #include <fapi.H>
 #include "mss_generic_shmoo.H"
@@ -82,7 +80,7 @@ using namespace fapi;
  * constructor: generic_shmoo
  * Description  :Constructor used to initialize variables and do the initial settings 
  *
- * Parameters: i_target: mba; 	iv_port: 0, 1
+ * Parameters: i_target: mba;		iv_port: 0, 1
  * ---------------------------------------------------------------------------*/
 generic_shmoo:: generic_shmoo(uint8_t addr,shmoo_type_t shmoo_mask,shmoo_algorithm_t shmoo_algorithm)
 {
@@ -97,8 +95,8 @@ generic_shmoo:: generic_shmoo(uint8_t addr,shmoo_type_t shmoo_mask,shmoo_algorit
     iv_pattern=0;
     iv_test_type=0;
     iv_dmm_type=0;
-	iv_shmoo_param=0;
-    
+    iv_shmoo_param=0;
+	
 	for(int p=0;p<MAX_PORT;++p)
     {
     for(int i=0;i<iv_MAX_RANKS[p];++i)
@@ -129,22 +127,22 @@ generic_shmoo:: generic_shmoo(uint8_t addr,shmoo_type_t shmoo_mask,shmoo_algorit
     if(shmoo_mask & WR_EYE)
     {
         FAPI_DBG("mss_generic_shmoo : WR_EYE selected %d",shmoo_mask);
-        iv_shmoo_type = 0;
+        iv_shmoo_type = 2;
         SHMOO[0].static_knob.min_val=0;
         SHMOO[0].static_knob.max_val=512;   
     }
     if(shmoo_mask & RD_EYE)
     {
         FAPI_DBG("mss_generic_shmoo : RD_EYE selected %d",shmoo_mask);
-        iv_shmoo_type = 2;
+        iv_shmoo_type = 8;
         SHMOO[2].static_knob.min_val=2;
         SHMOO[2].static_knob.max_val=128;
     }
 	
      if(shmoo_mask & WRT_DQS) //preet
     {
-        FAPI_DBG("mss_generic_shmoo : WRT_DQS selected %d",shmoo_mask);
-        iv_shmoo_type = 1;
+        FAPI_INF("mss_generic_shmoo : WRT_DQS selected %d",shmoo_mask);
+        iv_shmoo_type = 4;
 		iv_DQS_ON = 1;
         SHMOO[1].static_knob.min_val=0;
         SHMOO[1].static_knob.max_val=512;
@@ -164,28 +162,34 @@ generic_shmoo:: generic_shmoo(uint8_t addr,shmoo_type_t shmoo_mask,shmoo_algorit
     for(int j=0;j<iv_MAX_RANKS[i];++j)
     {
         init_multi_array(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.nom_val,0);
+		init_multi_array(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.right_err_cnt,0);
+		init_multi_array(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.left_err_cnt,0);
         init_multi_array(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.lb_regval,SHMOO[iv_shmoo_type].static_knob.min_val);
         init_multi_array(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.rb_regval,SHMOO[iv_shmoo_type].static_knob.max_val);
+		init_multi_array(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.lb_regval,20);
+        init_multi_array(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.rb_regval,300);
         init_multi_array(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.total_margin,0);
         init_multi_array(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.right_margin_val,0);
         init_multi_array(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.left_margin_val,0);
     }
 	}
 	
-	if(iv_DQS_ON == 1)
-	{	for(int i=0;i<MAX_PORT;++i)
-		{
-		for(int j=0;j<iv_MAX_RANKS[i];++j) //initialize values for DQS
-        {
-            init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.nom_val,0);
-            init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.lb_regval,SHMOO[iv_shmoo_type].static_knob.min_val);
-            init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.rb_regval,SHMOO[iv_shmoo_type].static_knob.max_val);
-            init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.total_margin,0);
-	    init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.right_margin_val,0);
-	    init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.left_margin_val,0);
-        }
-		}
-	}
+	// if(iv_DQS_ON == 1)
+	// {	for(int i=0;i<MAX_PORT;++i)
+		// {
+		// for(int j=0;j<iv_MAX_RANKS[i];++j) //initialize values for DQS
+        // {
+            // init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.nom_val,0);
+            // // init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.lb_regval,SHMOO[iv_shmoo_type].static_knob.min_val);
+            // // init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.rb_regval,SHMOO[iv_shmoo_type].static_knob.max_val);
+			// init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.lb_regval,20);
+            // init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.rb_regval,300);
+            // init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.total_margin,0);
+	    // init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.right_margin_val,0);
+	    // init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.left_margin_val,0);
+        // }
+		// }
+	// }
 }
 
 /*------------------------------------------------------------------------------
@@ -203,12 +207,17 @@ fapi::ReturnCode generic_shmoo::run(const fapi::Target & i_target,uint32_t *o_ri
 	iv_shmoo_param=i_shmoo_param;
 	
     ecmdDataBufferBase l_data_buffer1_64(64);
+	uint8_t l_dram_width=0;
+    
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_dram_width); if(rc) return rc;
     
     
     rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_per_dimm); if(rc) return rc;
     rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, l_attr_eff_dimm_type_u8); if(rc) return rc; 
     rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target, l_attr_schmoo_test_type_u8); if(rc) return rc; 
 	
+	
+	
     iv_MAX_RANKS[0]=num_ranks_per_dimm[0][0]+num_ranks_per_dimm[0][1];
 	iv_MAX_RANKS[1]=num_ranks_per_dimm[1][0]+num_ranks_per_dimm[1][1];
 	
@@ -240,7 +249,34 @@ fapi::ReturnCode generic_shmoo::run(const fapi::Target & i_target,uint32_t *o_ri
     FAPI_ERR("generic_shmoo::run MSS Generic Shmoo failed initial Sanity Check. Memory not in an all pass Condition");
     return rc; 
     }
+	}else if(l_attr_schmoo_test_type_u8 == 4){
+	
+	iv_shmoo_type=4;
+	//FAPI_INF("\n ABHIJIT IS HERE 1111  \n");
+	rc=get_all_noms_dqs(i_target);if(rc) return rc;
+	iv_shmoo_type=2;
+	//FAPI_INF("\n ABHIJIT IS HERE 2222  \n");
+	rc=get_all_noms(i_target);if(rc) return rc;
+	rc=schmoo_setup_mcb(i_target);if(rc) return rc;
+    //Find RIGHT BOUND OR SETUP BOUND
+    rc=find_bound(i_target,RIGHT);if(rc) return rc;
+	//FAPI_INF("\n ABHIJIT IS HERE 3333  \n");
+    //Find LEFT BOUND OR HOLD BOUND
+    rc=find_bound(i_target,LEFT);if(rc) return rc;
+	iv_shmoo_type=4;
+	
+	if(l_dram_width == 4 ){
+	rc=get_margin_dqs_by4(i_target);if(rc) return rc;
 	}else{
+	//FAPI_INF("\n ABHIJIT IS HERE 222  \n");
+	rc=get_margin_dqs_by8(i_target);if(rc) return rc;
+	}
+	//FAPI_INF("\n before the call \n");
+	rc=print_report_dqs(i_target);if(rc) return rc;
+	
+	
+	
+	} else {
 	// rc=sanity_check(i_target); // Run MCBIST by  default before for every schmoo to check if memory is in good condition. 
     // if(!rc.ok())
     // {
@@ -250,6 +286,7 @@ fapi::ReturnCode generic_shmoo::run(const fapi::Target & i_target,uint32_t *o_ri
     // If memory is OK then we continue to gather nominals and config values
     //  Now Read nominal values for all knobs configured
     // FAPI_DBG("mss_generic_shmoo : run() :read nominal values ");
+	
     rc=get_all_noms(i_target);if(rc) return rc;
 	rc=schmoo_setup_mcb(i_target);if(rc) return rc;
     //Find RIGHT BOUND OR SETUP BOUND
@@ -335,6 +372,11 @@ fapi::ReturnCode generic_shmoo::do_mcbist_test(const fapi::Target & i_target)
     rc = fapiPutScom(i_target,0x0201176e,l_data_buffer_64); if(rc) return(rc);
     rc = fapiPutScom(i_target,0x0201176f,l_data_buffer_64); if(rc) return(rc);
 	
+	rc = fapiPutScom(i_target,MBS_MCBIST01_MCB_ERRCNTA1Q_0x02011664,l_data_buffer_64); if(rc) return(rc);
+    rc = fapiPutScom(i_target,MBS_MCBIST01_MCB_ERRCNTA2Q_0x02011665,l_data_buffer_64); if(rc) return(rc);
+    rc = fapiPutScom(i_target,MBS_MCBIST01_MCB_ERRCNTB1Q_0x02011667,l_data_buffer_64); if(rc) return(rc);
+	rc = fapiPutScom(i_target,MBS_MCBIST01_MCB_ERRCNTB2Q_0x02011668,l_data_buffer_64); if(rc) return(rc);
+	
    rc = start_mcb(i_target);
     if(rc)
     {
@@ -480,6 +522,83 @@ fapi::ReturnCode generic_shmoo::check_error_map(const fapi::Target & i_target,ui
 	 }
     return rc;
 }
+
+fapi::ReturnCode generic_shmoo::get_error_cnt(const fapi::Target & i_target,uint8_t port,uint8_t rank,uint8_t rank_pair,uint8_t bit,bound_t bound)
+{
+fapi::ReturnCode rc;
+uint8_t l_nibble=0;
+uint8_t l_start_bit=0;
+uint16_t l_err_cnt_C=0;
+uint8_t rc_ecmd=0;
+uint8_t l_length_buffer=7;
+uint8_t l_val=0;
+
+
+input_type l_input_type_e =  ISDIMM_DQ;
+ecmdDataBufferBase data_buffer_64(64);
+ecmdDataBufferBase data_buffer_64_1(64);
+
+if(iv_dmm_type==1)
+    {
+	
+	//FAPI_INF("\n ISDIMM input byte=%d and nibble=%d and bit returned is %d \n",l_byte,l_nibble,l_val);
+	rc=rosetta_map(i_target,port,l_input_type_e,bit,0,l_val);if(rc) return rc;
+	//FAPI_INF("\n ISDIMM input byte=%d and nibble=%d and bit returned is %d \n",l_byte,l_nibble,l_val);
+	l_nibble=l_val/4;
+	
+	}else{
+	
+l_nibble=bit/4;
+}
+
+if(port==0)
+				{
+				    if(l_nibble<9)
+				    {
+					rc = fapiGetScom(i_target,MBS_MCBIST01_MCB_ERRCNTA1Q_0x02011664,data_buffer_64); if(rc) return rc;
+					l_start_bit=l_nibble*7;
+					rc_ecmd=data_buffer_64.extractToRight(&l_err_cnt_C,l_start_bit,l_length_buffer);if (rc_ecmd){ rc.setEcmdError(rc_ecmd); return rc;}
+				    }
+				    else
+				    {
+					rc = fapiGetScom(i_target,MBS_MCBIST01_MCB_ERRCNTA2Q_0x02011665,data_buffer_64); if(rc) return rc;
+					l_nibble=l_nibble-9;
+					l_start_bit=l_nibble*7;
+					rc_ecmd=data_buffer_64.extractToRight(&l_err_cnt_C,l_start_bit,l_length_buffer);if (rc_ecmd){ rc.setEcmdError(rc_ecmd); return rc;}
+				    }
+				}else
+				{
+				    if(l_nibble<9)
+				    {
+					rc = fapiGetScom(i_target,MBS_MCBIST01_MCB_ERRCNTB1Q_0x02011667,data_buffer_64_1); if(rc) return rc;
+					l_start_bit=l_nibble*7;
+					rc_ecmd=data_buffer_64.extractToRight(&l_err_cnt_C,l_start_bit,l_length_buffer);if (rc_ecmd){ rc.setEcmdError(rc_ecmd); return rc;}
+				    }
+				    else
+				    {
+					rc = fapiGetScom(i_target,MBS_MCBIST01_MCB_ERRCNTB2Q_0x02011668,data_buffer_64_1); if(rc) return rc;
+					l_nibble=l_nibble-9;
+					l_start_bit=l_nibble*7;
+					rc_ecmd=data_buffer_64.extractToRight(&l_err_cnt_C,l_start_bit,l_length_buffer);if (rc_ecmd){ rc.setEcmdError(rc_ecmd); return rc;}
+				    }
+				}
+				if(bound==RIGHT)
+    {
+		if(l_err_cnt_C){
+		SHMOO[iv_shmoo_type].MBA.P[port].S[rank].K.right_err_cnt[bit][rank_pair]=l_err_cnt_C;	
+		}
+		FAPI_INF("\n THE PORT=%d Rank=%d dq=%d and error count=%d \n",port,rank,bit,SHMOO[iv_shmoo_type].MBA.P[port].S[rank].K.right_err_cnt[bit][rank_pair]);
+	}else {
+	if(l_err_cnt_C){
+	SHMOO[iv_shmoo_type].MBA.P[port].S[rank].K.left_err_cnt[bit][rank_pair]=l_err_cnt_C;	
+}	
+		FAPI_INF("\n THE PORT=%d Rank=%d dq=%d and error count=%d \n",port,rank,bit,SHMOO[iv_shmoo_type].MBA.P[port].S[rank].K.left_err_cnt[bit][rank_pair]);
+		}
+	return rc;	
+				
+}				
+
+
 /*------------------------------------------------------------------------------
  * Function: init_multi_array
  * Description  : This function do the initialization of various schmoo parameters
@@ -560,12 +679,12 @@ fapi::ReturnCode generic_shmoo::get_all_noms(const fapi::Target & i_target)
     FAPI_DBG("mss_generic_shmoo : get_all_noms : Reading in all nominal values");
     
     
-             if(iv_shmoo_type == 1)
+             if(iv_shmoo_type == 4)
             {   
 		l_input_type_e = WR_DQS;
                 
             }
-            else if(iv_shmoo_type == 2)
+            else if(iv_shmoo_type == 8)
             {   
 		
 		l_input_type_e = RD_DQ;
@@ -605,6 +724,61 @@ fapi::ReturnCode generic_shmoo::get_all_noms(const fapi::Target & i_target)
     return rc;
 }
 
+fapi::ReturnCode generic_shmoo::get_all_noms_dqs(const fapi::Target & i_target)
+{
+    fapi::ReturnCode rc;
+    
+    uint8_t l_rnk;
+    //uint8_t i_rnk=0;
+    uint8_t i_rp=0;
+    uint32_t val=0;
+    //uint8_t l_dq=0;
+	uint8_t l_p=0;
+    uint8_t l_max_nibble=20;
+	uint8_t rank=0;
+	uint8_t l_n=0;
+	FAPI_INF("mss_generic_shmoo : get_all_noms_dqs : Reading in all nominal values and schmoo type=%d \n",iv_shmoo_type);
+	if(iv_dmm_type==1)
+		 {
+		 
+		 l_max_nibble=18;
+		 }
+		 
+    input_type_t l_input_type_e = WR_DQS;
+    access_type_t l_access_type_e = READ ;
+    FAPI_DBG("mss_generic_shmoo : get_all_noms : Reading in all nominal values");
+    
+    
+             if(iv_shmoo_type == 4)
+            {   
+		l_input_type_e = WR_DQS;
+                
+            }
+            
+			
+			for (l_p=0;l_p<MAX_PORT;l_p++){
+	for (l_rnk=0;l_rnk<iv_MAX_RANKS[l_p];++l_rnk)
+    {// Byte loop
+	rc = mss_getrankpair(i_target,l_p,0,&i_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rnk];
+		rc = mss_getrankpair(i_target,l_p,rank,&i_rp,valid_rank);if(rc) return rc; 
+	 for (l_n=0; l_n<l_max_nibble;l_n++){
+	 
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_n,0,val);if(rc) return rc; 
+		    SHMOO[iv_shmoo_type].MBA.P[l_p].S[rank].K.nom_val[l_n][i_rp]=val;
+		    FAPI_INF("Nominal  Value for port=%d rank=%d  and rank pair=%d and dqs=%d is  %d",l_p,rank,i_rp,l_n,SHMOO[iv_shmoo_type].MBA.P[l_p].S[rank].K.nom_val[l_n][i_rp]);
+	 }
+	 }
+	 }
+			
+			
+            
+	
+	
+    return rc;
+}
+
+
 /*------------------------------------------------------------------------------
  * Function: knob_update
  * Description  : This is a key function is used to find right and left bound using new algorithm -- there is an option u can chose not to use it by setting a flag
@@ -627,7 +801,7 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_
 	
 	uint8_t l_p=0;
     uint16_t l_delay=0;
-    //uint32_t l_max=0;
+    
 	uint16_t l_max_limit=500;
     uint8_t rank=0;
 	uint8_t l_rank=0;
@@ -650,7 +824,7 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_
 	 }
 	 }
 	
-    if(scenario == 2) {
+    if(scenario == 8) {
 	l_input_type_e = RD_DQ;
 	l_max_limit=127;
 	}
@@ -674,13 +848,15 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_
 		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
 	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
 	 
+	 //rc=get_error_cnt(i_target,l_p,rank,l_rp,l_dq,bound);
 	 if(schmoo_error_map[l_p][rank][l_n]==0){
 	 
 	 SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
 	 
 	 FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
 	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
-	  
+	  //rc=get_error_cnt(i_target,l_p,rank,l_rp,l_dq);
+	  //get_error_cnt(const fapi::Target & i_target,uint8_t port,uint8_t rank,uint8_t rank_pair,uint8_t bit)
 	 }
 	 
 	 if(SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]>l_max_limit){
@@ -701,7 +877,7 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_
 		    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
 		    return rc;
 		}
-		
+		//rc=get_error_cnt(i_target,l_p,rank,l_rp,l_dq);
 		rc=check_error_map(i_target,l_p,pass);
 		if(rc)
 		{   
@@ -746,7 +922,7 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_
 	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
 	 
 	 //l_max=SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp];
-	 
+	 //rc=get_error_cnt(i_target,l_p,rank,l_rp,l_dq,bound);
 	 
 	 if(schmoo_error_map[l_p][rank][l_n]==0){
 	 SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
@@ -808,96 +984,1146 @@ rc=check_error_map(i_target,l_p,pass);
  * Description  : This is a key function is used to find right and left bound using new algorithm -- there is an option u can chose not to use it by setting a flag
  *
  * Parameters: Target:MBA,bound:RIGHT/LEFT,scenario:type of schmoo,iv_port:0/1,rank:0-7,byte:0-7,nibble:0/1,bit:0-3,pass,
- * ---------------------------------------------------------------------------
-fapi::ReturnCode generic_shmoo::knob_update_dqs(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t rank,uint8_t byte,uint8_t nibble,uint8_t bit,uint8_t pass)
-{
+ * --------------------------------------------------------------------------- */
+fapi::ReturnCode generic_shmoo::knob_update_dqs_by4(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag)
+{	
     fapi::ReturnCode rc;
     ecmdDataBufferBase data_buffer_64(64);
     ecmdDataBufferBase data_buffer_64_1(64);
-    data_buffer_64.flushTo0();
-    data_buffer_64_1.flushTo0();
-    uint32_t l_current_val=0;
-    uint32_t l_max_value=0;
-    uint32_t l_min_value=0;
+    
+    
     
     uint8_t  l_rp=0;
-    input_type_t l_input_type_e = WR_DQS;
+    input_type_t l_input_type_e = WR_DQ;
+	input_type_t l_input_type_e_dqs = WR_DQS;
     uint8_t l_dq=0;
     access_type_t l_access_type_e = WRITE;
+	uint8_t l_n=0;
+	uint8_t l_dqs=4;
+	
 	
-    if(scenario == 1) 
+	uint8_t l_p=0;
+    uint16_t l_delay=0;
+    uint32_t __attribute__((unused)) l_max=0; //SW198827    
+	uint16_t l_max_limit=500;
+    uint8_t rank=0;
+	uint8_t l_rank=0;
+	uint8_t l_SCHMOO_NIBBLES=20;
+	uint8_t i_rp=0;
+	
+	
+	
+	if(iv_dmm_type==1)
     {
-	l_input_type_e = WR_DQS;
-    }
-    else if(scenario == 3) 
+	l_SCHMOO_NIBBLES=18;
+	}
+    //rc = mss_getrankpair(i_target,iv_port,rank,&l_rp,valid_rank);if(rc) return rc; 
+	
+	for (l_p=0;l_p<MAX_PORT;l_p++){
+	for(int i=0;i<iv_MAX_RANKS[l_p];i++){
+	rc = mss_getrankpair(i_target,l_p,0,&i_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[i];
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 schmoo_error_map[l_p][rank][l_n]=0;
+	 }
+	 }
+	 }
+	
+    
+	
+    
+    if(bound==RIGHT)
     {
-	l_input_type_e = RD_DQS;
-    }
+        
+	if(algorithm==SEQ_LIN)
+        {
+		
 	
+	 for (l_delay=1;((pass==0));l_delay++){
+	 
+	 for (l_p=0;l_p<MAX_PORT;l_p++){
+	 for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+	 l_dq=0;
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+		//FAPI_INF("\n abhijit here after  port=%d rank=%d \n",l_p,rank);
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 l_dq=4*l_n;
+	 if(schmoo_error_map[l_p][rank][l_n]==0){
+	 FAPI_INF("\n value of nominal delay scenario=%d rank=%d for port=%d dqs=%d is %d ",l_dqs,rank,l_p,l_n,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n][l_rp]);
+	 SHMOO[l_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_n][l_rp]=SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay scenario=%d rank=%d for port=%d dqs=%d is %d ",l_dqs,rank,l_p,l_n,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_n][l_rp]);
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,1,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_n][l_rp]);if(rc) return rc;
+	 SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay scenario=%d rank=%d for port=%d bit=%d is %d ",scenario,rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	 }
+	 //FAPI_INF("\n abhijit here before \n");
+	 if(SHMOO[l_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]>l_max_limit){
+	 schmoo_error_map[l_p][rank][l_n]=1;
+	 }
+		
+		} 
+		
+		
+	}
+		
+	 }
+	 rc=do_mcbist_test(i_target);
+		if(rc)
+		{   
+		    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
+		    return rc;
+		}
+		
+		rc=check_error_map(i_target,l_p,pass);
+		if(rc)
+		{   
+		    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
+		    return rc;
+		}		
+	
+	 }
+		
+		
+	for (l_p=0;l_p<MAX_PORT;l_p++){
+	for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 FAPI_INF("\n restoring nominal values for dqs=%d port=%d rank=%d is %d \n",l_n,l_p,rank,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n][l_rp]);
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,1,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n][l_rp]);if(rc) return rc;
+	 
+			} 
+		}
+		}
+		for(int l_bit=0;l_bit<4;l_bit++){
+		for (l_p=0;l_p<MAX_PORT;l_p++){
+	for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+	 l_dq=l_bit;
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]);if(rc) return rc;
+	 l_dq=l_dq+4;
+			} 
+		}
+	 }
+	}	
+		
+		
+	 }
+		
+	}
+ 	
     if(bound==LEFT)
     {
+        if(algorithm==SEQ_LIN)
+        {
+		
+		for (l_delay=1;(pass==0);l_delay++){
+	 
+	 for (l_p=0;l_p<MAX_PORT;l_p++){
+	 for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+	 l_dq=0;
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 l_dq=4*l_n;
+	 l_max=SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp];
+	 
+	 
+	 if(schmoo_error_map[l_p][rank][l_n]==0){
+	  SHMOO[l_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_n][l_rp]=SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n][l_rp]-l_delay;
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,1,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_n][l_rp]);if(rc) return rc;
+	 SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	 }
+	 if(SHMOO[l_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp] == 0){
+	 schmoo_error_map[l_p][rank][l_n] = 1;
+	 }
+	 
+	 
+	
+			} 
+		}
+			
+	 }
+	 rc=do_mcbist_test(i_target);
+		if(rc)
+		{   
+		    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
+		    return rc;
+		}
+		 
+rc=check_error_map(i_target,l_p,pass);
+		if(rc)
+		{   
+		    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
+		    return rc;
+		}		
+		
+	
+	 }
+		
+		
+	for (l_p=0;l_p<MAX_PORT;l_p++){
+	for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,1,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n][l_rp]);if(rc) return rc;
+	 
+			} 
+		}
+		}
+		
+		for(int l_bit=0;l_bit<4;l_bit++){
+		for (l_p=0;l_p<MAX_PORT;l_p++){
+	for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+	 l_dq=l_bit;
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]);if(rc) return rc;
+	 l_dq=l_dq+4;
+			} 
+		}
+	 }
+	}
+	 }
+	 
+	    
+	}
+    
+    return rc;	
+}
+fapi::ReturnCode generic_shmoo::knob_update_dqs_by4_isdimm(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag)
+{	
+    fapi::ReturnCode rc;
+    ecmdDataBufferBase data_buffer_64(64);
+    ecmdDataBufferBase data_buffer_64_1(64);
+    
+    
+    
+    uint8_t  l_rp=0;
+    input_type_t l_input_type_e = WR_DQ;
+	input_type_t l_input_type_e_dqs = WR_DQS;
+    uint8_t l_dq=0;
+    access_type_t l_access_type_e = WRITE;
+	uint8_t l_n=0;
+	uint8_t l_dqs=4;
+	uint8_t l_my_dqs=0;
+	
+	
+	uint8_t l_p=0;
+    uint16_t l_delay=0;
+    uint32_t __attribute__((unused)) l_max=0; //SW198827
+	uint16_t l_max_limit=500;
+    uint8_t rank=0;
+	uint8_t l_rank=0;
+	uint8_t l_SCHMOO_NIBBLES=20;
+	uint8_t i_rp=0;
+	
+	
+	
+	if(iv_dmm_type==1)
+    {
+	l_SCHMOO_NIBBLES=18;
+	}
+	uint8_t l_dqs_arr[18]={0,9,1,10,2,11,3,12,4,13,5,14,6,15,7,16,8,17};
+    //rc = mss_getrankpair(i_target,iv_port,rank,&l_rp,valid_rank);if(rc) return rc; 
+	
+	for (l_p=0;l_p<MAX_PORT;l_p++){
+	for(int i=0;i<iv_MAX_RANKS[l_p];i++){
+	rc = mss_getrankpair(i_target,l_p,0,&i_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[i];
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 schmoo_error_map[l_p][rank][l_n]=0;
+	 }
+	 }
+	 }
+	
+    
+    
+    if(bound==RIGHT)
+    {
         
+	if(algorithm==SEQ_LIN)
+        {
+		
+	
+	 for (l_delay=1;((pass==0));l_delay++){
+	 
+	 for (l_p=0;l_p<MAX_PORT;l_p++){
+	 for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+	 l_dq=0;
+	 l_my_dqs=0;
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+		//FAPI_INF("\n abhijit here after  port=%d rank=%d \n",l_p,rank);
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 l_dq=4*l_n;
+	 l_my_dqs=l_dqs_arr[l_n];
+	 if(schmoo_error_map[l_p][rank][l_n]==0){
+	 FAPI_INF("\n value of nominal delay scenario=%d rank=%d for port=%d dqs=%d is %d ",l_dqs,rank,l_p,l_my_dqs,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_my_dqs][l_rp]);
+	 SHMOO[l_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_my_dqs][l_rp]=SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_my_dqs][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay scenario=%d rank=%d for port=%d dqs=%d is %d ",l_dqs,rank,l_p,l_my_dqs,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_my_dqs][l_rp]);
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_my_dqs,0,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_my_dqs][l_rp]);if(rc) return rc;
+	 SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay scenario=%d rank=%d for port=%d bit=%d is %d ",scenario,rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	 }
+	 //FAPI_INF("\n abhijit here before \n");
+	 if(SHMOO[l_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]>l_max_limit){
+	 schmoo_error_map[l_p][rank][l_n]=1;
+	 }
+		
+		} 
+		
+		
+	}
+		
+	 }
+	 rc=do_mcbist_test(i_target);
+		if(rc)
+		{   
+		    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
+		    return rc;
+		}
+		
+		rc=check_error_map(i_target,l_p,pass);
+		if(rc)
+		{   
+		    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
+		    return rc;
+		}		
+	
+	 }
+		
+		
+	for (l_p=0;l_p<MAX_PORT;l_p++){
+	for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 FAPI_INF("\n restoring nominal values for dqs=%d port=%d rank=%d is %d \n",l_n,l_p,rank,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n][l_rp]);
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n][l_rp]);if(rc) return rc;
+	 
+			} 
+		}
+		}
+		
+		for(int l_bit=0;l_bit<4;l_bit++){
+		for (l_p=0;l_p<MAX_PORT;l_p++){
+	for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+	 l_dq=l_bit;
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]);if(rc) return rc;
+	 l_dq=l_dq+4;
+			} 
+		}
+	 }
+	}
+		
+		
+		
+	 }
+		
+	}
+ 	
+    if(bound==LEFT)
+    {
         if(algorithm==SEQ_LIN)
         {
-	    l_min_value=SHMOO[scenario].static_knob.min_val;
-	    FAPI_INF("  curr val in left above  = %d and pass=%d ",l_current_val,pass);
-	    for(l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp];((l_current_val >= 20)&&(pass==1));l_current_val-=20)
-	    {
-		    //use saurabh function for writing here 
-		    FAPI_INF("  curr val in left = %d and pass=%d ",l_current_val,pass);
-		    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,0,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc;
-		    
-		    rc=do_mcbist_test(i_target,rank,byte,nibble,pass);
-		    if(rc)
-		    {   
-			FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-			return rc;
-		    }
-       	    }
-	    if(!pass)
-	    {
-		SHMOO[scenario].MBA.P[iv_port].S[rank].K.lb_regval[l_dq][l_rp]=l_current_val;
-	    }
-	    FAPI_INF("  left  bound = %d  ",SHMOO[scenario].MBA.P[iv_port].S[rank].K.rb_regval[l_dq][l_rp]);
-	    l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp];
-	    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,0,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc;
+		
+		for (l_delay=1;(pass==0);l_delay++){
+	 
+	 for (l_p=0;l_p<MAX_PORT;l_p++){
+	 for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+	 l_dq=0;
+	 l_my_dqs=0;
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 l_dq=4*l_n;
+	 	 l_my_dqs=l_dqs_arr[l_n];
+	 l_max=SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp];
+	 
+	 
+	 if(schmoo_error_map[l_p][rank][l_n]==0){
+	  SHMOO[l_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_my_dqs][l_rp]=SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_my_dqs][l_rp]-l_delay;
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_my_dqs,0,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_my_dqs][l_rp]);if(rc) return rc;
+	 SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	 }
+	 if(SHMOO[l_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp] == 0){
+	 schmoo_error_map[l_p][rank][l_n] = 1;
+	 }
+	 
+	 
+	
+			} 
+		}
+			
+	 }
+	 rc=do_mcbist_test(i_target);
+		if(rc)
+		{   
+		    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
+		    return rc;
+		}
+		 
+rc=check_error_map(i_target,l_p,pass);
+		if(rc)
+		{   
+		    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
+		    return rc;
+		}		
+		
+	
+	 }
+		
+		
+	for (l_p=0;l_p<MAX_PORT;l_p++){
+	for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n][l_rp]);if(rc) return rc;
+	 
+			} 
+		}
+		}
+		
+		for(int l_bit=0;l_bit<4;l_bit++){
+		for (l_p=0;l_p<MAX_PORT;l_p++){
+	for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+	 l_dq=l_bit;
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]);if(rc) return rc;
+	 l_dq=l_dq+4;
+			} 
+		}
+	 }
+	}
+	 }
+	 
 	    
 	}
-    }
+    
+    return rc;	
+}
+fapi::ReturnCode generic_shmoo::knob_update_dqs_by8(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag)
+{	
+    fapi::ReturnCode rc;
+    ecmdDataBufferBase data_buffer_64(64);
+    ecmdDataBufferBase data_buffer_64_1(64);
+    
+    
+    
+    uint8_t  l_rp=0;
+    input_type_t l_input_type_e = WR_DQ;
+	input_type_t l_input_type_e_dqs = WR_DQS;
+    uint8_t l_dq=0;
+	uint8_t l_dqs=0;
+    access_type_t l_access_type_e = WRITE;
+	uint8_t l_n=0;
+	uint8_t l_scen_dqs=4;
+	
+	
+	uint8_t l_p=0;
+    uint16_t l_delay=0;
+    uint32_t __attribute__((unused)) l_max=0; //SW198827
+    uint16_t l_max_limit=500;
+    uint8_t rank=0;
+	uint8_t l_rank=0;
+        uint8_t __attribute__((unused))l_SCHMOO_BYTES=10; //SW198827
+	uint8_t l_SCHMOO_NIBBLES=20;
+	
+	uint8_t i_rp=0;
+	
+	
+	
+			
+		
+	
+	if(iv_dmm_type==1)
+    {
+	l_SCHMOO_BYTES=9;
+	l_SCHMOO_NIBBLES=18;
+	}
+    //rc = mss_getrankpair(i_target,iv_port,rank,&l_rp,valid_rank);if(rc) return rc; 
+	
+	for (l_p=0;l_p<MAX_PORT;l_p++){
+	for(int i=0;i<iv_MAX_RANKS[l_p];i++){
+	rc = mss_getrankpair(i_target,l_p,0,&i_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[i];
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 schmoo_error_map[l_p][rank][l_n]=0;
+	 }
+	 }
+	 }
+	
+    
+	
+    
+	
+    
+    if(bound==RIGHT)
+    {
+        
+	if(algorithm==SEQ_LIN)
+        {
+		
+	
+	 for (l_delay=1;((pass==0));l_delay++){
+	 
+	 //for (l_p=0;l_p<MAX_PORT;l_p++){
+	 for (l_p=0;l_p<MAX_PORT;l_p++){
+	 for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+	 l_dq=0;
+	 l_dqs=0;
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+		//FAPI_INF("\n abhijit here after  port=%d rank=%d \n",l_p,rank);
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 l_dq=4*l_n;
+	 if((schmoo_error_map[l_p][rank][l_n]==0)&&(schmoo_error_map[l_p][rank][l_n+1]==0)){
+	 FAPI_INF("\n value of nominal delay scenario=%d rank=%d for port=%d dqs=%d is %d ",l_scen_dqs,rank,l_p,l_n,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n][l_rp]);
+	 SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_n][l_rp]=SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay scenario=%d rank=%d for port=%d dqs=%d is %d ",l_scen_dqs,rank,l_p,l_n,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_n][l_rp]);
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_n][l_rp]);if(rc) return rc;
+	 SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay scenario=%d rank=%d for port=%d bit=%d is %d ",scenario,rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	 l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	  
+	 }
+	 //FAPI_INF("\n abhijit here before \n");
+	 if(SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]>l_max_limit){
+	 schmoo_error_map[l_p][rank][l_n]=1;
+	 schmoo_error_map[l_p][rank][l_n+1]=1;
+	 }
+		if((schmoo_error_map[l_p][rank][l_n]==1)||(schmoo_error_map[l_p][rank][l_n+1]==1)){
+		
+		schmoo_error_map[l_p][rank][l_n]=1;
+	 schmoo_error_map[l_p][rank][l_n+1]=1;
+	 }
+		
+		l_n=l_n+1;
+		l_dqs=l_dqs+1;
+		} 
+		
+		
+	}
+		
+	 }
+	 rc=do_mcbist_test(i_target);
+		if(rc)
+		{   
+		    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
+		    return rc;
+		}
+		
+		rc=check_error_map(i_target,l_p,pass);
+		if(rc)
+		{   
+		    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
+		    return rc;
+		}		
 	
-    else if(bound==RIGHT)
+	 }
+		
+		
+	for (l_p=0;l_p<MAX_PORT;l_p++){
+	for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 FAPI_INF("\n restoring nominal values for dqs=%d port=%d rank=%d is %d \n",l_n,l_p,rank,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n][l_rp]);
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n][l_rp]);if(rc) return rc;
+	 
+			} 
+		}
+		}
+		
+		for(int l_bit=0;l_bit<4;l_bit++){
+		for (l_p=0;l_p<MAX_PORT;l_p++){
+	for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+	 l_dq=l_bit;
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]);if(rc) return rc;
+	 l_dq=l_dq+4;
+			} 
+		}
+	 }
+	}
+		
+		
+		
+	 }
+		
+	}
+ 	
+    if(bound==LEFT)
     {
-         
         if(algorithm==SEQ_LIN)
-         {
-	    l_max_value=SHMOO[scenario].static_knob.max_val;
-	    for(l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp];((l_current_val<l_max_value)&&(pass==1));l_current_val+=100)
-	    {
-		    //use saurabh function for writing here 
-		    FAPI_INF("  curr val  = %d ",l_current_val);
-		    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,0,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc;
-		    
-		    rc=do_mcbist_test(i_target,rank,byte,nibble,pass);
-		    if(rc)
-		    {   
-			FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
+        {
+		
+		for (l_delay=1;(pass==0);l_delay++){
+	 
+	 for (l_p=0;l_p<MAX_PORT;l_p++){
+	 for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+	 l_dq=0;
+	 l_dqs=0;
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 l_dq=4*l_n;
+	 l_max=SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp];
+	 
+	 
+	 if((schmoo_error_map[l_p][rank][l_n]==0)&&(schmoo_error_map[l_p][rank][l_n+1]==0)){
+	  SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_n][l_rp]=SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n][l_rp]-l_delay;
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_n][l_rp]);if(rc) return rc;
+	 SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	 }
+	 if(SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp] == 0){
+	 schmoo_error_map[l_p][rank][l_n] = 1;
+	 schmoo_error_map[l_p][rank][l_n+1] = 1;
+	 }
+	 
+	 if((schmoo_error_map[l_p][rank][l_n]==1)||(schmoo_error_map[l_p][rank][l_n+1]==1)){
+		
+		schmoo_error_map[l_p][rank][l_n]=1;
+	 schmoo_error_map[l_p][rank][l_n+1]=1;
+	 }
+	 
+	l_n=l_n+1;
+	l_dqs=l_dq+1;
+			} 
+		}
+			
+	 }
+	 rc=do_mcbist_test(i_target);
+		if(rc)
+		{   
+		    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
 		    return rc;
-		    }
-	    }
-	    if(!pass)
-	    {
-		SHMOO[scenario].MBA.P[iv_port].S[rank].K.rb_regval[l_dq][l_rp]=l_current_val;
-	    }
-	    l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp];
+		}
+		 
+rc=check_error_map(i_target,l_p,pass);
+		if(rc)
+		{   
+		    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
+		    return rc;
+		}		
 		
-	    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,0,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc;
-	    FAPI_INF("  right bound = %d  ",SHMOO[scenario].MBA.P[iv_port].S[rank].K.rb_regval[l_dq][l_rp]);
-        }
+	
+	 }
+		
+		
+	for (l_p=0;l_p<MAX_PORT;l_p++){
+	for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 FAPI_INF("\n restoring nominal values for dqs=%d port=%d rank=%d is %d \n",l_n,l_p,rank,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n][l_rp]);
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n][l_rp]);if(rc) return rc;
+	 
+			} 
+		}
+		}
+		
+		for(int l_bit=0;l_bit<4;l_bit++){
+		for (l_p=0;l_p<MAX_PORT;l_p++){
+	for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+	 l_dq=l_bit;
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]);if(rc) return rc;
+	 l_dq=l_dq+4;
+			} 
+		}
+	 }
+	}
+	 }
+	 
 	    
-    }
-    return rc;
+	}
+    
+    return rc;	
 }
-*/
+fapi::ReturnCode generic_shmoo::knob_update_dqs_by8_isdimm(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag)
+{	
+    fapi::ReturnCode rc;
+    ecmdDataBufferBase data_buffer_64(64);
+    ecmdDataBufferBase data_buffer_64_1(64);
+    
+    
+    
+    uint8_t  l_rp=0;
+    input_type_t l_input_type_e = WR_DQ;
+	input_type_t l_input_type_e_dqs = WR_DQS;
+    uint8_t l_dq=0;
+	uint8_t l_dqs=0;
+    access_type_t l_access_type_e = WRITE;
+	uint8_t l_n=0;
+	uint8_t l_scen_dqs=4;
+	
+	
+	uint8_t l_p=0;
+    uint16_t l_delay=0;
+    uint32_t __attribute__((unused)) l_max=0; //SW198827
+	uint16_t l_max_limit=500;
+    uint8_t rank=0;
+	uint8_t l_rank=0;
+        uint8_t  __attribute__((unused)) l_SCHMOO_BYTES=10;  //SW198827
+	uint8_t l_SCHMOO_NIBBLES=20;
+	
+	uint8_t i_rp=0;
+	
+	
+	
+	if(iv_dmm_type==1)
+    {
+	l_SCHMOO_BYTES=9;
+	l_SCHMOO_NIBBLES=18;
+	}
+    //rc = mss_getrankpair(i_target,iv_port,rank,&l_rp,valid_rank);if(rc) return rc; 
+	
+	for (l_p=0;l_p<MAX_PORT;l_p++){
+	for(int i=0;i<iv_MAX_RANKS[l_p];i++){
+	rc = mss_getrankpair(i_target,l_p,0,&i_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[i];
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 schmoo_error_map[l_p][rank][l_n]=0;
+	 }
+	 }
+	 }
+	
+    
+	
+    
+    if(bound==RIGHT)
+    {
+        
+	if(algorithm==SEQ_LIN)
+        {
+		
+	
+	 for (l_delay=1;((pass==0));l_delay++){
+	 
+	 for (l_p=0;l_p<MAX_PORT;l_p++){
+	 for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+	 l_dq=0;
+	 l_dqs=0;
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+		//FAPI_INF("\n abhijit here after  port=%d rank=%d \n",l_p,rank);
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 l_dq=4*l_n;
+	 l_dqs=l_n/2;
+	 FAPI_INF("\n the value of error check is %d \n",schmoo_error_map[l_p][rank][l_n]);
+	 if((schmoo_error_map[l_p][rank][l_n]==0)&&(schmoo_error_map[l_p][rank][l_n+1]==0)){
+	 FAPI_INF("\n value of nominal delay scenario=%d rank=%d for port=%d dqs=%d is %d ",l_scen_dqs,rank,l_p,l_dqs,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_dqs][l_rp]);
+	 SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_dqs][l_rp]=SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_dqs][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay scenario=%d rank=%d for port=%d dqs=%d is %d ",l_scen_dqs,rank,l_p,l_dqs,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_dqs][l_rp]);
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_dqs,1,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_dqs][l_rp]);if(rc) return rc;
+	 SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay scenario=%d rank=%d for port=%d bit=%d is %d ",scenario,rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	 l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay;
+	 FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc;
+	  
+	 }
+	 //FAPI_INF("\n abhijit here before \n");
+	 if(SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_dqs][l_rp]>l_max_limit){
+	
+	 schmoo_error_map[l_p][rank][l_n]=1;
+	 schmoo_error_map[l_p][rank][l_n+1]=1;
+	 }
+	 
+	 if((schmoo_error_map[l_p][rank][l_n]==1)||(schmoo_error_map[l_p][rank][l_n+1]==1)){
+		
+		schmoo_error_map[l_p][rank][l_n]=1;
+	 schmoo_error_map[l_p][rank][l_n+1]=1;
+	 }
+		
+		l_n=l_n+1;
+		
+		} 
+		
+		
+	}
+		
+	 }
+	 rc=do_mcbist_test(i_target);
+		if(rc)
+		{   
+		    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
+		    return rc;
+		}
+		
+		rc=check_error_map(i_target,l_p,pass);
+		if(rc)
+		{   
+		    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
+		    return rc;
+		}		
+	
+	 }
+		
+		
+	for (l_p=0;l_p<MAX_PORT;l_p++){
+	for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 FAPI_INF("\n restoring nominal values for dqs=%d port=%d rank=%d is %d \n",l_n,l_p,rank,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n][l_rp]);
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,1,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n][l_rp]);if(rc) return rc;
+	 
+			} 
+		}
+		}
+		
+		for(int l_bit=0;l_bit<4;l_bit++){
+		for (l_p=0;l_p<MAX_PORT;l_p++){
+	for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+	 l_dq=l_bit;
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]);if(rc) return rc;
+	 l_dq=l_dq+4;
+			} 
+		}
+	 }
+	}
+		
+		
+		
+	 }
+		
+	}
+ 	
+    if(bound==LEFT)
+    {
+        if(algorithm==SEQ_LIN)
+        {
+		
+		for (l_delay=1;(pass==0);l_delay++){
+	 
+	 for (l_p=0;l_p<MAX_PORT;l_p++){
+	 for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+	 l_dq=0;
+	 l_dqs=0;
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 l_dq=4*l_n;
+	 l_max=SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp];
+	 l_dqs=l_n/2;
+	 
+	 if((schmoo_error_map[l_p][rank][l_n]==0)&&(schmoo_error_map[l_p][rank][l_n+1]==0)){
+	  SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_dqs][l_rp]=SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_dqs][l_rp]-l_delay;
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_dqs,1,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_dqs][l_rp]);if(rc) return rc;
+	 SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	  l_dq=l_dq+1;
+	  SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay;
+	 FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);
+	  rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc;
+	 }
+	 if(SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_dqs][l_rp] == 0){
+	 schmoo_error_map[l_p][rank][l_n] = 1;
+	 schmoo_error_map[l_p][rank][l_n+1] = 1;
+	 }
+	 
+	 if((schmoo_error_map[l_p][rank][l_n]==1)||(schmoo_error_map[l_p][rank][l_n+1]==1)){
+		
+		schmoo_error_map[l_p][rank][l_n]=1;
+	 schmoo_error_map[l_p][rank][l_n+1]=1;
+	 }
+	 
+	l_n=l_n+1;
+	
+			} 
+		}
+			
+	 }
+	 rc=do_mcbist_test(i_target);
+		if(rc)
+		{   
+		    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
+		    return rc;
+		}
+		 
+rc=check_error_map(i_target,l_p,pass);
+		if(rc)
+		{   
+		    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
+		    return rc;
+		}		
+		
+	
+	 }
+		
+		
+	for (l_p=0;l_p<MAX_PORT;l_p++){
+	for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,1,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n][l_rp]);if(rc) return rc;
+	 
+			} 
+		}
+		}
+		
+		for(int l_bit=0;l_bit<4;l_bit++){
+		for (l_p=0;l_p<MAX_PORT;l_p++){
+	for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank)
+    {
+	 l_dq=l_bit;
+	 rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		rank=valid_rank[l_rank];
+		rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
+	 for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
+	 rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,1,SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]);if(rc) return rc;
+	 l_dq=l_dq+4;
+			} 
+		}
+	 }
+	}
+	 }
+	 
+	    
+	}
+    
+    return rc;	
+}
+
 /*------------------------------------------------------------------------------
  * Function: find_bound
  * Description  : This function calls the knob_update for each DQ which is used to find bound  that is left/right according to schmoo type
@@ -905,32 +2131,50 @@ fapi::ReturnCode generic_shmoo::knob_update_dqs(const fapi::Target & i_target,bo
  * Parameters: Target:MBA,bound:RIGHT/LEFT,
  * ---------------------------------------------------------------------------*/
 fapi::ReturnCode generic_shmoo::find_bound(const fapi::Target & i_target,bound_t bound){
-    uint8_t l_bit;
+    uint8_t l_bit=0;
     fapi::ReturnCode rc;
     
     
 	uint8_t pass=0;
+	uint8_t l_dram_width=0;
     bool flag=false;
     
-    
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_dram_width); if(rc) return rc;
     
     FAPI_INF("generic_shmoo::find_bound running find_bound function ");
     
         
-        
-                
-                    
-		    //Bit loop
+        //rc=knob_update_dqs_by8_isdimm(i_target,bound,iv_shmoo_type,l_bit,pass,flag); if(rc) return rc;
+              if(iv_DQS_ON == 1){
+			  pass=0;
+			  if(l_dram_width == 4){
+			  if(iv_dmm_type==1)
+    {
+	rc=knob_update_dqs_by4_isdimm(i_target,bound,iv_shmoo_type,l_bit,pass,flag); if(rc) return rc; 
+	}else{
+			  rc=knob_update_dqs_by4(i_target,bound,iv_shmoo_type,l_bit,pass,flag); if(rc) return rc; 
+			  }
+              }else{
+			  if(iv_dmm_type==1)
+    {
+	rc=knob_update_dqs_by8_isdimm(i_target,bound,iv_shmoo_type,l_bit,pass,flag); if(rc) return rc;
+	}else{
+			   rc=knob_update_dqs_by8(i_target,bound,iv_shmoo_type,l_bit,pass,flag); if(rc) return rc;
+			   //rc=knob_update_dqs_by8_isdimm(i_target,bound,iv_shmoo_type,l_bit,pass,flag); if(rc) return rc;
+			   }
+			   }
+				}else{
+			//Bit loop
                     for(l_bit=0;l_bit< MAX_BITS;++l_bit)
                     {
 			// preetham function here
 			
 			pass=0;
-			//FAPI_INF("\n abhijit is inside find bound 0 \n");
+			FAPI_INF("\n abhijit is inside find bound and schmoo type is %d \n",iv_shmoo_type);
 			rc=knob_update(i_target,bound,iv_shmoo_type,l_bit,pass,flag); if(rc) return rc;   
                     
                 }
-            
+            }
         
     return rc;
 }
@@ -1003,11 +2247,11 @@ fapi::ReturnCode generic_shmoo::print_report(const fapi::Target & i_target)
 			{	
 			    l_dq=8*l_byte+4*l_nibble+l_bit;
 
-			    if(iv_shmoo_type==0)
+			    if(iv_shmoo_type==2)
 			    {
 				FAPI_INF("WR_EYE %d\t%d\t%d\t%d\t%d\t%d\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\n ",l_mbapos,l_p,i_rank,l_byte,l_nibble,l_bit,SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.nom_val[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.total_margin[l_dq][l_rp],l_attr_mss_freq_u32,iv_shmoo_param);
 			    }
-			    if(iv_shmoo_type==2)
+			    if(iv_shmoo_type==8)
 			    {
 				FAPI_INF("RD_EYE %d\t%d\t%d\t%d\t%d\t%d\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\n ",l_mbapos,l_p,i_rank,l_byte,l_nibble,l_bit,SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.nom_val[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.total_margin[l_dq][l_rp],l_attr_mss_freq_u32,iv_shmoo_param);
 			    }
@@ -1020,6 +2264,99 @@ fapi::ReturnCode generic_shmoo::print_report(const fapi::Target & i_target)
     
     return rc;
  }
+ 
+ fapi::ReturnCode generic_shmoo::print_report_dqs(const fapi::Target & i_target)
+{
+    fapi::ReturnCode rc;
+    
+    uint8_t l_rnk,l_nibble;
+    //uint8_t l_dq=0;
+    uint8_t l_rp=0;
+	uint8_t l_p=0;
+    uint8_t i_rank=0;
+    uint8_t l_mbapos = 0;
+    uint32_t l_attr_mss_freq_u32 = 0;
+    uint32_t l_attr_mss_volt_u32 = 0;
+    uint8_t l_attr_eff_dimm_type_u8 = 0;
+    uint8_t l_attr_eff_num_drops_per_port_u8 = 0;
+    uint8_t l_attr_eff_dram_width_u8 = 0;
+    fapi::Target l_target_centaur;
+    uint8_t l_SCHMOO_NIBBLES=20;
+	uint8_t l_by8_dqs=0;
+	
+	
+	if(iv_dmm_type==1)
+    {
+	l_SCHMOO_NIBBLES=18;
+	}
+    
+    rc = fapiGetParentChip(i_target, l_target_centaur); if(rc) return rc;
+   
+    rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_u32); if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_attr_mss_volt_u32); if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, l_attr_eff_dimm_type_u8); if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target, l_attr_eff_num_drops_per_port_u8); if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_attr_eff_dram_width_u8); if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbapos);if(rc) return rc;
+   
+   if(l_attr_eff_dram_width_u8 == 8){
+   l_SCHMOO_NIBBLES=10;
+   if(iv_dmm_type==1)
+    {
+	l_SCHMOO_NIBBLES=9;
+	}
+   }
+   
+   
+   
+    FAPI_INF("      freq = %d on %s.", l_attr_mss_freq_u32, l_target_centaur.toEcmdString());
+    FAPI_INF("volt = %d on %s.", l_attr_mss_volt_u32, l_target_centaur.toEcmdString());
+    FAPI_INF("dimm_type = %d on %s.", l_attr_eff_dimm_type_u8, i_target.toEcmdString());
+    if ( l_attr_eff_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM )
+    {
+	FAPI_INF("It is a CDIMM"); 
+    }
+    else
+    {
+	FAPI_INF("It is an ISDIMM"); 
+    }
+    //FAPI_INF("num_drops_per_port = %d on %s.", l_attr_eff_num_drops_per_port_u8, i_target.toEcmdString());
+    //FAPI_INF("num_ranks  = %d on %s.", iv_MAX_RANKS,i_target.toEcmdString());
+    //FAPI_INF("dram_width = %d on %s. \n\n", l_attr_eff_dram_width_u8, i_target.toEcmdString());
+	//fprintf(fp, "Schmoo  POS\tPort\tRank\tDQS\tNominal\t\tSetup_Limit\tHold_Limit\tWrD_Setup(ps)\tWrD_Hold(ps)\tEye_Width(ps)\tBitRate  \n");
+    FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");
+    FAPI_INF("Schmoo  POS\tPort\tRank\tDQS\tNominal\t\tSetup_Limit\tHold_Limit\tWrD_Setup(ps)\tWrD_Hold(ps)\tEye_Width(ps)\tBitRate  ");
+    
+    iv_shmoo_type=4;
+        
+	    
+		for (l_p=0;l_p<MAX_PORT;l_p++){
+		for (l_rnk=0;l_rnk<iv_MAX_RANKS[l_p];++l_rnk)
+	    {			rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+					    i_rank=valid_rank[l_rnk];
+			    rc = mss_getrankpair(i_target,l_p,i_rank,&l_rp,valid_rank);if(rc) return rc;
+		
+		    for(l_nibble=0;l_nibble< l_SCHMOO_NIBBLES;++l_nibble)
+		    {
+				
+			   l_by8_dqs=l_nibble;
+			if(l_attr_eff_dram_width_u8 == 8){
+			l_by8_dqs=l_nibble*2;
+			
+			}
+			  //fprintf(fp,"WR_DQS %d\t%d\t%d\t%d\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\n ",l_mbapos,l_p,i_rank,l_nibble,SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.nom_val[l_by8_dqs][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.rb_regval[l_by8_dqs][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.lb_regval[l_by8_dqs][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.right_margin_val[l_by8_dqs][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.left_margin_val[l_by8_dqs][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.total_margin[l_by8_dqs][l_rp],l_attr_mss_freq_u32);
+				FAPI_INF("WR_DQS %d\t%d\t%d\t%d\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\n ",l_mbapos,l_p,i_rank,l_nibble,SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.nom_val[l_by8_dqs][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.rb_regval[l_by8_dqs][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.lb_regval[l_by8_dqs][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.right_margin_val[l_by8_dqs][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.left_margin_val[l_by8_dqs][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.total_margin[l_by8_dqs][l_rp],l_attr_mss_freq_u32);
+			    
+			    
+			    
+			
+		    }
+		}
+	    }
+	
+    //fclose(fp);
+    return rc;
+ }
 //#endif
 /*------------------------------------------------------------------------------
  * Function: get_margin
@@ -1070,7 +2407,7 @@ fapi::ReturnCode generic_shmoo::get_margin(const fapi::Target & i_target)
 			{
 			    l_dq=8*l_byte+4*l_nibble+l_bit;
 			    //FAPI_INF("  the right bound = %d and nominal = %d",SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.nom_val[l_dq][l_rp]);
-				if(iv_shmoo_type==2)
+				if(iv_shmoo_type==8)
 			    {
 				if(SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq][l_rp] == 0){
 				//FAPI_INF("\n abhijit saurabh is here and dq=%d \n",l_dq);
@@ -1093,6 +2430,145 @@ fapi::ReturnCode generic_shmoo::get_margin(const fapi::Target & i_target)
     return rc;
  }
 
+ fapi::ReturnCode generic_shmoo::get_margin_dqs_by4(const fapi::Target & i_target)
+{
+    fapi::ReturnCode rc;
+    uint8_t l_rnk;
+    uint32_t l_attr_mss_freq_margin_u32 = 0;
+    uint32_t l_freq=0;
+	uint64_t l_cyc = 1000000000000000ULL;
+   // uint8_t l_dq=0;
+	uint8_t l_nibble=0;
+    uint8_t  l_rp=0;
+	uint8_t  l_p=0;
+    uint8_t i_rank=0;
+    uint64_t l_factor=0;
+	uint64_t l_factor_ps=1000000000;
+	uint8_t l_SCHMOO_NIBBLES=20;
+	
+	if(iv_dmm_type==1)
+    {
+	l_SCHMOO_NIBBLES=18;
+	}
+    
+	//FAPI_INF("   the factor is % llu ",l_cyc);
+    
+    fapi::Target l_target_centaur;
+    rc = fapiGetParentChip(i_target, l_target_centaur); if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_margin_u32); if(rc) return rc;
+    l_freq=l_attr_mss_freq_margin_u32/2;
+    l_cyc=l_cyc/l_freq;// converting to zepto to get more accurate data  
+    l_factor=l_cyc/128;
+	//FAPI_INF("l_factor is % llu ",l_factor);
+    
+    
+        	
+	    
+		for (l_p=0;l_p<MAX_PORT;l_p++){
+		//FAPI_INF("\n Abhijit is here before %d \n",l_p);  
+		for (l_rnk=0;l_rnk<iv_MAX_RANKS[l_p];++l_rnk)
+	    {
+		
+		rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		i_rank=valid_rank[l_rnk];
+		rc = mss_getrankpair(i_target,l_p,i_rank,&l_rp,valid_rank);if(rc) return rc; 
+		    
+		    //Nibble loop
+			// FAPI_INF("\n Abhijit is outside  %d \n",l_p); 
+		    for(l_nibble=0;l_nibble<l_SCHMOO_NIBBLES;l_nibble++)
+		    {
+			//FAPI_INF("\n Abhijit 11111 is here after schmoo type=%d  and port=%d \n",iv_shmoo_type,l_p);
+			//FAPI_INF("  the right bound = %d and nominal = %d",SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.nom_val[l_nibble][l_rp]);
+				SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble][l_rp]=SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble][l_rp]-1;
+				SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble][l_rp]=SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble][l_rp]+1;
+				SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble][l_rp]=((SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble][l_rp]-SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.nom_val[l_nibble][l_rp])*l_factor)/l_factor_ps;
+                            SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble][l_rp]= ((SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.nom_val[l_nibble][l_rp]-SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble][l_rp])*l_factor)/l_factor_ps;//((1/uint32_t_freq*1000000)/128);
+			    SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.total_margin[l_nibble][l_rp]=SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble][l_rp]+SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble][l_rp];
+				//FAPI_INF("\n Abhijit is here after %d  and port=%d \n",l_nibble,l_p);
+				//FAPI_INF("\n Abhijit is here after 2 %d \n",l_rnk); 
+            }
+          
+			
+        }
+		 
+	    }
+          
+     
+    return rc;
+ }
+ 
+ fapi::ReturnCode generic_shmoo::get_margin_dqs_by8(const fapi::Target & i_target)
+{
+    fapi::ReturnCode rc;
+    uint8_t l_rnk;
+    uint32_t l_attr_mss_freq_margin_u32 = 0;
+    uint32_t l_freq=0;
+	uint64_t l_cyc = 1000000000000000ULL;
+    //uint8_t l_dq=0;
+	uint8_t l_nibble=0;
+    uint8_t  l_rp=0;
+	uint8_t  l_p=0;
+    uint8_t i_rank=0;
+    uint64_t l_factor=0;
+	uint64_t l_factor_ps=1000000000;
+	uint8_t l_SCHMOO_NIBBLES=20;
+	
+	if(iv_dmm_type==1)
+    {
+	l_SCHMOO_NIBBLES=9;
+	}
+    
+	//FAPI_INF("   the factor is % llu ",l_cyc);
+    
+    fapi::Target l_target_centaur;
+    rc = fapiGetParentChip(i_target, l_target_centaur); if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_margin_u32); if(rc) return rc;
+    l_freq=l_attr_mss_freq_margin_u32/2;
+    l_cyc=l_cyc/l_freq;// converting to zepto to get more accurate data  
+    l_factor=l_cyc/128;
+	//FAPI_INF("l_factor is % llu ",l_factor);
+    
+    
+        	
+	    
+		for (l_p=0;l_p<MAX_PORT;l_p++){
+		//FAPI_INF("\n Abhijit is here before %d \n",l_p);  
+		for (l_rnk=0;l_rnk<iv_MAX_RANKS[l_p];++l_rnk)
+	    {
+		
+		rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc;
+		i_rank=valid_rank[l_rnk];
+		rc = mss_getrankpair(i_target,l_p,i_rank,&l_rp,valid_rank);if(rc) return rc; 
+		    
+		    //Nibble loop
+			 //FAPI_INF("\n Abhijit is outside  %d \n",l_p); 
+		    for(l_nibble=0;l_nibble<l_SCHMOO_NIBBLES;l_nibble++)
+		    {
+			if(iv_dmm_type==0)
+			{
+				if((l_nibble%2)){
+				continue ;
+				}
+			}
+			//FAPI_INF("\n Abhijit 11111 is here after schmoo type=%d  and port=%d \n",iv_shmoo_type,l_p);
+			FAPI_INF("  the port=%d rank=%d nibble=%d right bound = %d and nominal = %d",l_p,i_rank,l_nibble,SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.nom_val[l_nibble][l_rp]);
+				SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble][l_rp]=SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble][l_rp]-1;
+				SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble][l_rp]=SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble][l_rp]+1;
+				SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble][l_rp]=((SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble][l_rp]-SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.nom_val[l_nibble][l_rp])*l_factor)/l_factor_ps;
+                            SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble][l_rp]= ((SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.nom_val[l_nibble][l_rp]-SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble][l_rp])*l_factor)/l_factor_ps;//((1/uint32_t_freq*1000000)/128);
+			    SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.total_margin[l_nibble][l_rp]=SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble][l_rp]+SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble][l_rp];
+				//FAPI_INF("\n Abhijit is here after %d  and port=%d \n",l_nibble,l_p);
+				//FAPI_INF("\n Abhijit is here after 2 %d \n",l_rnk); 
+            }
+          
+			
+        }
+		 
+	    }
+          
+     
+    return rc;
+ }
 /*------------------------------------------------------------------------------
  * Function: get_min_margin
  * Description  : This function is used to get the minimum margin of all the schmoo margins  
@@ -1151,21 +2627,25 @@ fapi::ReturnCode generic_shmoo::get_min_margin(const fapi::Target & i_target,uin
 {
 
 
-	uint8_t __attribute__((unused)) l_socket=0; //SW198827
-
+    
+    
 	//uint32_t rc_num =0;
 	uint8_t l_pattern=0;
 	uint8_t l_testtype=0;
-	//uint8_t l_rank=0;
+	
     fapi::ReturnCode rc;
 	
 	uint64_t l_start =0x0000000000000000ull; 
     uint64_t l_end = 0x0000000000000000ull; 
 	
 	
-	mcbist_test_mem i_mcbtest = CENSHMOO; // bellows: initialize to this type
-	mcbist_data_gen i_mcbpatt = ABLE_FIVE; // bellows: initialize to this data type
-    
+	mcbist_test_mem i_mcbtest= CENSHMOO;
+	mcbist_data_gen i_mcbpatt= ABLE_FIVE;
+	
+	
+	  
+	
+	
     
 	
     
@@ -1258,6 +2738,15 @@ case 26 : i_mcbtest = R_ONLY;break;
 case 27 : i_mcbtest = W_ONLY_RAND;break;
 case 28 : i_mcbtest = R_ONLY_RAND;break;
 case 29 : i_mcbtest = R_ONLY_MULTI;break;
+case 30 : i_mcbtest = SHORT;break;  
+case 31 : i_mcbtest = SIMPLE_RAND_BARI;break; 
+case 32 : i_mcbtest = W_R_INFINITE;break; 
+case 33 : i_mcbtest = W_R_RAND_INFINITE;break; 
+case 34 : i_mcbtest = R_INFINITE1;break; 
+case 35 : i_mcbtest = R_INFINITE_RF;break; 
+case 36 : i_mcbtest = MARCH;break; 
+case 37 : i_mcbtest = SIMPLE_FIX_RF;break;
+case 38 : i_mcbtest = SHMOO_STRESS;break;
 default : FAPI_INF("Wrong Test_type,so using default test_type");
 }
 rc = setup_mcbist(i_target, 0,  i_mcbpatt, i_mcbtest, UNMASK_ALL, 0,iv_pattern,iv_test_type,0,0,l_start,l_end,iv_addr);if(rc) return rc;
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.H
index df73008ee..440b44774 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.H
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_generic_shmoo.H,v 1.13 2013/04/09 12:18:47 lapietra Exp $
+// $Id: mss_generic_shmoo.H,v 1.14 2013/04/25 08:23:52 sasethur Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -31,8 +31,8 @@
 // *! DESCRIPTION          : Memory Subsystem Generic Shmoo -- abstraction for HB
 // *! CONTEXT              : To make all shmoos share a common abstraction layer
 // *!
-// *! OWNER  NAME          : Varkey Varghese          Email: varkey.kv@in.ibm.com
-// *! BACKUP NAME          : Abhijit Saurabh          Email:  abhijit.saurabh@in.ibm.com   
+// *! OWNER  NAME          : Abhijit Saurabh          Email:  abhijit.saurabh@in.ibm.com
+// *! BACKUP NAME          :    
 // *!
 // *!***************************************************************************
 // CHANGE HISTORY:
@@ -111,17 +111,25 @@ class generic_shmoo
         void  init_multi_array(uint32_t (&array)[MAX_DQ][MAX_RPS],uint32_t init_val); //initialize multi dim arrays to known value
 	fapi::ReturnCode init_multi_array_dqs(uint32_t (&array)[MAX_DQ][MAX_RPS],uint32_t init_val);
         fapi::ReturnCode get_all_noms(const fapi::Target & i_target); //! Read in all the Nominal values of the relevant knobs
+		fapi::ReturnCode get_all_noms_dqs(const fapi::Target & i_target); //! Read in all the Nominal values of the relevant knobs
         fapi::ReturnCode find_bound(const fapi::Target & i_target,bound_t); // generic Right bound
         fapi::ReturnCode knob_update(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag); // Increment or decrement the knob
-	fapi::ReturnCode knob_update_dqs(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t rank,uint8_t byte,uint8_t nibble,uint8_t bit,uint8_t pass);
-        fapi::ReturnCode print_report(const fapi::Target & i_target); // Print Shmoo report to file or STDOUT
-        fapi::ReturnCode print_shmoo_parms();
+	fapi::ReturnCode knob_update_dqs_by8(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag); 
+	fapi::ReturnCode knob_update_dqs_by4(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag);
+        fapi::ReturnCode print_report(const fapi::Target & i_target); // Print Shmoo report to  STDOUT
+        fapi::ReturnCode print_report_dqs(const fapi::Target & i_target);
+		fapi::ReturnCode print_shmoo_parms();
 	fapi::ReturnCode get_margin(const fapi::Target & i_target);
+	fapi::ReturnCode get_margin_dqs_by8(const fapi::Target & i_target);
+	fapi::ReturnCode get_margin_dqs_by4(const fapi::Target & i_target);
 	fapi::ReturnCode get_min_margin(const fapi::Target & i_target,uint32_t *o_right_min_margin,uint32_t *o_left_min_margin);
         fapi::ReturnCode do_mcbist_test(const fapi::Target & i_target);
         fapi::ReturnCode  check_error_map(const fapi::Target & i_target,uint8_t port,uint8_t &pass);
         fapi::ReturnCode sanity_check(const fapi::Target & i_target);
 		fapi::ReturnCode schmoo_setup_mcb( const fapi::Target & i_target);
+		fapi::ReturnCode get_error_cnt(const fapi::Target & i_target,uint8_t port,uint8_t rank,uint8_t rank_pair,uint8_t bit,bound_t bound);
+		fapi::ReturnCode knob_update_dqs_by8_isdimm(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag); 
+	fapi::ReturnCode knob_update_dqs_by4_isdimm(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag);
         fapi::ReturnCode run(const fapi::Target & i_target,uint32_t *right_min_margin,uint32_t *left_min_margin,uint8_t i_pattern,uint8_t i_test_type,uint32_t i_shmoo_param);
 };
 #endif
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H
index f21a24f48..b917f4a20 100755
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_mcbist.H,v 1.28 2013/02/14 12:04:04 billyz Exp $
+// $Id: mss_mcbist.H,v 1.30 2013/04/22 13:01:27 lapietra Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -38,6 +38,7 @@
 //-------------------------------------------------------------------------------
 // Version:|Author: | Date:   | Comment:
 // --------|--------|---------|--------------------------------------------------
+//   1.30  |aditya  |04/22/13 |updated testtypes
 //   1.27  |aditya  |02/13/13 |updated testtypes
 //   1.25  |aditya  |02/12/13 |updated testtypes
 //   1.24  |aditya  |01/30/13 |Updated fw comments
@@ -119,7 +120,9 @@ enum mcbist_test_mem
     W_R_RAND_INFINITE,
     R_INFINITE1,
     R_INFINITE_RF,
-    MARCH
+    MARCH,
+    SIMPLE_FIX_RF,
+	SHMOO_STRESS
 };
 
 enum mcbist_data_gen
@@ -262,7 +265,7 @@ enum shmoo_addr_mode
 
 
 
-fapi::ReturnCode addr_gen_func(const fapi::Target & i_target_mba, mcbist_addr_mode i_addr_mode, uint8_t i_attr_eff_schmoo_addr_mode, uint64_t &io_end_address, uint64_t &io_start_address,uint8_t i_rank,uint8_t i_port);
+
 fapi::ReturnCode poll_mcb(const fapi::Target & i_target_mba,bool i_mcb_stop_on_fail,uint8_t *o_mcb_status,uint64_t i_time);
 fapi::ReturnCode mcb_error_map(const fapi::Target & i_target_mba,uint8_t  o_error_map[][8][10][2],uint8_t i_port,uint8_t i_rank);
 fapi::ReturnCode mcb_write_test_mem(const fapi::Target & i_target_mba,const uint64_t i_reg_addr,mcbist_oper_type i_operation_type,uint8_t i_cfg_test_123_cmd,mcbist_addr_mode i_addr_mode,mcbist_data_mode i_data_mode,uint8_t i_done,mcbist_data_select_mode i_data_select_mode, mcbist_add_select_mode i_addr_select_mode,uint8_t i_testnumber);
@@ -272,7 +275,7 @@ fapi::ReturnCode cfg_mcb_dgen(const fapi::Target & i_target_mba,mcbist_data_gen
 fapi::ReturnCode cfg_byte_mask(const fapi::Target & i_target_mba,uint8_t i_rank,uint8_t i_port);
 fapi::ReturnCode start_mcb(const fapi::Target & i_target_mba);
 fapi::ReturnCode setup_mcbist(const fapi::Target & i_target_mba, uint8_t i_port,mcbist_data_gen i_mcbpatt,mcbist_test_mem i_mcbtest,mcbist_byte_mask i_mcbbytemask,uint8_t i_mcbrotate,uint8_t i_pattern,uint8_t i_test_type,uint8_t i_rank,uint8_t i_bit32,uint64_t i_start,uint64_t i_end,uint8_t new_address_map);
-fapi::ReturnCode cfg_mcb_addr(const fapi::Target & i_target_mba,uint8_t i_rank,uint8_t i_port,uint64_t i_start,uint64_t i_end);
+
 fapi::ReturnCode  mcb_error_map_print(const fapi::Target & i_target_mba,uint8_t i_port,uint8_t i_rank,ecmdDataBufferBase & i_mcb_fail_320);
 }
 #endif
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_shmoo_common.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_shmoo_common.H
index d6438580e..f2a387a67 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_shmoo_common.H
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_shmoo_common.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_shmoo_common.H,v 1.12 2013/03/20 17:18:38 sasethur Exp $
+// $Id: mss_shmoo_common.H,v 1.13 2013/04/25 08:23:54 sasethur Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM 
@@ -52,7 +52,7 @@ enum shmoo_type_t { TEST_NONE=0,MCBIST=1,WR_EYE=2, WRT_DQS=4,RD_EYE=8,RD_GATE=16
 enum shmoo_algorithm_t { SEQ_LIN}; // Parallel bytes/ranks here .. no parallel targets in HB
 const uint8_t NINE = 9;
 const uint8_t MAX_RPS=4;// 4 Rank pairs in this design
-const uint8_t MAX_SHMOO=4;
+const uint8_t MAX_SHMOO=16;
 const uint8_t MAX_RANK_DIMM=4;
 const uint8_t MAX_NIBBLES=2;
 const uint8_t MAX_BITS=4;
@@ -87,5 +87,7 @@ struct shmoo_knob_data_t{
     uint32_t nom_val[MAX_DQ][MAX_RPS]; // nominal value of this instance of the knob
     uint32_t right_margin_val[MAX_DQ][MAX_RPS];
     uint32_t left_margin_val[MAX_DQ][MAX_RPS];
+	uint32_t right_err_cnt[MAX_DQ][MAX_RPS];
+	uint32_t left_err_cnt[MAX_DQ][MAX_RPS];
 };
 #endif
diff --git a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile
index e1453741d..4fe88ebe9 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile
@@ -1,8 +1,9 @@
-#-- $Id: p8.abus.custom.scom.initfile,v 1.1 2013/02/11 04:26:41 jmcgill Exp $
+#-- $Id: p8.abus.custom.scom.initfile,v 1.2 2013/04/18 22:30:04 jgrell Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--     1.2 |jgrell  |04/18/13|Added EC controled Recal enables
 #--     1.1 |thomsen |01/29/13|Created initial version
 #-- --------|--------|--------|--------------------------------------------------
 #--------------------------------------------------------------------------------
@@ -288,6 +289,19 @@ scom 0x800.0b(tx_mode_pg)(tx_grp0)(lane_na).0x(abus_gcr_addr) {
     tx_msbswap,               (ATTR_EI_BUS_TX_MSBSWAP & 0x01);
 }
 
+#--**************************************************************************************************************
+#----------------------------------------------------------------------------------------------------------------
+# Recal 
+#----------------------------------------------------------------------------------------------------------------
+#--**************************************************************************************************************
+# HW235842
+
+scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp0)(lane_na).0x(abus_gcr_addr) {
+bits,                         	scom_data, 	expr;
+#rx_rc_enable_dfe_h1_cal,      	0b0,       	ATTR_CHIP_EC_FEATURE_RECAL_DFE_ENABLE==0; # Set to 0b0 in figtree.
+rx_rc_enable_ddc,		0b0,		ATTR_CHIP_EC_FEATURE_RECAL_DDC_ENABLE==0;
+rx_rc_enable_ctle_cal,		0b0,		ATTR_CHIP_EC_FEATURE_RECAL_CTLE_ENABLE==0;
+}
 
 ############################################################################################
 # END OF FILE
diff --git a/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile
index d83326129..dcb8a0cf4 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile
@@ -1,21 +1,21 @@
-#-- $Id: p8.abus.scom.initfile,v 1.9 2013/03/15 21:16:40 thomsen Exp $ 
+#-- $Id: p8.abus.scom.initfile,v 1.10 2013/04/18 22:28:40 jgrell Exp $ 
 
 
 ####################################################################
 ##  
-##  ********** Auto-genrated by fig2scominit.pl  *********** HAND EDITED BY PETE THOMSEN on 3/7/13 to add the GCR Buffer Parity Mask workaround until the auto-gen'd/custom Abus initfile/procedure changes can be released
+##  Auto-genrated by fig2scominit.pl
 ##      Based on SETUP_ID_MODE A_BUS_TR_HW
 ##      from ../../logic/mesa_sim/fusion/run/IODUV_ABUS_WRAP.IODUV_ABUS_WRAP.figdb
 ##
-##   Created on Thu Jan 24 14:48:09 EST 2013, by derrin
+##   Created on Mon Apr 15 15:04:01 CDT 2013, by jgrell
 ####################################################################
 
 ## -- CHANGE HISTORY:
  ## --------------------------------------------------------------------------------
  ## -- VersionID: |Author:  | Date:  | Comment:
  ## -- -----------|---------|--------|-------------------------------------------------
-#--     1.9 |jgrell  |03/14/13|Added temporary masking of the GCR Buffer Parity Checkers in the GCR Master until the source of the error can be found. This ungates the lab.
-#--     1.8 |thomsen |03/07/13|Temporarily mask the GCR Buffer Parity Checker until the source of the error can be found. This ungates the lab.
+ ## -- jgr13041800| jgr     |04-18-13| Added missing entries from rel 0128
+ ## -- mbs13021100| mbs     |02-11-13| Changed A bus id's to 1,2,3 from 0,1,2 (HW239245)
  ## -- mbs13011802| mbs     |01-18-13| Added rx_fence to run_mode dial (HW236326)
  ## -- mbs12121100| mbs     |12-11-12| Added rx_prot_speed_slct and rx_c4_sel
  ## -- smr12112700| SMR     |11-27-12| Added rx_dyn_recal_overall_timeout_sel init to 0b001
@@ -41,599 +41,1125 @@ SyntaxVersion = 1
 ####################################################################
 include edi.io.define
 
-define def_IS_HW  = SYS.ATTR_IS_SIMULATION == 0;
-define def_IS_VBU = SYS.ATTR_IS_SIMULATION == 1;
+                    define def_IS_HW  = SYS.ATTR_IS_SIMULATION == 0;
+                    define def_IS_VBU = SYS.ATTR_IS_SIMULATION == 1;
+                
+
 
 define def_bus_id0 = (ATTR_CHIP_UNIT_POS == 0);
 define def_bus_id1 = (ATTR_CHIP_UNIT_POS == 1);
 define def_bus_id2 = (ATTR_CHIP_UNIT_POS == 2);
 
-define def_is_master = (TGT1.ATTR_FABRIC_NODE_ID < TGT2.ATTR_FABRIC_NODE_ID);
-define def_is_slave  = (TGT1.ATTR_FABRIC_NODE_ID > TGT2.ATTR_FABRIC_NODE_ID);
 
+define prim_id = (TGT1.ATTR_FABRIC_NODE_ID*100) + TGT1.ATTR_POS;
+define conn_id = (TGT3.ATTR_FABRIC_NODE_ID*100) + TGT3.ATTR_POS;
+
+define def_is_master = (prim_id < conn_id);
+define def_is_slave  = (prim_id > conn_id);
 
 
-#-------------------------------------------------------------------------------------
-#     __  ___           __               __  ___          __
-#    /  |/  /___ ______/ /____  _____   /  |/  /___  ____/ /__
-#   / /|_/ / __ `/ ___/ __/ _ \/ ___/  / /|_/ / __ \/ __  / _ \
-#  / /  / / /_/ (__  ) /_/  __/ /     / /  / / /_/ / /_/ /  __/
-# /_/  /_/\__,_/____/\__/\___/_/     /_/  /_/\____/\__,_/\___/
-#-------------------------------------------------------------------------------------
-#--*********************************************************************************************
-#-- rx_mode_pg: rx_master_mode
-#--*********************************************************************************************
-scom 0x800.0b(rx_mode_pg)(rx_grp0)(lane_na).0x(abus_gcr_addr){
-        bits,                               scom_data,   expr;
-        rx_master_mode,                     0b1,         (def_is_master);
-        rx_master_mode,                     0b0,         (def_is_slave);
-}
 
+#RX0.RXCTL.RX_CTL_REGS.RX_BER_CHK_PG
+scom 0x800AF00008010C3F { 
+	bits, scom_data, expr;
+     rx_max_ber_check_count,  0b00000011,   def_IS_HW && def_bus_id0;
+	rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id1;
+	rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id1;
+	rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id2;
+	rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id2;
+     rx_max_ber_check_count,  0b00000000,  def_IS_VBU && def_bus_id0;
+	rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id1;
+	rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id1;
+	rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id2;
+	rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id2;
+}
 
 #RX0.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP
-scom 0x800B780008010C3F {
+scom 0x800B780008010C3F { 
 	bits, scom_data, expr;
-     rx_amin_cfg,  0b010,   def_IS_HW;
-     rx_amin_cfg,  0b000,  def_IS_VBU;
-     rx_anap_cfg,  0b10,   def_IS_HW;
-     rx_anap_cfg,  0b00,  def_IS_VBU;
-     rx_h1ap_cfg,  0b011,   def_IS_HW;
-     rx_h1ap_cfg,  0b000,  def_IS_VBU;
-     rx_peak_cfg,  0b10,   def_IS_HW;
-     rx_peak_cfg,  0b00,  def_IS_VBU;
+     rx_amin_cfg,  0b010,   def_IS_HW && def_bus_id0;
+	rx_amin_cfg, 0b010, def_IS_HW && def_bus_id1;
+	rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id1;
+	rx_amin_cfg, 0b010, def_IS_HW && def_bus_id2;
+	rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id2;
+     rx_amin_cfg,  0b000,  def_IS_VBU && def_bus_id0;
+	rx_amin_cfg, 0b010, def_IS_HW && def_bus_id1;
+	rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id1;
+	rx_amin_cfg, 0b010, def_IS_HW && def_bus_id2;
+	rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id2;
+     rx_anap_cfg,  0b10,   def_IS_HW && def_bus_id0;
+	rx_anap_cfg, 0b10, def_IS_HW && def_bus_id1;
+	rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id1;
+	rx_anap_cfg, 0b10, def_IS_HW && def_bus_id2;
+	rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id2;
+     rx_anap_cfg,  0b00,  def_IS_VBU && def_bus_id0;
+	rx_anap_cfg, 0b10, def_IS_HW && def_bus_id1;
+	rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id1;
+	rx_anap_cfg, 0b10, def_IS_HW && def_bus_id2;
+	rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id2;
+     rx_h1ap_cfg,  0b011,   def_IS_HW && def_bus_id0;
+	rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id1;
+	rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id1;
+	rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id2;
+	rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id2;
+     rx_h1ap_cfg,  0b000,  def_IS_VBU && def_bus_id0;
+	rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id1;
+	rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id1;
+	rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id2;
+	rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id2;
+     rx_peak_cfg,  0b10,   def_IS_HW && def_bus_id0;
+	rx_peak_cfg, 0b10, def_IS_HW && def_bus_id1;
+	rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id1;
+	rx_peak_cfg, 0b10, def_IS_HW && def_bus_id2;
+	rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id2;
+     rx_peak_cfg,  0b00,  def_IS_VBU && def_bus_id0;
+	rx_peak_cfg, 0b10, def_IS_HW && def_bus_id1;
+	rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id1;
+	rx_peak_cfg, 0b10, def_IS_HW && def_bus_id2;
+	rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id2;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_DFE_TIMERS_PP
-scom 0x800B800008010C3F {
+scom 0x800B800008010C3F { 
 	bits, scom_data, expr;
-     rx_init_tmr_cfg,  0b100,   def_IS_HW;
-     rx_init_tmr_cfg,  0b000,  def_IS_VBU;
+     rx_init_tmr_cfg,  0b100,   def_IS_HW && def_bus_id0;
+	rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id1;
+	rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id1;
+	rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id2;
+	rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id2;
+     rx_init_tmr_cfg,  0b000,  def_IS_VBU && def_bus_id0;
+	rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id1;
+	rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id1;
+	rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id2;
+	rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id2;
+     rx_prot_cfg,  0b10,   def_IS_HW && def_bus_id0;
+	rx_prot_cfg, 0b10, def_IS_HW && def_bus_id1;
+	rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id1;
+	rx_prot_cfg, 0b10, def_IS_HW && def_bus_id2;
+	rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id2;
+     rx_prot_cfg,  0b00,  def_IS_VBU && def_bus_id0;
+	rx_prot_cfg, 0b10, def_IS_HW && def_bus_id1;
+	rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id1;
+	rx_prot_cfg, 0b10, def_IS_HW && def_bus_id2;
+	rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id2;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG
-scom 0x800A180008010C3F {
-	bits, scom_data;
-	rx_dyn_recal_overall_timeout_sel, 0b001;
+scom 0x800A180008010C3F { 
+	bits, scom_data, expr;
+	rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id0;
+	rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id1;
+	rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id2;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG
-scom 0x8009D80008010C3F {
-	bits, scom_data;
-	rx_dyn_rpr_bad_lane_max, 0b0001111;
-	rx_dyn_rpr_enc_bad_data_lane_width, 0b101;
-	rx_dyn_rpr_err_cntr1_duration, 0b1001;
+scom 0x8009D80008010C3F { 
+	bits, scom_data, expr;
+	rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id0;
+	rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id1;
+	rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id2;
+	rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id0;
+	rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id1;
+	rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id2;
+	rx_dyn_rpr_err_cntr1_duration, 0b1001, def_bus_id0;
+	rx_dyn_rpr_err_cntr1_duration, 0b1001, def_bus_id1;
+	rx_dyn_rpr_err_cntr1_duration, 0b1001, def_bus_id2;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG
-scom 0x800AE00008010C3F {
-	bits, scom_data;
-	rx_dyn_rpr_bad_bus_max, 0b0011111;
-	rx_dyn_rpr_err_cntr2_duration, 0b0110;
+scom 0x800AE00008010C3F { 
+	bits, scom_data, expr;
+	rx_dyn_rpr_bad_bus_max, 0b0011111, def_bus_id0;
+	rx_dyn_rpr_bad_bus_max, 0b0011111, def_bus_id1;
+	rx_dyn_rpr_bad_bus_max, 0b0011111, def_bus_id2;
+	rx_dyn_rpr_err_cntr2_duration, 0b0110, def_bus_id0;
+	rx_dyn_rpr_err_cntr2_duration, 0b0110, def_bus_id1;
+	rx_dyn_rpr_err_cntr2_duration, 0b0110, def_bus_id2;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_EO_CONVERGENCE_PG
+scom 0x800A800008010C3F { 
+	bits, scom_data, expr;
+     rx_eo_converged_end_count,  0b0111,   def_IS_HW && def_bus_id0;
+	rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id1;
+	rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id1;
+	rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id2;
+	rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id2;
+     rx_eo_converged_end_count,  0b0011,  def_IS_VBU && def_bus_id0;
+	rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id1;
+	rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id1;
+	rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id2;
+	rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id2;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG
-scom 0x800A380008010C3F {
-	bits, scom_data, expr;
-     rx_eo_enable_ber_test,  0b1,   def_IS_HW;
-     rx_eo_enable_ber_test,  0b0,  def_IS_VBU;
-     rx_eo_enable_ctle_cal,  0b1,   def_IS_HW;
-     rx_eo_enable_ctle_cal,  0b0,  def_IS_VBU;
-     rx_eo_enable_ddc,  0b1,   def_IS_HW;
-     rx_eo_enable_ddc,  0b0,  def_IS_VBU;
-	rx_eo_enable_dfe_h1_cal, 0b0, any;
-	rx_eo_enable_final_l2u_adj, 0b1, any;
-     rx_eo_enable_h1ap_tweak,  0b1,   def_IS_HW;
-     rx_eo_enable_h1ap_tweak,  0b0,  def_IS_VBU;
-     rx_eo_enable_latch_offset_cal,  0b1,   def_IS_HW;
-     rx_eo_enable_latch_offset_cal,  0b0,  def_IS_VBU;
-     rx_eo_enable_result_check,  0b1,   def_IS_HW;
-     rx_eo_enable_result_check,  0b0,  def_IS_VBU;
-     rx_eo_enable_vga_cal,  0b1,   def_IS_HW;
-     rx_eo_enable_vga_cal,  0b0,  def_IS_VBU;
+scom 0x800A380008010C3F { 
+	bits, scom_data, expr;
+     rx_eo_enable_ber_test,  0b1,   def_IS_HW && def_bus_id0;
+	rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_ber_test,  0b0,  def_IS_VBU && def_bus_id0;
+	rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_ctle_cal,  0b1,   def_IS_HW && def_bus_id0;
+	rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_ctle_cal,  0b0,  def_IS_VBU && def_bus_id0;
+	rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_ddc,  0b1,   def_IS_HW && def_bus_id0;
+	rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_ddc,  0b0,  def_IS_VBU && def_bus_id0;
+	rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id2;
+	rx_eo_enable_dfe_h1_cal, 0b0, def_bus_id0;
+	rx_eo_enable_dfe_h1_cal, 0b0, def_bus_id1;
+	rx_eo_enable_dfe_h1_cal, 0b0, def_bus_id2;
+	rx_eo_enable_final_l2u_adj, 0b1, def_bus_id0;
+	rx_eo_enable_final_l2u_adj, 0b1, def_bus_id1;
+	rx_eo_enable_final_l2u_adj, 0b1, def_bus_id2;
+     rx_eo_enable_h1ap_tweak,  0b1,   def_IS_HW && def_bus_id0;
+	rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_h1ap_tweak,  0b0,  def_IS_VBU && def_bus_id0;
+	rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_latch_offset_cal,  0b1,   def_IS_HW && def_bus_id0;
+	rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_latch_offset_cal,  0b0,  def_IS_VBU && def_bus_id0;
+	rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_result_check,  0b1,   def_IS_HW && def_bus_id0;
+	rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_result_check,  0b0,  def_IS_VBU && def_bus_id0;
+	rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_vga_cal,  0b1,   def_IS_HW && def_bus_id0;
+	rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_vga_cal,  0b0,  def_IS_VBU && def_bus_id0;
+	rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_FENCE_PG
-scom 0x8009A80008010C3F {
-	bits, scom_data;
-	rx_fence, 0b1;
+scom 0x8009A80008010C3F { 
+	bits, scom_data, expr;
+	rx_fence, 0b1, def_bus_id0;
+	rx_fence, 0b1, def_bus_id1;
+	rx_fence, 0b1, def_bus_id2;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_ID1_PG
-scom 0x8008500008010C3F {
+scom 0x8008500008010C3F { 
 	bits, scom_data, expr;
-	rx_bus_id, 0b000010, def_bus_id2;
-	rx_bus_id, 0b000001, def_bus_id1;
-	rx_bus_id, 0b000000, def_bus_id0;
-	rx_group_id, 0b000000, any;
+	rx_bus_id, 0b000001, def_bus_id0;
+	rx_bus_id, 0b000010, def_bus_id1;
+	rx_bus_id, 0b000011, def_bus_id2;
+	rx_group_id, 0b000000, def_bus_id0;
+	rx_group_id, 0b000000, def_bus_id1;
+	rx_group_id, 0b000000, def_bus_id2;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_ID2_PG
-scom 0x8008580008010C3F {
-	bits, scom_data;
-	rx_last_group_id, 0b000000;
+scom 0x8008580008010C3F { 
+	bits, scom_data, expr;
+	rx_last_group_id, 0b000000, def_bus_id0;
+	rx_last_group_id, 0b000000, def_bus_id1;
+	rx_last_group_id, 0b000000, def_bus_id2;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_ID3_PG
-scom 0x8008600008010C3F {
-	bits, scom_data;
-	rx_end_lane_id, 0b0010110;
-	rx_start_lane_id, 0b0000000;
+scom 0x8008600008010C3F { 
+	bits, scom_data, expr;
+	rx_end_lane_id, 0b0010110, def_bus_id0;
+	rx_end_lane_id, 0b0010110, def_bus_id1;
+	rx_end_lane_id, 0b0010110, def_bus_id2;
+	rx_start_lane_id, 0b0000000, def_bus_id0;
+	rx_start_lane_id, 0b0000000, def_bus_id1;
+	rx_start_lane_id, 0b0000000, def_bus_id2;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG
-scom 0x8009280008010C3F {
-	bits, scom_data;
-	rx_lane_disabled_vec_0_15, 0b0000000000000000;
+scom 0x8009280008010C3F { 
+	bits, scom_data, expr;
+	rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id0;
+	rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id1;
+	rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id2;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG
-scom 0x8009300008010C3F {
-	bits, scom_data;
-	rx_lane_disabled_vec_16_31, 0b0000000111111111;
+scom 0x8009300008010C3F { 
+	bits, scom_data, expr;
+	rx_lane_disabled_vec_16_31, 0b0000000111111111, def_bus_id0;
+	rx_lane_disabled_vec_16_31, 0b0000000111111111, def_bus_id1;
+	rx_lane_disabled_vec_16_31, 0b0000000111111111, def_bus_id2;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_MISC_ANALOG_PG
-scom 0x8009C00008010C3F {
+scom 0x8009C00008010C3F { 
+	bits, scom_data, expr;
+     rx_c4_sel,  0b00,   def_IS_HW && def_bus_id0;
+	rx_c4_sel, 0b00, def_IS_HW && def_bus_id1;
+	rx_c4_sel, 0b11, def_IS_VBU && def_bus_id1;
+	rx_c4_sel, 0b00, def_IS_HW && def_bus_id2;
+	rx_c4_sel, 0b11, def_IS_VBU && def_bus_id2;
+     rx_c4_sel,  0b11,  def_IS_VBU && def_bus_id0;
+	rx_c4_sel, 0b00, def_IS_HW && def_bus_id1;
+	rx_c4_sel, 0b11, def_IS_VBU && def_bus_id1;
+	rx_c4_sel, 0b00, def_IS_HW && def_bus_id2;
+	rx_c4_sel, 0b11, def_IS_VBU && def_bus_id2;
+     rx_prot_speed_slct,  0b0,   def_IS_HW && def_bus_id0;
+	rx_prot_speed_slct, 0b0, def_IS_HW && def_bus_id1;
+	rx_prot_speed_slct, 0b1, def_IS_VBU && def_bus_id1;
+	rx_prot_speed_slct, 0b0, def_IS_HW && def_bus_id2;
+	rx_prot_speed_slct, 0b1, def_IS_VBU && def_bus_id2;
+     rx_prot_speed_slct,  0b1,  def_IS_VBU && def_bus_id0;
+	rx_prot_speed_slct, 0b0, def_IS_HW && def_bus_id1;
+	rx_prot_speed_slct, 0b1, def_IS_VBU && def_bus_id1;
+	rx_prot_speed_slct, 0b0, def_IS_HW && def_bus_id2;
+	rx_prot_speed_slct, 0b1, def_IS_VBU && def_bus_id2;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_MODE1_PP
+scom 0x800B080008010C3F { 
 	bits, scom_data, expr;
-     rx_c4_sel,  0b00,   def_IS_HW;
-     rx_c4_sel,  0b11,  def_IS_VBU;
-     rx_prot_speed_slct,  0b0,   def_IS_HW;
-     rx_prot_speed_slct,  0b1,  def_IS_VBU;
+     rx_bit_lock_timeout_sel,  0b110,   def_IS_HW && def_bus_id0;
+	rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id1;
+	rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id1;
+	rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id2;
+	rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id2;
+     rx_bit_lock_timeout_sel,  0b101,  def_IS_VBU && def_bus_id0;
+	rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id1;
+	rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id1;
+	rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id2;
+	rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id2;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_MODE_PG
+scom 0x8008180008010C3F { 
+	bits, scom_data, expr;
+	rx_master_mode, 0b1, def_is_master;
+	rx_master_mode, 0b1, def_is_master;
+	rx_master_mode, 0b1, def_is_master;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG
-scom 0x800AB80008010C3F {
-	bits, scom_data, expr;
-     rx_rc_enable_ber_test,  0b1,   def_IS_HW;
-     rx_rc_enable_ber_test,  0b0,  def_IS_VBU;
-     rx_rc_enable_ctle_cal,  0b1,   def_IS_HW;
-     rx_rc_enable_ctle_cal,  0b0,  def_IS_VBU;
-     rx_rc_enable_ddc,  0b1,   def_IS_HW;
-     rx_rc_enable_ddc,  0b0,  def_IS_VBU;
-	rx_rc_enable_dfe_h1_cal, 0b0, any;
-     rx_rc_enable_h1ap_tweak,  0b1,   def_IS_HW;
-     rx_rc_enable_h1ap_tweak,  0b0,  def_IS_VBU;
-     rx_rc_enable_latch_offset_cal,  0b1,   def_IS_HW;
-     rx_rc_enable_latch_offset_cal,  0b0,  def_IS_VBU;
-     rx_rc_enable_result_check,  0b1,   def_IS_HW;
-     rx_rc_enable_result_check,  0b0,  def_IS_VBU;
-     rx_rc_enable_vga_cal,  0b1,   def_IS_HW;
-     rx_rc_enable_vga_cal,  0b0,  def_IS_VBU;
+scom 0x800AB80008010C3F { 
+	bits, scom_data, expr;
+     rx_rc_enable_ber_test,  0b1,   def_IS_HW && def_bus_id0;
+	rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_ber_test,  0b0,  def_IS_VBU && def_bus_id0;
+	rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_ctle_cal,  0b1,   def_IS_HW && def_bus_id0;
+	rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_ctle_cal,  0b0,  def_IS_VBU && def_bus_id0;
+	rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_ddc,  0b1,   def_IS_HW && def_bus_id0;
+	rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_ddc,  0b0,  def_IS_VBU && def_bus_id0;
+	rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id2;
+	rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id0;
+	rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id1;
+	rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id2;
+     rx_rc_enable_h1ap_tweak,  0b1,   def_IS_HW && def_bus_id0;
+	rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_h1ap_tweak,  0b0,  def_IS_VBU && def_bus_id0;
+	rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_latch_offset_cal,  0b1,   def_IS_HW && def_bus_id0;
+	rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_latch_offset_cal,  0b0,  def_IS_VBU && def_bus_id0;
+	rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_result_check,  0b1,   def_IS_HW && def_bus_id0;
+	rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_result_check,  0b0,  def_IS_VBU && def_bus_id0;
+	rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_vga_cal,  0b1,   def_IS_HW && def_bus_id0;
+	rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_vga_cal,  0b0,  def_IS_VBU && def_bus_id0;
+	rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP
-scom 0x800B980008010C3F {
+scom 0x800B980008010C3F { 
 	bits, scom_data, expr;
-     rx_recal_timeout_sel_g,  0b0111,   def_IS_HW;
-     rx_recal_timeout_sel_g,  0b0110,  def_IS_VBU;
-     rx_recal_timeout_sel_h,  0b0110,   def_IS_HW;
-     rx_recal_timeout_sel_h,  0b1000,  def_IS_VBU;
+     rx_recal_timeout_sel_g,  0b0111,   def_IS_HW && def_bus_id0;
+	rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1;
+	rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id1;
+	rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2;
+	rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id2;
+     rx_recal_timeout_sel_g,  0b0110,  def_IS_VBU && def_bus_id0;
+	rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1;
+	rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id1;
+	rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2;
+	rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id2;
+     rx_recal_timeout_sel_h,  0b0110,   def_IS_HW && def_bus_id0;
+	rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id1;
+	rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id2;
+	rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2;
+     rx_recal_timeout_sel_h,  0b1000,  def_IS_VBU && def_bus_id0;
+	rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id1;
+	rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id2;
+	rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_RECAL_TO3_PP
-scom 0x800BA00008010C3F {
+scom 0x800BA00008010C3F { 
 	bits, scom_data, expr;
-     rx_recal_timeout_sel_i,  0b0111,   def_IS_HW;
-     rx_recal_timeout_sel_i,  0b1000,  def_IS_VBU;
-     rx_recal_timeout_sel_l,  0b0100,   def_IS_HW;
-     rx_recal_timeout_sel_l,  0b0110,  def_IS_VBU;
+     rx_recal_timeout_sel_i,  0b0111,   def_IS_HW && def_bus_id0;
+	rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id1;
+	rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id2;
+	rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2;
+     rx_recal_timeout_sel_i,  0b1000,  def_IS_VBU && def_bus_id0;
+	rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id1;
+	rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id2;
+	rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2;
+     rx_recal_timeout_sel_l,  0b0100,   def_IS_HW && def_bus_id0;
+	rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id1;
+	rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id1;
+	rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id2;
+	rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id2;
+     rx_recal_timeout_sel_l,  0b0110,  def_IS_VBU && def_bus_id0;
+	rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id1;
+	rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id1;
+	rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id2;
+	rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id2;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP
-scom 0x800B600008010C3F {
+scom 0x800B600008010C3F { 
 	bits, scom_data, expr;
-     rx_servo_timeout_sel_d,  0b1010,   def_IS_HW;
-     rx_servo_timeout_sel_d,  0b1000,  def_IS_VBU;
+     rx_servo_timeout_sel_d,  0b1001,   def_IS_HW && def_bus_id0;
+	rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_d,  0b1000,  def_IS_VBU && def_bus_id0;
+	rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id2;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP
-scom 0x800B680008010C3F {
+scom 0x800B680008010C3F { 
 	bits, scom_data, expr;
-     rx_servo_timeout_sel_f,  0b0001,   def_IS_HW;
-     rx_servo_timeout_sel_f,  0b0110,  def_IS_VBU;
-     rx_servo_timeout_sel_g,  0b0111,   def_IS_HW;
-     rx_servo_timeout_sel_g,  0b0100,  def_IS_VBU;
+     rx_servo_timeout_sel_f,  0b0001,   def_IS_HW && def_bus_id0;
+	rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_f,  0b0110,  def_IS_VBU && def_bus_id0;
+	rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_g,  0b0111,   def_IS_HW && def_bus_id0;
+	rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_g,  0b0100,  def_IS_VBU && def_bus_id0;
+	rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_h,  0b1110,   def_IS_HW && def_bus_id0;
+	rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_h,  0b1000,  def_IS_VBU && def_bus_id0;
+	rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO3_PP
-scom 0x800B700008010C3F {
+scom 0x800B700008010C3F { 
 	bits, scom_data, expr;
-     rx_servo_timeout_sel_i,  0b0111,   def_IS_HW;
-     rx_servo_timeout_sel_i,  0b1000,  def_IS_VBU;
-     rx_servo_timeout_sel_k,  0b0111,   def_IS_HW;
-     rx_servo_timeout_sel_k,  0b1000,  def_IS_VBU;
+     rx_servo_timeout_sel_i,  0b1011,   def_IS_HW && def_bus_id0;
+	rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_i,  0b1000,  def_IS_VBU && def_bus_id0;
+	rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_j,  0b1100,   def_IS_HW && def_bus_id0;
+	rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_j,  0b1000,  def_IS_VBU && def_bus_id0;
+	rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_k,  0b1101,   def_IS_HW && def_bus_id0;
+	rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_k,  0b1000,  def_IS_VBU && def_bus_id0;
+	rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL1_PG
+scom 0x8009100008010C3F { 
+	bits, scom_data, expr;
+     rx_eo_amp_timeout_sel,  0b111,   def_IS_HW && def_bus_id0;
+	rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id1;
+	rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id2;
+     rx_eo_amp_timeout_sel,  0b110,  def_IS_VBU && def_bus_id0;
+	rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id1;
+	rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id2;
+     rx_eo_ctle_timeout_sel,  0b111,   def_IS_HW && def_bus_id0;
+	rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id1;
+	rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id2;
+     rx_eo_ctle_timeout_sel,  0b110,  def_IS_VBU && def_bus_id0;
+	rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id1;
+	rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id2;
+     rx_eo_ddc_timeout_sel,  0b111,   def_IS_HW && def_bus_id0;
+	rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id1;
+	rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id2;
+     rx_eo_ddc_timeout_sel,  0b110,  def_IS_VBU && def_bus_id0;
+	rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id1;
+	rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id2;
+     rx_eo_h1ap_timeout_sel,  0b111,   def_IS_HW && def_bus_id0;
+	rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id1;
+	rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id2;
+     rx_eo_h1ap_timeout_sel,  0b110,  def_IS_VBU && def_bus_id0;
+	rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id1;
+	rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id2;
+     rx_eo_offset_timeout_sel,  0b111,   def_IS_HW && def_bus_id0;
+	rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id1;
+	rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id2;
+     rx_eo_offset_timeout_sel,  0b110,  def_IS_VBU && def_bus_id0;
+	rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id1;
+	rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id2;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG
-scom 0x8008980008010C3F {
-	bits, scom_data;
-	rx_sls_timeout_sel, 0b001;
+scom 0x8008980008010C3F { 
+	bits, scom_data, expr;
+     rx_ds_bl_timeout_sel,  0b101,   def_IS_HW && def_bus_id0;
+	rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id1;
+	rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id1;
+	rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id2;
+	rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id2;
+     rx_ds_bl_timeout_sel,  0b001,  def_IS_VBU && def_bus_id0;
+	rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id1;
+	rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id1;
+	rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id2;
+	rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id2;
+     rx_ds_timeout_sel,  0b110,   def_IS_HW && def_bus_id0;
+	rx_ds_timeout_sel, 0b110, def_IS_HW && def_bus_id1;
+	rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id1;
+	rx_ds_timeout_sel, 0b110, def_IS_HW && def_bus_id2;
+	rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id2;
+     rx_ds_timeout_sel,  0b010,  def_IS_VBU && def_bus_id0;
+	rx_ds_timeout_sel, 0b110, def_IS_HW && def_bus_id1;
+	rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id1;
+	rx_ds_timeout_sel, 0b110, def_IS_HW && def_bus_id2;
+	rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id2;
+	rx_sls_timeout_sel, 0b001, def_bus_id0;
+	rx_sls_timeout_sel, 0b001, def_bus_id1;
+	rx_sls_timeout_sel, 0b001, def_bus_id2;
+     rx_wt_timeout_sel,  0b111,   def_IS_HW && def_bus_id0;
+	rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id1;
+	rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id2;
+     rx_wt_timeout_sel,  0b011,  def_IS_VBU && def_bus_id0;
+	rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id1;
+	rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id2;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG
-scom 0x8009980008010C3F {
-	bits, scom_data;
-	rx_rx_bus_width, 0b0010111;
-	rx_tx_bus_width, 0b0010111;
+scom 0x8009980008010C3F { 
+	bits, scom_data, expr;
+	rx_rx_bus_width, 0b0010111, def_bus_id0;
+	rx_rx_bus_width, 0b0010111, def_bus_id1;
+	rx_rx_bus_width, 0b0010111, def_bus_id2;
+	rx_tx_bus_width, 0b0010111, def_bus_id0;
+	rx_tx_bus_width, 0b0010111, def_bus_id1;
+	rx_tx_bus_width, 0b0010111, def_bus_id2;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG
-scom 0x8009580008010C3F {
-	bits, scom_data;
-	rx_wtr_max_bad_lanes, 0b00001;
+scom 0x8009580008010C3F { 
+	bits, scom_data, expr;
+	rx_wtr_max_bad_lanes, 0b00001, def_bus_id0;
+	rx_wtr_max_bad_lanes, 0b00001, def_bus_id1;
+	rx_wtr_max_bad_lanes, 0b00001, def_bus_id2;
 }
 
 #RX0.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG
-scom 0x800A300008010C3F {
+scom 0x800A300008010C3F { 
 	bits, scom_data, expr;
-     rx_wt_cu_pll_pgooddly,  0b001,   def_IS_HW;
-     rx_wt_cu_pll_pgooddly,  0b000,  def_IS_VBU;
-     rx_wt_cu_pll_reset,  0b0,   def_IS_HW;
-     rx_wt_cu_pll_reset,  0b1,  def_IS_VBU;
+     rx_wt_cu_pll_pgooddly,  0b001,   def_IS_HW && def_bus_id0;
+	rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id1;
+	rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id1;
+	rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id2;
+	rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id2;
+     rx_wt_cu_pll_pgooddly,  0b000,  def_IS_VBU && def_bus_id0;
+	rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id1;
+	rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id1;
+	rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id2;
+	rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id2;
+     rx_wt_cu_pll_reset,  0b0,   def_IS_HW && def_bus_id0;
+	rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id1;
+	rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id1;
+	rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id2;
+	rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id2;
+     rx_wt_cu_pll_reset,  0b1,  def_IS_VBU && def_bus_id0;
+	rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id1;
+	rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id1;
+	rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id2;
+	rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id2;
 }
 
 #RX0.RXPACKS#0.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B01508010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b001;
+scom 0x8000B01508010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, def_bus_id0;
+	rx_prbs_tap_id, 0b001, def_bus_id1;
+	rx_prbs_tap_id, 0b001, def_bus_id2;
 }
 
 #RX0.RXPACKS#0.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B01408010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b010;
+scom 0x8000B01408010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, def_bus_id0;
+	rx_prbs_tap_id, 0b010, def_bus_id1;
+	rx_prbs_tap_id, 0b010, def_bus_id2;
 }
 
 #RX0.RXPACKS#0.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B01608010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b000;
+scom 0x8000B01608010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, def_bus_id0;
+	rx_prbs_tap_id, 0b000, def_bus_id1;
+	rx_prbs_tap_id, 0b000, def_bus_id2;
 }
 
 #RX0.RXPACKS#0.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00A08010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b010;
+scom 0x8000B00A08010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, def_bus_id0;
+	rx_prbs_tap_id, 0b010, def_bus_id1;
+	rx_prbs_tap_id, 0b010, def_bus_id2;
 }
 
 #RX0.RXPACKS#0.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00B08010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b011;
+scom 0x8000B00B08010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b011, def_bus_id0;
+	rx_prbs_tap_id, 0b011, def_bus_id1;
+	rx_prbs_tap_id, 0b011, def_bus_id2;
 }
 
 #RX0.RXPACKS#0.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00908010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b001;
+scom 0x8000B00908010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, def_bus_id0;
+	rx_prbs_tap_id, 0b001, def_bus_id1;
+	rx_prbs_tap_id, 0b001, def_bus_id2;
 }
 
 #RX0.RXPACKS#1.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B01208010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b100;
+scom 0x8000B01208010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b100, def_bus_id0;
+	rx_prbs_tap_id, 0b100, def_bus_id1;
+	rx_prbs_tap_id, 0b100, def_bus_id2;
 }
 
 #RX0.RXPACKS#1.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B01708010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b000;
+scom 0x8000B01708010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, def_bus_id0;
+	rx_prbs_tap_id, 0b000, def_bus_id1;
+	rx_prbs_tap_id, 0b000, def_bus_id2;
 }
 
 #RX0.RXPACKS#1.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00708010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b111;
+scom 0x8000B00708010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b111, def_bus_id0;
+	rx_prbs_tap_id, 0b111, def_bus_id1;
+	rx_prbs_tap_id, 0b111, def_bus_id2;
 }
 
 #RX0.RXPACKS#1.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B01308010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b011;
+scom 0x8000B01308010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b011, def_bus_id0;
+	rx_prbs_tap_id, 0b011, def_bus_id1;
+	rx_prbs_tap_id, 0b011, def_bus_id2;
 }
 
 #RX0.RXPACKS#1.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00608010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b110;
+scom 0x8000B00608010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b110, def_bus_id0;
+	rx_prbs_tap_id, 0b110, def_bus_id1;
+	rx_prbs_tap_id, 0b110, def_bus_id2;
 }
 
 #RX0.RXPACKS#1.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00808010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b000;
+scom 0x8000B00808010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, def_bus_id0;
+	rx_prbs_tap_id, 0b000, def_bus_id1;
+	rx_prbs_tap_id, 0b000, def_bus_id2;
 }
 
 #RX0.RXPACKS#2.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00508010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b101;
+scom 0x8000B00508010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b101, def_bus_id0;
+	rx_prbs_tap_id, 0b101, def_bus_id1;
+	rx_prbs_tap_id, 0b101, def_bus_id2;
 }
 
 #RX0.RXPACKS#2.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00308010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b011;
+scom 0x8000B00308010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b011, def_bus_id0;
+	rx_prbs_tap_id, 0b011, def_bus_id1;
+	rx_prbs_tap_id, 0b011, def_bus_id2;
 }
 
 #RX0.RXPACKS#2.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B01108010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b101;
+scom 0x8000B01108010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b101, def_bus_id0;
+	rx_prbs_tap_id, 0b101, def_bus_id1;
+	rx_prbs_tap_id, 0b101, def_bus_id2;
 }
 
 #RX0.RXPACKS#2.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00408010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b100;
+scom 0x8000B00408010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b100, def_bus_id0;
+	rx_prbs_tap_id, 0b100, def_bus_id1;
+	rx_prbs_tap_id, 0b100, def_bus_id2;
 }
 
 #RX0.RXPACKS#2.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B01008010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b110;
+scom 0x8000B01008010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b110, def_bus_id0;
+	rx_prbs_tap_id, 0b110, def_bus_id1;
+	rx_prbs_tap_id, 0b110, def_bus_id2;
 }
 
 #RX0.RXPACKS#2.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00F08010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b111;
+scom 0x8000B00F08010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b111, def_bus_id0;
+	rx_prbs_tap_id, 0b111, def_bus_id1;
+	rx_prbs_tap_id, 0b111, def_bus_id2;
 }
 
 #RX0.RXPACKS#3.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00008010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b000;
+scom 0x8000B00008010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, def_bus_id0;
+	rx_prbs_tap_id, 0b000, def_bus_id1;
+	rx_prbs_tap_id, 0b000, def_bus_id2;
 }
 
 #RX0.RXPACKS#3.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00208010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b010;
+scom 0x8000B00208010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, def_bus_id0;
+	rx_prbs_tap_id, 0b010, def_bus_id1;
+	rx_prbs_tap_id, 0b010, def_bus_id2;
 }
 
 #RX0.RXPACKS#3.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00108010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b001;
+scom 0x8000B00108010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, def_bus_id0;
+	rx_prbs_tap_id, 0b001, def_bus_id1;
+	rx_prbs_tap_id, 0b001, def_bus_id2;
 }
 
 #RX0.RXPACKS#3.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00E08010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b000;
+scom 0x8000B00E08010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, def_bus_id0;
+	rx_prbs_tap_id, 0b000, def_bus_id1;
+	rx_prbs_tap_id, 0b000, def_bus_id2;
 }
 
 #RX0.RXPACKS#3.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00C08010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b010;
+scom 0x8000B00C08010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, def_bus_id0;
+	rx_prbs_tap_id, 0b010, def_bus_id1;
+	rx_prbs_tap_id, 0b010, def_bus_id2;
 }
 
 #RX0.RXPACKS#3.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00D08010C3F {
-	bits, scom_data;
-	rx_prbs_tap_id, 0b001;
+scom 0x8000B00D08010C3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, def_bus_id0;
+	rx_prbs_tap_id, 0b001, def_bus_id1;
+	rx_prbs_tap_id, 0b001, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG
-scom 0x800CC40008010C3F {
-	bits, scom_data;
-	tx_drv_clk_pattern_gcrmsg, 0b00;
+scom 0x800CC40008010C3F { 
+	bits, scom_data, expr;
+	tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id0;
+	tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id1;
+	tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID1_PG
-scom 0x800C940008010C3F {
+scom 0x800C940008010C3F { 
 	bits, scom_data, expr;
-	tx_bus_id, 0b000010, def_bus_id2;
-	tx_bus_id, 0b000001, def_bus_id1;
-	tx_bus_id, 0b000000, def_bus_id0;
-	tx_group_id, 0b100000, any;
+	tx_bus_id, 0b000001, def_bus_id0;
+	tx_bus_id, 0b000010, def_bus_id1;
+	tx_bus_id, 0b000011, def_bus_id2;
+	tx_group_id, 0b100000, def_bus_id0;
+	tx_group_id, 0b100000, def_bus_id1;
+	tx_group_id, 0b100000, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID2_PG
-scom 0x800C9C0008010C3F {
-	bits, scom_data;
-	tx_last_group_id, 0b100000;
+scom 0x800C9C0008010C3F { 
+	bits, scom_data, expr;
+	tx_last_group_id, 0b100000, def_bus_id0;
+	tx_last_group_id, 0b100000, def_bus_id1;
+	tx_last_group_id, 0b100000, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID3_PG
-scom 0x800CA40008010C3F {
-	bits, scom_data;
-	tx_end_lane_id, 0b0010110;
-	tx_start_lane_id, 0b0000000;
+scom 0x800CA40008010C3F { 
+	bits, scom_data, expr;
+	tx_end_lane_id, 0b0010110, def_bus_id0;
+	tx_end_lane_id, 0b0010110, def_bus_id1;
+	tx_end_lane_id, 0b0010110, def_bus_id2;
+	tx_start_lane_id, 0b0000000, def_bus_id0;
+	tx_start_lane_id, 0b0000000, def_bus_id1;
+	tx_start_lane_id, 0b0000000, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG
-scom 0x800D1C0008010C3F {
-	bits, scom_data;
-	tx_lane_disabled_vec_0_15, 0b0000000000000000;
+scom 0x800D1C0008010C3F { 
+	bits, scom_data, expr;
+	tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id0;
+	tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id1;
+	tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG
-scom 0x800D240008010C3F {
-	bits, scom_data;
-	tx_lane_disabled_vec_16_31, 0b0000000111111111;
+scom 0x800D240008010C3F { 
+	bits, scom_data, expr;
+	tx_lane_disabled_vec_16_31, 0b0000000111111111, def_bus_id0;
+	tx_lane_disabled_vec_16_31, 0b0000000111111111, def_bus_id1;
+	tx_lane_disabled_vec_16_31, 0b0000000111111111, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_MODE_PG
-scom 0x800C1C0008010C3F {
-	bits, scom_data;
-	tx_max_bad_lanes, 0b00001;
+scom 0x800C1C0008010C3F { 
+	bits, scom_data, expr;
+	tx_max_bad_lanes, 0b00001, def_bus_id0;
+	tx_max_bad_lanes, 0b00001, def_bus_id1;
+	tx_max_bad_lanes, 0b00001, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004341108010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b101;
+scom 0x8004341108010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b101, def_bus_id0;
+	tx_prbs_tap_id, 0b101, def_bus_id1;
+	tx_prbs_tap_id, 0b101, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004341208010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b100;
+scom 0x8004341208010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b100, def_bus_id0;
+	tx_prbs_tap_id, 0b100, def_bus_id1;
+	tx_prbs_tap_id, 0b100, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004341608010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b000;
+scom 0x8004341608010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b000, def_bus_id0;
+	tx_prbs_tap_id, 0b000, def_bus_id1;
+	tx_prbs_tap_id, 0b000, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340008010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b000;
+scom 0x8004340008010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b000, def_bus_id0;
+	tx_prbs_tap_id, 0b000, def_bus_id1;
+	tx_prbs_tap_id, 0b000, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004341008010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b110;
+scom 0x8004341008010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b110, def_bus_id0;
+	tx_prbs_tap_id, 0b110, def_bus_id1;
+	tx_prbs_tap_id, 0b110, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340108010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b001;
+scom 0x8004340108010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b001, def_bus_id0;
+	tx_prbs_tap_id, 0b001, def_bus_id1;
+	tx_prbs_tap_id, 0b001, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004341408010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b010;
+scom 0x8004341408010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b010, def_bus_id0;
+	tx_prbs_tap_id, 0b010, def_bus_id1;
+	tx_prbs_tap_id, 0b010, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004341508010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b001;
+scom 0x8004341508010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b001, def_bus_id0;
+	tx_prbs_tap_id, 0b001, def_bus_id1;
+	tx_prbs_tap_id, 0b001, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340E08010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b000;
+scom 0x8004340E08010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b000, def_bus_id0;
+	tx_prbs_tap_id, 0b000, def_bus_id1;
+	tx_prbs_tap_id, 0b000, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340908010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b001;
+scom 0x8004340908010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b001, def_bus_id0;
+	tx_prbs_tap_id, 0b001, def_bus_id1;
+	tx_prbs_tap_id, 0b001, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340208010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b010;
+scom 0x8004340208010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b010, def_bus_id0;
+	tx_prbs_tap_id, 0b010, def_bus_id1;
+	tx_prbs_tap_id, 0b010, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004341308010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b011;
+scom 0x8004341308010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b011, def_bus_id0;
+	tx_prbs_tap_id, 0b011, def_bus_id1;
+	tx_prbs_tap_id, 0b011, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340308010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b011;
+scom 0x8004340308010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b011, def_bus_id0;
+	tx_prbs_tap_id, 0b011, def_bus_id1;
+	tx_prbs_tap_id, 0b011, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340508010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b101;
+scom 0x8004340508010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b101, def_bus_id0;
+	tx_prbs_tap_id, 0b101, def_bus_id1;
+	tx_prbs_tap_id, 0b101, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340408010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b100;
+scom 0x8004340408010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b100, def_bus_id0;
+	tx_prbs_tap_id, 0b100, def_bus_id1;
+	tx_prbs_tap_id, 0b100, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340D08010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b001;
+scom 0x8004340D08010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b001, def_bus_id0;
+	tx_prbs_tap_id, 0b001, def_bus_id1;
+	tx_prbs_tap_id, 0b001, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340808010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b000;
+scom 0x8004340808010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b000, def_bus_id0;
+	tx_prbs_tap_id, 0b000, def_bus_id1;
+	tx_prbs_tap_id, 0b000, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340608010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b110;
+scom 0x8004340608010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b110, def_bus_id0;
+	tx_prbs_tap_id, 0b110, def_bus_id1;
+	tx_prbs_tap_id, 0b110, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340708010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b111;
+scom 0x8004340708010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b111, def_bus_id0;
+	tx_prbs_tap_id, 0b111, def_bus_id1;
+	tx_prbs_tap_id, 0b111, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340C08010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b010;
+scom 0x8004340C08010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b010, def_bus_id0;
+	tx_prbs_tap_id, 0b010, def_bus_id1;
+	tx_prbs_tap_id, 0b010, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340B08010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b011;
+scom 0x8004340B08010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b011, def_bus_id0;
+	tx_prbs_tap_id, 0b011, def_bus_id1;
+	tx_prbs_tap_id, 0b011, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340A08010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b010;
+scom 0x8004340A08010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b010, def_bus_id0;
+	tx_prbs_tap_id, 0b010, def_bus_id1;
+	tx_prbs_tap_id, 0b010, def_bus_id2;
 }
 
 #TX_WRAP.TX0.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340F08010C3F {
-	bits, scom_data;
-	tx_prbs_tap_id, 0b111;
-}
-
-#--**************************************************************************************************************
-#----------------------------------------------------------------------------------------------------------------
-#    ________________     ____        ________             ____             _ __           __  ___           __  
-#   / ____/ ____/ __ \   / __ )__  __/ __/ __/__  _____   / __ \____ ______(_) /___  __   /  |/  /___ ______/ /__
-#  / / __/ /   / /_/ /  / __  / / / / /_/ /_/ _ \/ ___/  / /_/ / __ `/ ___/ / __/ / / /  / /|_/ / __ `/ ___/ //_/
-# / /_/ / /___/ _, _/  / /_/ / /_/ / __/ __/  __/ /     / ____/ /_/ / /  / / /_/ /_/ /  / /  / / /_/ (__  ) ,<   
-# \____/\____/_/ |_|  /_____/\__,_/_/ /_/  \___/_/     /_/    \__,_/_/  /_/\__/\__, /  /_/  /_/\__,_/____/_/|_|  
-#                                                                             /____/                             
-#----------------------------------------------------------------------------------------------------------------
-#--**************************************************************************************************************
-# HW242564: Temporarily mask the GCR Buffer Parity Checker until the source of the error can be found. This ungates the lab.
-# 0x800???0002011E3F
-# This is applied to all configured clkgrp's via chiplet targetting
-scom 0x800.0b(rx_fir1_mask_pg)(rx_grp0)(lane_na).0x(abus_gcr_addr) {
-bits,                             scom_data;
-rx_pg_fir_err_mask_gcr_buff,      0b1;
-}
-scom 0x800.0b(tx_fir_mask_pg)(tx_grp0)(lane_na).0x(abus_gcr_addr) {
-bits,                             scom_data;
-tx_pg_fir_err_mask_gcr_buff,      0b1;
-}
-scom 0x800.0b(rx_fir_mask_pb)(rx_grp0)(lane_na).0x(abus_gcr_addr) {
-bits,                             scom_data;
-rx_pb_fir_err_mask_gcr_buff0,    0b1;
-rx_pb_fir_err_mask_gcr_buff1,    0b1;
-rx_pb_fir_err_mask_gcr_buff2,    0b1;
-}
-
-# Mask off all rx and tx parity errors in the fir register
-scom 0x08010C03 {
-scom_data;
-0xC000000000000000;
-}
-
-######################################
-##      END OF FILE
-#######################################
+scom 0x8004340F08010C3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b111, def_bus_id0;
+	tx_prbs_tap_id, 0b111, def_bus_id1;
+	tx_prbs_tap_id, 0b111, def_bus_id2;
+}
+
diff --git a/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile
index eee853719..0c3d2ed1f 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile
@@ -1,4 +1,4 @@
-#-- $Id: p8.dmi.scom.initfile,v 1.16 2013/03/22 20:55:00 jgrell Exp $ 
+#-- $Id: p8.dmi.scom.initfile,v 1.17 2013/04/18 19:13:44 jgrell Exp $ 
 
 
 ####################################################################
@@ -7,13 +7,14 @@
 ##      Based on SETUP_ID_MODE DMI_BUS_TR_HW
 ##      from ../../logic/mesa_sim/fusion/run/IODPV_MC_WRAP.IODPV_MC_WRAP.figdb
 ##
-##   Created on Fri Mar 22 14:31:13 CDT 2013, by jgrell
+##   Created on Mon Apr 15 15:03:50 CDT 2013, by jgrell
 ####################################################################
 
 ## -- CHANGE HISTORY:
  ## --------------------------------------------------------------------------------
  ## -- VersionID: |Author:  | Date:  | Comment:
  ## -- -----------|---------|--------|-------------------------------------------------
+ ## -- jgr13041800| jgr     |04-18-13| Added rx_max_ber_check_count setting to 0x03
  ## -- jgr13031300| jgr     |03-13-13| Added missing entries from rel 0128
  ## -- mbs13011802| mbs     |01-18-13| Added rx_fence to run_mode dial (HW236326)
  ## -- mbs12121100| mbs     |12-11-12| Added rx_prot_speed_slct and rx_c4_sel
@@ -70,6 +71,25 @@ define def_bus_id0 = ((ATTR_CHIP_UNIT_POS == 3) || (ATTR_CHIP_UNIT_POS == 6));
 
 
 
+#RX3.RXCTL.RX_CTL_REGS.RX_BER_CHK_PG
+scom 0x800AF06002011A3F { 
+	bits, scom_data, expr;
+     rx_max_ber_check_count,  0b00000011,   def_IS_HW && def_bus_id3;
+	rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id0;
+	rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id0;
+	rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id1;
+	rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id1;
+	rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id2;
+	rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id2;
+     rx_max_ber_check_count,  0b00000000,  def_IS_VBU && def_bus_id3;
+	rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id0;
+	rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id0;
+	rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id1;
+	rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id1;
+	rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id2;
+	rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id2;
+}
+
 #RX3.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP
 scom 0x800B786002011A3F { 
 	bits, scom_data, expr;
diff --git a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C
index 3da56e4d3..baa154ae8 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C
@@ -697,12 +697,6 @@ void* call_proc_abus_scominit( void    *io_pArgs )
                        (const_cast<TARGETING::Target*>(l_abusTarget)));
                 targets.push_back(l_fapi_abus_target);
 
-                const fapi::Target l_fapi_this_cpu_target(
-                       TARGET_TYPE_PROC_CHIP,
-                       (const_cast<TARGETING::Target*>(
-                               l_cpuTarget)));
-                targets.push_back(l_fapi_this_cpu_target);
-
                 const fapi::Target l_fapi_other_cpu_target(
                        TARGET_TYPE_PROC_CHIP,
                        (const_cast<TARGETING::Target*>(
@@ -719,7 +713,6 @@ void* call_proc_abus_scominit( void    *io_pArgs )
 
                 FAPI_INVOKE_HWP(l_err, proc_abus_scominit,
                                 l_fapi_abus_target,
-                                l_fapi_this_cpu_target,
                                 l_fapi_other_cpu_target);
                 if (l_err)
                 {
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit.C b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit.C
index aa6e86607..69d4f0a92 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_abus_scominit.C,v 1.3 2013/02/11 04:27:40 jmcgill Exp $
+// $Id: proc_abus_scominit.C,v 1.4 2013/04/18 22:35:35 jgrell Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_abus_scominit.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -36,6 +36,14 @@
 // *! ADDITIONAL COMMENTS :
 // *!
 //------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+//  Version		Date		Owner		Description
+//------------------------------------------------------------------------------
+//    1.4	   	02/18/13	thomsen		Changed targeting to use Abus_chiplet, chip, connected_Abus_chiplet & connected_chip to match Xbus and DMI target list so they are common
+//    1.3	   	02/10/13	jmcgill     Leverage chiplet level targeting, invoke custom initfile
+//    1.2	   	01/20/13	jmcgill		Add consistency check for A chiplet partial good support
+//    1.1       8/11/12     jmcgill		Initial release
+//------------------------------------------------------------------------------
 
 //------------------------------------------------------------------------------
 //  Includes
@@ -50,13 +58,13 @@ extern "C" {
 //------------------------------------------------------------------------------
 
 // HWP entry point, comments in header
-fapi::ReturnCode proc_abus_scominit(
-    const fapi::Target & i_abus_target,
-    const fapi::Target & i_this_pu_target,
-    const fapi::Target & i_other_pu_target)
+fapi::ReturnCode proc_abus_scominit( const fapi::Target & i_abus_target,
+                                     const fapi::Target & i_connected_abus_target)
 {
     fapi::ReturnCode rc;
     std::vector<fapi::Target> targets;
+    fapi::Target i_this_pu_target;
+    fapi::Target i_connected_pu_target;
     uint8_t abus_enable_attr;
 
     // mark HWP entry
@@ -64,6 +72,17 @@ fapi::ReturnCode proc_abus_scominit(
 
     do
     {
+
+	    // Get parent chip targets
+        rc = fapiGetParentChip(i_abus_target, i_this_pu_target); if(rc) return rc;
+        rc = fapiGetParentChip(i_connected_abus_target, i_connected_pu_target); if(rc) return rc;
+
+		// populate targets vector
+        targets.push_back(i_abus_target);               // Chiplet target
+        targets.push_back(i_this_pu_target);            // Proc target
+        targets.push_back(i_connected_abus_target);     // Connected Chiplet target
+        targets.push_back(i_connected_pu_target);       // Connected Proc target
+
         // query ABUS partial good attribute
         rc = FAPI_ATTR_GET(ATTR_PROC_A_ENABLE,
                            &i_this_pu_target,
@@ -81,36 +100,39 @@ fapi::ReturnCode proc_abus_scominit(
             break;
         }
 
-        // obtain target type to determine which initfile(s) to execute
-        targets.push_back(i_abus_target);
-        targets.push_back(i_this_pu_target);
-        targets.push_back(i_other_pu_target);
-
-        // processor ABUS chiplet target
-        if ((i_abus_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT) &&
-            (i_this_pu_target.getType() == fapi::TARGET_TYPE_PROC_CHIP) &&
-            (i_other_pu_target.getType() == fapi::TARGET_TYPE_PROC_CHIP))
+        // processor target, processor MCS chiplet target
+        // test target types to confirm correct before calling initfile(s) to execute
+        if ((i_this_pu_target.getType()        == fapi::TARGET_TYPE_PROC_CHIP)     &&
+            (i_abus_target.getType()           == fapi::TARGET_TYPE_ABUS_ENDPOINT) &&
+            (i_connected_pu_target.getType()   == fapi::TARGET_TYPE_PROC_CHIP)     &&
+            (i_connected_abus_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT))
         {
-            FAPI_INF("proc_abus_scominit: Executing %s on %s",
-                     ABUS_BASE_IF, i_abus_target.toEcmdString());
+		    // Call BASE DMI SCOMINIT
+            FAPI_INF("proc_abus_scominit: fapiHwpExecInitfile executing %s on %s, %s, %s, %s",
+                     ABUS_BASE_IF, i_this_pu_target.toEcmdString(), i_abus_target.toEcmdString(),
+			    	                 i_connected_pu_target.toEcmdString(), i_connected_abus_target.toEcmdString());
             FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, targets, ABUS_BASE_IF);
             if (!rc.ok())
             {
-                FAPI_ERR("proc_abus_scominit: Error from fapiHwpExecInitfile executing %s on %s",
-                         ABUS_BASE_IF, i_abus_target.toEcmdString());
+                FAPI_ERR("proc_abus_scominit: Error from fapiHwpExecInitfile executing %s on %s, %s, %s, %s",
+                     ABUS_BASE_IF, i_this_pu_target.toEcmdString(), i_abus_target.toEcmdString(),
+			   	                 i_connected_pu_target.toEcmdString(), i_connected_abus_target.toEcmdString());
                 break;
             }
 
-            FAPI_INF("proc_abus_scominit: Executing %s on %s",
-                     ABUS_CUSTOM_IF, i_abus_target.toEcmdString());
+		    // Call CUSTOMIZED DMI SCOMINIT (system specific)
+            FAPI_INF("proc_abus_scominit: fapiHwpExecInitfile executing %s on %s, %s, %s, %s",
+                     ABUS_CUSTOM_IF, i_this_pu_target.toEcmdString(), i_abus_target.toEcmdString(),
+			    	                 i_connected_pu_target.toEcmdString(), i_connected_abus_target.toEcmdString());
             FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, targets, ABUS_CUSTOM_IF);
             if (!rc.ok())
             {
-                FAPI_ERR("proc_abus_scominit: Error from fapiHwpExecInitfile executing %s on %s",
-                         ABUS_CUSTOM_IF, i_abus_target.toEcmdString());
+                FAPI_ERR("proc_abus_scominit: Error from fapiHwpExecInitfile executing %s on %s, %s, %s, %s",
+                         ABUS_CUSTOM_IF, i_abus_target.toEcmdString(), i_abus_target.toEcmdString(),
+			   	                 i_connected_pu_target.toEcmdString(), i_connected_abus_target.toEcmdString());
                 break;
             }
-        }
+		}
         // unsupported target type
         else
         {
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit.H b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit.H
index ed47f04b2..255c14242 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit.H
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_abus_scominit.H,v 1.2 2013/02/11 04:27:41 jmcgill Exp $
+// $Id: proc_abus_scominit.H,v 1.3 2013/04/18 22:36:20 jgrell Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_abus_scominit.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -58,8 +58,7 @@ const char * const ABUS_CUSTOM_IF = "p8.abus.custom.scom.if";
 // function pointer typedef definition for HWP call support
 typedef fapi::ReturnCode
 (*proc_abus_scominit_FP_t)(const fapi::Target & i_abus_target,
-                           const fapi::Target & i_this_pu_target,
-                           const fapi::Target & i_other_pu_target);
+                           const fapi::Target & i_connected_abus_target);
 
 extern "C" {
 
@@ -85,8 +84,7 @@ extern "C" {
  */
 fapi::ReturnCode proc_abus_scominit(
     const fapi::Target & i_abus_target,
-    const fapi::Target & i_this_pu_target,
-    const fapi::Target & i_other_pu_target);
+    const fapi::Target & i_connected_abus_target);
 
 
 } // extern "C"