diff options
| author | Thi Tran <thi@us.ibm.com> | 2015-02-27 13:24:03 -0600 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2015-03-03 02:51:35 -0600 |
| commit | 794bbee76901ed6362547323f6c9105a2ebc02ea (patch) | |
| tree | 54dcd4f7b9a8c6635dd7d3c0946ad1b69ec0fdbb /src/usr/hwpf | |
| parent | e78326126776180e9e043a7b111269a332a97228 (diff) | |
| download | talos-hostboot-794bbee76901ed6362547323f6c9105a2ebc02ea.tar.gz talos-hostboot-794bbee76901ed6362547323f6c9105a2ebc02ea.zip | |
SW296793: New rx_fifo_final_l2u_dly setting for brazos (venice )only - A/X bus
Change-Id: I8ea68987bc3e3af22c8c42f5155217784c358dba
CQ:SW296793
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/16035
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/16044
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf')
| -rw-r--r-- | src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile | 7 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile | 27 |
2 files changed, 32 insertions, 2 deletions
diff --git a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile index b78305ff4..988e7e911 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile @@ -1,8 +1,9 @@ -#-- $Id: p8.abus.custom.scom.initfile,v 1.15 2014/11/18 17:23:22 jmcgill Exp $ +#-- $Id: p8.abus.custom.scom.initfile,v 1.16 2015/02/25 21:00:12 jgrell Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.15|jgrell |02/25/15| Added rx_fifo_final_l2u_dly for Venice only (SW296793) #-- 1.14|garyp |02/19/14| Added rx_min_eye_width and rx_min_eye_height for manufacturing and lab thresholding #-- 1.13|jgrell |02/12/14| Added rx_wt_lane_disabled=1 on lane 17 (SW244284) #-- 1.12|jgrell |12/03/13| Set rx_eo_ddc_timeout_sel to 110 for DD2 @@ -487,6 +488,10 @@ scom 0x8004340B08010C3F { tx_prbs_tap_id, 0b011, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } +scom 0x800.0b(rx_fifo_mode_pg)(rx_grp0)(lane_na).0x(abus_gcr_addr) { + bits, scom_data, expr; + rx_fifo_final_l2u_dly, 0b0011, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; +} #--*********************************************************************************** #------------------------------------------------------------------------------------- diff --git a/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile index d76204a88..6323938a3 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile @@ -1,8 +1,9 @@ -#-- $Id: p8.xbus.custom.scom.initfile,v 1.8 2014/02/20 15:29:11 garyp Exp $ +#-- $Id: p8.xbus.custom.scom.initfile,v 1.9 2015/02/25 21:00:13 jgrell Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.9 |jgrell |02/25/15|Added rx_fifo_final_l2u_dly for Venice only (SW296793) #-- 1.8 |garyp |02/19/14|Added rx_min_eye_width for manufacturing and lab thresholding #-- 1.7 |jgrell |12/03/13|Set rx_sls_extend_sel to 001 for DD2 #-- 1.5 |jgrell |09/17/13|Added DD2 specific inits @@ -101,6 +102,30 @@ scom 0x800.0b(rx_result_chk_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr) { #} +#--************************************************************************************************************** +#---------------------------------------------------------------------------------------------------------------- +# Venice Specific Inits +#---------------------------------------------------------------------------------------------------------------- +#--************************************************************************************************************** + +scom 0x800.0b(rx_fifo_mode_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr) { + bits, scom_data, expr; + rx_fifo_final_l2u_dly, 0b0100, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; +} +scom 0x800.0b(rx_fifo_mode_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr) { + bits, scom_data, expr; + rx_fifo_final_l2u_dly, 0b0100, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; +} +scom 0x800.0b(rx_fifo_mode_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr) { + bits, scom_data, expr; + rx_fifo_final_l2u_dly, 0b0100, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; +} +scom 0x800.0b(rx_fifo_mode_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr) { + bits, scom_data, expr; + rx_fifo_final_l2u_dly, 0b0100, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; +} + + #--*********************************************************************************** #------------------------------------------------------------------------------------- #-- DD2+ Murano & Venice |
