proc_prep_master_winkle

Change-Id: I7e0ea508c75e0e368e3bfde9dcaef1788169dcf3
RTC: 44818
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1517
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

28 files changed, 6291 insertions, 115 deletions

diff --git a/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.C b/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.C
index 7b49ff936..9c2b54ba4 100644
--- a/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.C
+++ b/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.C
@@ -455,15 +455,9 @@ void    call_proc_set_pore_bar( void    *io_pArgs )
         l_cpu_target->getAttr<TARGETING::ATTR_SLW_IMAGE_ADDR>();
 
 
-        //  $$ @todo the hardware wants a mask to cover the size of the image,
-        //  with the added proviso that the lower 5 nybbles of the mask must
-        //  always be 0.
-        //  Thus, as long as the image is under 1M, this value will be 0 .
-        //  The HWP guys will probably pull this calculation inside
-        //  proc_set_pore_bar() so that we just specify the size in bytes.
-        //  This comment will be left until we integrate the new version.
-        //  In the meantime, l_mem_mask should be set to 0 to work correctly.
-        uint64_t l_mem_mask =  0;
+        // Size in Meg of the image, this is rounded up to the nearest power
+        //  of 2.  So far our images are less than 1 meg so this is 1
+        uint64_t l_mem_size =  1;
 
         //  defined in proc_set_pore_bar.H
         uint32_t        l_mem_type  =   SLW_L3 ;
@@ -480,7 +474,7 @@ void    call_proc_set_pore_bar( void    *io_pArgs )
                    "Call proc_set_pore_bar, membar=0x%lx, size=0x%lx, mask=0x%lx, type=0x%x",
                    l_imageAddr,
                    (l_cpu_target->getAttr<ATTR_SLW_IMAGE_SIZE>()),
-                   l_mem_mask,
+                   l_mem_size,
                    l_mem_type );
 
 
@@ -491,7 +485,7 @@ void    call_proc_set_pore_bar( void    *io_pArgs )
                          l_fapi_cpu_target,
                          l_pImage,
                          l_imageAddr,
-                         l_mem_mask,
+                         l_mem_size,
                          l_mem_type
                        );
 
diff --git a/src/usr/hwpf/hwp/build_winkle_images/makefile b/src/usr/hwpf/hwp/build_winkle_images/makefile
index 815db6200..b8afa2c87 100644
--- a/src/usr/hwpf/hwp/build_winkle_images/makefile
+++ b/src/usr/hwpf/hwp/build_winkle_images/makefile
@@ -43,7 +43,7 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/proc_slw_build
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/proc_pba_bar_config
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/pore_gen_cpureg
+EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/proc_gen_cpureg
 
 CUSTOMFLAGS+= -D __FAPI
 
@@ -65,7 +65,7 @@ OBJS =  build_winkle_images.o   \
 VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/proc_slw_build
 VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar
 VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/proc_pba_bar_config
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/pore_gen_cpureg
+VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/proc_gen_cpureg
 
 ##  Point to the PORE image in PNOR
 BINARY_FILES = $(IMGDIR)/procpore.dat:72cc5bef88f4d55dd9bbc9ad096e7dacff7d46e4
diff --git a/src/usr/hwpf/hwp/build_winkle_images/pore_gen_cpureg/HvPlicModule.H b/src/usr/hwpf/hwp/build_winkle_images/proc_gen_cpureg/HvPlicModule.H
index 859c217cd..859c217cd 100644
--- a/src/usr/hwpf/hwp/build_winkle_images/pore_gen_cpureg/HvPlicModule.H
+++ b/src/usr/hwpf/hwp/build_winkle_images/proc_gen_cpureg/HvPlicModule.H
diff --git a/src/usr/hwpf/hwp/build_winkle_images/pore_gen_cpureg/p8_pore_table_gen_api.H b/src/usr/hwpf/hwp/build_winkle_images/proc_gen_cpureg/p8_pore_table_gen_api.H
index e78a31e7a..e78a31e7a 100644
--- a/src/usr/hwpf/hwp/build_winkle_images/pore_gen_cpureg/p8_pore_table_gen_api.H
+++ b/src/usr/hwpf/hwp/build_winkle_images/proc_gen_cpureg/p8_pore_table_gen_api.H
diff --git a/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/pba_firmware_register.H b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/pba_firmware_register.H
new file mode 100644
index 000000000..8529b3194
--- /dev/null
+++ b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/pba_firmware_register.H
@@ -0,0 +1,1437 @@
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/pba_firmware_register.H $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+// Subversion Repositories OCC
+// (root)/ssx/trunk/pgp/registers/pba_firmware_registers.h - Rev 1095
+// Rev
+
+// Rev 1077 | Blame | Compare with Previous | Last modification | View Log | RSS feed
+#ifndef __PBA_FIRMWARE_REGISTERS_H__
+#define __PBA_FIRMWARE_REGISTERS_H__
+
+#ifndef SIXTYFOUR_BIT_CONSTANT
+#ifdef __ASSEMBLER__
+#define SIXTYFOUR_BIT_CONSTANT(x) x
+#else
+#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
+#endif
+#endif
+
+#ifndef __ASSEMBLER__
+
+// $Id: pba_firmware_register.H,v 1.1 2012/01/09 13:46:34 kgungl Exp $
+
+/// \file pba_firmware_registers.h
+/// \brief C register structs for the PBA unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+#include <stdint.h>
+
+
+typedef union pba_barn {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t cmd_scope : 3;
+        uint64_t reserved0 : 1;
+        uint64_t reserved1 : 10;
+        uint64_t addr : 30;
+        uint64_t _reserved0 : 20;
+#else
+        uint64_t _reserved0 : 20;
+        uint64_t addr : 30;
+        uint64_t reserved1 : 10;
+        uint64_t reserved0 : 1;
+        uint64_t cmd_scope : 3;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_barn_t;
+
+
+
+typedef union pba_barmskn {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t reserved0 : 23;
+        uint64_t mask : 21;
+        uint64_t _reserved0 : 20;
+#else
+        uint64_t _reserved0 : 20;
+        uint64_t mask : 21;
+        uint64_t reserved0 : 23;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_barmskn_t;
+
+
+
+typedef union pba_fir {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t oci_apar_err : 1;
+        uint64_t pb_rdadrerr_fw : 1;
+        uint64_t pb_rddatato_fw : 1;
+        uint64_t pb_sue_fw : 1;
+        uint64_t pb_ue_fw : 1;
+        uint64_t pb_ce_fw : 1;
+        uint64_t oci_slave_init : 1;
+        uint64_t oci_wrpar_err : 1;
+        uint64_t oci_rereqto : 1;
+        uint64_t pb_unexpcresp : 1;
+        uint64_t pb_unexpdata : 1;
+        uint64_t pb_parity_err : 1;
+        uint64_t pb_wradrerr_fw : 1;
+        uint64_t pb_badcresp : 1;
+        uint64_t pb_ackdead_fw : 1;
+        uint64_t pb_crespto : 1;
+        uint64_t bcue_setup_err : 1;
+        uint64_t bcue_pb_ack_dead : 1;
+        uint64_t bcue_pb_adrerr : 1;
+        uint64_t bcue_oci_dataerr : 1;
+        uint64_t bcde_setup_err : 1;
+        uint64_t bcde_pb_ack_dead : 1;
+        uint64_t bcde_pb_adrerr : 1;
+        uint64_t bcde_rddatato_err : 1;
+        uint64_t bcde_sue_err : 1;
+        uint64_t bcde_ue_err : 1;
+        uint64_t bcde_ce : 1;
+        uint64_t bcde_oci_dataerr : 1;
+        uint64_t internal_err : 1;
+        uint64_t illegal_cache_op : 1;
+        uint64_t oci_bad_reg_addr : 1;
+        uint64_t axpush_wrerr : 1;
+        uint64_t axrcv_dlo_err : 1;
+        uint64_t axrcv_dlo_to : 1;
+        uint64_t axrcv_rsvdata_to : 1;
+        uint64_t axflow_err : 1;
+        uint64_t axsnd_dhi_rtyto : 1;
+        uint64_t axsnd_dlo_rtyto : 1;
+        uint64_t axsnd_rsvto : 1;
+        uint64_t axsnd_rsverr : 1;
+        uint64_t reserved : 4;
+        uint64_t fir_parity_error : 1;
+        uint64_t _reserved0 : 19;
+#else
+        uint64_t _reserved0 : 19;
+        uint64_t fir_parity_error : 1;
+        uint64_t reserved : 4;
+        uint64_t axsnd_rsverr : 1;
+        uint64_t axsnd_rsvto : 1;
+        uint64_t axsnd_dlo_rtyto : 1;
+        uint64_t axsnd_dhi_rtyto : 1;
+        uint64_t axflow_err : 1;
+        uint64_t axrcv_rsvdata_to : 1;
+        uint64_t axrcv_dlo_to : 1;
+        uint64_t axrcv_dlo_err : 1;
+        uint64_t axpush_wrerr : 1;
+        uint64_t oci_bad_reg_addr : 1;
+        uint64_t illegal_cache_op : 1;
+        uint64_t internal_err : 1;
+        uint64_t bcde_oci_dataerr : 1;
+        uint64_t bcde_ce : 1;
+        uint64_t bcde_ue_err : 1;
+        uint64_t bcde_sue_err : 1;
+        uint64_t bcde_rddatato_err : 1;
+        uint64_t bcde_pb_adrerr : 1;
+        uint64_t bcde_pb_ack_dead : 1;
+        uint64_t bcde_setup_err : 1;
+        uint64_t bcue_oci_dataerr : 1;
+        uint64_t bcue_pb_adrerr : 1;
+        uint64_t bcue_pb_ack_dead : 1;
+        uint64_t bcue_setup_err : 1;
+        uint64_t pb_crespto : 1;
+        uint64_t pb_ackdead_fw : 1;
+        uint64_t pb_badcresp : 1;
+        uint64_t pb_wradrerr_fw : 1;
+        uint64_t pb_parity_err : 1;
+        uint64_t pb_unexpdata : 1;
+        uint64_t pb_unexpcresp : 1;
+        uint64_t oci_rereqto : 1;
+        uint64_t oci_wrpar_err : 1;
+        uint64_t oci_slave_init : 1;
+        uint64_t pb_ce_fw : 1;
+        uint64_t pb_ue_fw : 1;
+        uint64_t pb_sue_fw : 1;
+        uint64_t pb_rddatato_fw : 1;
+        uint64_t pb_rdadrerr_fw : 1;
+        uint64_t oci_apar_err : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_fir_t;
+
+
+
+typedef union pba_fir_and {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t oci_apar_err : 1;
+        uint64_t pb_rdadrerr_fw : 1;
+        uint64_t pb_rddatato_fw : 1;
+        uint64_t pb_sue_fw : 1;
+        uint64_t pb_ue_fw : 1;
+        uint64_t pb_ce_fw : 1;
+        uint64_t oci_slave_init : 1;
+        uint64_t oci_wrpar_err : 1;
+        uint64_t oci_rereqto : 1;
+        uint64_t pb_unexpcresp : 1;
+        uint64_t pb_unexpdata : 1;
+        uint64_t pb_parity_err : 1;
+        uint64_t pb_wradrerr_fw : 1;
+        uint64_t pb_badcresp : 1;
+        uint64_t pb_ackdead_fw : 1;
+        uint64_t pb_crespto : 1;
+        uint64_t bcue_setup_err : 1;
+        uint64_t bcue_pb_ack_dead : 1;
+        uint64_t bcue_pb_adrerr : 1;
+        uint64_t bcue_oci_dataerr : 1;
+        uint64_t bcde_setup_err : 1;
+        uint64_t bcde_pb_ack_dead : 1;
+        uint64_t bcde_pb_adrerr : 1;
+        uint64_t bcde_rddatato_err : 1;
+        uint64_t bcde_sue_err : 1;
+        uint64_t bcde_ue_err : 1;
+        uint64_t bcde_ce : 1;
+        uint64_t bcde_oci_dataerr : 1;
+        uint64_t internal_err : 1;
+        uint64_t illegal_cache_op : 1;
+        uint64_t oci_bad_reg_addr : 1;
+        uint64_t axpush_wrerr : 1;
+        uint64_t axrcv_dlo_err : 1;
+        uint64_t axrcv_dlo_to : 1;
+        uint64_t axrcv_rsvdata_to : 1;
+        uint64_t axflow_err : 1;
+        uint64_t axsnd_dhi_rtyto : 1;
+        uint64_t axsnd_dlo_rtyto : 1;
+        uint64_t axsnd_rsvto : 1;
+        uint64_t axsnd_rsverr : 1;
+        uint64_t reserved : 4;
+        uint64_t fir_parity_error : 1;
+        uint64_t _reserved0 : 19;
+#else
+        uint64_t _reserved0 : 19;
+        uint64_t fir_parity_error : 1;
+        uint64_t reserved : 4;
+        uint64_t axsnd_rsverr : 1;
+        uint64_t axsnd_rsvto : 1;
+        uint64_t axsnd_dlo_rtyto : 1;
+        uint64_t axsnd_dhi_rtyto : 1;
+        uint64_t axflow_err : 1;
+        uint64_t axrcv_rsvdata_to : 1;
+        uint64_t axrcv_dlo_to : 1;
+        uint64_t axrcv_dlo_err : 1;
+        uint64_t axpush_wrerr : 1;
+        uint64_t oci_bad_reg_addr : 1;
+        uint64_t illegal_cache_op : 1;
+        uint64_t internal_err : 1;
+        uint64_t bcde_oci_dataerr : 1;
+        uint64_t bcde_ce : 1;
+        uint64_t bcde_ue_err : 1;
+        uint64_t bcde_sue_err : 1;
+        uint64_t bcde_rddatato_err : 1;
+        uint64_t bcde_pb_adrerr : 1;
+        uint64_t bcde_pb_ack_dead : 1;
+        uint64_t bcde_setup_err : 1;
+        uint64_t bcue_oci_dataerr : 1;
+        uint64_t bcue_pb_adrerr : 1;
+        uint64_t bcue_pb_ack_dead : 1;
+        uint64_t bcue_setup_err : 1;
+        uint64_t pb_crespto : 1;
+        uint64_t pb_ackdead_fw : 1;
+        uint64_t pb_badcresp : 1;
+        uint64_t pb_wradrerr_fw : 1;
+        uint64_t pb_parity_err : 1;
+        uint64_t pb_unexpdata : 1;
+        uint64_t pb_unexpcresp : 1;
+        uint64_t oci_rereqto : 1;
+        uint64_t oci_wrpar_err : 1;
+        uint64_t oci_slave_init : 1;
+        uint64_t pb_ce_fw : 1;
+        uint64_t pb_ue_fw : 1;
+        uint64_t pb_sue_fw : 1;
+        uint64_t pb_rddatato_fw : 1;
+        uint64_t pb_rdadrerr_fw : 1;
+        uint64_t oci_apar_err : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_fir_and_t;
+
+
+
+typedef union pba_fir_or {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t oci_apar_err : 1;
+        uint64_t pb_rdadrerr_fw : 1;
+        uint64_t pb_rddatato_fw : 1;
+        uint64_t pb_sue_fw : 1;
+        uint64_t pb_ue_fw : 1;
+        uint64_t pb_ce_fw : 1;
+        uint64_t oci_slave_init : 1;
+        uint64_t oci_wrpar_err : 1;
+        uint64_t oci_rereqto : 1;
+        uint64_t pb_unexpcresp : 1;
+        uint64_t pb_unexpdata : 1;
+        uint64_t pb_parity_err : 1;
+        uint64_t pb_wradrerr_fw : 1;
+        uint64_t pb_badcresp : 1;
+        uint64_t pb_ackdead_fw : 1;
+        uint64_t pb_crespto : 1;
+        uint64_t bcue_setup_err : 1;
+        uint64_t bcue_pb_ack_dead : 1;
+        uint64_t bcue_pb_adrerr : 1;
+        uint64_t bcue_oci_dataerr : 1;
+        uint64_t bcde_setup_err : 1;
+        uint64_t bcde_pb_ack_dead : 1;
+        uint64_t bcde_pb_adrerr : 1;
+        uint64_t bcde_rddatato_err : 1;
+        uint64_t bcde_sue_err : 1;
+        uint64_t bcde_ue_err : 1;
+        uint64_t bcde_ce : 1;
+        uint64_t bcde_oci_dataerr : 1;
+        uint64_t internal_err : 1;
+        uint64_t illegal_cache_op : 1;
+        uint64_t oci_bad_reg_addr : 1;
+        uint64_t axpush_wrerr : 1;
+        uint64_t axrcv_dlo_err : 1;
+        uint64_t axrcv_dlo_to : 1;
+        uint64_t axrcv_rsvdata_to : 1;
+        uint64_t axflow_err : 1;
+        uint64_t axsnd_dhi_rtyto : 1;
+        uint64_t axsnd_dlo_rtyto : 1;
+        uint64_t axsnd_rsvto : 1;
+        uint64_t axsnd_rsverr : 1;
+        uint64_t reserved : 4;
+        uint64_t fir_parity_error : 1;
+        uint64_t _reserved0 : 19;
+#else
+        uint64_t _reserved0 : 19;
+        uint64_t fir_parity_error : 1;
+        uint64_t reserved : 4;
+        uint64_t axsnd_rsverr : 1;
+        uint64_t axsnd_rsvto : 1;
+        uint64_t axsnd_dlo_rtyto : 1;
+        uint64_t axsnd_dhi_rtyto : 1;
+        uint64_t axflow_err : 1;
+        uint64_t axrcv_rsvdata_to : 1;
+        uint64_t axrcv_dlo_to : 1;
+        uint64_t axrcv_dlo_err : 1;
+        uint64_t axpush_wrerr : 1;
+        uint64_t oci_bad_reg_addr : 1;
+        uint64_t illegal_cache_op : 1;
+        uint64_t internal_err : 1;
+        uint64_t bcde_oci_dataerr : 1;
+        uint64_t bcde_ce : 1;
+        uint64_t bcde_ue_err : 1;
+        uint64_t bcde_sue_err : 1;
+        uint64_t bcde_rddatato_err : 1;
+        uint64_t bcde_pb_adrerr : 1;
+        uint64_t bcde_pb_ack_dead : 1;
+        uint64_t bcde_setup_err : 1;
+        uint64_t bcue_oci_dataerr : 1;
+        uint64_t bcue_pb_adrerr : 1;
+        uint64_t bcue_pb_ack_dead : 1;
+        uint64_t bcue_setup_err : 1;
+        uint64_t pb_crespto : 1;
+        uint64_t pb_ackdead_fw : 1;
+        uint64_t pb_badcresp : 1;
+        uint64_t pb_wradrerr_fw : 1;
+        uint64_t pb_parity_err : 1;
+        uint64_t pb_unexpdata : 1;
+        uint64_t pb_unexpcresp : 1;
+        uint64_t oci_rereqto : 1;
+        uint64_t oci_wrpar_err : 1;
+        uint64_t oci_slave_init : 1;
+        uint64_t pb_ce_fw : 1;
+        uint64_t pb_ue_fw : 1;
+        uint64_t pb_sue_fw : 1;
+        uint64_t pb_rddatato_fw : 1;
+        uint64_t pb_rdadrerr_fw : 1;
+        uint64_t oci_apar_err : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_fir_or_t;
+
+
+
+typedef union pba_fir_mask {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t mask : 44;
+        uint64_t _reserved0 : 20;
+#else
+        uint64_t _reserved0 : 20;
+        uint64_t mask : 44;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_fir_mask_t;
+
+
+
+typedef union pba_fir_mask_and {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t mask : 44;
+        uint64_t _reserved0 : 20;
+#else
+        uint64_t _reserved0 : 20;
+        uint64_t mask : 44;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_fir_mask_and_t;
+
+
+
+typedef union pba_fir_mask_or {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t mask : 44;
+        uint64_t _reserved0 : 20;
+#else
+        uint64_t _reserved0 : 20;
+        uint64_t mask : 44;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_fir_mask_or_t;
+
+
+
+typedef union pba_fir_action0 {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t fir_action0 : 44;
+        uint64_t _reserved0 : 20;
+#else
+        uint64_t _reserved0 : 20;
+        uint64_t fir_action0 : 44;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_fir_action0_t;
+
+
+
+typedef union pba_fir_action1 {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t fir_action1 : 44;
+        uint64_t _reserved0 : 20;
+#else
+        uint64_t _reserved0 : 20;
+        uint64_t fir_action1 : 44;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_fir_action1_t;
+
+
+
+typedef union pba_occ_action {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t occ_action_set : 44;
+        uint64_t _reserved0 : 20;
+#else
+        uint64_t _reserved0 : 20;
+        uint64_t occ_action_set : 44;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_occ_action_t;
+
+
+
+typedef union pba_rbufvaln {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t rd_slvnum : 2;
+        uint64_t cur_rd_addr : 23;
+        uint64_t spare1 : 3;
+        uint64_t prefetch : 1;
+        uint64_t spare2 : 2;
+        uint64_t abort : 1;
+        uint64_t spare3 : 1;
+        uint64_t buffer_status : 7;
+        uint64_t spare4 : 4;
+        uint64_t _reserved0 : 20;
+#else
+        uint64_t _reserved0 : 20;
+        uint64_t spare4 : 4;
+        uint64_t buffer_status : 7;
+        uint64_t spare3 : 1;
+        uint64_t abort : 1;
+        uint64_t spare2 : 2;
+        uint64_t prefetch : 1;
+        uint64_t spare1 : 3;
+        uint64_t cur_rd_addr : 23;
+        uint64_t rd_slvnum : 2;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_rbufvaln_t;
+
+
+
+typedef union pba_wbufvaln {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t wr_slvnum : 2;
+        uint64_t start_wr_addr : 30;
+        uint64_t spare1 : 3;
+        uint64_t wr_buffer_status : 5;
+        uint64_t spare2 : 1;
+        uint64_t wr_byte_count : 7;
+        uint64_t spare3 : 16;
+#else
+        uint64_t spare3 : 16;
+        uint64_t wr_byte_count : 7;
+        uint64_t spare2 : 1;
+        uint64_t wr_buffer_status : 5;
+        uint64_t spare1 : 3;
+        uint64_t start_wr_addr : 30;
+        uint64_t wr_slvnum : 2;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_wbufvaln_t;
+
+
+
+typedef union pba_mode {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t reserved0 : 4;
+        uint64_t dis_rearb : 1;
+        uint64_t reserved1 : 1;
+        uint64_t dis_slave_rdpipe : 1;
+        uint64_t dis_slave_wrpipe : 1;
+        uint64_t en_marker_ack : 1;
+        uint64_t dis_slvmatch_order : 1;
+        uint64_t en_second_wrbuf : 1;
+        uint64_t dis_rerequest_to : 1;
+        uint64_t inject_type : 2;
+        uint64_t inject_mode : 2;
+        uint64_t pba_region : 2;
+        uint64_t oci_marker_space : 3;
+        uint64_t bcde_ocitrans : 2;
+        uint64_t bcue_ocitrans : 2;
+        uint64_t dis_master_rd_pipe : 1;
+        uint64_t dis_master_wr_pipe : 1;
+        uint64_t en_slave_fairness : 1;
+        uint64_t en_ecvent_count : 1;
+        uint64_t pb_noci_event_sel : 1;
+        uint64_t slv_event_mux : 2;
+        uint64_t enable_debug_bus : 1;
+        uint64_t debug_pb_not_oci : 1;
+        uint64_t debug_oci_mode : 5;
+        uint64_t reserved2 : 1;
+        uint64_t ocislv_fairness_mask : 5;
+        uint64_t ocislv_rereq_hang_div : 5;
+        uint64_t dis_chgrate_count : 1;
+        uint64_t pbreq_event_mux : 2;
+        uint64_t _reserved0 : 11;
+#else
+        uint64_t _reserved0 : 11;
+        uint64_t pbreq_event_mux : 2;
+        uint64_t dis_chgrate_count : 1;
+        uint64_t ocislv_rereq_hang_div : 5;
+        uint64_t ocislv_fairness_mask : 5;
+        uint64_t reserved2 : 1;
+        uint64_t debug_oci_mode : 5;
+        uint64_t debug_pb_not_oci : 1;
+        uint64_t enable_debug_bus : 1;
+        uint64_t slv_event_mux : 2;
+        uint64_t pb_noci_event_sel : 1;
+        uint64_t en_ecvent_count : 1;
+        uint64_t en_slave_fairness : 1;
+        uint64_t dis_master_wr_pipe : 1;
+        uint64_t dis_master_rd_pipe : 1;
+        uint64_t bcue_ocitrans : 2;
+        uint64_t bcde_ocitrans : 2;
+        uint64_t oci_marker_space : 3;
+        uint64_t pba_region : 2;
+        uint64_t inject_mode : 2;
+        uint64_t inject_type : 2;
+        uint64_t dis_rerequest_to : 1;
+        uint64_t en_second_wrbuf : 1;
+        uint64_t dis_slvmatch_order : 1;
+        uint64_t en_marker_ack : 1;
+        uint64_t dis_slave_wrpipe : 1;
+        uint64_t dis_slave_rdpipe : 1;
+        uint64_t reserved1 : 1;
+        uint64_t dis_rearb : 1;
+        uint64_t reserved0 : 4;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_mode_t;
+
+
+
+typedef union pba_slvrst {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t set : 3;
+        uint64_t notimp1 : 1;
+        uint64_t in_prog : 4;
+        uint64_t busy_status : 4;
+        uint64_t _reserved0 : 52;
+#else
+        uint64_t _reserved0 : 52;
+        uint64_t busy_status : 4;
+        uint64_t in_prog : 4;
+        uint64_t notimp1 : 1;
+        uint64_t set : 3;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_slvrst_t;
+
+
+
+typedef union pba_slvctln {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t enable : 1;
+        uint64_t mid_match_value : 3;
+        uint64_t _reserved0 : 1;
+        uint64_t mid_care_mask : 3;
+        uint64_t write_ttype : 3;
+        uint64_t _reserved1 : 4;
+        uint64_t read_ttype : 1;
+        uint64_t read_prefetch_ctl : 2;
+        uint64_t buf_invalidate_ctl : 1;
+        uint64_t buf_alloc_w : 1;
+        uint64_t buf_alloc_a : 1;
+        uint64_t buf_alloc_b : 1;
+        uint64_t buf_alloc_c : 1;
+        uint64_t _reserved2 : 1;
+        uint64_t dis_write_gather : 1;
+        uint64_t wr_gather_timeout : 3;
+        uint64_t write_tsize : 7;
+        uint64_t extaddr : 14;
+        uint64_t _reserved3 : 15;
+#else
+        uint64_t _reserved3 : 15;
+        uint64_t extaddr : 14;
+        uint64_t write_tsize : 7;
+        uint64_t wr_gather_timeout : 3;
+        uint64_t dis_write_gather : 1;
+        uint64_t _reserved2 : 1;
+        uint64_t buf_alloc_c : 1;
+        uint64_t buf_alloc_b : 1;
+        uint64_t buf_alloc_a : 1;
+        uint64_t buf_alloc_w : 1;
+        uint64_t buf_invalidate_ctl : 1;
+        uint64_t read_prefetch_ctl : 2;
+        uint64_t read_ttype : 1;
+        uint64_t _reserved1 : 4;
+        uint64_t write_ttype : 3;
+        uint64_t mid_care_mask : 3;
+        uint64_t _reserved0 : 1;
+        uint64_t mid_match_value : 3;
+        uint64_t enable : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_slvctln_t;
+
+
+
+typedef union pba_bcde_ctl {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t stop : 1;
+        uint64_t start : 1;
+        uint64_t _reserved0 : 62;
+#else
+        uint64_t _reserved0 : 62;
+        uint64_t start : 1;
+        uint64_t stop : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_bcde_ctl_t;
+
+#endif // __ASSEMBLER__
+#define PBA_BCDE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
+#define PBA_BCDE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
+#ifndef __ASSEMBLER__
+
+
+typedef union pba_bcde_set {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t _reserved0 : 2;
+        uint64_t copy_length : 6;
+        uint64_t _reserved1 : 56;
+#else
+        uint64_t _reserved1 : 56;
+        uint64_t copy_length : 6;
+        uint64_t _reserved0 : 2;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_bcde_set_t;
+
+
+
+typedef union pba_bcde_status {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t running : 1;
+        uint64_t waiting : 1;
+        uint64_t wrcmp : 6;
+        uint64_t _reserved0 : 6;
+        uint64_t rdcmp : 6;
+        uint64_t debug : 9;
+        uint64_t stopped : 1;
+        uint64_t error : 1;
+        uint64_t done : 1;
+        uint64_t _reserved1 : 32;
+#else
+        uint64_t _reserved1 : 32;
+        uint64_t done : 1;
+        uint64_t error : 1;
+        uint64_t stopped : 1;
+        uint64_t debug : 9;
+        uint64_t rdcmp : 6;
+        uint64_t _reserved0 : 6;
+        uint64_t wrcmp : 6;
+        uint64_t waiting : 1;
+        uint64_t running : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_bcde_status_t;
+
+
+
+typedef union pba_bcde_pbadr {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t _reserved0 : 2;
+        uint64_t pb_offset : 23;
+        uint64_t _reserved1 : 2;
+        uint64_t extaddr : 14;
+        uint64_t _reserved2 : 23;
+#else
+        uint64_t _reserved2 : 23;
+        uint64_t extaddr : 14;
+        uint64_t _reserved1 : 2;
+        uint64_t pb_offset : 23;
+        uint64_t _reserved0 : 2;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_bcde_pbadr_t;
+
+
+
+typedef union pba_bcde_ocibar {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t addr : 25;
+        uint64_t _reserved0 : 39;
+#else
+        uint64_t _reserved0 : 39;
+        uint64_t addr : 25;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_bcde_ocibar_t;
+
+
+
+typedef union pba_bcue_ctl {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t stop : 1;
+        uint64_t start : 1;
+        uint64_t _reserved0 : 62;
+#else
+        uint64_t _reserved0 : 62;
+        uint64_t start : 1;
+        uint64_t stop : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_bcue_ctl_t;
+
+#endif // __ASSEMBLER__
+#define PBA_BCUE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
+#define PBA_BCUE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
+#ifndef __ASSEMBLER__
+
+
+typedef union pba_bcue_set {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t _reserved0 : 2;
+        uint64_t copy_length : 6;
+        uint64_t _reserved1 : 56;
+#else
+        uint64_t _reserved1 : 56;
+        uint64_t copy_length : 6;
+        uint64_t _reserved0 : 2;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_bcue_set_t;
+
+
+
+typedef union pba_bcue_status {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t running : 1;
+        uint64_t waiting : 1;
+        uint64_t wrcmp : 6;
+        uint64_t _reserved0 : 6;
+        uint64_t rdcmp : 6;
+        uint64_t debug : 9;
+        uint64_t stopped : 1;
+        uint64_t error : 1;
+        uint64_t done : 1;
+        uint64_t _reserved1 : 32;
+#else
+        uint64_t _reserved1 : 32;
+        uint64_t done : 1;
+        uint64_t error : 1;
+        uint64_t stopped : 1;
+        uint64_t debug : 9;
+        uint64_t rdcmp : 6;
+        uint64_t _reserved0 : 6;
+        uint64_t wrcmp : 6;
+        uint64_t waiting : 1;
+        uint64_t running : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_bcue_status_t;
+
+
+
+typedef union pba_bcue_pbadr {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t _reserved0 : 2;
+        uint64_t pb_offset : 23;
+        uint64_t _reserved1 : 2;
+        uint64_t extaddr : 14;
+        uint64_t _reserved2 : 23;
+#else
+        uint64_t _reserved2 : 23;
+        uint64_t extaddr : 14;
+        uint64_t _reserved1 : 2;
+        uint64_t pb_offset : 23;
+        uint64_t _reserved0 : 2;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_bcue_pbadr_t;
+
+
+
+typedef union pba_bcue_ocibar {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t addr : 25;
+        uint64_t _reserved0 : 39;
+#else
+        uint64_t _reserved0 : 39;
+        uint64_t addr : 25;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_bcue_ocibar_t;
+
+
+
+typedef union pba_pbocrn {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t _reserved0 : 16;
+        uint64_t event : 16;
+        uint64_t _reserved1 : 12;
+        uint64_t accum : 20;
+#else
+        uint64_t accum : 20;
+        uint64_t _reserved1 : 12;
+        uint64_t event : 16;
+        uint64_t _reserved0 : 16;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_pbocrn_t;
+
+
+
+typedef union pba_xsndtx {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t snd_scope : 3;
+        uint64_t snd_qid : 1;
+        uint64_t snd_type : 1;
+        uint64_t snd_reservation : 1;
+        uint64_t spare1 : 2;
+        uint64_t snd_nodeid : 3;
+        uint64_t snd_chipid : 3;
+        uint64_t spare2 : 2;
+        uint64_t _reserved0 : 48;
+#else
+        uint64_t _reserved0 : 48;
+        uint64_t spare2 : 2;
+        uint64_t snd_chipid : 3;
+        uint64_t snd_nodeid : 3;
+        uint64_t spare1 : 2;
+        uint64_t snd_reservation : 1;
+        uint64_t snd_type : 1;
+        uint64_t snd_qid : 1;
+        uint64_t snd_scope : 3;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_xsndtx_t;
+
+
+
+typedef union pba_xcfg {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t pbax_en : 1;
+        uint64_t reservation_en : 1;
+        uint64_t snd_reset : 1;
+        uint64_t rcv_reset : 1;
+        uint64_t rcv_nodeid : 3;
+        uint64_t rcv_chipid : 3;
+        uint64_t spare1 : 2;
+        uint64_t rcv_brdcst_group : 8;
+        uint64_t rcv_datalo_thresh : 8;
+        uint64_t snd_retry_thresh : 8;
+        uint64_t snd_rsv_req_thresh : 2;
+        uint64_t snd_retry_count_overcom : 1;
+        uint64_t _reserved0 : 25;
+#else
+        uint64_t _reserved0 : 25;
+        uint64_t snd_retry_count_overcom : 1;
+        uint64_t snd_rsv_req_thresh : 2;
+        uint64_t snd_retry_thresh : 8;
+        uint64_t rcv_datalo_thresh : 8;
+        uint64_t rcv_brdcst_group : 8;
+        uint64_t spare1 : 2;
+        uint64_t rcv_chipid : 3;
+        uint64_t rcv_nodeid : 3;
+        uint64_t rcv_reset : 1;
+        uint64_t snd_reset : 1;
+        uint64_t reservation_en : 1;
+        uint64_t pbax_en : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_xcfg_t;
+
+
+
+typedef union pba_xsndstat {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t snd_in_progress : 1;
+        uint64_t snd_error : 1;
+        uint64_t snd_status : 6;
+        uint64_t snd_retry_count : 8;
+        uint64_t _reserved0 : 48;
+#else
+        uint64_t _reserved0 : 48;
+        uint64_t snd_retry_count : 8;
+        uint64_t snd_status : 6;
+        uint64_t snd_error : 1;
+        uint64_t snd_in_progress : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_xsndstat_t;
+
+
+
+typedef union pba_xsnddat {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t pbax_datahi : 32;
+        uint64_t pbax_datalo : 32;
+#else
+        uint64_t pbax_datalo : 32;
+        uint64_t pbax_datahi : 32;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_xsnddat_t;
+
+
+
+typedef union pba_xrcvstat {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t rcv_in_progress : 1;
+        uint64_t rcv_error : 1;
+        uint64_t rcv_write_in_progress : 1;
+        uint64_t rcv_reservation_set : 1;
+        uint64_t rcv_capture : 14;
+        uint64_t _reserved0 : 46;
+#else
+        uint64_t _reserved0 : 46;
+        uint64_t rcv_capture : 14;
+        uint64_t rcv_reservation_set : 1;
+        uint64_t rcv_write_in_progress : 1;
+        uint64_t rcv_error : 1;
+        uint64_t rcv_in_progress : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_xrcvstat_t;
+
+
+
+typedef union pba_xshbrn {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t push_start : 29;
+        uint64_t _reserved0 : 35;
+#else
+        uint64_t _reserved0 : 35;
+        uint64_t push_start : 29;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_xshbrn_t;
+
+
+
+typedef union pba_xshcsn {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t push_full : 1;
+        uint64_t push_empty : 1;
+        uint64_t spare1 : 2;
+        uint64_t push_intr_action : 2;
+        uint64_t push_length : 5;
+        uint64_t notimp1 : 2;
+        uint64_t push_write_ptr : 5;
+        uint64_t notimp2 : 3;
+        uint64_t push_read_ptr : 5;
+        uint64_t notimp3 : 5;
+        uint64_t push_enable : 1;
+        uint64_t _reserved0 : 32;
+#else
+        uint64_t _reserved0 : 32;
+        uint64_t push_enable : 1;
+        uint64_t notimp3 : 5;
+        uint64_t push_read_ptr : 5;
+        uint64_t notimp2 : 3;
+        uint64_t push_write_ptr : 5;
+        uint64_t notimp1 : 2;
+        uint64_t push_length : 5;
+        uint64_t push_intr_action : 2;
+        uint64_t spare1 : 2;
+        uint64_t push_empty : 1;
+        uint64_t push_full : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_xshcsn_t;
+
+
+
+typedef union pba_xshincn {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint64_t reserved : 64;
+#else
+        uint64_t reserved : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_xshincn_t;
+
+
+#endif // __ASSEMBLER__
+#endif // __PBA_FIRMWARE_REGISTERS_H__
+
+
diff --git a/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/pba_firmware_registers.h b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/pba_firmware_registers.h
new file mode 100644
index 000000000..be6f860b7
--- /dev/null
+++ b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/pba_firmware_registers.h
@@ -0,0 +1,2108 @@
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/pba_firmware_registers.h $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+#ifndef __PBA_FIRMWARE_REGISTERS_H__
+#define __PBA_FIRMWARE_REGISTERS_H__
+
+#ifndef SIXTYFOUR_BIT_CONSTANT
+#ifdef __ASSEMBLER__
+#define SIXTYFOUR_BIT_CONSTANT(x) x
+#else
+#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
+#endif
+#endif
+
+#ifndef __ASSEMBLER__
+
+// $Id$
+
+/// \file pba_firmware_registers.h
+/// \brief C register structs for the PBA unit
+
+// *** WARNING *** - This file is generated automatically, do not edit.
+
+#include <stdint.h>
+
+
+
+typedef union pba_barn {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t cmd_scope : 3;
+	uint64_t reserved0 : 1;
+	uint64_t reserved1 : 10;
+	uint64_t addr : 30;
+	uint64_t _reserved0 : 20;
+#else
+	uint64_t _reserved0 : 20;
+	uint64_t addr : 30;
+	uint64_t reserved1 : 10;
+	uint64_t reserved0 : 1;
+	uint64_t cmd_scope : 3;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_barn_t;
+
+#endif // __ASSEMBLER__
+#define PBA_BARN_CMD_SCOPE_MASK SIXTYFOUR_BIT_CONSTANT(0xe000000000000000)
+#define PBA_BARN_ADDR_MASK SIXTYFOUR_BIT_CONSTANT(0x0003fffffff00000)
+#ifndef __ASSEMBLER__
+
+
+typedef union pba_barmskn {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t reserved0 : 23;
+	uint64_t mask : 21;
+	uint64_t _reserved0 : 20;
+#else
+	uint64_t _reserved0 : 20;
+	uint64_t mask : 21;
+	uint64_t reserved0 : 23;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_barmskn_t;
+
+#endif // __ASSEMBLER__
+#define PBA_BARMSKN_MASK_MASK SIXTYFOUR_BIT_CONSTANT(0x000001fffff00000)
+#ifndef __ASSEMBLER__
+
+
+typedef union pba_fir {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t oci_apar_err : 1;
+	uint64_t pb_rdadrerr_fw : 1;
+	uint64_t pb_rddatato_fw : 1;
+	uint64_t pb_sue_fw : 1;
+	uint64_t pb_ue_fw : 1;
+	uint64_t pb_ce_fw : 1;
+	uint64_t oci_slave_init : 1;
+	uint64_t oci_wrpar_err : 1;
+	uint64_t oci_rereqto : 1;
+	uint64_t pb_unexpcresp : 1;
+	uint64_t pb_unexpdata : 1;
+	uint64_t pb_parity_err : 1;
+	uint64_t pb_wradrerr_fw : 1;
+	uint64_t pb_badcresp : 1;
+	uint64_t pb_ackdead_fw : 1;
+	uint64_t pb_crespto : 1;
+	uint64_t bcue_setup_err : 1;
+	uint64_t bcue_pb_ack_dead : 1;
+	uint64_t bcue_pb_adrerr : 1;
+	uint64_t bcue_oci_dataerr : 1;
+	uint64_t bcde_setup_err : 1;
+	uint64_t bcde_pb_ack_dead : 1;
+	uint64_t bcde_pb_adrerr : 1;
+	uint64_t bcde_rddatato_err : 1;
+	uint64_t bcde_sue_err : 1;
+	uint64_t bcde_ue_err : 1;
+	uint64_t bcde_ce : 1;
+	uint64_t bcde_oci_dataerr : 1;
+	uint64_t internal_err : 1;
+	uint64_t illegal_cache_op : 1;
+	uint64_t oci_bad_reg_addr : 1;
+	uint64_t axpush_wrerr : 1;
+	uint64_t axrcv_dlo_err : 1;
+	uint64_t axrcv_dlo_to : 1;
+	uint64_t axrcv_rsvdata_to : 1;
+	uint64_t axflow_err : 1;
+	uint64_t axsnd_dhi_rtyto : 1;
+	uint64_t axsnd_dlo_rtyto : 1;
+	uint64_t axsnd_rsvto : 1;
+	uint64_t axsnd_rsverr : 1;
+	uint64_t reserved : 4;
+	uint64_t fir_parity_error : 1;
+	uint64_t _reserved0 : 19;
+#else
+	uint64_t _reserved0 : 19;
+	uint64_t fir_parity_error : 1;
+	uint64_t reserved : 4;
+	uint64_t axsnd_rsverr : 1;
+	uint64_t axsnd_rsvto : 1;
+	uint64_t axsnd_dlo_rtyto : 1;
+	uint64_t axsnd_dhi_rtyto : 1;
+	uint64_t axflow_err : 1;
+	uint64_t axrcv_rsvdata_to : 1;
+	uint64_t axrcv_dlo_to : 1;
+	uint64_t axrcv_dlo_err : 1;
+	uint64_t axpush_wrerr : 1;
+	uint64_t oci_bad_reg_addr : 1;
+	uint64_t illegal_cache_op : 1;
+	uint64_t internal_err : 1;
+	uint64_t bcde_oci_dataerr : 1;
+	uint64_t bcde_ce : 1;
+	uint64_t bcde_ue_err : 1;
+	uint64_t bcde_sue_err : 1;
+	uint64_t bcde_rddatato_err : 1;
+	uint64_t bcde_pb_adrerr : 1;
+	uint64_t bcde_pb_ack_dead : 1;
+	uint64_t bcde_setup_err : 1;
+	uint64_t bcue_oci_dataerr : 1;
+	uint64_t bcue_pb_adrerr : 1;
+	uint64_t bcue_pb_ack_dead : 1;
+	uint64_t bcue_setup_err : 1;
+	uint64_t pb_crespto : 1;
+	uint64_t pb_ackdead_fw : 1;
+	uint64_t pb_badcresp : 1;
+	uint64_t pb_wradrerr_fw : 1;
+	uint64_t pb_parity_err : 1;
+	uint64_t pb_unexpdata : 1;
+	uint64_t pb_unexpcresp : 1;
+	uint64_t oci_rereqto : 1;
+	uint64_t oci_wrpar_err : 1;
+	uint64_t oci_slave_init : 1;
+	uint64_t pb_ce_fw : 1;
+	uint64_t pb_ue_fw : 1;
+	uint64_t pb_sue_fw : 1;
+	uint64_t pb_rddatato_fw : 1;
+	uint64_t pb_rdadrerr_fw : 1;
+	uint64_t oci_apar_err : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_fir_t;
+
+#endif // __ASSEMBLER__
+#define PBA_FIR_OCI_APAR_ERR SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
+#define PBA_FIR_PB_RDADRERR_FW SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
+#define PBA_FIR_PB_RDDATATO_FW SIXTYFOUR_BIT_CONSTANT(0x2000000000000000)
+#define PBA_FIR_PB_SUE_FW SIXTYFOUR_BIT_CONSTANT(0x1000000000000000)
+#define PBA_FIR_PB_UE_FW SIXTYFOUR_BIT_CONSTANT(0x0800000000000000)
+#define PBA_FIR_PB_CE_FW SIXTYFOUR_BIT_CONSTANT(0x0400000000000000)
+#define PBA_FIR_OCI_SLAVE_INIT SIXTYFOUR_BIT_CONSTANT(0x0200000000000000)
+#define PBA_FIR_OCI_WRPAR_ERR SIXTYFOUR_BIT_CONSTANT(0x0100000000000000)
+#define PBA_FIR_OCI_REREQTO SIXTYFOUR_BIT_CONSTANT(0x0080000000000000)
+#define PBA_FIR_PB_UNEXPCRESP SIXTYFOUR_BIT_CONSTANT(0x0040000000000000)
+#define PBA_FIR_PB_UNEXPDATA SIXTYFOUR_BIT_CONSTANT(0x0020000000000000)
+#define PBA_FIR_PB_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0010000000000000)
+#define PBA_FIR_PB_WRADRERR_FW SIXTYFOUR_BIT_CONSTANT(0x0008000000000000)
+#define PBA_FIR_PB_BADCRESP SIXTYFOUR_BIT_CONSTANT(0x0004000000000000)
+#define PBA_FIR_PB_ACKDEAD_FW SIXTYFOUR_BIT_CONSTANT(0x0002000000000000)
+#define PBA_FIR_PB_CRESPTO SIXTYFOUR_BIT_CONSTANT(0x0001000000000000)
+#define PBA_FIR_BCUE_SETUP_ERR SIXTYFOUR_BIT_CONSTANT(0x0000800000000000)
+#define PBA_FIR_BCUE_PB_ACK_DEAD SIXTYFOUR_BIT_CONSTANT(0x0000400000000000)
+#define PBA_FIR_BCUE_PB_ADRERR SIXTYFOUR_BIT_CONSTANT(0x0000200000000000)
+#define PBA_FIR_BCUE_OCI_DATAERR SIXTYFOUR_BIT_CONSTANT(0x0000100000000000)
+#define PBA_FIR_BCDE_SETUP_ERR SIXTYFOUR_BIT_CONSTANT(0x0000080000000000)
+#define PBA_FIR_BCDE_PB_ACK_DEAD SIXTYFOUR_BIT_CONSTANT(0x0000040000000000)
+#define PBA_FIR_BCDE_PB_ADRERR SIXTYFOUR_BIT_CONSTANT(0x0000020000000000)
+#define PBA_FIR_BCDE_RDDATATO_ERR SIXTYFOUR_BIT_CONSTANT(0x0000010000000000)
+#define PBA_FIR_BCDE_SUE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000008000000000)
+#define PBA_FIR_BCDE_UE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000004000000000)
+#define PBA_FIR_BCDE_CE SIXTYFOUR_BIT_CONSTANT(0x0000002000000000)
+#define PBA_FIR_BCDE_OCI_DATAERR SIXTYFOUR_BIT_CONSTANT(0x0000001000000000)
+#define PBA_FIR_INTERNAL_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000800000000)
+#define PBA_FIR_ILLEGAL_CACHE_OP SIXTYFOUR_BIT_CONSTANT(0x0000000400000000)
+#define PBA_FIR_OCI_BAD_REG_ADDR SIXTYFOUR_BIT_CONSTANT(0x0000000200000000)
+#define PBA_FIR_AXPUSH_WRERR SIXTYFOUR_BIT_CONSTANT(0x0000000100000000)
+#define PBA_FIR_AXRCV_DLO_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000080000000)
+#define PBA_FIR_AXRCV_DLO_TO SIXTYFOUR_BIT_CONSTANT(0x0000000040000000)
+#define PBA_FIR_AXRCV_RSVDATA_TO SIXTYFOUR_BIT_CONSTANT(0x0000000020000000)
+#define PBA_FIR_AXFLOW_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000010000000)
+#define PBA_FIR_AXSND_DHI_RTYTO SIXTYFOUR_BIT_CONSTANT(0x0000000008000000)
+#define PBA_FIR_AXSND_DLO_RTYTO SIXTYFOUR_BIT_CONSTANT(0x0000000004000000)
+#define PBA_FIR_AXSND_RSVTO SIXTYFOUR_BIT_CONSTANT(0x0000000002000000)
+#define PBA_FIR_AXSND_RSVERR SIXTYFOUR_BIT_CONSTANT(0x0000000001000000)
+#define PBA_FIR_FIR_PARITY_ERROR SIXTYFOUR_BIT_CONSTANT(0x0000000000080000)
+#ifndef __ASSEMBLER__
+
+
+typedef union pba_fir_and {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t oci_apar_err : 1;
+	uint64_t pb_rdadrerr_fw : 1;
+	uint64_t pb_rddatato_fw : 1;
+	uint64_t pb_sue_fw : 1;
+	uint64_t pb_ue_fw : 1;
+	uint64_t pb_ce_fw : 1;
+	uint64_t oci_slave_init : 1;
+	uint64_t oci_wrpar_err : 1;
+	uint64_t oci_rereqto : 1;
+	uint64_t pb_unexpcresp : 1;
+	uint64_t pb_unexpdata : 1;
+	uint64_t pb_parity_err : 1;
+	uint64_t pb_wradrerr_fw : 1;
+	uint64_t pb_badcresp : 1;
+	uint64_t pb_ackdead_fw : 1;
+	uint64_t pb_crespto : 1;
+	uint64_t bcue_setup_err : 1;
+	uint64_t bcue_pb_ack_dead : 1;
+	uint64_t bcue_pb_adrerr : 1;
+	uint64_t bcue_oci_dataerr : 1;
+	uint64_t bcde_setup_err : 1;
+	uint64_t bcde_pb_ack_dead : 1;
+	uint64_t bcde_pb_adrerr : 1;
+	uint64_t bcde_rddatato_err : 1;
+	uint64_t bcde_sue_err : 1;
+	uint64_t bcde_ue_err : 1;
+	uint64_t bcde_ce : 1;
+	uint64_t bcde_oci_dataerr : 1;
+	uint64_t internal_err : 1;
+	uint64_t illegal_cache_op : 1;
+	uint64_t oci_bad_reg_addr : 1;
+	uint64_t axpush_wrerr : 1;
+	uint64_t axrcv_dlo_err : 1;
+	uint64_t axrcv_dlo_to : 1;
+	uint64_t axrcv_rsvdata_to : 1;
+	uint64_t axflow_err : 1;
+	uint64_t axsnd_dhi_rtyto : 1;
+	uint64_t axsnd_dlo_rtyto : 1;
+	uint64_t axsnd_rsvto : 1;
+	uint64_t axsnd_rsverr : 1;
+	uint64_t reserved : 4;
+	uint64_t fir_parity_error : 1;
+	uint64_t _reserved0 : 19;
+#else
+	uint64_t _reserved0 : 19;
+	uint64_t fir_parity_error : 1;
+	uint64_t reserved : 4;
+	uint64_t axsnd_rsverr : 1;
+	uint64_t axsnd_rsvto : 1;
+	uint64_t axsnd_dlo_rtyto : 1;
+	uint64_t axsnd_dhi_rtyto : 1;
+	uint64_t axflow_err : 1;
+	uint64_t axrcv_rsvdata_to : 1;
+	uint64_t axrcv_dlo_to : 1;
+	uint64_t axrcv_dlo_err : 1;
+	uint64_t axpush_wrerr : 1;
+	uint64_t oci_bad_reg_addr : 1;
+	uint64_t illegal_cache_op : 1;
+	uint64_t internal_err : 1;
+	uint64_t bcde_oci_dataerr : 1;
+	uint64_t bcde_ce : 1;
+	uint64_t bcde_ue_err : 1;
+	uint64_t bcde_sue_err : 1;
+	uint64_t bcde_rddatato_err : 1;
+	uint64_t bcde_pb_adrerr : 1;
+	uint64_t bcde_pb_ack_dead : 1;
+	uint64_t bcde_setup_err : 1;
+	uint64_t bcue_oci_dataerr : 1;
+	uint64_t bcue_pb_adrerr : 1;
+	uint64_t bcue_pb_ack_dead : 1;
+	uint64_t bcue_setup_err : 1;
+	uint64_t pb_crespto : 1;
+	uint64_t pb_ackdead_fw : 1;
+	uint64_t pb_badcresp : 1;
+	uint64_t pb_wradrerr_fw : 1;
+	uint64_t pb_parity_err : 1;
+	uint64_t pb_unexpdata : 1;
+	uint64_t pb_unexpcresp : 1;
+	uint64_t oci_rereqto : 1;
+	uint64_t oci_wrpar_err : 1;
+	uint64_t oci_slave_init : 1;
+	uint64_t pb_ce_fw : 1;
+	uint64_t pb_ue_fw : 1;
+	uint64_t pb_sue_fw : 1;
+	uint64_t pb_rddatato_fw : 1;
+	uint64_t pb_rdadrerr_fw : 1;
+	uint64_t oci_apar_err : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_fir_and_t;
+
+
+
+typedef union pba_fir_or {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t oci_apar_err : 1;
+	uint64_t pb_rdadrerr_fw : 1;
+	uint64_t pb_rddatato_fw : 1;
+	uint64_t pb_sue_fw : 1;
+	uint64_t pb_ue_fw : 1;
+	uint64_t pb_ce_fw : 1;
+	uint64_t oci_slave_init : 1;
+	uint64_t oci_wrpar_err : 1;
+	uint64_t oci_rereqto : 1;
+	uint64_t pb_unexpcresp : 1;
+	uint64_t pb_unexpdata : 1;
+	uint64_t pb_parity_err : 1;
+	uint64_t pb_wradrerr_fw : 1;
+	uint64_t pb_badcresp : 1;
+	uint64_t pb_ackdead_fw : 1;
+	uint64_t pb_crespto : 1;
+	uint64_t bcue_setup_err : 1;
+	uint64_t bcue_pb_ack_dead : 1;
+	uint64_t bcue_pb_adrerr : 1;
+	uint64_t bcue_oci_dataerr : 1;
+	uint64_t bcde_setup_err : 1;
+	uint64_t bcde_pb_ack_dead : 1;
+	uint64_t bcde_pb_adrerr : 1;
+	uint64_t bcde_rddatato_err : 1;
+	uint64_t bcde_sue_err : 1;
+	uint64_t bcde_ue_err : 1;
+	uint64_t bcde_ce : 1;
+	uint64_t bcde_oci_dataerr : 1;
+	uint64_t internal_err : 1;
+	uint64_t illegal_cache_op : 1;
+	uint64_t oci_bad_reg_addr : 1;
+	uint64_t axpush_wrerr : 1;
+	uint64_t axrcv_dlo_err : 1;
+	uint64_t axrcv_dlo_to : 1;
+	uint64_t axrcv_rsvdata_to : 1;
+	uint64_t axflow_err : 1;
+	uint64_t axsnd_dhi_rtyto : 1;
+	uint64_t axsnd_dlo_rtyto : 1;
+	uint64_t axsnd_rsvto : 1;
+	uint64_t axsnd_rsverr : 1;
+	uint64_t reserved : 4;
+	uint64_t fir_parity_error : 1;
+	uint64_t _reserved0 : 19;
+#else
+	uint64_t _reserved0 : 19;
+	uint64_t fir_parity_error : 1;
+	uint64_t reserved : 4;
+	uint64_t axsnd_rsverr : 1;
+	uint64_t axsnd_rsvto : 1;
+	uint64_t axsnd_dlo_rtyto : 1;
+	uint64_t axsnd_dhi_rtyto : 1;
+	uint64_t axflow_err : 1;
+	uint64_t axrcv_rsvdata_to : 1;
+	uint64_t axrcv_dlo_to : 1;
+	uint64_t axrcv_dlo_err : 1;
+	uint64_t axpush_wrerr : 1;
+	uint64_t oci_bad_reg_addr : 1;
+	uint64_t illegal_cache_op : 1;
+	uint64_t internal_err : 1;
+	uint64_t bcde_oci_dataerr : 1;
+	uint64_t bcde_ce : 1;
+	uint64_t bcde_ue_err : 1;
+	uint64_t bcde_sue_err : 1;
+	uint64_t bcde_rddatato_err : 1;
+	uint64_t bcde_pb_adrerr : 1;
+	uint64_t bcde_pb_ack_dead : 1;
+	uint64_t bcde_setup_err : 1;
+	uint64_t bcue_oci_dataerr : 1;
+	uint64_t bcue_pb_adrerr : 1;
+	uint64_t bcue_pb_ack_dead : 1;
+	uint64_t bcue_setup_err : 1;
+	uint64_t pb_crespto : 1;
+	uint64_t pb_ackdead_fw : 1;
+	uint64_t pb_badcresp : 1;
+	uint64_t pb_wradrerr_fw : 1;
+	uint64_t pb_parity_err : 1;
+	uint64_t pb_unexpdata : 1;
+	uint64_t pb_unexpcresp : 1;
+	uint64_t oci_rereqto : 1;
+	uint64_t oci_wrpar_err : 1;
+	uint64_t oci_slave_init : 1;
+	uint64_t pb_ce_fw : 1;
+	uint64_t pb_ue_fw : 1;
+	uint64_t pb_sue_fw : 1;
+	uint64_t pb_rddatato_fw : 1;
+	uint64_t pb_rdadrerr_fw : 1;
+	uint64_t oci_apar_err : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_fir_or_t;
+
+
+
+typedef union pba_firmask {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t oci_apar_err : 1;
+	uint64_t pb_rdadrerr_fw : 1;
+	uint64_t pb_rddatato_fw : 1;
+	uint64_t pb_sue_fw : 1;
+	uint64_t pb_ue_fw : 1;
+	uint64_t pb_ce_fw : 1;
+	uint64_t oci_slave_init : 1;
+	uint64_t oci_wrpar_err : 1;
+	uint64_t oci_rereqto : 1;
+	uint64_t pb_unexpcresp : 1;
+	uint64_t pb_unexpdata : 1;
+	uint64_t pb_parity_err : 1;
+	uint64_t pb_wradrerr_fw : 1;
+	uint64_t pb_badcresp : 1;
+	uint64_t pb_ackdead_fw : 1;
+	uint64_t pb_crespto : 1;
+	uint64_t bcue_setup_err : 1;
+	uint64_t bcue_pb_ack_dead : 1;
+	uint64_t bcue_pb_adrerr : 1;
+	uint64_t bcue_oci_dataerr : 1;
+	uint64_t bcde_setup_err : 1;
+	uint64_t bcde_pb_ack_dead : 1;
+	uint64_t bcde_pb_adrerr : 1;
+	uint64_t bcde_rddatato_err : 1;
+	uint64_t bcde_sue_err : 1;
+	uint64_t bcde_ue_err : 1;
+	uint64_t bcde_ce : 1;
+	uint64_t bcde_oci_dataerr : 1;
+	uint64_t internal_err : 1;
+	uint64_t illegal_cache_op : 1;
+	uint64_t oci_bad_reg_addr : 1;
+	uint64_t axpush_wrerr : 1;
+	uint64_t axrcv_dlo_err : 1;
+	uint64_t axrcv_dlo_to : 1;
+	uint64_t axrcv_rsvdata_to : 1;
+	uint64_t axflow_err : 1;
+	uint64_t axsnd_dhi_rtyto : 1;
+	uint64_t axsnd_dlo_rtyto : 1;
+	uint64_t axsnd_rsvto : 1;
+	uint64_t axsnd_rsverr : 1;
+	uint64_t reserved : 4;
+	uint64_t fir_parity_error : 1;
+	uint64_t _reserved0 : 19;
+#else
+	uint64_t _reserved0 : 19;
+	uint64_t fir_parity_error : 1;
+	uint64_t reserved : 4;
+	uint64_t axsnd_rsverr : 1;
+	uint64_t axsnd_rsvto : 1;
+	uint64_t axsnd_dlo_rtyto : 1;
+	uint64_t axsnd_dhi_rtyto : 1;
+	uint64_t axflow_err : 1;
+	uint64_t axrcv_rsvdata_to : 1;
+	uint64_t axrcv_dlo_to : 1;
+	uint64_t axrcv_dlo_err : 1;
+	uint64_t axpush_wrerr : 1;
+	uint64_t oci_bad_reg_addr : 1;
+	uint64_t illegal_cache_op : 1;
+	uint64_t internal_err : 1;
+	uint64_t bcde_oci_dataerr : 1;
+	uint64_t bcde_ce : 1;
+	uint64_t bcde_ue_err : 1;
+	uint64_t bcde_sue_err : 1;
+	uint64_t bcde_rddatato_err : 1;
+	uint64_t bcde_pb_adrerr : 1;
+	uint64_t bcde_pb_ack_dead : 1;
+	uint64_t bcde_setup_err : 1;
+	uint64_t bcue_oci_dataerr : 1;
+	uint64_t bcue_pb_adrerr : 1;
+	uint64_t bcue_pb_ack_dead : 1;
+	uint64_t bcue_setup_err : 1;
+	uint64_t pb_crespto : 1;
+	uint64_t pb_ackdead_fw : 1;
+	uint64_t pb_badcresp : 1;
+	uint64_t pb_wradrerr_fw : 1;
+	uint64_t pb_parity_err : 1;
+	uint64_t pb_unexpdata : 1;
+	uint64_t pb_unexpcresp : 1;
+	uint64_t oci_rereqto : 1;
+	uint64_t oci_wrpar_err : 1;
+	uint64_t oci_slave_init : 1;
+	uint64_t pb_ce_fw : 1;
+	uint64_t pb_ue_fw : 1;
+	uint64_t pb_sue_fw : 1;
+	uint64_t pb_rddatato_fw : 1;
+	uint64_t pb_rdadrerr_fw : 1;
+	uint64_t oci_apar_err : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_firmask_t;
+
+
+
+typedef union pba_firmask_and {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t oci_apar_err : 1;
+	uint64_t pb_rdadrerr_fw : 1;
+	uint64_t pb_rddatato_fw : 1;
+	uint64_t pb_sue_fw : 1;
+	uint64_t pb_ue_fw : 1;
+	uint64_t pb_ce_fw : 1;
+	uint64_t oci_slave_init : 1;
+	uint64_t oci_wrpar_err : 1;
+	uint64_t oci_rereqto : 1;
+	uint64_t pb_unexpcresp : 1;
+	uint64_t pb_unexpdata : 1;
+	uint64_t pb_parity_err : 1;
+	uint64_t pb_wradrerr_fw : 1;
+	uint64_t pb_badcresp : 1;
+	uint64_t pb_ackdead_fw : 1;
+	uint64_t pb_crespto : 1;
+	uint64_t bcue_setup_err : 1;
+	uint64_t bcue_pb_ack_dead : 1;
+	uint64_t bcue_pb_adrerr : 1;
+	uint64_t bcue_oci_dataerr : 1;
+	uint64_t bcde_setup_err : 1;
+	uint64_t bcde_pb_ack_dead : 1;
+	uint64_t bcde_pb_adrerr : 1;
+	uint64_t bcde_rddatato_err : 1;
+	uint64_t bcde_sue_err : 1;
+	uint64_t bcde_ue_err : 1;
+	uint64_t bcde_ce : 1;
+	uint64_t bcde_oci_dataerr : 1;
+	uint64_t internal_err : 1;
+	uint64_t illegal_cache_op : 1;
+	uint64_t oci_bad_reg_addr : 1;
+	uint64_t axpush_wrerr : 1;
+	uint64_t axrcv_dlo_err : 1;
+	uint64_t axrcv_dlo_to : 1;
+	uint64_t axrcv_rsvdata_to : 1;
+	uint64_t axflow_err : 1;
+	uint64_t axsnd_dhi_rtyto : 1;
+	uint64_t axsnd_dlo_rtyto : 1;
+	uint64_t axsnd_rsvto : 1;
+	uint64_t axsnd_rsverr : 1;
+	uint64_t reserved : 4;
+	uint64_t fir_parity_error : 1;
+	uint64_t _reserved0 : 19;
+#else
+	uint64_t _reserved0 : 19;
+	uint64_t fir_parity_error : 1;
+	uint64_t reserved : 4;
+	uint64_t axsnd_rsverr : 1;
+	uint64_t axsnd_rsvto : 1;
+	uint64_t axsnd_dlo_rtyto : 1;
+	uint64_t axsnd_dhi_rtyto : 1;
+	uint64_t axflow_err : 1;
+	uint64_t axrcv_rsvdata_to : 1;
+	uint64_t axrcv_dlo_to : 1;
+	uint64_t axrcv_dlo_err : 1;
+	uint64_t axpush_wrerr : 1;
+	uint64_t oci_bad_reg_addr : 1;
+	uint64_t illegal_cache_op : 1;
+	uint64_t internal_err : 1;
+	uint64_t bcde_oci_dataerr : 1;
+	uint64_t bcde_ce : 1;
+	uint64_t bcde_ue_err : 1;
+	uint64_t bcde_sue_err : 1;
+	uint64_t bcde_rddatato_err : 1;
+	uint64_t bcde_pb_adrerr : 1;
+	uint64_t bcde_pb_ack_dead : 1;
+	uint64_t bcde_setup_err : 1;
+	uint64_t bcue_oci_dataerr : 1;
+	uint64_t bcue_pb_adrerr : 1;
+	uint64_t bcue_pb_ack_dead : 1;
+	uint64_t bcue_setup_err : 1;
+	uint64_t pb_crespto : 1;
+	uint64_t pb_ackdead_fw : 1;
+	uint64_t pb_badcresp : 1;
+	uint64_t pb_wradrerr_fw : 1;
+	uint64_t pb_parity_err : 1;
+	uint64_t pb_unexpdata : 1;
+	uint64_t pb_unexpcresp : 1;
+	uint64_t oci_rereqto : 1;
+	uint64_t oci_wrpar_err : 1;
+	uint64_t oci_slave_init : 1;
+	uint64_t pb_ce_fw : 1;
+	uint64_t pb_ue_fw : 1;
+	uint64_t pb_sue_fw : 1;
+	uint64_t pb_rddatato_fw : 1;
+	uint64_t pb_rdadrerr_fw : 1;
+	uint64_t oci_apar_err : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_firmask_and_t;
+
+
+
+typedef union pba_firmask_or {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t oci_apar_err : 1;
+	uint64_t pb_rdadrerr_fw : 1;
+	uint64_t pb_rddatato_fw : 1;
+	uint64_t pb_sue_fw : 1;
+	uint64_t pb_ue_fw : 1;
+	uint64_t pb_ce_fw : 1;
+	uint64_t oci_slave_init : 1;
+	uint64_t oci_wrpar_err : 1;
+	uint64_t oci_rereqto : 1;
+	uint64_t pb_unexpcresp : 1;
+	uint64_t pb_unexpdata : 1;
+	uint64_t pb_parity_err : 1;
+	uint64_t pb_wradrerr_fw : 1;
+	uint64_t pb_badcresp : 1;
+	uint64_t pb_ackdead_fw : 1;
+	uint64_t pb_crespto : 1;
+	uint64_t bcue_setup_err : 1;
+	uint64_t bcue_pb_ack_dead : 1;
+	uint64_t bcue_pb_adrerr : 1;
+	uint64_t bcue_oci_dataerr : 1;
+	uint64_t bcde_setup_err : 1;
+	uint64_t bcde_pb_ack_dead : 1;
+	uint64_t bcde_pb_adrerr : 1;
+	uint64_t bcde_rddatato_err : 1;
+	uint64_t bcde_sue_err : 1;
+	uint64_t bcde_ue_err : 1;
+	uint64_t bcde_ce : 1;
+	uint64_t bcde_oci_dataerr : 1;
+	uint64_t internal_err : 1;
+	uint64_t illegal_cache_op : 1;
+	uint64_t oci_bad_reg_addr : 1;
+	uint64_t axpush_wrerr : 1;
+	uint64_t axrcv_dlo_err : 1;
+	uint64_t axrcv_dlo_to : 1;
+	uint64_t axrcv_rsvdata_to : 1;
+	uint64_t axflow_err : 1;
+	uint64_t axsnd_dhi_rtyto : 1;
+	uint64_t axsnd_dlo_rtyto : 1;
+	uint64_t axsnd_rsvto : 1;
+	uint64_t axsnd_rsverr : 1;
+	uint64_t reserved : 4;
+	uint64_t fir_parity_error : 1;
+	uint64_t _reserved0 : 19;
+#else
+	uint64_t _reserved0 : 19;
+	uint64_t fir_parity_error : 1;
+	uint64_t reserved : 4;
+	uint64_t axsnd_rsverr : 1;
+	uint64_t axsnd_rsvto : 1;
+	uint64_t axsnd_dlo_rtyto : 1;
+	uint64_t axsnd_dhi_rtyto : 1;
+	uint64_t axflow_err : 1;
+	uint64_t axrcv_rsvdata_to : 1;
+	uint64_t axrcv_dlo_to : 1;
+	uint64_t axrcv_dlo_err : 1;
+	uint64_t axpush_wrerr : 1;
+	uint64_t oci_bad_reg_addr : 1;
+	uint64_t illegal_cache_op : 1;
+	uint64_t internal_err : 1;
+	uint64_t bcde_oci_dataerr : 1;
+	uint64_t bcde_ce : 1;
+	uint64_t bcde_ue_err : 1;
+	uint64_t bcde_sue_err : 1;
+	uint64_t bcde_rddatato_err : 1;
+	uint64_t bcde_pb_adrerr : 1;
+	uint64_t bcde_pb_ack_dead : 1;
+	uint64_t bcde_setup_err : 1;
+	uint64_t bcue_oci_dataerr : 1;
+	uint64_t bcue_pb_adrerr : 1;
+	uint64_t bcue_pb_ack_dead : 1;
+	uint64_t bcue_setup_err : 1;
+	uint64_t pb_crespto : 1;
+	uint64_t pb_ackdead_fw : 1;
+	uint64_t pb_badcresp : 1;
+	uint64_t pb_wradrerr_fw : 1;
+	uint64_t pb_parity_err : 1;
+	uint64_t pb_unexpdata : 1;
+	uint64_t pb_unexpcresp : 1;
+	uint64_t oci_rereqto : 1;
+	uint64_t oci_wrpar_err : 1;
+	uint64_t oci_slave_init : 1;
+	uint64_t pb_ce_fw : 1;
+	uint64_t pb_ue_fw : 1;
+	uint64_t pb_sue_fw : 1;
+	uint64_t pb_rddatato_fw : 1;
+	uint64_t pb_rdadrerr_fw : 1;
+	uint64_t oci_apar_err : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_firmask_or_t;
+
+
+
+typedef union pba_firact0 {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t oci_apar_err : 1;
+	uint64_t pb_rdadrerr_fw : 1;
+	uint64_t pb_rddatato_fw : 1;
+	uint64_t pb_sue_fw : 1;
+	uint64_t pb_ue_fw : 1;
+	uint64_t pb_ce_fw : 1;
+	uint64_t oci_slave_init : 1;
+	uint64_t oci_wrpar_err : 1;
+	uint64_t oci_rereqto : 1;
+	uint64_t pb_unexpcresp : 1;
+	uint64_t pb_unexpdata : 1;
+	uint64_t pb_parity_err : 1;
+	uint64_t pb_wradrerr_fw : 1;
+	uint64_t pb_badcresp : 1;
+	uint64_t pb_ackdead_fw : 1;
+	uint64_t pb_crespto : 1;
+	uint64_t bcue_setup_err : 1;
+	uint64_t bcue_pb_ack_dead : 1;
+	uint64_t bcue_pb_adrerr : 1;
+	uint64_t bcue_oci_dataerr : 1;
+	uint64_t bcde_setup_err : 1;
+	uint64_t bcde_pb_ack_dead : 1;
+	uint64_t bcde_pb_adrerr : 1;
+	uint64_t bcde_rddatato_err : 1;
+	uint64_t bcde_sue_err : 1;
+	uint64_t bcde_ue_err : 1;
+	uint64_t bcde_ce : 1;
+	uint64_t bcde_oci_dataerr : 1;
+	uint64_t internal_err : 1;
+	uint64_t illegal_cache_op : 1;
+	uint64_t oci_bad_reg_addr : 1;
+	uint64_t axpush_wrerr : 1;
+	uint64_t axrcv_dlo_err : 1;
+	uint64_t axrcv_dlo_to : 1;
+	uint64_t axrcv_rsvdata_to : 1;
+	uint64_t axflow_err : 1;
+	uint64_t axsnd_dhi_rtyto : 1;
+	uint64_t axsnd_dlo_rtyto : 1;
+	uint64_t axsnd_rsvto : 1;
+	uint64_t axsnd_rsverr : 1;
+	uint64_t reserved : 4;
+	uint64_t fir_parity_error : 1;
+	uint64_t _reserved0 : 19;
+#else
+	uint64_t _reserved0 : 19;
+	uint64_t fir_parity_error : 1;
+	uint64_t reserved : 4;
+	uint64_t axsnd_rsverr : 1;
+	uint64_t axsnd_rsvto : 1;
+	uint64_t axsnd_dlo_rtyto : 1;
+	uint64_t axsnd_dhi_rtyto : 1;
+	uint64_t axflow_err : 1;
+	uint64_t axrcv_rsvdata_to : 1;
+	uint64_t axrcv_dlo_to : 1;
+	uint64_t axrcv_dlo_err : 1;
+	uint64_t axpush_wrerr : 1;
+	uint64_t oci_bad_reg_addr : 1;
+	uint64_t illegal_cache_op : 1;
+	uint64_t internal_err : 1;
+	uint64_t bcde_oci_dataerr : 1;
+	uint64_t bcde_ce : 1;
+	uint64_t bcde_ue_err : 1;
+	uint64_t bcde_sue_err : 1;
+	uint64_t bcde_rddatato_err : 1;
+	uint64_t bcde_pb_adrerr : 1;
+	uint64_t bcde_pb_ack_dead : 1;
+	uint64_t bcde_setup_err : 1;
+	uint64_t bcue_oci_dataerr : 1;
+	uint64_t bcue_pb_adrerr : 1;
+	uint64_t bcue_pb_ack_dead : 1;
+	uint64_t bcue_setup_err : 1;
+	uint64_t pb_crespto : 1;
+	uint64_t pb_ackdead_fw : 1;
+	uint64_t pb_badcresp : 1;
+	uint64_t pb_wradrerr_fw : 1;
+	uint64_t pb_parity_err : 1;
+	uint64_t pb_unexpdata : 1;
+	uint64_t pb_unexpcresp : 1;
+	uint64_t oci_rereqto : 1;
+	uint64_t oci_wrpar_err : 1;
+	uint64_t oci_slave_init : 1;
+	uint64_t pb_ce_fw : 1;
+	uint64_t pb_ue_fw : 1;
+	uint64_t pb_sue_fw : 1;
+	uint64_t pb_rddatato_fw : 1;
+	uint64_t pb_rdadrerr_fw : 1;
+	uint64_t oci_apar_err : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_firact0_t;
+
+
+
+typedef union pba_firact1 {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t oci_apar_err : 1;
+	uint64_t pb_rdadrerr_fw : 1;
+	uint64_t pb_rddatato_fw : 1;
+	uint64_t pb_sue_fw : 1;
+	uint64_t pb_ue_fw : 1;
+	uint64_t pb_ce_fw : 1;
+	uint64_t oci_slave_init : 1;
+	uint64_t oci_wrpar_err : 1;
+	uint64_t oci_rereqto : 1;
+	uint64_t pb_unexpcresp : 1;
+	uint64_t pb_unexpdata : 1;
+	uint64_t pb_parity_err : 1;
+	uint64_t pb_wradrerr_fw : 1;
+	uint64_t pb_badcresp : 1;
+	uint64_t pb_ackdead_fw : 1;
+	uint64_t pb_crespto : 1;
+	uint64_t bcue_setup_err : 1;
+	uint64_t bcue_pb_ack_dead : 1;
+	uint64_t bcue_pb_adrerr : 1;
+	uint64_t bcue_oci_dataerr : 1;
+	uint64_t bcde_setup_err : 1;
+	uint64_t bcde_pb_ack_dead : 1;
+	uint64_t bcde_pb_adrerr : 1;
+	uint64_t bcde_rddatato_err : 1;
+	uint64_t bcde_sue_err : 1;
+	uint64_t bcde_ue_err : 1;
+	uint64_t bcde_ce : 1;
+	uint64_t bcde_oci_dataerr : 1;
+	uint64_t internal_err : 1;
+	uint64_t illegal_cache_op : 1;
+	uint64_t oci_bad_reg_addr : 1;
+	uint64_t axpush_wrerr : 1;
+	uint64_t axrcv_dlo_err : 1;
+	uint64_t axrcv_dlo_to : 1;
+	uint64_t axrcv_rsvdata_to : 1;
+	uint64_t axflow_err : 1;
+	uint64_t axsnd_dhi_rtyto : 1;
+	uint64_t axsnd_dlo_rtyto : 1;
+	uint64_t axsnd_rsvto : 1;
+	uint64_t axsnd_rsverr : 1;
+	uint64_t reserved : 4;
+	uint64_t fir_parity_error : 1;
+	uint64_t _reserved0 : 19;
+#else
+	uint64_t _reserved0 : 19;
+	uint64_t fir_parity_error : 1;
+	uint64_t reserved : 4;
+	uint64_t axsnd_rsverr : 1;
+	uint64_t axsnd_rsvto : 1;
+	uint64_t axsnd_dlo_rtyto : 1;
+	uint64_t axsnd_dhi_rtyto : 1;
+	uint64_t axflow_err : 1;
+	uint64_t axrcv_rsvdata_to : 1;
+	uint64_t axrcv_dlo_to : 1;
+	uint64_t axrcv_dlo_err : 1;
+	uint64_t axpush_wrerr : 1;
+	uint64_t oci_bad_reg_addr : 1;
+	uint64_t illegal_cache_op : 1;
+	uint64_t internal_err : 1;
+	uint64_t bcde_oci_dataerr : 1;
+	uint64_t bcde_ce : 1;
+	uint64_t bcde_ue_err : 1;
+	uint64_t bcde_sue_err : 1;
+	uint64_t bcde_rddatato_err : 1;
+	uint64_t bcde_pb_adrerr : 1;
+	uint64_t bcde_pb_ack_dead : 1;
+	uint64_t bcde_setup_err : 1;
+	uint64_t bcue_oci_dataerr : 1;
+	uint64_t bcue_pb_adrerr : 1;
+	uint64_t bcue_pb_ack_dead : 1;
+	uint64_t bcue_setup_err : 1;
+	uint64_t pb_crespto : 1;
+	uint64_t pb_ackdead_fw : 1;
+	uint64_t pb_badcresp : 1;
+	uint64_t pb_wradrerr_fw : 1;
+	uint64_t pb_parity_err : 1;
+	uint64_t pb_unexpdata : 1;
+	uint64_t pb_unexpcresp : 1;
+	uint64_t oci_rereqto : 1;
+	uint64_t oci_wrpar_err : 1;
+	uint64_t oci_slave_init : 1;
+	uint64_t pb_ce_fw : 1;
+	uint64_t pb_ue_fw : 1;
+	uint64_t pb_sue_fw : 1;
+	uint64_t pb_rddatato_fw : 1;
+	uint64_t pb_rdadrerr_fw : 1;
+	uint64_t oci_apar_err : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_firact1_t;
+
+
+
+typedef union pba_occact {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t oci_apar_err : 1;
+	uint64_t pb_rdadrerr_fw : 1;
+	uint64_t pb_rddatato_fw : 1;
+	uint64_t pb_sue_fw : 1;
+	uint64_t pb_ue_fw : 1;
+	uint64_t pb_ce_fw : 1;
+	uint64_t oci_slave_init : 1;
+	uint64_t oci_wrpar_err : 1;
+	uint64_t oci_rereqto : 1;
+	uint64_t pb_unexpcresp : 1;
+	uint64_t pb_unexpdata : 1;
+	uint64_t pb_parity_err : 1;
+	uint64_t pb_wradrerr_fw : 1;
+	uint64_t pb_badcresp : 1;
+	uint64_t pb_ackdead_fw : 1;
+	uint64_t pb_crespto : 1;
+	uint64_t bcue_setup_err : 1;
+	uint64_t bcue_pb_ack_dead : 1;
+	uint64_t bcue_pb_adrerr : 1;
+	uint64_t bcue_oci_dataerr : 1;
+	uint64_t bcde_setup_err : 1;
+	uint64_t bcde_pb_ack_dead : 1;
+	uint64_t bcde_pb_adrerr : 1;
+	uint64_t bcde_rddatato_err : 1;
+	uint64_t bcde_sue_err : 1;
+	uint64_t bcde_ue_err : 1;
+	uint64_t bcde_ce : 1;
+	uint64_t bcde_oci_dataerr : 1;
+	uint64_t internal_err : 1;
+	uint64_t illegal_cache_op : 1;
+	uint64_t oci_bad_reg_addr : 1;
+	uint64_t axpush_wrerr : 1;
+	uint64_t axrcv_dlo_err : 1;
+	uint64_t axrcv_dlo_to : 1;
+	uint64_t axrcv_rsvdata_to : 1;
+	uint64_t axflow_err : 1;
+	uint64_t axsnd_dhi_rtyto : 1;
+	uint64_t axsnd_dlo_rtyto : 1;
+	uint64_t axsnd_rsvto : 1;
+	uint64_t axsnd_rsverr : 1;
+	uint64_t reserved : 4;
+	uint64_t fir_parity_error : 1;
+	uint64_t _reserved0 : 19;
+#else
+	uint64_t _reserved0 : 19;
+	uint64_t fir_parity_error : 1;
+	uint64_t reserved : 4;
+	uint64_t axsnd_rsverr : 1;
+	uint64_t axsnd_rsvto : 1;
+	uint64_t axsnd_dlo_rtyto : 1;
+	uint64_t axsnd_dhi_rtyto : 1;
+	uint64_t axflow_err : 1;
+	uint64_t axrcv_rsvdata_to : 1;
+	uint64_t axrcv_dlo_to : 1;
+	uint64_t axrcv_dlo_err : 1;
+	uint64_t axpush_wrerr : 1;
+	uint64_t oci_bad_reg_addr : 1;
+	uint64_t illegal_cache_op : 1;
+	uint64_t internal_err : 1;
+	uint64_t bcde_oci_dataerr : 1;
+	uint64_t bcde_ce : 1;
+	uint64_t bcde_ue_err : 1;
+	uint64_t bcde_sue_err : 1;
+	uint64_t bcde_rddatato_err : 1;
+	uint64_t bcde_pb_adrerr : 1;
+	uint64_t bcde_pb_ack_dead : 1;
+	uint64_t bcde_setup_err : 1;
+	uint64_t bcue_oci_dataerr : 1;
+	uint64_t bcue_pb_adrerr : 1;
+	uint64_t bcue_pb_ack_dead : 1;
+	uint64_t bcue_setup_err : 1;
+	uint64_t pb_crespto : 1;
+	uint64_t pb_ackdead_fw : 1;
+	uint64_t pb_badcresp : 1;
+	uint64_t pb_wradrerr_fw : 1;
+	uint64_t pb_parity_err : 1;
+	uint64_t pb_unexpdata : 1;
+	uint64_t pb_unexpcresp : 1;
+	uint64_t oci_rereqto : 1;
+	uint64_t oci_wrpar_err : 1;
+	uint64_t oci_slave_init : 1;
+	uint64_t pb_ce_fw : 1;
+	uint64_t pb_ue_fw : 1;
+	uint64_t pb_sue_fw : 1;
+	uint64_t pb_rddatato_fw : 1;
+	uint64_t pb_rdadrerr_fw : 1;
+	uint64_t oci_apar_err : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_occact_t;
+
+
+
+typedef union pba_cfg {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t writable : 48;
+	uint64_t _reserved0 : 16;
+#else
+	uint64_t _reserved0 : 16;
+	uint64_t writable : 48;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_cfg_t;
+
+
+
+typedef union pba_errpt0 {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t cerr_pb_rddatato_fw : 6;
+	uint64_t cerr_pb_rdadrerr_fw : 6;
+	uint64_t cerr_pb_wradrerr_fw : 6;
+	uint64_t cerr_pb_ackdead_fw : 6;
+	uint64_t cerr_pb_unexpcresp : 11;
+	uint64_t cerr_pb_unexpdata : 6;
+	uint64_t _reserved0 : 23;
+#else
+	uint64_t _reserved0 : 23;
+	uint64_t cerr_pb_unexpdata : 6;
+	uint64_t cerr_pb_unexpcresp : 11;
+	uint64_t cerr_pb_ackdead_fw : 6;
+	uint64_t cerr_pb_wradrerr_fw : 6;
+	uint64_t cerr_pb_rdadrerr_fw : 6;
+	uint64_t cerr_pb_rddatato_fw : 6;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_errpt0_t;
+
+
+
+typedef union pba_errpt1 {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t cerr_pb_badcresp : 12;
+	uint64_t cerr_pb_crespto : 12;
+	uint64_t cerr_oci_rereqto : 6;
+	uint64_t cerr_bcde_setup_err : 2;
+	uint64_t cerr_bcue_setup_err : 2;
+	uint64_t cerr_bcue_oci_dataerr : 2;
+	uint64_t _reserved0 : 28;
+#else
+	uint64_t _reserved0 : 28;
+	uint64_t cerr_bcue_oci_dataerr : 2;
+	uint64_t cerr_bcue_setup_err : 2;
+	uint64_t cerr_bcde_setup_err : 2;
+	uint64_t cerr_oci_rereqto : 6;
+	uint64_t cerr_pb_crespto : 12;
+	uint64_t cerr_pb_badcresp : 12;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_errpt1_t;
+
+
+
+typedef union pba_errpt2 {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t cerr_slv_internal_err : 8;
+	uint64_t cerr_bcde_internal_err : 4;
+	uint64_t cerr_bcue_internal_err : 4;
+	uint64_t cerr_bar_parity_err : 4;
+	uint64_t cerr_pbdout_parity_err : 1;
+	uint64_t cerr_pb_parity_err : 3;
+	uint64_t cerr_axflow_err : 5;
+	uint64_t cerr_axpush_wrerr : 2;
+	uint64_t _reserved0 : 33;
+#else
+	uint64_t _reserved0 : 33;
+	uint64_t cerr_axpush_wrerr : 2;
+	uint64_t cerr_axflow_err : 5;
+	uint64_t cerr_pb_parity_err : 3;
+	uint64_t cerr_pbdout_parity_err : 1;
+	uint64_t cerr_bar_parity_err : 4;
+	uint64_t cerr_bcue_internal_err : 4;
+	uint64_t cerr_bcde_internal_err : 4;
+	uint64_t cerr_slv_internal_err : 8;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_errpt2_t;
+
+
+
+typedef union pba_rbufvaln {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t rd_slvnum : 2;
+	uint64_t cur_rd_addr : 23;
+	uint64_t spare1 : 3;
+	uint64_t prefetch : 1;
+	uint64_t spare2 : 2;
+	uint64_t abort : 1;
+	uint64_t spare3 : 1;
+	uint64_t buffer_status : 7;
+	uint64_t spare4 : 4;
+	uint64_t _reserved0 : 20;
+#else
+	uint64_t _reserved0 : 20;
+	uint64_t spare4 : 4;
+	uint64_t buffer_status : 7;
+	uint64_t spare3 : 1;
+	uint64_t abort : 1;
+	uint64_t spare2 : 2;
+	uint64_t prefetch : 1;
+	uint64_t spare1 : 3;
+	uint64_t cur_rd_addr : 23;
+	uint64_t rd_slvnum : 2;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_rbufvaln_t;
+
+
+
+typedef union pba_wbufvaln {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t wr_slvnum : 2;
+	uint64_t start_wr_addr : 30;
+	uint64_t spare1 : 3;
+	uint64_t wr_buffer_status : 5;
+	uint64_t spare2 : 1;
+	uint64_t wr_byte_count : 7;
+	uint64_t spare3 : 16;
+#else
+	uint64_t spare3 : 16;
+	uint64_t wr_byte_count : 7;
+	uint64_t spare2 : 1;
+	uint64_t wr_buffer_status : 5;
+	uint64_t spare1 : 3;
+	uint64_t start_wr_addr : 30;
+	uint64_t wr_slvnum : 2;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_wbufvaln_t;
+
+
+
+typedef union pba_mode {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t reserved0 : 4;
+	uint64_t dis_rearb : 1;
+	uint64_t reserved1 : 1;
+	uint64_t dis_slave_rdpipe : 1;
+	uint64_t dis_slave_wrpipe : 1;
+	uint64_t en_marker_ack : 1;
+	uint64_t dis_slvmatch_order : 1;
+	uint64_t en_second_wrbuf : 1;
+	uint64_t dis_rerequest_to : 1;
+	uint64_t inject_type : 2;
+	uint64_t inject_mode : 2;
+	uint64_t pba_region : 2;
+	uint64_t oci_marker_space : 3;
+	uint64_t bcde_ocitrans : 2;
+	uint64_t bcue_ocitrans : 2;
+	uint64_t dis_master_rd_pipe : 1;
+	uint64_t dis_master_wr_pipe : 1;
+	uint64_t en_slave_fairness : 1;
+	uint64_t en_ecvent_count : 1;
+	uint64_t pb_noci_event_sel : 1;
+	uint64_t slv_event_mux : 2;
+	uint64_t enable_debug_bus : 1;
+	uint64_t debug_pb_not_oci : 1;
+	uint64_t debug_oci_mode : 5;
+	uint64_t reserved2 : 1;
+	uint64_t ocislv_fairness_mask : 5;
+	uint64_t ocislv_rereq_hang_div : 5;
+	uint64_t dis_chgrate_count : 1;
+	uint64_t pbreq_event_mux : 2;
+	uint64_t _reserved0 : 11;
+#else
+	uint64_t _reserved0 : 11;
+	uint64_t pbreq_event_mux : 2;
+	uint64_t dis_chgrate_count : 1;
+	uint64_t ocislv_rereq_hang_div : 5;
+	uint64_t ocislv_fairness_mask : 5;
+	uint64_t reserved2 : 1;
+	uint64_t debug_oci_mode : 5;
+	uint64_t debug_pb_not_oci : 1;
+	uint64_t enable_debug_bus : 1;
+	uint64_t slv_event_mux : 2;
+	uint64_t pb_noci_event_sel : 1;
+	uint64_t en_ecvent_count : 1;
+	uint64_t en_slave_fairness : 1;
+	uint64_t dis_master_wr_pipe : 1;
+	uint64_t dis_master_rd_pipe : 1;
+	uint64_t bcue_ocitrans : 2;
+	uint64_t bcde_ocitrans : 2;
+	uint64_t oci_marker_space : 3;
+	uint64_t pba_region : 2;
+	uint64_t inject_mode : 2;
+	uint64_t inject_type : 2;
+	uint64_t dis_rerequest_to : 1;
+	uint64_t en_second_wrbuf : 1;
+	uint64_t dis_slvmatch_order : 1;
+	uint64_t en_marker_ack : 1;
+	uint64_t dis_slave_wrpipe : 1;
+	uint64_t dis_slave_rdpipe : 1;
+	uint64_t reserved1 : 1;
+	uint64_t dis_rearb : 1;
+	uint64_t reserved0 : 4;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_mode_t;
+
+
+
+typedef union pba_slvrst {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t set : 3;
+	uint64_t notimp1 : 1;
+	uint64_t in_prog : 4;
+	uint64_t busy_status : 4;
+	uint64_t _reserved0 : 52;
+#else
+	uint64_t _reserved0 : 52;
+	uint64_t busy_status : 4;
+	uint64_t in_prog : 4;
+	uint64_t notimp1 : 1;
+	uint64_t set : 3;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_slvrst_t;
+
+
+
+typedef union pba_slvctln {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t enable : 1;
+	uint64_t mid_match_value : 3;
+	uint64_t _reserved0 : 1;
+	uint64_t mid_care_mask : 3;
+	uint64_t write_ttype : 3;
+	uint64_t _reserved1 : 4;
+	uint64_t read_ttype : 1;
+	uint64_t read_prefetch_ctl : 2;
+	uint64_t buf_invalidate_ctl : 1;
+	uint64_t buf_alloc_w : 1;
+	uint64_t buf_alloc_a : 1;
+	uint64_t buf_alloc_b : 1;
+	uint64_t buf_alloc_c : 1;
+	uint64_t _reserved2 : 1;
+	uint64_t dis_write_gather : 1;
+	uint64_t wr_gather_timeout : 3;
+	uint64_t write_tsize : 7;
+	uint64_t extaddr : 14;
+	uint64_t _reserved3 : 15;
+#else
+	uint64_t _reserved3 : 15;
+	uint64_t extaddr : 14;
+	uint64_t write_tsize : 7;
+	uint64_t wr_gather_timeout : 3;
+	uint64_t dis_write_gather : 1;
+	uint64_t _reserved2 : 1;
+	uint64_t buf_alloc_c : 1;
+	uint64_t buf_alloc_b : 1;
+	uint64_t buf_alloc_a : 1;
+	uint64_t buf_alloc_w : 1;
+	uint64_t buf_invalidate_ctl : 1;
+	uint64_t read_prefetch_ctl : 2;
+	uint64_t read_ttype : 1;
+	uint64_t _reserved1 : 4;
+	uint64_t write_ttype : 3;
+	uint64_t mid_care_mask : 3;
+	uint64_t _reserved0 : 1;
+	uint64_t mid_match_value : 3;
+	uint64_t enable : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_slvctln_t;
+
+
+
+typedef union pba_bcde_ctl {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t stop : 1;
+	uint64_t start : 1;
+	uint64_t _reserved0 : 62;
+#else
+	uint64_t _reserved0 : 62;
+	uint64_t start : 1;
+	uint64_t stop : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_bcde_ctl_t;
+
+#endif // __ASSEMBLER__
+#define PBA_BCDE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
+#define PBA_BCDE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
+#ifndef __ASSEMBLER__
+
+
+typedef union pba_bcde_set {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t _reserved0 : 2;
+	uint64_t copy_length : 6;
+	uint64_t _reserved1 : 56;
+#else
+	uint64_t _reserved1 : 56;
+	uint64_t copy_length : 6;
+	uint64_t _reserved0 : 2;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_bcde_set_t;
+
+
+
+typedef union pba_bcde_stat {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t running : 1;
+	uint64_t waiting : 1;
+	uint64_t wrcmp : 6;
+	uint64_t _reserved0 : 6;
+	uint64_t rdcmp : 6;
+	uint64_t debug : 9;
+	uint64_t stopped : 1;
+	uint64_t error : 1;
+	uint64_t done : 1;
+	uint64_t _reserved1 : 32;
+#else
+	uint64_t _reserved1 : 32;
+	uint64_t done : 1;
+	uint64_t error : 1;
+	uint64_t stopped : 1;
+	uint64_t debug : 9;
+	uint64_t rdcmp : 6;
+	uint64_t _reserved0 : 6;
+	uint64_t wrcmp : 6;
+	uint64_t waiting : 1;
+	uint64_t running : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_bcde_stat_t;
+
+
+
+typedef union pba_bcde_pbadr {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t _reserved0 : 2;
+	uint64_t pb_offset : 23;
+	uint64_t _reserved1 : 2;
+	uint64_t extaddr : 14;
+	uint64_t _reserved2 : 23;
+#else
+	uint64_t _reserved2 : 23;
+	uint64_t extaddr : 14;
+	uint64_t _reserved1 : 2;
+	uint64_t pb_offset : 23;
+	uint64_t _reserved0 : 2;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_bcde_pbadr_t;
+
+
+
+typedef union pba_bcde_ocibar {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t addr : 25;
+	uint64_t _reserved0 : 39;
+#else
+	uint64_t _reserved0 : 39;
+	uint64_t addr : 25;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_bcde_ocibar_t;
+
+
+
+typedef union pba_bcue_ctl {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t stop : 1;
+	uint64_t start : 1;
+	uint64_t _reserved0 : 62;
+#else
+	uint64_t _reserved0 : 62;
+	uint64_t start : 1;
+	uint64_t stop : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_bcue_ctl_t;
+
+#endif // __ASSEMBLER__
+#define PBA_BCUE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
+#define PBA_BCUE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
+#ifndef __ASSEMBLER__
+
+
+typedef union pba_bcue_set {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t _reserved0 : 2;
+	uint64_t copy_length : 6;
+	uint64_t _reserved1 : 56;
+#else
+	uint64_t _reserved1 : 56;
+	uint64_t copy_length : 6;
+	uint64_t _reserved0 : 2;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_bcue_set_t;
+
+
+
+typedef union pba_bcue_stat {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t running : 1;
+	uint64_t waiting : 1;
+	uint64_t wrcmp : 6;
+	uint64_t _reserved0 : 6;
+	uint64_t rdcmp : 6;
+	uint64_t debug : 9;
+	uint64_t stopped : 1;
+	uint64_t error : 1;
+	uint64_t done : 1;
+	uint64_t _reserved1 : 32;
+#else
+	uint64_t _reserved1 : 32;
+	uint64_t done : 1;
+	uint64_t error : 1;
+	uint64_t stopped : 1;
+	uint64_t debug : 9;
+	uint64_t rdcmp : 6;
+	uint64_t _reserved0 : 6;
+	uint64_t wrcmp : 6;
+	uint64_t waiting : 1;
+	uint64_t running : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_bcue_stat_t;
+
+
+
+typedef union pba_bcue_pbadr {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t _reserved0 : 2;
+	uint64_t pb_offset : 23;
+	uint64_t _reserved1 : 2;
+	uint64_t extaddr : 14;
+	uint64_t _reserved2 : 23;
+#else
+	uint64_t _reserved2 : 23;
+	uint64_t extaddr : 14;
+	uint64_t _reserved1 : 2;
+	uint64_t pb_offset : 23;
+	uint64_t _reserved0 : 2;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_bcue_pbadr_t;
+
+
+
+typedef union pba_bcue_ocibar {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t addr : 25;
+	uint64_t _reserved0 : 39;
+#else
+	uint64_t _reserved0 : 39;
+	uint64_t addr : 25;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_bcue_ocibar_t;
+
+
+
+typedef union pba_pbocrn {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t _reserved0 : 16;
+	uint64_t event : 16;
+	uint64_t _reserved1 : 12;
+	uint64_t accum : 20;
+#else
+	uint64_t accum : 20;
+	uint64_t _reserved1 : 12;
+	uint64_t event : 16;
+	uint64_t _reserved0 : 16;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_pbocrn_t;
+
+
+
+typedef union pba_xsndtx {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t snd_scope : 3;
+	uint64_t snd_qid : 1;
+	uint64_t snd_type : 1;
+	uint64_t snd_reservation : 1;
+	uint64_t spare1 : 2;
+	uint64_t snd_nodeid : 3;
+	uint64_t snd_chipid : 3;
+	uint64_t spare2 : 2;
+	uint64_t _reserved0 : 48;
+#else
+	uint64_t _reserved0 : 48;
+	uint64_t spare2 : 2;
+	uint64_t snd_chipid : 3;
+	uint64_t snd_nodeid : 3;
+	uint64_t spare1 : 2;
+	uint64_t snd_reservation : 1;
+	uint64_t snd_type : 1;
+	uint64_t snd_qid : 1;
+	uint64_t snd_scope : 3;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_xsndtx_t;
+
+
+
+typedef union pba_xcfg {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t pbax_en : 1;
+	uint64_t reservation_en : 1;
+	uint64_t snd_reset : 1;
+	uint64_t rcv_reset : 1;
+	uint64_t rcv_nodeid : 3;
+	uint64_t rcv_chipid : 3;
+	uint64_t spare1 : 2;
+	uint64_t rcv_brdcst_group : 8;
+	uint64_t rcv_datalo_thresh : 8;
+	uint64_t snd_retry_thresh : 8;
+	uint64_t snd_rsv_req_thresh : 2;
+	uint64_t snd_retry_count_overcom : 1;
+	uint64_t _reserved0 : 25;
+#else
+	uint64_t _reserved0 : 25;
+	uint64_t snd_retry_count_overcom : 1;
+	uint64_t snd_rsv_req_thresh : 2;
+	uint64_t snd_retry_thresh : 8;
+	uint64_t rcv_datalo_thresh : 8;
+	uint64_t rcv_brdcst_group : 8;
+	uint64_t spare1 : 2;
+	uint64_t rcv_chipid : 3;
+	uint64_t rcv_nodeid : 3;
+	uint64_t rcv_reset : 1;
+	uint64_t snd_reset : 1;
+	uint64_t reservation_en : 1;
+	uint64_t pbax_en : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_xcfg_t;
+
+
+
+typedef union pba_xsndstat {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t snd_in_progress : 1;
+	uint64_t snd_error : 1;
+	uint64_t snd_status : 6;
+	uint64_t snd_retry_count : 8;
+	uint64_t _reserved0 : 48;
+#else
+	uint64_t _reserved0 : 48;
+	uint64_t snd_retry_count : 8;
+	uint64_t snd_status : 6;
+	uint64_t snd_error : 1;
+	uint64_t snd_in_progress : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_xsndstat_t;
+
+
+
+typedef union pba_xsnddat {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t pbax_datahi : 32;
+	uint64_t pbax_datalo : 32;
+#else
+	uint64_t pbax_datalo : 32;
+	uint64_t pbax_datahi : 32;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_xsnddat_t;
+
+
+
+typedef union pba_xrcvstat {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t rcv_in_progress : 1;
+	uint64_t rcv_error : 1;
+	uint64_t rcv_write_in_progress : 1;
+	uint64_t rcv_reservation_set : 1;
+	uint64_t rcv_capture : 14;
+	uint64_t _reserved0 : 46;
+#else
+	uint64_t _reserved0 : 46;
+	uint64_t rcv_capture : 14;
+	uint64_t rcv_reservation_set : 1;
+	uint64_t rcv_write_in_progress : 1;
+	uint64_t rcv_error : 1;
+	uint64_t rcv_in_progress : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_xrcvstat_t;
+
+
+
+typedef union pba_xshbrn {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t push_start : 29;
+	uint64_t _reserved0 : 35;
+#else
+	uint64_t _reserved0 : 35;
+	uint64_t push_start : 29;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_xshbrn_t;
+
+
+
+typedef union pba_xshcsn {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t push_full : 1;
+	uint64_t push_empty : 1;
+	uint64_t spare1 : 2;
+	uint64_t push_intr_action : 2;
+	uint64_t push_length : 5;
+	uint64_t notimp1 : 2;
+	uint64_t push_write_ptr : 5;
+	uint64_t notimp2 : 3;
+	uint64_t push_read_ptr : 5;
+	uint64_t notimp3 : 5;
+	uint64_t push_enable : 1;
+	uint64_t _reserved0 : 32;
+#else
+	uint64_t _reserved0 : 32;
+	uint64_t push_enable : 1;
+	uint64_t notimp3 : 5;
+	uint64_t push_read_ptr : 5;
+	uint64_t notimp2 : 3;
+	uint64_t push_write_ptr : 5;
+	uint64_t notimp1 : 2;
+	uint64_t push_length : 5;
+	uint64_t push_intr_action : 2;
+	uint64_t spare1 : 2;
+	uint64_t push_empty : 1;
+	uint64_t push_full : 1;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_xshcsn_t;
+
+
+
+typedef union pba_xshincn {
+
+    uint64_t value;
+    struct {
+#ifdef _BIG_ENDIAN
+        uint32_t high_order;
+        uint32_t low_order;
+#else
+        uint32_t low_order;
+        uint32_t high_order;
+#endif // _BIG_ENDIAN
+    } words;
+    struct {
+#ifdef _BIG_ENDIAN
+	uint64_t reserved : 64;
+#else
+	uint64_t reserved : 64;
+#endif // _BIG_ENDIAN
+    } fields;
+} pba_xshincn_t;
+
+
+#endif // __ASSEMBLER__
+#endif // __PBA_FIRMWARE_REGISTERS_H__
+
diff --git a/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/pgp_common.h b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/pgp_common.h
new file mode 100644
index 000000000..2fb33877a
--- /dev/null
+++ b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/pgp_common.h
@@ -0,0 +1,666 @@
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/pgp_common.h $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+// $Id: pgp_common.h,v 1.2 2012/08/13 16:11:58 stillgs Exp $
+
+#ifndef __PGP_COMMON_H__
+#define __PGP_COMMON_H__
+
+/// \file pgp_common.h
+/// \brief Common header for SSX and PMX versions of PgP
+///
+/// This header is maintained as part of the SSX port for PgP, but needs to be
+/// physically present in the PMX area to allow dropping PMX code as a whole
+/// to other teams.
+
+// -*- WARNING: This file is maintained as part of SSX.  Do not edit in -*-
+// -*- the PMX area as your edits will be lost.                         -*-
+
+#ifndef __ASSEMBLER__
+#include <stdint.h>
+#endif
+
+////////////////////////////////////////////////////////////////////////////
+// Configuration
+////////////////////////////////////////////////////////////////////////////
+
+#define PGP_NCORES  16
+#define PGP_NMCS     8
+#define PGP_NCENTAUR 8
+#define PGP_NTHREADS 8
+
+////////////////////////////////////////////////////////////////////////////
+// Clocking
+////////////////////////////////////////////////////////////////////////////
+
+/// PgP nest runs at 2.4 GHz
+///
+/// \todo This drives the pervasive domain clocking, and there is some idea to
+/// make this frequency variable.  If so then this will be a system-specific
+/// constant.  Thus it's a good idea to keep as much timing information as
+/// possible relative to the nest frequency.
+///
+/// \bug This constant needs to be read and handled as an attribute
+#define NEST_FREQUENCY_KHZ 2400000
+
+/// Pervasive clock is nest / 4
+#define PERVASIVE_FREQUENCY_HZ (NEST_FREQUENCY_KHZ * 250)
+
+/// PgP/OCC uses the pervasive frequency directly to drive PPC405 timers
+#define SSX_TIMEBASE_FREQUENCY_HZ PERVASIVE_FREQUENCY_HZ
+
+/// The pervasive hang timer divider used for the OCB
+#define OCB_TIMER_DIVIDER 512
+
+/// The OCB timer frequency
+///
+/// The frequency is based on a pervasive hang timer that is formed by
+/// dividing the nominal 600 MHz pervasive clock by 512 to yield a 1.1719 MHz
+/// clock (853ns period).  This is a dynamic configuration option, but is
+/// assumed to be initialized as the given frequency.  If not, then firmware
+/// will have to do some SCOMs to figure out what the real divider and
+/// frequency are.
+#define OCB_TIMER_FREQUENCY_HZ (PERVASIVE_FREQUENCY_HZ / OCB_TIMER_DIVIDER)
+
+
+/// The pervasive hang timer divider used for the PMC
+#define PMC_HANG_PULSE_DIVIDER (32 * 1024)
+
+/// The PMC Hang Pulse Frequency
+///
+/// The frequency is based on a pervasive hang timer that is formed by
+/// dividing the nominal 600 MHz pervasive clock by 32K to yield a 18.3 KHz
+/// clock (54.6us period).  This is a dynamic configuration option, but is
+/// assumed to be initialized as the given frequency.  If not, then firmware
+/// will have to do some SCOMs to figure out what the real divider and
+/// frequency are.
+#define PMC_HANG_PULSE_FREQUENCY_HZ \
+    (PERVASIVE_FREQUENCY_HZ / PMC_HANG_PULSE_DIVIDER)
+
+
+////////////////////////////////////////////////////////////////////////////
+// OCI
+////////////////////////////////////////////////////////////////////////////
+
+// OCI Master Id assigments - required for PBA slave programming.  These Ids
+// also appear as bits 12:15 of the OCI register space addresses of the OCI
+// registers for each device that contains OCI-addressable registers (GPE,
+// PMC, PBA, SLW and OCB).
+
+#define OCI_MASTER_ID_PORE_GPE 0
+#define OCI_MASTER_ID_PMC      1
+#define OCI_MASTER_ID_PBA      2
+#define OCI_MASTER_ID_UNUSED   3
+#define OCI_MASTER_ID_PORE_SLW 4
+#define OCI_MASTER_ID_OCB      5
+#define OCI_MASTER_ID_OCC_ICU  6
+#define OCI_MASTER_ID_OCC_DCU  7
+
+
+////////////////////////////////////////////////////////////////////////////
+// IRQ
+////////////////////////////////////////////////////////////////////////////
+
+// The OCB interrupt controller consists of 2 x 32-bit controllers.  Unlike
+// PPC ASICs, the OCB controllers are _not_ cascaded.  The combined
+// controllers are presented to the application as if there were a single
+// 64-bit interrupt controller, while the code underlying the abstraction
+// manipulates the 2 x 32-bit controllers independently.
+//
+// Note that the bits named *RESERVED* are actually implemented in the
+// controller, but the interrupt input is tied low. That means they can also
+// be used as IPI targets. Logical bits 32..63 are not implemented.
+
+#define PGP_IRQ_DEBUGGER                        0 /* 0x00 */
+#define PGP_IRQ_TRACE_TRIGGER                   1 /* 0x01 */
+#define PGP_IRQ_RESERVED_2                      2 /* 0x02 */
+#define PGP_IRQ_PBA_ERROR                       3 /* 0x03 */
+#define PGP_IRQ_SRT_ERROR                       4 /* 0x04 */
+#define PGP_IRQ_PORE_SW_ERROR                   5 /* 0x05 */
+#define PGP_IRQ_PORE_GPE0_FATAL_ERROR           6 /* 0x06 */
+#define PGP_IRQ_PORE_GPE1_FATAL_ERROR           7 /* 0x07 */
+#define PGP_IRQ_PORE_SBE_FATAL_ERROR            8 /* 0x08 */
+#define PGP_IRQ_PMC_ERROR                       9 /* 0x09 */
+#define PGP_IRQ_OCB_ERROR                      10 /* 0x0a */
+#define PGP_IRQ_SPIPSS_ERROR                   11 /* 0x0b */
+#define PGP_IRQ_CHECK_STOP                     12 /* 0x0c */
+#define PGP_IRQ_PMC_MALF_ALERT                 13 /* 0x0d */
+#define PGP_IRQ_ADU_MALF_ALERT                 14 /* 0x0e */
+#define PGP_IRQ_EXTERNAL_TRAP                  15 /* 0x0f */
+#define PGP_IRQ_OCC_TIMER0                     16 /* 0x10 */
+#define PGP_IRQ_OCC_TIMER1                     17 /* 0x11 */
+#define PGP_IRQ_PORE_GPE0_ERROR                18 /* 0x12 */
+#define PGP_IRQ_PORE_GPE1_ERROR                19 /* 0x13 */
+#define PGP_IRQ_PORE_SBE_ERROR                 20 /* 0x14 */
+#define PGP_IRQ_PMC_INTERCHIP_MSG_RECV         21 /* 0x15 */
+#define PGP_IRQ_RESERVED_22                    22 /* 0x16 */
+#define PGP_IRQ_PORE_GPE0_COMPLETE             23 /* 0x17 */
+#define PGP_IRQ_PORE_GPE1_COMPLETE             24 /* 0x18 */
+#define PGP_IRQ_ADCFSM_ONGOING                 25 /* 0x19 */
+#define PGP_IRQ_RESERVED_26                    26 /* 0x1a */
+#define PGP_IRQ_PBA_OCC_PUSH0                  27 /* 0x1b */
+#define PGP_IRQ_PBA_OCC_PUSH1                  28 /* 0x1c */
+#define PGP_IRQ_PBA_BCDE_ATTN                  29 /* 0x1d */
+#define PGP_IRQ_PBA_BCUE_ATTN                  30 /* 0x1e */
+#define PGP_IRQ_RESERVED_31                    31 /* 0x1f */
+
+#define PGP_IRQ_RESERVED_32                    32 /* 0x20 */
+#define PGP_IRQ_RESERVED_33                    33 /* 0x21 */
+#define PGP_IRQ_STRM0_PULL                     34 /* 0x22 */
+#define PGP_IRQ_STRM0_PUSH                     35 /* 0x23 */
+#define PGP_IRQ_STRM1_PULL                     36 /* 0x24 */
+#define PGP_IRQ_STRM1_PUSH                     37 /* 0x25 */
+#define PGP_IRQ_STRM2_PULL                     38 /* 0x26 */
+#define PGP_IRQ_STRM2_PUSH                     39 /* 0x27 */
+#define PGP_IRQ_STRM3_PULL                     40 /* 0x28 */
+#define PGP_IRQ_STRM3_PUSH                     41 /* 0x29 */
+#define PGP_IRQ_RESERVED_42                    42 /* 0x2a */
+#define PGP_IRQ_RESERVED_43                    43 /* 0x2b */
+#define PGP_IRQ_PMC_VOLTAGE_CHANGE_ONGOING     44 /* 0x2c */
+#define PGP_IRQ_PMC_PROTOCOL_ONGOING           45 /* 0x2d */
+#define PGP_IRQ_PMC_SYNC                       46 /* 0x2e */
+#define PGP_IRQ_PMC_PSTATE_REQUEST             47 /* 0x2f */
+#define PGP_IRQ_RESERVED_48                    48 /* 0x30 */
+#define PGP_IRQ_RESERVED_49                    49 /* 0x31 */
+#define PGP_IRQ_PMC_IDLE_EXIT                  50 /* 0x32 */
+#define PGP_IRQ_PORE_SW_COMPLETE               51 /* 0x33 */
+#define PGP_IRQ_PMC_IDLE_ENTER                 52 /* 0x34 */
+#define PGP_IRQ_RESERVED_53                    53 /* 0x35 */
+#define PGP_IRQ_PMC_INTERCHIP_MSG_SEND_ONGOING 54 /* 0x36 */
+#define PGP_IRQ_OCI2SPIVID_ONGOING             55 /* 0x37 */
+#define PGP_IRQ_PMC_OCB_O2P_ONGOING            56 /* 0x38 */
+#define PGP_IRQ_PSSBRIDGE_ONGOING              57 /* 0x39 */
+#define PGP_IRQ_PORE_SBE_COMPLETE              58 /* 0x3a */
+#define PGP_IRQ_IPI0                           59 /* 0x3b */
+#define PGP_IRQ_IPI1                           60 /* 0x3c */
+#define PGP_IRQ_IPI2                           61 /* 0x3d */
+#define PGP_IRQ_IPI3                           62 /* 0x3e */
+#define PGP_IRQ_RESERVED_63                    63 /* 0x3f */
+
+
+// Note: All standard-product IPI uses are declared here to avoid conflicts
+// Validation- and lab-only IPI uses are documented in validation.h
+
+/// The deferred callback queue interrupt
+///
+/// This IPI is reserved for use of the async deferred callback mechanism.
+/// This IPI is used by both critical and noncritical async handlers to
+/// activate the deferred callback mechanism.
+#define PGP_IRQ_ASYNC_IPI PGP_IRQ_IPI3
+
+
+// Please keep the string definitions up-to-date as they are used for
+// reporting in the Simics simulation.
+
+#define PGP_IRQ_STRINGS(var)                      \
+    const char* var[64] = {                       \
+        "PGP_IRQ_DEBUGGER",                       \
+        "PGP_IRQ_TRACE_TRIGGER",                  \
+        "PGP_IRQ_RESERVED_2",                     \
+        "PGP_IRQ_PBA_ERROR",                      \
+        "PGP_IRQ_SRT_ERROR",                      \
+        "PGP_IRQ_PORE_SW_ERROR",                  \
+        "PGP_IRQ_PORE_GPE0_FATAL_ERROR",          \
+        "PGP_IRQ_PORE_GPE1_FATAL_ERROR",          \
+        "PGP_IRQ_PORE_SBE_FATAL_ERROR",           \
+        "PGP_IRQ_PMC_ERROR",                      \
+        "PGP_IRQ_OCB_ERROR",                      \
+        "PGP_IRQ_SPIPSS_ERROR",                   \
+        "PGP_IRQ_CHECK_STOP",                     \
+        "PGP_IRQ_PMC_MALF_ALERT",                 \
+        "PGP_IRQ_ADU_MALF_ALERT",                 \
+        "PGP_IRQ_EXTERNAL_TRAP",                  \
+        "PGP_IRQ_OCC_TIMER0",                     \
+        "PGP_IRQ_OCC_TIMER1",                     \
+        "PGP_IRQ_PORE_GPE0_ERROR",                \
+        "PGP_IRQ_PORE_GPE1_ERROR",                \
+        "PGP_IRQ_PORE_SBE_ERROR",                 \
+        "PGP_IRQ_PMC_INTERCHIP_MSG_RECV",         \
+        "PGP_IRQ_RESERVED_22",                    \
+        "PGP_IRQ_PORE_GPE0_COMPLETE",             \
+        "PGP_IRQ_PORE_GPE1_COMPLETE",             \
+        "PGP_IRQ_ADCFSM_ONGOING",                 \
+        "PGP_IRQ_RESERVED_26",                    \
+        "PGP_IRQ_PBA_OCC_PUSH0",                  \
+        "PGP_IRQ_PBA_OCC_PUSH1",                  \
+        "PGP_IRQ_PBA_BCDE_ATTN",                  \
+        "PGP_IRQ_PBA_BCUE_ATTN",                  \
+        "PGP_IRQ_RESERVED_31",                    \
+        "PGP_IRQ_RESERVED_32",                    \
+        "PGP_IRQ_RESERVED_33",                    \
+        "PGP_IRQ_STRM0_PULL",                     \
+        "PGP_IRQ_STRM0_PUSH",                     \
+        "PGP_IRQ_STRM1_PULL",                     \
+        "PGP_IRQ_STRM1_PUSH",                     \
+        "PGP_IRQ_STRM2_PULL",                     \
+        "PGP_IRQ_STRM2_PUSH",                     \
+        "PGP_IRQ_STRM3_PULL",                     \
+        "PGP_IRQ_STRM3_PUSH",                     \
+        "PGP_IRQ_RESERVED_42",                    \
+        "PGP_IRQ_RESERVED_43",                    \
+        "PGP_IRQ_PMC_VOLTAGE_CHANGE_ONGOING",     \
+        "PGP_IRQ_PMC_PROTOCOL_ONGOING",           \
+        "PGP_IRQ_PMC_SYNC",                       \
+        "PGP_IRQ_PMC_PSTATE_REQUEST",             \
+        "PGP_IRQ_RESERVED_48",                    \
+        "PGP_IRQ_RESERVED_49",                    \
+        "PGP_IRQ_PMC_IDLE_EXIT",                  \
+        "PGP_IRQ_PORE_SW_COMPLETE",               \
+        "PGP_IRQ_PMC_IDLE_ENTER",                 \
+        "PGP_IRQ_RESERVED_53",                    \
+        "PGP_IRQ_PMC_INTERCHIP_MSG_SEND_ONGOING", \
+        "PGP_IRQ_OCI2SPIVID_ONGOING",             \
+        "PGP_IRQ_PMC_OCB_O2P_ONGOING",            \
+        "PGP_IRQ_PSSBRIDGE_ONGOING",              \
+        "PGP_IRQ_PORE_SBE_COMPLETE",              \
+        "PGP_IRQ_IPI0",                           \
+        "PGP_IRQ_IPI1",                           \
+        "PGP_IRQ_IPI2",                           \
+        "PGP_IRQ_IPI3 (ASYNC-IPI)",               \
+        "PGP_IRQ_RESERVED_63"                     \
+    };
+
+
+/// This constant is used to define the size of the table of interrupt handler
+/// structures as well as a limit for error checking.  The entire 64-bit
+/// vector is now in use.
+
+#define PPC405_IRQS 64
+
+#ifndef __ASSEMBLER__
+
+/// This expression recognizes only those IRQ numbers that have named
+/// (non-reserved) interrupts in the OCB interrupt controller.
+
+// There are so many invalid interrupts now that it's a slight improvement in
+// code size to let the compiler optimize the invalid IRQs to a bit mask for
+// the comparison.
+
+#define PGP_IRQ_VALID(irq) \
+    ({unsigned __irq = (unsigned)(irq); \
+        ((__irq < PPC405_IRQS) &&                               \
+         ((PGP_IRQ_MASK64(__irq) &                              \
+           (PGP_IRQ_MASK64(PGP_IRQ_RESERVED_2)  |               \
+            PGP_IRQ_MASK64(PGP_IRQ_RESERVED_22) |               \
+            PGP_IRQ_MASK64(PGP_IRQ_RESERVED_26) |               \
+            PGP_IRQ_MASK64(PGP_IRQ_RESERVED_31) |               \
+            PGP_IRQ_MASK64(PGP_IRQ_RESERVED_32) |               \
+            PGP_IRQ_MASK64(PGP_IRQ_RESERVED_33) |               \
+            PGP_IRQ_MASK64(PGP_IRQ_RESERVED_42) |               \
+            PGP_IRQ_MASK64(PGP_IRQ_RESERVED_43) |               \
+            PGP_IRQ_MASK64(PGP_IRQ_RESERVED_48) |               \
+            PGP_IRQ_MASK64(PGP_IRQ_RESERVED_49) |               \
+            PGP_IRQ_MASK64(PGP_IRQ_RESERVED_53) |               \
+            PGP_IRQ_MASK64(PGP_IRQ_RESERVED_63))) == 0));})
+
+/// This is a 32-bit mask, with big-endian bit (irq % 32) set.
+#define PGP_IRQ_MASK32(irq) (((uint32_t)0x80000000) >> ((irq) % 32))
+
+/// This is a 64-bit mask, with big-endian bit 'irq' set.
+#define PGP_IRQ_MASK64(irq) (0x8000000000000000ull >> (irq))
+
+#endif  /* __ASSEMBLER__ */
+
+
+////////////////////////////////////////////////////////////////////////////
+// OCB
+////////////////////////////////////////////////////////////////////////////
+
+/// The base address of the OCI control register space
+#define OCI_REGISTER_SPACE_BASE 0x40000000
+
+/// The base address of the entire PIB port mapped by the OCB.  The
+/// OCB-contained PIB registers are based at OCB_PIB_BASE.
+#define OCB_PIB_SLAVE_BASE 0x00060000
+
+/// The size of the OCI control register address space
+///
+/// There are at most 8 slaves, each of which maps 2**16 bytes of register
+/// address space.
+#define OCI_REGISTER_SPACE_SIZE POW2_32(19)
+
+/// This macro converts an OCI register space address into a PIB address as
+/// seen through the OCB direct bridge.
+#define OCI2PIB(addr) ((((addr) & 0x0007ffff) >> 3) + OCB_PIB_SLAVE_BASE)
+
+
+// OCB communication channel constants
+
+#define OCB_INDIRECT_CHANNELS 4
+
+#define OCB_RW_READ  0
+#define OCB_RW_WRITE 1
+
+#define OCB_STREAM_MODE_DISABLED 0
+#define OCB_STREAM_MODE_ENABLED  1
+
+#define OCB_STREAM_TYPE_LINEAR   0
+#define OCB_STREAM_TYPE_CIRCULAR 1
+
+#define OCB_INTR_ACTION_FULL      0
+#define OCB_INTR_ACTION_NOT_FULL  1
+#define OCB_INTR_ACTION_EMPTY     2
+#define OCB_INTR_ACTION_NOT_EMPTY 3
+
+#ifndef __ASSEMBLER__
+
+// These macros select OCB interrupt controller registers based on the IRQ
+// number.
+
+#define OCB_OIMR_AND(irq) (((irq) & 0x20) ? OCB_OIMR1_AND : OCB_OIMR0_AND)
+#define OCB_OIMR_OR(irq)  (((irq) & 0x20) ? OCB_OIMR1_OR  : OCB_OIMR0_OR)
+
+#define OCB_OISR(irq)     (((irq) & 0x20) ? OCB_OISR1     : OCB_OISR0)
+#define OCB_OISR_AND(irq) (((irq) & 0x20) ? OCB_OISR1_AND : OCB_OISR0_AND)
+#define OCB_OISR_OR(irq)  (((irq) & 0x20) ? OCB_OISR1_OR  : OCB_OISR0_OR)
+
+#define OCB_OIEPR(irq) (((irq) & 0x20) ? OCB_OIEPR1 : OCB_OIEPR0)
+#define OCB_OITR(irq)  (((irq) & 0x20) ? OCB_OITR1  : OCB_OITR0)
+#define OCB_OCIR(irq)  (((irq) & 0x20) ? OCB_OCIR1  : OCB_OCIR0)
+#define OCB_OUDER(irq) (((irq) & 0x20) ? OCB_OUDER1 : OCB_OUDER0)
+
+#endif  /* __ASSEMBLER__ */
+
+
+////////////////////////////////////////////////////////////////////////////
+// PMC
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __ASSEMBLER__
+
+/// A Pstate type
+///
+/// Pstates are signed, but our register access macros operate on unsigned
+/// values.  To avoid bugs, Pstate register fields should always be extracted
+/// to a variable of type Pstate.  If the size of Pstate variables ever
+/// changes we will have to revisit this convention.
+typedef int8_t Pstate;
+
+/// A DPLL frequency code
+///
+/// DPLL frequency codes moved from 8 to 9 bits going from P7 to P8
+typedef uint16_t DpllCode;
+
+/// A VRM11 VID code
+typedef uint8_t Vid11;
+
+#endif  /* __ASSEMBLER__ */
+
+/// The minimum Pstate
+#define PSTATE_MIN -128
+
+/// The maximum Pstate
+#define PSTATE_MAX 127
+
+/// The minimum \e legal DPLL frequency code
+///
+/// This is ~1GHz with a 16.6MHz tick frequency.
+#define DPLL_MIN 0x03c
+
+/// The maximum DPLL frequency code
+#define DPLL_MAX 0x1ff
+
+/// The minimum \a legal (non-power-off) VRM11 VID code
+#define VID11_MIN 0x02
+
+/// The maximum \a legal (non-power-off) VRM11 VID code
+#define VID11_MAX 0xfd
+
+
+////////////////////////////////////////////////////////////////////////////
+// PCB
+////////////////////////////////////////////////////////////////////////////
+
+/// Convert a core chiplet 0 SCOM address to the equivalent address for any
+/// other core chiplet.
+///
+/// Note that it is unusual to address core chiplet SCOMs directly.  Normally
+/// this is done as part of a GPE program where the program iterates over core
+/// chiplets, using the chiplet-0 address + a programmable offset held in a
+/// chiplet address register.  Therefore the only address macro defined is the
+/// chiplet-0 address. This macro is used for the rare cases of explicit
+/// getscom()/ putscom() to a particular chiplet.
+
+#define CORE_CHIPLET_ADDRESS(addr, core) ((addr) + ((core) << 24))
+
+
+// PCB Error codes
+
+#define PCB_ERROR_NONE              0
+#define PCB_ERROR_RESOURCE_OCCUPIED 1
+#define PCB_ERROR_CHIPLET_OFFLINE   2
+#define PCB_ERROR_PARTIAL_GOOD      3
+#define PCB_ERROR_ADDRESS_ERROR     4
+#define PCB_ERROR_CLOCK_ERROR       5
+#define PCB_ERROR_PACKET_ERROR      6
+#define PCB_ERROR_TIMEOUT           7
+
+// PCB Multicast modes
+
+#define PCB_MULTICAST_OR      0
+#define PCB_MULTICAST_AND     1
+#define PCB_MULTICAST_SELECT  2
+#define PCB_MULTICAST_COMPARE 4
+#define PCB_MULTICAST_WRITE   5
+
+/// \defgroup pcb_multicast_groups PCB Multicast Groups
+///
+/// Technically the multicast groups are programmable; This is the multicast
+/// grouping established by proc_sbe_chiplet_init().
+///
+/// - Group 0 : All functional chiplets (PRV PB XBUS ABUS PCIE TPCEX)
+/// - Group 1 : All functional EX chiplets (no cores)
+/// - Group 2 : All functional EX chiplets (core only)
+/// - Group 3 : All functional chiplets except pervasive (PRV)
+///
+/// @{
+
+#define MC_GROUP_ALL         0
+#define MC_GROUP_EX          1
+#define MC_GROUP_EX_CORE     2
+#define MC_GROUP_ALL_BUT_PRV 3
+
+/// @}
+
+
+/// Convert any SCOM address to a multicast address
+#define MC_ADDRESS(address, group, mode) \
+    (((address) & 0x00ffffff) | ((0x40 | ((mode) << 3) | (group)) << 24))
+
+
+
+////////////////////////////////////////////////////////////////////////////
+// PBA
+////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////
+// Macros for fields of PBA_MODECTL
+////////////////////////////////////
+
+/// The 64KB OCI HTM marker space is enabled by default at 0x40070000
+///
+/// See the comments for pgp_trace.h
+
+#define PBA_OCI_MARKER_BASE 0x40070000
+
+
+// SSX Kernel reserved trace addresses, see pgp_trace.h.
+
+#define SSX_TRACE_CRITICAL_IRQ_ENTRY_BASE           0xf000
+#define SSX_TRACE_CRITICAL_IRQ_EXIT_BASE            0xf100
+#define SSX_TRACE_NONCRITICAL_IRQ_ENTRY_BASE        0xf200
+#define SSX_TRACE_NONCRITICAL_IRQ_EXIT_BASE         0xf300
+#define SSX_TRACE_THREAD_SWITCH_BASE                0xf400
+#define SSX_TRACE_THREAD_SLEEP_BASE                 0xf500
+#define SSX_TRACE_THREAD_WAKEUP_BASE                0xf600
+#define SSX_TRACE_THREAD_SEMAPHORE_PEND_BASE        0xf700
+#define SSX_TRACE_THREAD_SEMAPHORE_POST_BASE        0xf800
+#define SSX_TRACE_THREAD_SEMAPHORE_TIMEOUT_BASE     0xf900
+#define SSX_TRACE_THREAD_SUSPENDED_BASE             0xfa00
+#define SSX_TRACE_THREAD_DELETED_BASE               0xfb00
+#define SSX_TRACE_THREAD_COMPLETED_BASE             0xfc00
+#define SSX_TRACE_THREAD_MAPPED_RUNNABLE_BASE       0xfd00
+#define SSX_TRACE_THREAD_MAPPED_SEMAPHORE_PEND_BASE 0xfe00
+#define SSX_TRACE_THREAD_MAPPED_SLEEPING_BASE       0xff00
+
+
+// Please keep the string definitions up to date as they are used for
+// reporting in the Simics simulation.
+
+#define SSX_TRACE_STRINGS(var)                  \
+    const char* var[16] = {                     \
+        "Critical IRQ Entry             ",      \
+        "Critical IRQ Exit              ",      \
+        "Noncritical IRQ Entry          ",      \
+        "Noncritical IRQ Exit           ",      \
+        "Thread Switch                  ",      \
+        "Thread Blocked : Sleep         ",      \
+        "Thread Unblocked : Wakeup      ",      \
+        "Thread Blocked : Semaphore     ",      \
+        "Thread Unblocked : Semaphore   ",      \
+        "Thread Unblocked : Sem. Timeout",      \
+        "Thread Suspended               ",      \
+        "Thread Deleted                 ",      \
+        "Thread Completed               ",      \
+        "Thread Mapped Runnable         ",      \
+        "Thread Mapped Semaphore Pend.  ",      \
+        "Thread Mapped Sleeping         ",      \
+    };
+
+
+// PBA transaction sizes for the block copy engines
+
+#define PBA_BCE_OCI_TRANSACTION_32_BYTES 0
+#define PBA_BCE_OCI_TRANSACTION_64_BYTES 1
+#define PBA_BCE_OCI_TRANSACTION_8_BYTES  2
+
+
+// PBAX communication channel constants
+
+#define PBAX_CHANNELS 2
+
+#define PBAX_INTR_ACTION_FULL      0
+#define PBAX_INTR_ACTION_NOT_FULL  1
+#define PBAX_INTR_ACTION_EMPTY     2
+#define PBAX_INTR_ACTION_NOT_EMPTY 3
+
+
+////////////////////////////////////////////////////////////////////////////
+// VRM
+////////////////////////////////////////////////////////////////////////////
+
+// These are the command types recognized by the VRMs
+
+#define VRM_WRITE_VOLTAGE  0x0
+#define VRM_READ_STATE     0xc
+#define VRM_READ_VOLTAGE   0x3
+
+// Voltage rail designations for the read voltage command
+#define VRM_RD_VDD_RAIL    0x0
+#define VRM_RD_VCS_RAIL    0x1
+
+
+////////////////////////////////////////////////////////////////////////////
+// OHA
+////////////////////////////////////////////////////////////////////////////
+
+// Power proxy trace record idle state encodings.  These encodings are unique
+// to the Power proxy trace record.
+
+#define PPT_IDLE_NON_IDLE     0x0
+#define PPT_IDLE_NAP          0x1
+#define PPT_IDLE_LIGHT_SLEEP  0x2
+#define PPT_IDLE_FAST_SLEEP   0x3
+#define PPT_IDLE_DEEP_SLEEP   0x4
+#define PPT_IDLE_LIGHT_WINKLE 0x5
+#define PPT_IDLE_FAST_WINKLE  0x6
+#define PPT_IDLE_DEEP_WINKLE  0x7
+
+
+////////////////////////////////////////////////////////////////////////////
+// PC
+////////////////////////////////////////////////////////////////////////////
+
+// SPRC numbers for PC counters.  The low-order 3 bits are always defined as
+// 0. The address can also be modifed to indicate auto-increment addressing.
+// Note that the frequency-sensitivity counters are called "workrate" counters
+// in the hardware documentation.
+
+#define SPRN_CORE_INSTRUCTION_DISPATCH         0x200
+#define SPRN_CORE_INSTRUCTION_COMPLETE         0x208
+#define SPRN_CORE_FREQUENCY_SENSITIVITY_BUSY   0x210
+#define SPRN_CORE_FREQUENCY_SENSITIVITY_FINISH 0x218
+#define SPRN_CORE_RUN_CYCLE                    0x220
+#define SPRN_CORE_RAW_CYCLE                    0x228
+#define SPRN_CORE_MEM_HIER_A                   0x230
+#define SPRN_CORE_MEM_HIER_B                   0x238
+#define SPRN_CORE_MEM_C_LPAR(p)                (0x240 + (8 * (p)))
+#define SPRN_WEIGHTED_INSTRUCTION_PROCESSING   0x260
+#define SPRN_WEIGHTED_GPR_REGFILE_ACCESS       0x268
+#define SPRN_WEIGHTED_VRF_REGFILE_ACCESS       0x270
+#define SPRN_WEIGHTED_FLOATING_POINT_ISSUE     0x278
+#define SPRN_WEIGHTED_CACHE_READ               0x280
+#define SPRN_WEIGHTED_CACHE_WRITE              0x288
+#define SPRN_WEIGHTED_ISSUE                    0x290
+#define SPRN_WEIGHTED_CACHE_ACCESS             0x298
+#define SPRN_WEIGHTED_VSU_ISSUE                0x2a0
+#define SPRN_WEIGHTED_FXU_ISSUE                0x2a8
+
+#define SPRN_THREAD_RUN_CYCLES(t)              (0x2b0 + (0x20 * (t)))
+#define SPRN_THREAD_INSTRUCTION_COMPLETE(t)    (0x2b8 + (0x20 * (t)))
+#define SPRN_THREAD_MEM_HIER_A(t)              (0x2c0 + (0x20 * (t)))
+#define SPRN_THREAD_MEM_HIER_B(t)              (0x2c8 + (0x20 * (t)))
+
+#define SPRN_PC_AUTOINCREMENT                  0x400
+
+
+////////////////////////////////////////////////////////////////////////////
+// Centaur
+////////////////////////////////////////////////////////////////////////////
+
+// DIMM sensor status codes
+
+/// The next sampling period began before this sensor was read or the master
+/// enable is off, or the individual sensor is disabled. If the subsequent
+/// read completes on time, this will return to valid reading. Sensor data may
+/// be accurate, but stale.  If due to a stall, the StallError FIR will be
+/// set.
+#define DIMM_SENSOR_STATUS_STALLED 0
+
+/// The sensor data was not returned correctly either due to parity
+/// error or PIB bus error code. Will return to valid if the next PIB
+/// access to this sensor is valid, but a FIR will be set; Refer to FIR
+/// for exact error. Sensor data should not be considered valid while
+/// this code is present.
+#define DIMM_SENSOR_STATUS_ERROR 1
+
+/// Sensor data is valid, and has been valid since the last time this
+/// register was read.
+#define DIMM_SENSOR_STATUS_VALID_OLD 2
+
+/// Sensor data is valid and has not yet been read by a SCOM. The status code
+/// return to DIMM_SENSOR_STATUS_VALID_OLD after this register is read.
+#define DIMM_SENSOR_STATUS_VALID_NEW 3
+
+
+#endif  /* __PGP_COMMON_H__ */
diff --git a/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/pgp_pba.h b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/pgp_pba.h
new file mode 100644
index 000000000..20b59ce62
--- /dev/null
+++ b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/pgp_pba.h
@@ -0,0 +1,357 @@
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/pgp_pba.h $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+#ifndef __PGP_PBA_H__
+#define __PGP_PBA_H__
+
+// $Id: pgp_pba.h,v 1.1 2012/08/13 13:04:35 stillgs Exp $
+
+/// \file pgp_pba.h
+/// \brief PBA unit header.  Local and mechanically generated macros.
+
+/// \todo Add Doxygen grouping to constant groups
+
+//#include "pba_register_addresses.h"
+#include "pba_firmware_registers.h"
+
+#define POWERBUS_CACHE_LINE_SIZE 128
+#define LOG_POWERBUS_CACHE_LINE_SIZE 7
+
+/// The PBA OCI region is always either 0 or 3
+#define PBA_OCI_REGION 0
+
+// It is assumed the the PBA BAR sets will be assigned according to the
+// following scheme.  There are still many open questions concerning PBA
+// setup. 
+
+/// The number of PBA Base Address Registers (BARS)
+#define PBA_BARS 4
+
+#define PBA_BAR_CHIP    0
+#define PBA_BAR_NODE    1
+#define PBA_BAR_SYSTEM  2
+#define PBA_BAR_CENTAUR 3
+
+// Standard PBA slave assignments, set up by FAPI procedure prior to releasing
+// OCC from reset.
+
+#define PBA_SLAVE_PORE_GPE 0    /* GPE0/1, but only 1 can access mainstore */
+#define PBA_SLAVE_OCC      1	/* 405 I- and D-cache */
+#define PBA_SLAVE_PORE_SLW 2	
+#define PBA_SLAVE_OCB      3	
+
+/// The maximum number of bytes a PBA block-copy engine can transfer at once
+#define PBA_BCE_SIZE_MAX 4096
+
+/// The base-2 log of the minimum PBA translation window size in bytes
+#define PBA_LOG_SIZE_MIN 20
+
+/// The base-2 log of the maximum PBA translation window size in bytes
+///
+/// Note that windows > 2**27 bytes require the extended address.
+#define PBA_LOG_SIZE_MAX 41
+
+/// The number of PBA slaves
+#define PBA_SLAVES 4
+
+/// The number of PBA read buffers
+#define PBA_READ_BUFFERS 6
+
+/// The number of PBA write buffers
+#define PBA_WRITE_BUFFERS 2
+
+
+////////////////////////////////////
+// Macros for fields of PBA_SLVCTLn
+////////////////////////////////////
+
+// PBA write Ttypes
+
+#define PBA_WRITE_TTYPE_DMA_PR_WR    0x0 /// DMA Partial Write
+#define PBA_WRITE_TTYPE_LCO_M        0x1 /// L3 LCO, Tsize denotes chiplet
+#define PBA_WRITE_TTYPE_ATOMIC_RMW   0x2 /// Atomic operations
+#define PBA_WRITE_TTYPE_CACHE_INJECT 0x3 /// ?
+#define PBA_WRITE_TTYPE_CI_PR_W      0x4 /// Cache-inhibited partial write for Centaur putscom().
+
+#define PBA_WRITE_TTYPE_DC PBA_WRITE_TTYPE_DMA_PR_WR // Don't care
+
+
+// PBA write Tsize is only required for PBA_WRITE_TTYPE_LCO_M (where it
+// actually specifies a core chiplet id) and PBA_WRITE_TTYPE_ATOMIC_RMW.
+
+#define PBA_WRITE_TSIZE_CHIPLET(chiplet) (chiplet)
+
+#define PBA_WRITE_TSIZE_ARMW_ADD 0x03
+#define PBA_WRITE_TSIZE_ARMW_AND 0x13
+#define PBA_WRITE_TSIZE_ARMW_OR  0x23
+#define PBA_WRITE_TSIZE_ARMW_XOR 0x33
+
+#define PBA_WRITE_TSIZE_DC 0x0
+
+
+// PBA write gather timeouts are defined in terms of the number of 'pulses'. A
+// pulse occurs every 64 OCI cycles. The timing of the last write of a
+// sequence is variable, so the timeout will occur somewhere between (N - 1) *
+// 64 and N * 64 OCI cycles.  If write gather timeouts are disabled, the PBA
+// holds the data until some condition occurs that causes it to disgorge the
+// data. Slaves using cache-inhibited partial write never gather write
+// data. Note from spec. : "Write gather timeouts must NOT be disabled if
+// multiple masters are enabled to write through the PBA".  The only case
+// where write gather timeouts will be disabled is for the IPL-time injection
+// of data into the L3 caches.
+
+#define PBA_WRITE_GATHER_TIMEOUT_DISABLE   0x0
+#define PBA_WRITE_GATHER_TIMEOUT_2_PULSES  0x4
+#define PBA_WRITE_GATHER_TIMEOUT_4_PULSES  0x5
+#define PBA_WRITE_GATHER_TIMEOUT_8_PULSES  0x6
+#define PBA_WRITE_GATHER_TIMEOUT_16_PULSES 0x7
+
+/// PBA write gather timeout don't care assignment
+#define PBA_WRITE_GATHER_TIMEOUT_DC PBA_WRITE_GATHER_TIMEOUT_2_PULSES
+
+
+// PBA read Ttype
+
+#define PBA_READ_TTYPE_CL_RD_NC      0x0 /// Cache line read
+#define PBA_READ_TTYPE_CI_PR_RD      0x1 /// Cache-inhibited partial read for Centaur getscom().
+
+/// PBA read TTYPE don't care assignment
+#define PBA_READ_TTYPE_DC PBA_READ_TTYPE_CL_RD_NC      
+
+
+// PBA read prefetch options
+
+#define PBA_READ_PREFETCH_AUTO_EARLY  0x0 /// Aggressive prefetch
+#define PBA_READ_PREFETCH_NONE        0x1 /// No prefetch
+#define PBA_READ_PREFETCH_AUTO_LATE   0x2 /// Non-aggressive prefetch
+
+/// PBA read prefetch don't care assignment
+#define PBA_READ_PREFETCH_DC PBA_READ_PREFETCH_NONE        
+
+
+// PBA PowerBus command scope and priority, and PBA defaults
+
+/// Nodal, Local Node
+#define POWERBUS_COMMAND_SCOPE_NODAL 0x0 
+
+/// Group, Local 4-chip, (aka, node pump)
+#define POWERBUS_COMMAND_SCOPE_GROUP 0x1
+
+/// System,  All units in the system
+#define POWERBUS_COMMAND_SCOPE_SYSTEM 0x2ss
+
+/// RGP, All units in the system (aka, system pump)
+#define POWERBUS_COMMAND_SCOPE_RGP 0x3
+
+/// Foreign, All units on the local chip, local SMP, and remote chip (pivot
+/// nodes), In P8, only 100 and 101 are valid.
+#define POWERBUS_COMMAND_SCOPE_FOREIGN0 0x4 
+
+/// Foreign, All units on the local chip, local SMP, and remote chip (pivot
+/// nodes), In P8, only 100 and 101 are valid.
+#define POWERBUS_COMMAND_SCOPE_FOREIGN1 0x5
+
+
+/// Default command scope for BCDE/BCUE transfers
+#define PBA_POWERBUS_COMMAND_SCOPE_DEFAULT POWERBUS_COMMAND_SCOPE_NODAL
+
+
+
+// Abstract fields of the PBA Slave Reset register used in pba_slave_reset(),
+// which checks 'n' for validity.p
+
+#define PBA_SLVRST_SET(n) (4 + (n))
+#define PBA_SLVRST_IN_PROG(n) (0x8 >> (n))
+
+/// The default timeout for pba_slave_reset().
+///
+/// Currently the procedure pba_slave_reset() is thought to be an
+/// initialization-only and/or lab-only procedure, so this long polling
+/// timeout is not a problem.  In the lab, a SCOM poll is ~1us to this
+/// value is in ~us units
+#ifndef PBA_SLAVE_RESET_TIMEOUT
+#define PBA_SLAVE_RESET_TIMEOUT 100 
+#endif 
+
+
+// PBA Error/Panic codes
+
+#define PBA_SCOM_ERROR       0x00722001
+#define PBA_SLVRST_TIMED_OUT 0x00722002
+
+#ifndef __ASSEMBLER__
+
+/// The PBA extended address in the form of a 'firmware register'
+///
+/// The extended address covers only bits 23:36 of the 50-bit PowerBus address.
+
+typedef union pba_extended_address {
+
+    uint64_t value;
+    uint32_t word[2];
+    struct {
+	uint64_t reserved0        : 23;
+	uint64_t extended_address : 14;
+	uint64_t reserved1        : 27;
+    } fields;
+} pba_extended_address_t;
+
+
+int 
+pba_barset_initialize(int idx, uint64_t base, int log_size);
+
+
+
+////////////////////////////////////////////////////////////////////////////
+// PBAX
+////////////////////////////////////////////////////////////////////////////
+
+// PBAX error/panic codes
+
+#define PBAX_SEND_TIMEOUT  0x00722901
+#define PBAX_SEND_ERROR    0x00722902
+#define PBAX_RECEIVE_ERROR 0x00722903
+
+/// The number of receive queues implemented by PBAX
+#define PBAX_QUEUES 2
+
+/// The number of PBAX Node Ids
+#define PBAX_NODES 8
+
+/// The number of PBAX Chip Ids (and group Ids)
+#define PBAX_CHIPS 8
+#define PBAX_GROUPS PBAX_CHIPS
+
+/// The maximum legal PBAX group mask
+#define PBAX_GROUP_MASK_MAX 0xff
+
+// PBAX Send Message Scope
+
+#define PBAX_GROUP  1
+#define PBAX_SYSTEM 2
+
+// PBAX Send Type
+
+#define PBAX_UNICAST   0
+#define PBAX_BROADCAST 1
+
+// Default timeout for pbax_send()
+
+#ifndef PBAX_SEND_DEFAULT_TIMEOUT
+#define PBAX_SEND_DEFAULT_TIMEOUT SSX_MICROSECONDS(15)
+#endif
+
+/*
+/// An abstract target for PBAX send operations
+///
+/// This structure contains an abstraction of a communication target for PBAX
+/// send operations.  An application using PBAX to transmit data first creates
+/// an instance of the PbaxTarget for each abstract target using
+/// pbax_target_create(), then calls pbax_send() or _pbax_send() with a
+/// PbaxTarget and an 8-byte data packet to effect a transmission.
+///
+/// For applications that use GPE programs to implement PBAX sends, a pointer
+/// to this object could also be passed to the GPE program.
+
+typedef struct {
+
+    /// The abstract target
+    ///
+    /// pbax_target_create() condenses the target parameters into a copy of
+    /// the PBAXSNDTX register used to configure the transmission.
+    pba_xsndtx_t target;
+
+} PbaxTarget;
+
+
+int
+pbax_target_create(PbaxTarget* target,
+                   int type, int scope, int queue, 
+                   int node, int chip_or_group);
+
+int
+pbax_configure(int master, int node, int chip, int group_mask);
+
+int
+_pbax_send(PbaxTarget* target, uint64_t data, SsxInterval timeout);
+
+int
+pbax_send(PbaxTarget* target, uint64_t data);
+
+
+/// Enable the PBAX send mechanism
+
+static inline void
+pbax_send_enable()
+{
+    pba_xcfg_t pxc;
+
+    pxc.words.high_order = in32(PBA_XCFG);
+    pxc.fields.pbax_en = 1;
+    out32(PBA_XCFG, pxc.words.high_order);
+    
+}
+
+
+/// Disable the PBAX send mechanism
+
+static inline void
+pbax_send_disable()
+{
+    pba_xcfg_t pxc;
+
+    pxc.words.high_order = in32(PBA_XCFG);
+    pxc.fields.pbax_en = 0;
+    out32(PBA_XCFG, pxc.words.high_order);
+    
+}
+
+
+/// Clear the PBAX send error condition
+
+static inline void
+pbax_clear_send_error()
+{
+    pba_xcfg_t pxc;
+
+    pxc.words.high_order = in32(PBA_XCFG);
+    pxc.fields.snd_reset = 1;
+    out32(PBA_XCFG, pxc.words.high_order);
+}    
+
+
+/// Clear the PBAX receive error condition
+
+static inline void
+pbax_clear_receive_error()
+{
+    pba_xcfg_t pxc;
+
+    pxc.words.high_order = in32(PBA_XCFG);
+    pxc.fields.rcv_reset = 1;
+    out32(PBA_XCFG, pxc.words.high_order);
+}    
+*/
+#endif /* __ASSEMBLER__ */
+
+#endif	/* __PGP_PBA_H__ */
diff --git a/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_pba_bar_config.C b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_pba_bar_config.C
new file mode 100644
index 000000000..5e1dd7f6c
--- /dev/null
+++ b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_pba_bar_config.C
@@ -0,0 +1,301 @@
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_pba_bar_config.C $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+// $Id: proc_pba_bar_config.C,v 1.8 2012/08/13 13:04:20 stillgs Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pba_bar_config.C,v $
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! OWNER NAME: Klaus P. Gungl         Email: kgungl@de.ibm.com
+// *!
+// *! 
+/// \file proc_pba_bar_config.C
+/// \brief Initialize PAB and PAB_MSK of PBA
+// *!        
+// *! The purpose of this procedure is to set the PBA BAR, PBA BAR Mask and PBA scope value / registers
+// *! 
+// *! Following proposals here: pass values for one set of pbabar, pass reference to structure for one set of pbabar, pass struct of struct containing  
+// *! all setup values  
+// *!   
+// *! High-level procedure flow:
+// *!   parameter checking
+// *!   set PBA_BAR
+// *!   set PBA_BARMSK
+// *!  
+// *! Procedure Prereq:
+// *!   o System clocks are running
+// *!
+// *! list of changes
+// *! 2011/11/22 all variables / passing calling parameters are uint64_t, cmd_scope is enum, MASK is not bitmask parameter but size
+// *!            structure for init contain uint64_t only.       
+// *!
+//------------------------------------------------------------------------------
+
+    
+// ----------------------------------------------------------------------
+// Includes
+// ----------------------------------------------------------------------
+#include <fapi.H>
+#include "p8_scom_addresses.H"
+#include "proc_pba_init.H"
+#include "proc_pba_bar_config.H"
+#include "pba_firmware_register.H"
+#include "proc_pm.H"
+
+
+extern "C" {
+
+
+using namespace fapi;  
+
+// ---------------------------------------------------------------------- 
+// Constant definitions
+// ----------------------------------------------------------------------
+                              
+// for range checking            0x0123456701234567
+#define BAR_ADDR_RANGECHECK_     0x0003FFFFFFF00000ull
+#define BAR_ADDR_RANGECHECK_HIGH 0xFFFC000000000000ull
+#define BAR_ADDR_RANGECHECK_LOW  0x00000000000FFFFFull
+#define BAR_SIZE_RANGECHECK      0x000001FFFFF00000ull
+#define BAR_SIZE_RANGECHECK_HIGH 0xFFFFFE0000000000ull
+#define BAR_SIZE_RANGECHECK_LOW  0x00000000000FFFFFull
+
+// ----------------------------------------------------------------------
+// Global variables
+// ----------------------------------------------------------------------
+
+// ----------------------------------------------------------------------
+// Prototypes
+// ----------------------------------------------------------------------
+
+// ---------------------------------------------------------------------- 
+// Function definitions
+// ----------------------------------------------------------------------
+
+uint64_t PowerOf2Roundedup (uint64_t value);
+
+
+// --------------------------------------------- proc_pba_bar_config ----
+// function: 
+// initialize initialize a specific set of PBA_BAR (=cmd_scope and address), PBA_BARMSK (mask/size)
+// pass values directly
+//! init_pba_bar_ps
+//! initialize a set of  PBA_BAR and PBA_BARMSK registers, calling parameters: reference to structure of initialization values
+/*!
+@param i_target the target 
+@param i_index specifies which set of BAR / BARMSK registers to set. [0..3]
+@param i_pba_bar_addr PBA base address - 1MB grandularity
+@param i_pba_bar_size PBA region size in MB;  if not a power of two value, 
+        the value will be rounded up to the next power of 2 for setting the 
+        hardware mask
+@param i_pba_cmd_scope command scope according to pba spec
+*/ 
+
+fapi::ReturnCode 
+proc_pba_bar_config (const Target&  i_target,
+		             uint32_t       i_index, 
+		             uint64_t       i_pba_bar_addr,
+		             uint64_t       i_pba_bar_size,
+		             uint64_t       i_pba_cmd_scope 
+                     )
+{
+
+
+    ecmdDataBufferBase  data(64); 
+    fapi::ReturnCode    l_rc;
+    uint32_t            l_ecmdRc = 0;
+    
+    pba_barn_t          bar;  
+    pba_barmskn_t       barmask;
+    
+    uint64_t            work_size;
+
+    FAPI_DBG("Called with index %x, address 0x%16llX, size 0x%16llX scope 0x%16llX", 
+                        i_index, i_pba_bar_addr, i_pba_bar_size, i_pba_cmd_scope);
+
+    // check if pba_bar scope in range
+    if ( i_pba_cmd_scope > PBA_CMD_SCOPE_FOREIGN1 ) 
+    {
+        FAPI_ERR("ERROR: PB Command Scope out of Range");
+        FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_BAR_SCOPE_OUT_OF_RANGE);
+        return l_rc;
+    }
+
+    // check if pba_addr amd pba_size are within range, high order bits checked, not low order!
+    // this means if we need a check for "is this value on the correct boundary value => needs to be implemented
+    if ( (BAR_ADDR_RANGECHECK_HIGH & i_pba_bar_addr) != 0x0ull) 
+    {
+        FAPI_ERR("ERROR: Address out of Range");
+        FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_ADDR_OUT_OF_RANGE);
+        return l_rc;
+    } 
+    if ( (i_pba_bar_size) == 0x0ull) 
+    {
+        FAPI_ERR("ERROR: Size must be 1MB or greater");
+        FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_BAR_MASK_OUT_OF_RANGE);  // \todo change xml!!!
+        return l_rc;
+    } 
+    
+    // The PBA Mask indicates which bits from 23:43 (1MB grandularity) are
+    // enabled to be passed from the OCI addresses.  Inverting this mask
+    // indicates which address bits are going to come from the PBA BAR value.
+    // The image address (the starting address) must match these post mask bits
+    // to be resident in the range.
+    //
+    // Starting bit number: 64 bit Big Endian
+    //                                          12223344
+    //                                          60482604
+    // region_inverted_mask = i_mem_mask ^ BAR_MASK_LIMIT;  // XOR
+
+
+    // Check that the image address passed is within the memory region that
+    // is also passed.
+    //
+    // The PBA Mask indicates which bits from 23:43 (1MB grandularity) are
+    // enabled to be passed from the OCI addresses.  Inverting this mask
+    // indicates which address bits are going to come from the PBA BAR value.
+    // The image address (the starting address) must match these post mask bits
+    // to be resident in the range.
+    //
+    // Starting bit number: 64 bit Big Endian
+    //                                          12223344
+    //                                          60482604
+    // region_inverted_mask = i_mem_mask ^ BAR_MASK_LIMIT;  // XOR
+
+    // Set bits 14:22 as these are unconditional address bits
+    //region_inverted_mask = region_inverted_mask | BAR_ADDR_UNMASKED;
+    //computed_image_address = region_inverted_mask && image_address;
+    // Need to AND the address
+    //if (computed_image_address != i_mem_bar )
+    //{
+    //    FAPI_ERR("SLW image address check failure. ");
+    //    FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_IMAGE_ADDR_ERROR);
+    //    return rc;
+    //}
+    
+    
+    
+    // put the parameters into the correct fields 
+    bar.value=0;
+    bar.fields.cmd_scope = i_pba_cmd_scope;
+    bar.fields.addr = i_pba_bar_addr >> 20;
+    
+    FAPI_DBG("bar.fields   address  0x%16llX, scope  0x%16llX", 
+                        bar.fields.addr, bar.fields.cmd_scope);
+    FAPI_DBG("bar.value             0x%16llX", bar.value);
+    
+     // Write the BAR
+    l_ecmdRc |= data.setDoubleWord(0, bar.value);
+    if (l_ecmdRc) 
+    {
+       FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc);
+       l_rc.setEcmdError(l_ecmdRc);
+       return l_rc;
+    }
+    
+    FAPI_DBG("  PBA_BAR%x:  %16llX", i_index,  data.getDoubleWord(0));
+    l_rc = fapiPutScom(i_target, PBA_BARs[i_index], data);
+    if(l_rc) 
+    { 
+        FAPI_ERR("PBA_BAR Putscom failed");
+        return l_rc;
+    }
+  
+    // Compute and write the mask based on passed region size.
+    
+    // If the size is already a power of 2, then set the mask to that value - 1. 
+    // If the is not a power of 2, then set the mask the rounded up power of 2
+    // value minus 1.
+    
+    work_size = PowerOf2Roundedup(i_pba_bar_size);
+    FAPI_DBG("  i_pba_bar_size %16llu work_size:  %16llu", i_pba_bar_size, work_size);   
+    
+    barmask.value=0;   
+    barmask.fields.mask = work_size-1;
+    
+    FAPI_DBG("bar.fields   mask  0x%16llX", barmask.fields.mask);
+   
+    
+    // Write the MASK
+     
+    // The size is tranlated to a mask by:
+    //  Shifting the s
+    //
+    //
+    //
+    
+    l_ecmdRc |= data.setDoubleWord(0, barmask.value);
+    if (l_ecmdRc) 
+    {
+       FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc);
+       l_rc.setEcmdError(l_ecmdRc);
+       return l_rc;
+    }
+     
+    FAPI_DBG("  PBA_BARMSK%x:  %16llu", i_index,  data.getDoubleWord(0));
+    l_rc = fapiPutScom(i_target, PBA_BARMSKs[i_index], data);
+    if(l_rc) 
+    { 
+      FAPI_ERR("PBA_MASK Putscom failed");
+      return l_rc;
+    }
+
+    return l_rc;
+}  
+
+///-----------------------------------------------------------------------------
+/// Determine if a number is a power of two or not
+///----------------------------------------------------------------------------- 
+bool
+isPowerOfTwo(uint64_t value)
+{
+    // if value ANDed with the value-1 is 0, then value is a power of 2. 
+    // if value is 0, this is considered not a power of 2 and will return false.
+   
+    return !(value & (value - 1));
+   
+} 
+ 
+///----------------------------------------------------------------------------- 
+/// Round up to next higher power of 2 (return value if it's already a power of 
+/// 2).
+///----------------------------------------------------------------------------- 
+uint64_t
+PowerOf2Roundedup (uint64_t value)
+{
+    if (value < 0)
+        return 0;
+    --value;
+    value |= value >> 1;
+    value |= value >> 2;
+    value |= value >> 4;
+    value |= value >> 8;
+    value |= value >> 16;
+    return value+1;
+}
+
+ 
+} //end extern C
+
diff --git a/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_pba_bar_config.H b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_pba_bar_config.H
new file mode 100644
index 000000000..c9e15c404
--- /dev/null
+++ b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_pba_bar_config.H
@@ -0,0 +1,57 @@
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_pba_bar_config.H $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+#
+
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! OWNER NAME: Klaus P. Gungl         Email: kgungl@de.ibm.com
+// *!
+// *! General Description:
+// *!        
+// *! include file for proc_pba_bar_config 
+// *!
+//------------------------------------------------------------------------------
+// 
+
+
+// function pointer typedef definition for HWP call support
+typedef fapi::ReturnCode (*proc_pba_bar_config_FP_t) (const fapi::Target&, 
+                                                            uint32_t, 
+                                                            uint64_t, 
+                                                            uint64_t, 
+                                                            uint64_t);
+
+extern "C" 
+{				
+
+fapi::ReturnCode 
+proc_pba_bar_config (const fapi::Target&    i_target, 
+		             uint32_t               index, 
+		             uint64_t               pba_bar_addr,
+		             uint64_t               pba_bar_size,
+		             uint64_t               pba_cmd_scope);
+}
diff --git a/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_pba_slave_config.H b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_pba_slave_config.H
new file mode 100644
index 000000000..1cda73385
--- /dev/null
+++ b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_pba_slave_config.H
@@ -0,0 +1,94 @@
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_pba_slave_config.H $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+
+
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! OWNER NAME: Klaus P. Gungl         Email: kgungl@de.ibm.com
+// *!
+// *! General Description:
+// *!        
+// *! include file for proc_pba_slave_config 
+// *!
+//------------------------------------------------------------------------------
+// 
+
+
+// function pointer typedef definition for HWP call support
+typedef fapi::ReturnCode (*proc_pba_slave_config_FP_t) (const fapi::Target&, int, int, uint64_t);
+
+
+extern "C" 
+{
+
+
+
+typedef struct {
+    unsigned  enable:1;
+    unsigned  mid_match_value:2;
+    unsigned  Reserved1:1;
+    unsigned  mid_care_mask:3;
+    unsigned  write_ttype:3;
+    unsigned  Reserved2: 1;
+    unsigned  read_ttype:1;
+    unsigned  read_prefetch_ctl:2;
+    unsigned  buf_invalidate_ctl:8;
+    unsigned  buf_alloc_w:1;
+    unsigned  buf_alloc_a:1;
+    unsigned  buf_alloc_b:1;
+    unsigned  buf_alloc_c:1;
+    unsigned  Reserved3:1;
+    unsigned  dis_write_gather:1;
+    unsigned  wr_gather_timeout:3;
+    unsigned  write_tsize: 7;
+    unsigned  extaddr: 14;
+    unsigned  Reserved4: 2;
+    unsigned  Reserved5: 13;
+} pba_slvctl_reg_type;
+
+typedef union {
+  pba_slvctl_reg_type fields;
+  uint64_t value;
+} slvcntl_reg_type;
+
+
+
+  // ReturnCode proc_pba_slave_config (Target i_target, 
+  // 				proc_mode_type proc_mode, 
+  // 				int index, 
+  // 		     		struct_pba_bar_msk_scope_init_type* ps_pba_init
+  // 				// pba_slvctl_type pba_slvctl_init
+  // 				);
+
+fapi::ReturnCode 
+proc_pba_slave_config (const fapi::Target& i_target, 
+                       int proc_mode, 
+		               int index, 
+		               uint64_t pba_slvctl_init);
+}
+
+
diff --git a/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_set_pore_bar.C b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_set_pore_bar.C
index 5e91313c1..aca990fcb 100644
--- a/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_set_pore_bar.C
+++ b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_set_pore_bar.C
@@ -21,13 +21,13 @@
  *
  *  IBM_PROLOG_END_TAG
  */
-// $Id: proc_set_pore_bar.C,v 1.7 2012/07/25 12:26:28 stillgs Exp $
+// $Id: proc_set_pore_bar.C,v 1.8 2012/08/13 13:04:28 stillgs Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_set_pore_bar.C,v $
-//------------------------------------------------------------------------------
+//-------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
-//------------------------------------------------------------------------------
+//-------------------------------------------------------------------------------
 // *! OWNER NAME: Greg Still         Email: stillgs@us.ibm.com
 // *!
 /// \file proc_set_pore_bar.C
@@ -71,18 +71,21 @@
 ///     - SLW image memory region has been allocated and XIP image loaded.
 /// \endverbatim
 ///
-//------------------------------------------------------------------------------
+//-------------------------------------------------------------------------------
 
 
-// ----------------------------------------------------------------------
+// ------------------------------------------------------------------------------
 // Includes
-// ----------------------------------------------------------------------
+// ------------------------------------------------------------------------------
 #include <fapi.H>
 #include "p8_scom_addresses.H"
+#include "pgp_common.h"
 #include "proc_set_pore_bar.H"
 #include "proc_pm.H"
 #include "proc_pba_init.H"
 #include "proc_pba_bar_config.H"
+#include "pba_firmware_register.H"
+#include "pgp_pba.h"
 #include "sbe_xip_image.h"
 
 
@@ -90,32 +93,38 @@ extern "C" {
 
 using namespace fapi;
 
-// ----------------------------------------------------------------------
+// ------------------------------------------------------------------------------
 // Constant definitions
-// ----------------------------------------------------------------------
+// ------------------------------------------------------------------------------
 
 const uint32_t  SLW_PBA_BAR = 2;
+const uint32_t  SLW_PBA_SLAVE = 2;
 
-// ----------------------------------------------------------------------
+// ------------------------------------------------------------------------------
 // Global variables
-// ----------------------------------------------------------------------
+// ------------------------------------------------------------------------------
 
-// ----------------------------------------------------------------------
+// ------------------------------------------------------------------------------
 // Function prototypes
-// ----------------------------------------------------------------------
+// ------------------------------------------------------------------------------
 
-// ----------------------------------------------------------------------
+fapi::ReturnCode pba_slave_reset(   const fapi::Target& i_target,
+                                    uint32_t id);
+
+// ------------------------------------------------------------------------------
 // Function definitions
-// ----------------------------------------------------------------------
+// ------------------------------------------------------------------------------
 
 
 /// \param[in] i_target     Procesor Chip target
 /// \param[in] i_image      Platform memory pointer where image is
 ///                         located
 /// \param[in] i_mem_bar    Base address of the region where image is located
-/// \param[in] i_mem_mask   Mask that defines which address bits of the
-///                         BAR apply such to define the region size
-/// \param[in] i_mem_type Defines where the SLW image was loaded.  See
+/// \param[in] i_mem_size   Size (in MB) of the region where image is located
+///                         if not a power of two value, the value will be 
+///                         rounded up to the next power of 2 for setting the 
+///                         hardware mask
+/// \param[in] i_mem_type   Defines where the SLW image was loaded.  See
 ///                         proc_set_pore_bar.H enum for valid values.
 ///
 /// \retval SUCCESS
@@ -128,12 +137,12 @@ fapi::ReturnCode
 proc_set_pore_bar(      const fapi::Target& i_target,
                         void                *i_image,
                         uint64_t            i_mem_bar,
-                        uint64_t            i_mem_mask,
+                        uint64_t            i_mem_size,
                         uint32_t            i_mem_type)
 {
     fapi::ReturnCode    rc;
     uint32_t            l_ecmdRc = 0;
-    ecmdDataBufferBase  data;
+    ecmdDataBufferBase  data(64);
 
     uint64_t            image_address;
     uint64_t            image_size;
@@ -145,6 +154,8 @@ proc_set_pore_bar(      const fapi::Target& i_target,
 //    uint64_t            computed_last_image_address;
 
     uint64_t            slw_branch_table_address;
+    
+    pba_slvctln_t       ps;                         // PBA Slave
 
     // Hardcoded use of PBA BAR and Slave
     const uint32_t      pba_bar = PBA_BAR2;
@@ -395,20 +406,15 @@ proc_set_pore_bar(      const fapi::Target& i_target,
         FAPI_ERR("Put SCOM error for Memory Relocation Address");
         return rc;
     }
-    
-    
-
-
-    
-
-    FAPI_DBG("Calling pba_bar_config to BAR %x Addr: 0x%16llX  Mask: 0x%16llX",
-                    pba_bar, i_mem_bar, i_mem_mask);
+   
+    FAPI_DBG("Calling pba_bar_config to BAR %x Addr: 0x%16llX  Size: 0x%16llX",
+                    pba_bar, i_mem_bar, i_mem_size);
 
     // Set the PBA BAR for the SLW region
     FAPI_EXEC_HWP(rc, proc_pba_bar_config, i_target,
                                            pba_bar,
                                            i_mem_bar,
-                                           i_mem_mask,
+                                           i_mem_size,
                                            slw_pba_cmd_scope);
     if(rc) { return rc; }
 
@@ -423,7 +429,7 @@ proc_set_pore_bar(      const fapi::Target& i_target,
     // read_prefetch_ctl=0;        // Auto Early
     // buf_invalidate_ctl=0;       // Disabled
     // buf_alloc_w=0;              // SLW does not write.  24x7 will
-    // buf_alloc_a=0;              // SLW uses Buf A
+    // buf_alloc_a=1;              // SLW uses Buf A
     // buf_alloc_b=0;              // SLW does not use buffer B
     // buf_alloc_c=0;              // SLW does not use buffer C
     // dis_write_gather=0;         // SLW does not write.  \todo 24x7
@@ -432,6 +438,7 @@ proc_set_pore_bar(      const fapi::Target& i_target,
     // extaddr=0;                  // Bits 23:36.  NA for SLW
     //
 
+/*
     // Clear the data buffer (for cleanliness)
     l_ecmdRc |= data.flushTo0();
 
@@ -440,7 +447,39 @@ proc_set_pore_bar(      const fapi::Target& i_target,
     l_ecmdRc |= data.setBit(0);     // Enable the slave
     l_ecmdRc |= data.setBit(1);     // PORE-SLW engine - 0b100
     l_ecmdRc |= data.setBit(5,3);   // Care mask-only PORE-SLW
+    l_ecmdRc |= data.setBit(5,3);   // Allocate read buffer
+    l_ecmdRc |= data.setBit(5,3);   // Care mask-only PORE-SLW
+*/
+    
+    // Slave 2 (PORE-SLW).  This is a read/write slave. Write gathering is
+    // allowed, but with the shortest possible timeout.  The slave is set up
+    // to allow normal reads and writes at initialization.  The 24x7 code may
+    // reprogram this slave for IMA writes using special code sequences that
+    // restore normal DMA writes after each IMA sequence.
+
+    rc = pba_slave_reset(i_target, SLW_PBA_SLAVE);
+    if (rc)
+    {
+        FAPI_ERR("PBA Slave Reset failed");
+        // \todo add FFDC
+        return rc;
+    }
 
+    
+    ps.value = 0;
+    ps.fields.enable = 1;
+    ps.fields.mid_match_value = OCI_MASTER_ID_PORE_SLW;
+    ps.fields.mid_care_mask = 0x7;
+    ps.fields.read_ttype = PBA_READ_TTYPE_CL_RD_NC;
+    ps.fields.read_prefetch_ctl = PBA_READ_PREFETCH_NONE;
+    ps.fields.write_ttype = PBA_WRITE_TTYPE_DMA_PR_WR;
+    ps.fields.wr_gather_timeout = PBA_WRITE_GATHER_TIMEOUT_2_PULSES;
+    ps.fields.buf_alloc_a = 1;
+    ps.fields.buf_alloc_b = 1;
+    ps.fields.buf_alloc_c = 1;
+    ps.fields.buf_alloc_w = 1;
+    
+    l_ecmdRc |=  data.setDoubleWord(0, ps.value);
     if(l_ecmdRc)
     {
         FAPI_ERR("Error (0x%x) manipulating ecmdDataBufferBase for PBASLVCTL", l_ecmdRc);
@@ -459,5 +498,90 @@ proc_set_pore_bar(      const fapi::Target& i_target,
     return rc;
 }
 
+/// Reset a PBA slave with explicit timeout.  
+///
+/// \param id A PBA slave id in the range 0..3
+///
+/// \param timeout A value of SsxInterval type.  The special value
+/// SSX_WAIT_FOREVER indicates no timeout.
+///
+/// This form of pba_slave_reset() gives the caller control over timeouts and
+/// error handling.
+///
+/// \retval 0 Succes
+///
+/// \retval RC_PROCPM_PBA_SLVRST_TIMED_OUT The procedure timed out waiting for the PBA
+/// to reset the slave.
+
+fapi::ReturnCode
+pba_slave_reset(const fapi::Target& i_target, uint32_t id)
+{
+    
+    uint32_t            poll_count = 0;
+    pba_slvrst_t        psr;
+    fapi::ReturnCode    rc;
+    uint32_t            l_ecmdRc = 0;
+    ecmdDataBufferBase  data(64);
+
+    
+    // Tell PBA to reset the slave, then poll for completion with timeout.
+    // The PBA is always polled at least twice to guarantee that we always
+    // poll once after a timeout.
+
+    psr.value = 0;
+    psr.fields.set = PBA_SLVRST_SET(id);
+    
+    FAPI_DBG("  PBA_SLVRST%x: 0x%16llx", id, psr.value);
+    
+    l_ecmdRc |= data.setDoubleWord(0, psr.value);
+    if(l_ecmdRc)
+    {
+        FAPI_ERR("Error (0x%x) manipulating ecmdDataBufferBase for PBA_SLVRST", l_ecmdRc);
+        rc.setEcmdError(l_ecmdRc);
+        return rc;
+    }
+        
+    rc = fapiPutScom(i_target, PBA_SLVRST_0x00064001, data);
+    if (rc)
+    {
+        FAPI_ERR("Put SCOM error for PBA Slave Reset");
+        return rc;
+    }
+    
+    do 
+    {
+        rc = fapiGetScom(i_target, PBA_SLVRST_0x00064001, data);
+        if (rc)
+        {
+            FAPI_ERR("Put SCOM error for PBA Slave Reset");
+            return rc;
+        }
+
+        psr.value = data.getDoubleWord(0);
+        if(l_ecmdRc)
+        {
+            FAPI_ERR("Error (0x%x) manipulating ecmdDataBufferBase for PBA_SLVRST", l_ecmdRc);
+            rc.setEcmdError(l_ecmdRc);
+            return rc;
+        }
+        
+        
+        if (!(psr.fields.in_prog & PBA_SLVRST_IN_PROG(id))) 
+        {
+	        break;
+	    }
+        
+        poll_count++;
+	    if (poll_count == PBA_SLAVE_RESET_TIMEOUT) 
+        {
+	        FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PBA_SLVRST_TIMED_OUT);
+            break;
+	    }
+	  
+    } while (1);
+
+    return rc;
+}
+
 
 } //end extern C
diff --git a/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_set_pore_bar.H b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_set_pore_bar.H
index 3083ff35c..897a150ac 100644
--- a/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_set_pore_bar.H
+++ b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_set_pore_bar.H
@@ -21,7 +21,7 @@
  *
  *  IBM_PROLOG_END_TAG
  */
-// $Id: proc_set_pore_bar.H,v 1.3 2012/07/20 21:14:11 stillgs Exp $
+// $Id: proc_set_pore_bar.H,v 1.4 2012/08/13 13:04:30 stillgs Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_set_pore_bar.H,v $
 //------------------------------------------------------------------------------
 // *|
@@ -105,8 +105,10 @@ enum PORE__BA_SLAVE {
 /// \param[in] i_image      Platform memory pointer where image is
 ///                         located
 /// \param[in] i_mem_bar    Base address of the region where image is located
-/// \param[in] i_mem_mask   Mask that defines which address bits of the
-///                         BAR apply such to define the region size
+/// \param[in] i_mem_size   Size (in MB) of the region where image is located
+///                         if not a power of two value, the value will be 
+///                         rounded up to the next power of 2 for setting the 
+///                         hardware mask
 /// \param[in] i_mem_type   Defines where the SLW image was loaded.  See
 ///                         proc_set_pore_bar.H enum for valid values.
 
@@ -114,7 +116,7 @@ fapi::ReturnCode
 proc_set_pore_bar(  const fapi::Target& i_target, 
                     void *i_image, 
                     uint64_t i_mem_bar, 
-                    uint64_t i_mem_mask, 
+                    uint64_t i_mem_size, 
                     uint32_t i_mem_type);
 
 
diff --git a/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_set_pore_bar_errors.xml b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_set_pore_bar_errors.xml
index d053b9fcb..e660bdd85 100644
--- a/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_set_pore_bar_errors.xml
+++ b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/proc_set_pore_bar_errors.xml
@@ -37,6 +37,11 @@
     <rc>RC_PROCPM_POREBAR_PBABAR_ERROR</rc>
     <description>PBA BAR image location passed to proc_set_pore_bar</description>
   </hwpError>
+    <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROCPM_PBA_SLVRST_TIMED_OUT</rc>
+    <description>PBA Slave Reset timed out in proc_set_pore_bar</description>
+  </hwpError>
   <!-- *********************************************************************** -->
   <hwpError>
     <rc>RC_PROCPM_POREBAR_IMAGE_SIZE_ERROR</rc>
diff --git a/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/sbe_xip_image.h b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/sbe_xip_image.h
index 4109659ea..7a83c2aea 100644
--- a/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/sbe_xip_image.h
+++ b/src/usr/hwpf/hwp/build_winkle_images/proc_set_pore_bar/sbe_xip_image.h
@@ -24,7 +24,7 @@
 #ifndef __SBE_XIP_IMAGE_H
 #define __SBE_XIP_IMAGE_H
 
-// $Id: sbe_xip_image.h,v 1.17 2012/06/12 13:30:28 bcbrock Exp $
+// $Id: sbe_xip_image.h,v 1.18 2012/07/06 20:03:09 bcbrock Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/sbe/sbe_xip_image.h,v $
 //-----------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -134,7 +134,7 @@
 /// Maximum section alignment for SBE-XIP sections
 #define SBE_XIP_MAX_SECTION_ALIGNMENT 128
 
-/// defgroup sbe_xip_toc_types SBE-XIP Table of Contents data types
+/// \defgroup sbe_xip_toc_types SBE-XIP Table of Contents data types
 ///
 /// These are the data types stored in the \a iv_type field of the SbeXipToc
 /// objects.  These must be defined as manifest constants because they are
@@ -859,7 +859,7 @@ sbe_xip_set_element(void *i_image,
 
 /// Set string data in an SBE-XIP image
 ///
-/// \param[in] i_image A pointer to an SBE-XIP image in host memory.  The
+/// \param[in,out] io_image A pointer to an SBE-XIP image in host memory.  The
 /// image is assumed to be consistent with the information contained in the
 /// header regarding the presence of and sizes of all sections.  The image is
 /// also required to have been normalized.
@@ -941,7 +941,7 @@ sbe_xip_write_uint64(void *io_image,
 /// \retval 0 Success; All TOC entries were mapped, including the case that
 /// the .toc section is empty.
 ///
-/// \revtal non-0 May be either one of the SBE-XIP image error codes (see \ref
+/// \retval non-0 May be either one of the SBE-XIP image error codes (see \ref
 /// sbe_xip_image_errors), or a non-zero code from \a i_fn. Since the standard
 /// SBE_XIP return codes are > 0, application-defined codes should be < 0.
 int
@@ -1014,6 +1014,8 @@ sbe_xip_find(void* i_image,
 ///             const char* i_rcString,
 ///             void* io_arg)
 ///
+/// \endcode
+///
 /// \param[in,out] io_arg The private argument of \a i_fn.
 ///
 /// This API iterates over each entry of the .halt section, calling \a i_fn
@@ -1025,10 +1027,10 @@ sbe_xip_find(void* i_image,
 ///
 /// \retval 0 Success, including the case that the image has no .halt section.
 ///
-/// \revtal non-0 May be either one of the SBE-XIP image error codes (see \ref
+/// \retval non-0 May be either one of the SBE-XIP image error codes (see \ref
 /// sbe_xip_image_errors), or any non-zero code from \a i_fn.  Since the
-/// standard SBE_XIP return codes are > 0, application-defined codes should be
-/// < 0.
+/// standard SBE_XIP return codes are \> 0, application-defined codes should
+/// be \< 0.
 int
 sbe_xip_map_halt(void* io_image, 
                  int (*i_fn)(void* io_image, 
@@ -1055,19 +1057,19 @@ sbe_xip_map_halt(void* io_image,
 ///
 /// \retval 0 Success
 ///
-/// \retval SBE_XIP_ITEM_NOT_FOUND The \a i_poreAddress is not associated
+/// \revtal SBE_XIP_ITEM_NOT_FOUND The \a i_poreAddress is not associated
 /// with a halt code in .halt.
 ///
 /// \revtal Other See \ref sbe_xip_image_errors
 int
 sbe_xip_get_halt(void* io_image, 
-                 const uint64_t i_poreAdress,
+                 const uint64_t i_poreAddress,
                  const char** o_rcString);
 
 
 /// Delete a section from an SBE-XIP image in host memory
 ///
-/// \param[in,out] i_image A pointer to an SBE-XIP image in host memory.  The
+/// \param[in,out] io_image A pointer to an SBE-XIP image in host memory.  The
 /// image is assumed to be consistent with the information contained in the
 /// header regarding the presence of and sizes of all sections. The image is
 /// also required to have been normalized.
@@ -1107,10 +1109,10 @@ sbe_xip_delete_section(void* io_image, const int i_sectionId);
 /// section.  
 ///
 /// This API creates a bytewise duplicate of a non-empty section into newly
-/// malloc()-ed memory. At exit \a o_duplicate points to the duplicate, and \i
+/// malloc()-ed memory. At exit \a o_duplicate points to the duplicate, and \a
 /// o_size is set the the size of the duplicated section. The caller is
 /// responsible for free()-ing the memory when no longer required.  The
-/// pointer at \o_duplicate is set to NULL (0) and teh \a o_size is set to 0
+/// pointer at \a o_duplicate is set to NULL (0) and the \a o_size is set to 0
 /// in the event of any failure.
 ///
 /// \retval 0 Success
@@ -1120,7 +1122,7 @@ int
 sbe_xip_duplicate_section(const void* i_image, 
                           const int i_sectionId,
                           void** o_duplicate,
-                          uint32_t* size);
+                          uint32_t* o_size);
 
 
 /// Append binary data to an SBE-XIP image held in host memory
@@ -1317,7 +1319,7 @@ sbe_xip_pore2section(const void* i_image,
 int
 sbe_xip_host2pore(const void* i_image, 
                   void* i_hostAddress,
-                  uint64_t* i_poreAddress);
+                  uint64_t* o_poreAddress);
 
 
 /// \defgroup sbe_xip_image_errors Error codes from SBE-XIP image APIs
diff --git a/src/usr/hwpf/hwp/core_activate/core_activate.C b/src/usr/hwpf/hwp/core_activate/core_activate.C
index 0cecf46d3..7aac36637 100644
--- a/src/usr/hwpf/hwp/core_activate/core_activate.C
+++ b/src/usr/hwpf/hwp/core_activate/core_activate.C
@@ -61,7 +61,8 @@
 #include    <sys/misc.h>
 
 //  Uncomment these files as they become available:
-// #include    "host_activate_master/host_activate_master.H"
+#include    "proc_prep_master_winkle.H"
+#include    "proc_stop_deadman_timer.H"
 // #include    "host_activate_slave_cores/host_activate_slave_cores.H"
 // #include    "host_ipl_complete/host_ipl_complete.H"
 
@@ -82,7 +83,7 @@ using   namespace   ISTEP;
     {
         errlHndl_t  l_errl  =   NULL;
 
-        TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                    "call_host_activate_master entry" );
 
         // @@@@@    CUSTOM BLOCK:   @@@@@
@@ -108,26 +109,24 @@ using   namespace   ISTEP;
 
             // cast OUR type of target to a FAPI type of target.
             const fapi::Target l_fapi_cpu_target(
-                                TARGET_TYPE_PROC_CHIP,
-                                reinterpret_cast<void *>
-                                (const_cast<TARGETING::Target*>(l_cpu_target))
-                               );
-
+                                                TARGET_TYPE_PROC_CHIP,
+                                                reinterpret_cast<void *>
+                                                (const_cast<TARGETING::Target*>
+                                                            (l_cpu_target)) );
 
-#if 1
             TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "Call proc_prep_master_winkle when integrated..." );
-#else
+                   "call_host_activate_master: call proc_prep_master_winkle." );
+
             //  call the HWP with each fapi::Target
             FAPI_INVOKE_HWP( l_errl,
                              proc_prep_master_winkle,
-                             l_fapi_cpu_target );
-#endif
+                             l_fapi_cpu_target,
+                             true  );
             if ( l_errl )
             {
                 TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                           "proc_prep_master_winkle ERROR : Returning errorlog, PLID=0x%x",
-                           l_errl->plid() );
+                "proc_prep_master_winkle ERROR : Returning errorlog, PLID=0x%x",
+                    l_errl->plid() );
                 break;
             }
             else
@@ -136,14 +135,12 @@ using   namespace   ISTEP;
                            "proc_prep_master_winkle SUCCESS"  );
             }
 
-            if (is_vpo()) // TODO: RTC 46651 - Simics doesn't support winkle.
-            {
 
             //  put the master into winkle.
+            //  Simics should work after build b0815a_1233.810 .
             TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                        "call_host_activate_master: put master into winkle..." );
 
-            //  @todo 2012-07-30  currently this is just a stub...
             int l_rc    =   cpu_master_winkle( );
             if ( l_rc )
             {
@@ -168,23 +165,19 @@ using   namespace   ISTEP;
                 break;
             }
 
-            } // TODO: Remove with RTC 46651
-
-
             //  --------------------------------------------------------
             //  should return from Winkle at this point
             //  --------------------------------------------------------
+            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                       "Returned from Winkle." );
 
-
-#if 1
             TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "Call proc_stop_deadman_timer when integrated..." );
-#else
+                       "Call proc_stop_deadman_timer..." );
+
             //  call the HWP with each fapi::Target
             FAPI_INVOKE_HWP( l_errl,
                              proc_stop_deadman_timer,
                              l_fapi_cpu_target  );
-#endif
             if ( l_errl )
             {
                 TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
@@ -203,7 +196,7 @@ using   namespace   ISTEP;
         // @@@@@    END CUSTOM BLOCK:   @@@@@
 
 
-        TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                    "call_host_activate_master exit" );
 
         // end task, returning any errorlogs to IStepDisp
diff --git a/src/usr/hwpf/hwp/core_activate/makefile b/src/usr/hwpf/hwp/core_activate/makefile
index e76695c3b..c296d3b44 100644
--- a/src/usr/hwpf/hwp/core_activate/makefile
+++ b/src/usr/hwpf/hwp/core_activate/makefile
@@ -1,4 +1,4 @@
-#  IBM_PROLOG_BEGIN_TAG
+#   IBM_PROLOG_BEGIN_TAG
 #  This is an automatically generated prolog.
 #
 #  $Source: src/usr/hwpf/hwp/core_activate/makefile $
@@ -19,8 +19,7 @@
 #
 #  Origin: 30
 #
-#  IBM_PROLOG_END
-
+#  IBM_PROLOG_END_TAG
 ROOTPATH = ../../../../..
 
 MODULE = core_activate
@@ -34,22 +33,30 @@ EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
 ## pointer to common HWP files
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
 
-##  NOTE: add the base istep dir here. 
+##  NOTE: add the base istep dir here.
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate
 
 ##  Include sub dirs
 ##  NOTE: add a new EXTRAINCDIR when you add a new HWP
 ##  EXAMPLE:
 ##  EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/<HWP_dir>
+EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle
+EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer
+
 
 
 ##  NOTE: add new object files when you add a new HWP
-OBJS =  core_activate.o
+OBJS =  core_activate.o \
+        proc_prep_master_winkle.o   \
+        proc_sbe_ffdc.o             \
+        proc_stop_deadman_timer.o
+
 
-        
 ##  NOTE: add a new directory onto the vpaths when you add a new HWP
 ##  EXAMPLE:
 #   VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/<HWP_dir>
+VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle
+VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer
 
 
 include ${ROOTPATH}/config.mk
diff --git a/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/p8_istep_num.H b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/p8_istep_num.H
new file mode 100644
index 000000000..58791a89a
--- /dev/null
+++ b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/p8_istep_num.H
@@ -0,0 +1,78 @@
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/p8_istep_num.H $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+#ifndef __P8_ISTEP_NUM_H
+#define __P8_ISTEP_NUM_H
+
+// $Id: p8_istep_num.H,v 1.11 2012/08/01 02:50:49 venton Exp $
+
+/// Istep number encoding for all SEEPROM and PNOR procedures.  Used to update
+/// the SBEVITAL register to record procedure progress and to create unique
+/// hooki bind points on procedure completion.
+
+CONST_UINT64_T(proc_sbe_enable_seeprom_istep_num,           ULL(0x0101));
+
+CONST_UINT64_T(proc_sbe_tp_chiplet_init1_istep_num,         ULL(0x0201));
+CONST_UINT64_T(proc_sbe_tp_ld_image_istep_num,              ULL(0x0202));
+CONST_UINT64_T(proc_sbe_npll_initf_istep_num,               ULL(0x0203));
+CONST_UINT64_T(proc_sbe_npll_setup_istep_num,               ULL(0x0204));
+CONST_UINT64_T(proc_sbe_tp_switch_gears_istep_num,          ULL(0x0205));
+CONST_UINT64_T(proc_sbe_tp_chiplet_init2_istep_num,         ULL(0x0206));
+CONST_UINT64_T(proc_sbe_tp_arrayinit_istep_num,             ULL(0x0207));
+CONST_UINT64_T(proc_sbe_tp_chiplet_init3_istep_num,         ULL(0x0208));
+CONST_UINT64_T(proc_sbe_chiplet_init_istep_num,             ULL(0x0209));
+CONST_UINT64_T(proc_sbe_arrayinit_istep_num,                ULL(0x020A));
+CONST_UINT64_T(proc_sbe_setup_evid_istep_num,               ULL(0x020B));
+CONST_UINT64_T(proc_sbe_initf_istep_num,                    ULL(0x020C));
+CONST_UINT64_T(proc_sbe_pb_startclocks_istep_num,           ULL(0x020D));
+CONST_UINT64_T(proc_sbe_scominit_istep_num,                 ULL(0x020E));
+CONST_UINT64_T(proc_sbe_fabricinit_istep_num,               ULL(0x020F));
+CONST_UINT64_T(proc_sbe_check_master_istep_num,             ULL(0x0210));
+CONST_UINT64_T(proc_sbe_select_ex_istep_num,                ULL(0x0211));
+CONST_UINT64_T(proc_sbe_run_exinit_istep_num,               ULL(0x0212));
+
+CONST_UINT64_T(proc_sbe_pnor_setup_istep_num,               ULL(0x0301));
+
+CONST_UINT64_T(proc_sbe_ex_chiplet_reset_istep_num,         ULL(0x0401));
+CONST_UINT64_T(proc_sbe_ex_gptr_time_initf_istep_num,       ULL(0x0402));
+CONST_UINT64_T(proc_sbe_ex_core_gptr_time_initf_istep_num,  ULL(0x0403));
+CONST_UINT64_T(proc_sbe_ex_dpll_initf_istep_num,            ULL(0x0404));
+CONST_UINT64_T(proc_sbe_ex_chiplet_init_istep_num,          ULL(0x0405));
+CONST_UINT64_T(proc_sbe_ex_repair_initf_istep_num,          ULL(0x0406));
+CONST_UINT64_T(proc_sbe_ex_core_repair_initf_istep_num,     ULL(0x0407));
+CONST_UINT64_T(proc_sbe_ex_arrayinit_istep_num,             ULL(0x0408));
+CONST_UINT64_T(proc_sbe_ex_initf_istep_num,                 ULL(0x0409));
+CONST_UINT64_T(proc_sbe_ex_core_initf_istep_num,            ULL(0x040A));
+CONST_UINT64_T(proc_sbe_ex_do_manual_inits_istep_num,       ULL(0x040B));
+CONST_UINT64_T(proc_sbe_ex_startclocks_istep_num,           ULL(0x040C));
+CONST_UINT64_T(proc_sbe_ex_init_escape_istep_num,           ULL(0x040D));
+CONST_UINT64_T(proc_sbe_ex_sp_runtime_scom_istep_num,       ULL(0x040E));
+CONST_UINT64_T(proc_sbe_ex_occ_runtime_scom_istep_num,      ULL(0x040F));
+CONST_UINT64_T(proc_sbe_ex_host_runtime_scom_istep_num,     ULL(0x0410));
+
+CONST_UINT64_T(proc_sbe_lco_loader_istep_num,               ULL(0x0500));
+CONST_UINT64_T(proc_sbe_instruct_start_istep_num,           ULL(0x0501));
+
+CONST_UINT64_T(proc_sbe_trigger_winkle_istep_num,           ULL(0x0F01));
+
+#endif  // __P8_ISTEP_NUM_H
diff --git a/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.C b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.C
new file mode 100644
index 000000000..bfcd48b93
--- /dev/null
+++ b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.C
@@ -0,0 +1,201 @@
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.C $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+// -*- mode: C++; c-file-style: "linux";  -*-
+// $Id: proc_prep_master_winkle.C,v 1.7 2012/08/01 18:58:38 jeshua Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_prep_master_winkle.C,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2012
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_prep_master_winkle.C
+// *! DESCRIPTION : Prepares for the master core to winkle
+// *!
+// *! OWNER NAME  : Jeshua Smith            Email: jeshua@us.ibm.com
+// *!
+// *! Overview:
+// *!    Wait for SBE ready
+// *!    Start SBE deadman timer
+// *!    *Enter winkle*
+// *!
+// *!    Note: Hostboot should always run with useRealSBE = true
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include "proc_prep_master_winkle.H"
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+extern "C"
+{
+
+
+
+//------------------------------------------------------------------------------
+// function: proc_prep_master_winkle
+//     Wait for SBE ready
+//     Start SBE deadman timer
+//     *Enter winkle*
+//
+// parameters: i_target  => chip target
+// returns: FAPI_RC_SUCCESS if operation was successful, else error
+//------------------------------------------------------------------------------
+    fapi::ReturnCode proc_prep_master_winkle(const fapi::Target & i_target,
+                                             bool useRealSBE = true)
+    {
+        // data buffer to hold register values
+        ecmdDataBufferBase data(64);
+
+        // return codes
+        uint32_t rc_ecmd = 0;
+        fapi::ReturnCode rc;
+
+        // mark function entry
+        FAPI_INF("Entry\n");
+
+        do
+        {
+
+            // Wait for SBE ready
+            // ie. SBE running, and istep num and substep num correct
+            if( useRealSBE )
+            {
+
+//  $$$$$
+//  $$$$$ mww need to set up action file to fill in the SBE regs
+//  $$$$$       These scoms are not set to the right value.
+//  $$$$$       In simics, we need an action file to set them up.
+//  $$$$$
+                FAPI_INF("mww read PORE_SBE_CONTROL_0x000E0001");
+                rc = fapiGetScom(i_target, PORE_SBE_CONTROL_0x000E0001, data);
+                if(!rc.ok())
+                {
+                    FAPI_ERR("Scom error reading SBE STATUS\n");
+                    break;
+                }
+
+                // $$$$$    @todo HACK
+                data.clearBit( 0 ) ;
+
+                if( data.isBitSet( 0 ) )
+                {
+                    FAPI_ERR("SBE isn't running when it should be\n");
+                    const fapi::Target & CHIP_IN_ERROR = i_target;
+                    ecmdDataBufferBase & SBE_STATUS = data;
+                    FAPI_SET_HWP_ERROR(rc, RC_PROC_PREP_MASTER_WINKLE_SBE_NOT_RUNNING);
+                    break;
+                }
+            }
+
+            FAPI_INF("mww read MBOX_SBEVITAL_0x0005001C");
+
+            rc = fapiGetScom(i_target, MBOX_SBEVITAL_0x0005001C, data);
+            if(!rc.ok())
+            {
+                FAPI_ERR("Scom error reading SBE VITAL\n");
+                break;
+            }
+
+
+            uint32_t istep_num = 0;
+            uint8_t substep_num = 0;
+            rc_ecmd |= data.extractToRight(&istep_num,
+                                           istep_num_bit_position,
+                                           istep_num_bit_length);
+            rc_ecmd |= data.extractToRight(&substep_num,
+                                           substep_num_bit_position,
+                                           substep_num_bit_length);
+            if(rc_ecmd)
+            {
+                FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd);
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+
+            //  $$  @todo HACK
+            istep_num   =   0x0f01;
+            substep_num =   0x01;
+
+            if( istep_num != proc_sbe_trigger_winkle_istep_num )
+            {
+                FAPI_ERR("Expected istep num %llX but found %X\n",
+                         proc_sbe_trigger_winkle_istep_num,
+                         istep_num );
+                const fapi::Target & CHIP_IN_ERROR = i_target;
+                ecmdDataBufferBase & SBE_VITAL = data;
+                FAPI_SET_HWP_ERROR(rc, RC_PROC_PREP_MASTER_WINKLE_BAD_ISTEP_NUM);
+                break;
+            }
+            if( substep_num != substep_sbe_ready )
+            {
+                FAPI_ERR("Expected substep num %X but found %X\n",
+                         substep_sbe_ready,
+                         substep_num );
+                const fapi::Target & CHIP_IN_ERROR = i_target;
+                ecmdDataBufferBase & SBE_VITAL = data;
+                FAPI_SET_HWP_ERROR(rc, RC_PROC_PREP_MASTER_WINKLE_BAD_SUBSTEP_NUM);
+                break;
+            }
+
+            FAPI_INF("SBE is ready for master to enter winkle\n");
+
+            //Start the deadman timer
+            substep_num = substep_deadman_start;
+            rc_ecmd |= data.insertFromRight(&substep_num,
+                                            substep_num_bit_position,
+                                            substep_num_bit_length);
+            if(rc_ecmd)
+            {
+                FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd);
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+            FAPI_INF("mww write MBOX_SBEVITAL_0x0005001C");
+            rc = fapiPutScom(i_target, MBOX_SBEVITAL_0x0005001C, data);
+            if(!rc.ok())
+            {
+                FAPI_ERR("Scom error updating SBE VITAL\n");
+                break;
+            }
+
+            //Enter winlke
+            FAPI_INF("HB should enter winkle now, FSP should execute proc_force_winkle now\n");
+
+        } while (0);
+
+        // mark function exit
+        FAPI_INF("Exit");
+        return rc;
+    }
+
+} // extern "C"
+/* Local Variables: */
+/* c-basic-offset: 4 */
+/* End: */
diff --git a/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.H b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.H
new file mode 100644
index 000000000..fd4048c7e
--- /dev/null
+++ b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.H
@@ -0,0 +1,84 @@
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.H $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+// $Id: proc_prep_master_winkle.H,v 1.3 2012/08/01 18:37:38 jeshua Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_prep_master_winkle.H,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2012
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_prep_master_winkle.H
+// *! DESCRIPTION : Prepares for the master core to winkle
+// *!
+// *! OWNER NAME  : Jeshua Smith            Email: jeshua@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+#ifndef _PROC_PREP_MASTER_WINKLE_H_
+#define _PROC_PREP_MASTER_WINKLE_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <fapi.H>
+#include "p8_scom_addresses.H"
+#include "proc_sbe_ffdc.H"
+#include "p8_istep_num.H"
+#include "proc_sbe_trigger_winkle.H"
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+// function pointer typedef definition for HWP call support
+typedef fapi::ReturnCode (*proc_prep_master_winkle_FP_t)(const fapi::Target &,
+                                                         const bool &);
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+
+extern "C"
+{
+
+/**
+ * @brief Start the auto-POR engine and the SBE
+ *
+ * @param[in] i_target  Reference to chip target
+ *
+ * @return ReturnCode
+ */
+  fapi::ReturnCode proc_prep_master_winkle(const fapi::Target & i_target,
+                                           const bool useRealSBE);
+
+} // extern "C"
+
+#endif // _PROC_PREP_MASTER_WINKLE_H_
diff --git a/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle_errors.xml b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle_errors.xml
new file mode 100644
index 000000000..400d9e700
--- /dev/null
+++ b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle_errors.xml
@@ -0,0 +1,46 @@
+<!--  IBM_PROLOG_BEGIN_TAG
+     This is an automatically generated prolog.
+
+     $Source: src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle_errors.xml $
+
+     IBM CONFIDENTIAL
+
+     COPYRIGHT International Business Machines Corp. 2012
+
+     p1
+
+     Object Code Only (OCO) source materials
+     Licensed Internal Code Source Materials
+     IBM HostBoot Licensed Internal Code
+
+     The source code for this program is not published or other-
+     wise divested of its trade secrets, irrespective of what has
+     been deposited with the U.S. Copyright Office.
+
+     Origin: 30
+
+     IBM_PROLOG_END_TAG -->
+<!-- Error definitions for proc_prep_master_winkle procedure  -->
+<hwpErrors>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_PREP_MASTER_WINKLE_SBE_NOT_RUNNING</rc>
+    <description>The SBE is stopped and so will never wake up the master core</description>
+    <collectFfdc>proc_sbe_ffdc, CHIP_IN_ERROR</collectFfdc>
+    <ffdc>SBE_STATUS</ffdc>
+  </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_PREP_MASTER_WINKLE_BAD_ISTEP_NUM</rc>
+    <description>The SBE is not at the correct istep number</description>
+    <collectFfdc>proc_sbe_ffdc, CHIP_IN_ERROR</collectFfdc>
+    <ffdc>SBE_VITAL</ffdc>
+  </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_PREP_MASTER_WINKLE_BAD_SUBSTEP_NUM</rc>
+    <description>The SBE is not at the correct substep number</description>
+    <collectFfdc>proc_sbe_ffdc, CHIP_IN_ERROR</collectFfdc>
+    <ffdc>SBE_VITAL</ffdc>
+  </hwpError>
+</hwpErrors>
diff --git a/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_sbe_ffdc.C b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_sbe_ffdc.C
new file mode 100644
index 000000000..f5f1bb2b8
--- /dev/null
+++ b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_sbe_ffdc.C
@@ -0,0 +1,162 @@
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_sbe_ffdc.C $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+// -*- mode: C++; c-file-style: "linux";  -*-
+// $Id: proc_sbe_ffdc.C,v 1.4 2012/05/23 18:48:50 jeshua Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_sbe_ffdc.C,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_sbe_ffdc.C
+// *! DESCRIPTION : Log data for SBE fails (FAPI)
+// *!
+// *! OWNER NAME  : Jeshua Smith   Email: jeshua@us.ibm.com
+// *! BACKUP NAME : Andreas Koenig Email: koenig@de.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include "proc_sbe_ffdc.H"
+
+extern "C" {
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// function: proc_sbe_ffdc
+// parameters: i_target => proc chip target
+// returns: FAPI_RC_SUCCESS if operation was successful, else error
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// FFDC Procedure
+//------------------------------------------------------------------------------
+    fapi::ReturnCode proc_sbe_ffdc(const fapi::Target& i_target,
+                                   fapi::ReturnCode & o_rc)
+{
+    fapi::ReturnCode rc;
+    ecmdDataBufferBase dataBuff(32);
+    uint32_t data_32 = 0;
+    uint64_t data_64 = 0;
+    const uint16_t END_CFAMS = 0xFFFFull;
+    const uint64_t END_SCOMS = 0xFFFFFFFFFFFFFFFFull;
+
+    // mark HWP entry
+    FAPI_IMP("proc_sbe_ffdc: Entering ...");
+
+    uint16_t cfams [] =
+    {
+        FSI_STATUS_0x1007,
+        FSI_GP3_0x2812   ,
+        FSI_GP4_0x2813   ,
+        FSI_GP5_0x2814   ,
+        FSI_GP6_0x2815   ,
+        FSI_GP7_0x2816   ,
+        FSI_GP8_0x2817   ,
+        FSI_GP3MIR_0x281B,
+        END_CFAMS
+    };
+
+    int cfam_index = 0;
+    do
+    {
+        //Collect SBE Cfams
+        rc = fapiGetCfamRegister( i_target, cfams[cfam_index], dataBuff );
+        if( rc )
+        {
+            break;
+        }
+        data_32 = dataBuff.getWord( 0 );
+        fapi::ReturnCodeFfdc::addEIFfdc(o_rc, data_32);
+        cfam_index++;
+    } while (cfams[cfam_index] != END_CFAMS);
+
+    if( !rc )
+    {
+        uint64_t scoms [] =
+            {
+                PORE_SBE_STATUS_0x000E0000            ,
+                PORE_SBE_CONTROL_0x000E0001           ,
+                PORE_SBE_RESET_0x000E0002             ,
+                PORE_SBE_ERROR_MASK_0x000E0003        ,
+                PORE_SBE_PRV_BASE_ADDRESS0_0x000E0004 ,
+                PORE_SBE_PRV_BASE_ADDRESS1_0x000E0005 ,
+                PORE_SBE_OCI_BASE_ADDRESS0_0x000E0006 ,
+                PORE_SBE_OCI_BASE_ADDRESS1_0x000E0007 ,
+                PORE_SBE_TABLE_BASE_ADDR_0x000E0008   ,
+                PORE_SBE_EXE_TRIGGER_0x000E0009       ,
+                PORE_SBE_SCRATCH0_0x000E000A          ,
+                PORE_SBE_SCRATCH1_0x000E000B          ,
+                PORE_SBE_SCRATCH2_0x000E000C          ,
+                PORE_SBE_IBUF_01_0x000E000D           ,
+                PORE_SBE_IBUF_2_0x000E000E            ,
+                PORE_SBE_DBG0_0x000E000F              ,
+                PORE_SBE_DBG1_0x000E0010              ,
+                PORE_SBE_PC_STACK0_0x000E0011         ,
+                PORE_SBE_PC_STACK1_0x000E0012         ,
+                PORE_SBE_PC_STACK2_0x000E0013         ,
+                PORE_SBE_ID_FLAGS_0x000E0014          ,
+                PORE_SBE_DATA0_0x000E0015             ,
+                PORE_SBE_MEMORY_RELOC_0x000E0016      ,
+                PORE_SBE_I2C_E0_PARAM_0x000E0017      ,
+                PORE_SBE_I2C_E1_PARAM_0x000E0018      ,
+                PORE_SBE_I2C_E2_PARAM_0x000E0019      ,
+                PIBMEM_STATUS_0x00088005              ,
+                TP_CLK_STATUS_0x01030008              ,
+                END_SCOMS
+            };
+
+        int scom_index = 0;
+        do
+        {
+            //Collect SBE Scoms
+            rc = fapiGetScom( i_target, scoms[scom_index], dataBuff );
+            if( rc )
+            {
+                break;
+            }
+            data_64 = dataBuff.getDoubleWord( 0 );
+            fapi::ReturnCodeFfdc::addEIFfdc(o_rc, data_64);
+
+            scom_index++;
+        } while (scoms[scom_index] != END_SCOMS);
+    }
+
+    FAPI_IMP("proc_sbe_ffdc: Exiting ...");
+    return rc;
+}
+
+} //end extern C
+/* Local Variables: */
+/* c-basic-offset: 4 */
+/* End: */
diff --git a/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_sbe_ffdc.H b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_sbe_ffdc.H
new file mode 100644
index 000000000..20739aeb3
--- /dev/null
+++ b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_sbe_ffdc.H
@@ -0,0 +1,96 @@
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_sbe_ffdc.H $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+// $Id: proc_sbe_ffdc.H,v 1.2 2012/04/25 19:56:34 jeshua Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_sbe_ffdc.H,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_sbe_ffdc.H
+// *! DESCRIPTION : Log data for SBE fails (FAPI)
+// *!
+// *! OWNER NAME  : Jeshua Smith   Email: jeshua@us.ibm.com
+// *! BACKUP NAME : Andreas Koenig Email: koenig@de.ibm.com
+// *!
+// *! ADDITIONAL COMMENTS :
+// *!
+// *! Collects:
+// *!   o
+// *!
+// *! Successful operations assumes that:
+// *!   o System clocks are running
+// *!
+//------------------------------------------------------------------------------
+
+#ifndef _PROC_SBE_FFDC_H_
+#define _PROC_SBE_FFDC_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <fapi.H>
+#include "p8_scom_addresses.H"
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+// function pointer typedef definition for HWP call support
+typedef fapi::ReturnCode
+(*proc_sbe_ffdc_FP_t) (const fapi::Target&, fapi::ReturnCode&);
+
+extern "C" {
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+const uint16_t FSI_STATUS_0x1007 = 0x1007;
+const uint16_t FSI_GP3_0x2812    = 0x2812;
+const uint16_t FSI_GP4_0x2813    = 0x2813;
+const uint16_t FSI_GP5_0x2814    = 0x2814;
+const uint16_t FSI_GP6_0x2815    = 0x2815;
+const uint16_t FSI_GP7_0x2816    = 0x2816;
+const uint16_t FSI_GP8_0x2817    = 0x2817;
+const uint16_t FSI_GP3MIR_0x281B = 0x281B;
+
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+// function: FAPI proc_sbe_ffdc HWP entry point
+//           ffdc collection for SBE cache errors
+// parameters: i_target => proc chip target
+//             o_rc => return code to add ffdc data to
+// returns: FAPI_RC_SUCCESS if no errors
+//          else FAPI putscom return code for failing operation
+fapi::ReturnCode proc_sbe_ffdc(const fapi::Target& i_target,
+                               fapi::ReturnCode & o_rc);
+
+} // extern "C"
+
+#endif // _PROC_SBE_FFDC_H_
diff --git a/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_sbe_trigger_winkle.H b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_sbe_trigger_winkle.H
new file mode 100644
index 000000000..4614bd682
--- /dev/null
+++ b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_sbe_trigger_winkle.H
@@ -0,0 +1,46 @@
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_sbe_trigger_winkle.H $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+// $Id: proc_sbe_trigger_winkle.H,v 1.3 2012/05/11 21:16:15 jeshua Exp $
+
+/// Istep number encoding for all SEEPROM and PNOR procedures.  Used to update
+/// the SBEVITAL register to record procedure progress
+
+#ifndef __PROC_SBE_TRIGGER_WINKLE_H
+#define __PROC_SBE_TRIGGER_WINKLE_H
+
+#include "fapi_sbe_common.H"
+
+CONST_UINT8_T(substep_proc_entry,           ULL(0x0));
+CONST_UINT8_T(substep_sbe_ready,            ULL(0x1));
+CONST_UINT8_T(substep_deadman_start,        ULL(0x2));
+CONST_UINT8_T(substep_deadman_waiting_for_winlke, ULL(0x3));
+CONST_UINT8_T(substep_deadman_waiting_for_wakeup, ULL(0x4));
+CONST_UINT8_T(substep_hostboot_alive_again, ULL(0x5));
+
+CONST_UINT8_T(istep_num_bit_position,       ULL(16));
+CONST_UINT8_T(istep_num_bit_length,         ULL(12));
+CONST_UINT8_T(substep_num_bit_position,     ULL(28));
+CONST_UINT8_T(substep_num_bit_length,       ULL(4));
+
+#endif  // __PROC_SBE_TRIGGER_WINKLE_H
diff --git a/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.C b/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.C
new file mode 100644
index 000000000..94edaac0d
--- /dev/null
+++ b/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.C
@@ -0,0 +1,197 @@
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.C $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+// -*- mode: C++; c-file-style: "linux";  -*-
+// $Id: proc_stop_deadman_timer.C,v 1.4 2012/08/10 14:19:16 jeshua Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_stop_deadman_timer.C,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2012
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_stop_deadman_timer.C
+// *! DESCRIPTION : Stops deadman timer and SBE
+// *!
+// *! OWNER NAME  : Jeshua Smith            Email: jeshua@us.ibm.com
+// *!
+// *! Overview:
+// *!    Notify SBE that HB is alive again
+// *!    Make sure SBE stopped
+// *!
+// *!    Here's the flow of SBE_VITAL substeps:
+// *!    SBE (automatic on procedure entry): substep_proc_entry
+// *!    SBE                               : substep_sbe_ready
+// *!    HB (proc_prep_master_winkle)      : substep_deadman_start
+// *!    SBE                               : substep_deadman_waiting_for_winkle
+// *!    SBE                               : substep_deadman_waiting_for_wakeup
+// *!    HB (proc_stop_deadman_timer)      : substep_hostboot_alive_again
+// *!    SBE                   : (stops with error code 0xF to indicate success)
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include "proc_stop_deadman_timer.H"
+#include "p8_scom_addresses.H"
+#include "proc_sbe_ffdc.H"
+#include "p8_istep_num.H"
+#include "proc_sbe_trigger_winkle.H"
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+extern "C"
+{
+
+
+//------------------------------------------------------------------------------
+// function: proc_stop_deadman_timer
+//     Notify SBE that HB is alive again
+//     Force the SBE to stop running
+//
+// parameters: i_target  => chip target
+// returns: FAPI_RC_SUCCESS if operation was successful, else error
+//------------------------------------------------------------------------------
+    fapi::ReturnCode proc_stop_deadman_timer(const fapi::Target & i_target)
+    {
+        // data buffer to hold register values
+        ecmdDataBufferBase data(64);
+
+        // return codes
+        uint32_t rc_ecmd = 0;
+        fapi::ReturnCode rc;
+
+        // mark function entry
+        FAPI_INF("Entry\n");
+
+        do
+        {
+            //Check that SBE is running the deadman timer
+            rc = fapiGetScom(i_target, MBOX_SBEVITAL_0x0005001C, data);
+            if(!rc.ok())
+            {
+                FAPI_ERR("Scom error reading SBE VITAL\n");
+                break;
+            }
+
+            uint32_t istep_num = 0;
+            uint8_t substep_num = 0;
+            rc_ecmd |= data.extractToRight(&istep_num,
+                                           istep_num_bit_position,
+                                           istep_num_bit_length);
+            rc_ecmd |= data.extractToRight(&substep_num,
+                                           substep_num_bit_position,
+                                           substep_num_bit_length);
+            if(rc_ecmd)
+            {
+                FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd);
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+
+            //  $$  @todo HACK
+            istep_num   =   0x0f01;
+            substep_num =   0x04;
+
+            if( istep_num != proc_sbe_trigger_winkle_istep_num )
+            {
+                FAPI_ERR("Expected istep num %llX but found %X\n",
+                         proc_sbe_trigger_winkle_istep_num,
+                         istep_num );
+                const fapi::Target & CHIP_IN_ERROR = i_target;
+                ecmdDataBufferBase & SBE_VITAL = data;
+                FAPI_SET_HWP_ERROR(rc, RC_PROC_STOP_DEADMAN_TIMER_BAD_ISTEP_NUM);
+                break;
+            }
+            if( substep_num != substep_deadman_waiting_for_wakeup )
+            {
+                FAPI_ERR("Expected substep num %X but found %X\n",
+                         substep_deadman_waiting_for_wakeup,
+                         substep_num );
+                const fapi::Target & CHIP_IN_ERROR = i_target;
+                ecmdDataBufferBase & SBE_VITAL = data;
+                FAPI_SET_HWP_ERROR(rc, RC_PROC_STOP_DEADMAN_TIMER_BAD_SUBSTEP_NUM);
+                break;
+            }
+
+            //Notify SBE that HB is alive again
+            substep_num = substep_hostboot_alive_again;
+            rc_ecmd |= data.insertFromRight(&substep_num,
+                                            substep_num_bit_position,
+                                            substep_num_bit_length);
+            if(rc_ecmd)
+            {
+                FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd);
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+            rc = fapiPutScom(i_target, MBOX_SBEVITAL_0x0005001C, data);
+            if(!rc.ok())
+            {
+                FAPI_ERR("Scom error updating SBE VITAL\n");
+                break;
+            }
+
+            // Stop SBE if needed
+            rc = fapiGetScom(i_target, PORE_SBE_CONTROL_0x000E0001, data);
+            if(!rc.ok())
+            {
+                FAPI_ERR("Scom error reading SBE STATUS\n");
+                break;
+            }
+            if( data.isBitSet( 0 ) )
+            {
+                FAPI_INF("SBE/Deadman timer successfully stopped\n");
+                break;
+            }
+            else
+            {
+                rc_ecmd |= data.setBit( 0 );
+                if(rc_ecmd)
+                {
+                    FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd);
+                    rc.setEcmdError(rc_ecmd);
+                    break;
+                }
+                rc = fapiPutScom(i_target, PORE_SBE_CONTROL_0x000E0001, data);
+                if(!rc.ok())
+                {
+                    FAPI_ERR("Scom error stopping SBE\n");
+                    break;
+                }
+            }
+
+        } while (0);
+
+        // mark function exit
+        FAPI_INF("Exit");
+        return rc;
+    }
+
+} // extern "C"
+/* Local Variables: */
+/* c-basic-offset: 4 */
+/* End: */
diff --git a/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.H b/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.H
new file mode 100644
index 000000000..5a016790b
--- /dev/null
+++ b/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.H
@@ -0,0 +1,78 @@
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.H $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+// $Id: proc_stop_deadman_timer.H,v 1.2 2012/08/10 14:17:49 jeshua Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_stop_deadman_timer.H,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2012
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_stop_deadman_timer.H
+// *! DESCRIPTION : Stops deadman timer and SBE
+// *!
+// *! OWNER NAME  : Jeshua Smith            Email: jeshua@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+#ifndef _PROC_STOP_DEADMAN_TIMER_H_
+#define _PROC_STOP_DEADMAN_TIMER_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <fapi.H>
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+// function pointer typedef definition for HWP call support
+typedef fapi::ReturnCode (*proc_stop_deadman_timer_FP_t)(const fapi::Target &);
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+
+extern "C"
+{
+
+/**
+ * @brief Stop the deadman timer and the SBE
+ *
+ * @param[in] i_target  Reference to chip target
+ *
+ * @return ReturnCode
+ */
+  fapi::ReturnCode proc_stop_deadman_timer(const fapi::Target & i_target);
+
+} // extern "C"
+
+#endif // _PROC_STOP_DEADMAN_TIMER_H_
diff --git a/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer_errors.xml b/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer_errors.xml
new file mode 100644
index 000000000..b54043d2f
--- /dev/null
+++ b/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer_errors.xml
@@ -0,0 +1,39 @@
+<!--  IBM_PROLOG_BEGIN_TAG
+     This is an automatically generated prolog.
+
+     $Source: src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer_errors.xml $
+
+     IBM CONFIDENTIAL
+
+     COPYRIGHT International Business Machines Corp. 2012
+
+     p1
+
+     Object Code Only (OCO) source materials
+     Licensed Internal Code Source Materials
+     IBM HostBoot Licensed Internal Code
+
+     The source code for this program is not published or other-
+     wise divested of its trade secrets, irrespective of what has
+     been deposited with the U.S. Copyright Office.
+
+     Origin: 30
+
+     IBM_PROLOG_END_TAG -->
+<!-- Error definitions for proc_stop_deadman_timer procedure -->
+<hwpErrors>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_STOP_DEADMAN_TIMER_BAD_ISTEP_NUM</rc>
+    <description>The SBE is not at the correct istep number</description>
+    <collectFfdc>proc_sbe_ffdc, CHIP_IN_ERROR</collectFfdc>
+    <ffdc>SBE_VITAL</ffdc>
+  </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_STOP_DEADMAN_TIMER_BAD_SUBSTEP_NUM</rc>
+    <description>The SBE is not at the correct substep number</description>
+    <collectFfdc>proc_sbe_ffdc, CHIP_IN_ERROR</collectFfdc>
+    <ffdc>SBE_VITAL</ffdc>
+  </hwpError>
+</hwpErrors>
diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile
index 5410b9a8a..8fb57a76c 100644
--- a/src/usr/hwpf/makefile
+++ b/src/usr/hwpf/makefile
@@ -1,25 +1,25 @@
-# IBM_PROLOG_BEGIN_TAG 
-# This is an automatically generated prolog. 
-#  
-# $Source: src/usr/hwpf/makefile $ 
-#  
-# IBM CONFIDENTIAL 
-#  
-# COPYRIGHT International Business Machines Corp. 2011,2012 
-#  
-# p1 
-#  
-# Object Code Only (OCO) source materials 
-# Licensed Internal Code Source Materials 
-# IBM HostBoot Licensed Internal Code 
-#  
-# The source code for this program is not published or otherwise 
-# divested of its trade secrets, irrespective of what has been 
-# deposited with the U.S. Copyright Office. 
-#  
-# Origin: 30 
-#  
-# IBM_PROLOG_END_TAG 
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/usr/hwpf/makefile $
+#
+# IBM CONFIDENTIAL
+#
+# COPYRIGHT International Business Machines Corp. 2011,2012
+#
+# p1
+#
+# Object Code Only (OCO) source materials
+# Licensed Internal Code Source Materials
+# IBM HostBoot Licensed Internal Code
+#
+# The source code for this program is not published or otherwise
+# divested of its trade secrets, irrespective of what has been
+# deposited with the U.S. Copyright Office.
+#
+# Origin: 30
+#
+# IBM_PROLOG_END_TAG
 ROOTPATH = ../../..
 SUBDIRS = fapi.d hwp.d plat.d test.d
 
@@ -44,7 +44,9 @@ HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml   \
     hwp/dram_initialization/proc_setup_bars/proc_fab_smp_errors.xml     \
     hwp/build_winkle_images/proc_set_pore_bar/proc_set_pore_bar_errors.xml  \
     hwp/build_winkle_images/proc_pba_bar_config/proc_pba_bar_config_errors.xml \
-    hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup_errors.xml
+    hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup_errors.xml \
+    hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle_errors.xml \
+    hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer_errors.xml
 
 
 ## these get generated into obj/genfiles/AttributeIds.H