diff options
| author | Thi Tran <thi@us.ibm.com> | 2013-04-13 11:26:04 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-04-18 14:26:36 -0500 |
| commit | 37975f1274aff10c9e19015030c8fec2c58bc277 (patch) | |
| tree | 51502babe2e8fef531ffdee7548cca4a4991b8f7 /src/usr/hwpf | |
| parent | 196b577c0df9eaa90a3fbb87f6d2cb1222c790a2 (diff) | |
| download | talos-hostboot-37975f1274aff10c9e19015030c8fec2c58bc277.tar.gz talos-hostboot-37975f1274aff10c9e19015030c8fec2c58bc277.zip | |
Memory HW procedure update 04/13/2013
SW197154
Change-Id: I7fb5e3e45ed5c6ca2e9c3dea8b0b8f2eb77be86c
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4052
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf')
22 files changed, 3170 insertions, 1700 deletions
diff --git a/src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.C b/src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.C index 5b7ff7c78..cd3dfd6d8 100644 --- a/src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.C +++ b/src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: cen_switch_rec_attn.C,v 1.3 2013/01/18 17:18:31 mfred Exp $ +// $Id: cen_switch_rec_attn.C,v 1.4 2013/03/04 17:56:36 mfred Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_switch_rec_attn.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -30,6 +30,8 @@ // *! TITLE : cen_switch_rec_attn // *! DESCRIPTION : The purpose of this procedure is to route Centaur recoverable attns and special attns to the FSP. // *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com +// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com +// *! SCREEN : pervasive_screen // #! ADDITIONAL COMMENTS : See inline comments below. // //------------------------------------------------------------------------------ @@ -106,6 +108,9 @@ fapi::ReturnCode cen_switch_rec_attn(const fapi::Target & i_target) This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: cen_switch_rec_attn.C,v $ +Revision 1.4 2013/03/04 17:56:36 mfred +Add some header comments for BACKUP and SCREEN. + Revision 1.3 2013/01/18 17:18:31 mfred Clear mask to allow special attentions to go to FSP, along with recoverables. diff --git a/src/usr/hwpf/hwp/dram_training/makefile b/src/usr/hwpf/hwp/dram_training/makefile index 13f468553..3fe9152b0 100644 --- a/src/usr/hwpf/hwp/dram_training/makefile +++ b/src/usr/hwpf/hwp/dram_training/makefile @@ -67,7 +67,8 @@ OBJS = dram_training.o \ mss_generic_shmoo.o \ mss_mcbist.o \ mss_mcbist_common.o\ - hbVddrMsg.o + hbVddrMsg.o \ + mss_mcbist_address.o ## NOTE: add a new directory onto the vpaths when you add a new HWP ##@ VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/??? diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C index b8d6d9b2f..6b586c7fb 100755 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit.C,v 1.46 2013/02/12 17:24:16 jdsloat Exp $ +// $Id: mss_draminit.C,v 1.47 2013/04/09 23:31:21 jdsloat Exp $ //------------------------------------------------------------------------------ // Don't forget to create CVS comments when you check in your changes! //------------------------------------------------------------------------------ @@ -28,6 +28,10 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.47 | jdsloat | 04/09/13| Added position info to debug messages +// | | | Added setup cycle for 2N mode +// | | | Added CKE high for RCD +// | | | Moved address mirror mode into its own function in mss_funcs // 1.46 | jdsloat | 02/12/13| Fixed RTT_WR in MR2 // 1.45 | jdsloat | 01/28/13| is_sim check for address mirror mode // 1.44 | jdsloat | 01/25/13| Address Mirror Mode added for dual drop CDIMMs @@ -225,7 +229,7 @@ ReturnCode mss_draminit_cloned(Target& i_target) && (is_sim == 0) ) { - FAPI_INF( "Setting Address Mirroring in the PHY"); + FAPI_INF( "Setting Address Mirroring in the PHY on %s ", i_target.toEcmdString()); //Set the Address and BA bits affected by mirroring rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); @@ -258,7 +262,7 @@ ReturnCode mss_draminit_cloned(Target& i_target) ( primary_ranks_array[rank_pair_group][port_number] == 0x06) || ( primary_ranks_array[rank_pair_group][port_number] == 0x07) ) { - FAPI_INF( "Address Mirroring on PORT%d RANKPAIR%d RANK%d", port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); + FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); bit_position = 2 * rank_pair_group + 48; FAPI_INF( "Setting bit %d", bit_position); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); @@ -272,7 +276,7 @@ ReturnCode mss_draminit_cloned(Target& i_target) ( secondary_ranks_array[rank_pair_group][port_number] == 0x06) || ( secondary_ranks_array[rank_pair_group][port_number] == 0x07) ) { - FAPI_INF( "Address Mirroring on PORT%d RANKPAIR%d RANK%d", port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); + FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); bit_position = 2 * rank_pair_group + 49; FAPI_INF( "Setting bit %d", bit_position); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); @@ -286,7 +290,7 @@ ReturnCode mss_draminit_cloned(Target& i_target) ( tertiary_ranks_array[rank_pair_group][port_number] == 0x06) || ( tertiary_ranks_array[rank_pair_group][port_number] == 0x07) ) { - FAPI_INF( "Address Mirroring on PORT%d RANKPAIR%d RANK%d", port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); + FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); bit_position = 2 * rank_pair_group + 48; FAPI_INF( "Setting bit %d", bit_position); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64); @@ -300,7 +304,7 @@ ReturnCode mss_draminit_cloned(Target& i_target) ( quaternary_ranks_array[rank_pair_group][port_number] == 0x06) || ( quaternary_ranks_array[rank_pair_group][port_number] == 0x07) ) { - FAPI_INF( "Address Mirroring on PORT%d RANKPAIR%d RANK%d", port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); + FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); bit_position = 2 * rank_pair_group + 49; FAPI_INF( "Setting bit %d", bit_position); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64); @@ -317,7 +321,7 @@ ReturnCode mss_draminit_cloned(Target& i_target) ( primary_ranks_array[rank_pair_group][port_number] == 0x06) || ( primary_ranks_array[rank_pair_group][port_number] == 0x07) ) { - FAPI_INF( "Address Mirroring on PORT%d RANKPAIR%d RANK%d", port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); + FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); bit_position = 2 * rank_pair_group + 48; FAPI_INF( "Setting bit %d", bit_position); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); @@ -331,7 +335,7 @@ ReturnCode mss_draminit_cloned(Target& i_target) ( secondary_ranks_array[rank_pair_group][port_number] == 0x06) || ( secondary_ranks_array[rank_pair_group][port_number] == 0x07) ) { - FAPI_INF( "Address Mirroring on PORT%d RANKPAIR%d RANK%d", port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); + FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); bit_position = 2 * rank_pair_group + 49; FAPI_INF( "Setting bit %d", bit_position); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); @@ -345,7 +349,7 @@ ReturnCode mss_draminit_cloned(Target& i_target) ( tertiary_ranks_array[rank_pair_group][port_number] == 0x06) || ( tertiary_ranks_array[rank_pair_group][port_number] == 0x07) ) { - FAPI_INF( "Address Mirroring on PORT%d RANKPAIR%d RANK%d", port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); + FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); bit_position = 2 * rank_pair_group + 48; FAPI_INF( "Setting bit %d", bit_position); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, data_buffer_64); @@ -480,25 +484,25 @@ ReturnCode mss_draminit_cloned(Target& i_target) rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS0 ); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0 ); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P0_0x8000C01D0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS1); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P0_0x8000C01E0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS2); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P0_0x8000C01F0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS3); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); } else if (rank_pair_group == 1) @@ -507,25 +511,25 @@ ReturnCode mss_draminit_cloned(Target& i_target) rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS0); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P0_0x8000C11D0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS1); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P0_0x8000C11E0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS2); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP1_P0_0x8000C11F0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS3); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); } else if (rank_pair_group == 2) @@ -534,25 +538,25 @@ ReturnCode mss_draminit_cloned(Target& i_target) rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS0); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P0_0x8000C21D0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS1); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P0_0x8000C21E0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS2); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP2_P0_0x8000C21F0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS3); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); } else if (rank_pair_group == 3) { @@ -560,25 +564,25 @@ ReturnCode mss_draminit_cloned(Target& i_target) rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS0); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P0_0x8000C31D0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS1); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P0_0x8000C31E0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS2); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP3_P0_0x8000C31F0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS3); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); } } else if (port_number == 1) @@ -589,25 +593,25 @@ ReturnCode mss_draminit_cloned(Target& i_target) rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS0 ); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0 ); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P1_0x8001C01D0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS1); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P1_0x8001C01E0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS2); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P1_0x8001C01F0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS3); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); } else if (rank_pair_group == 1) @@ -616,25 +620,25 @@ ReturnCode mss_draminit_cloned(Target& i_target) rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS0); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P1_0x8001C11D0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS1); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P1_0x8001C11E0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS2); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP1_P1_0x8001C11F0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS3); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); } else if (rank_pair_group == 2) @@ -643,25 +647,25 @@ ReturnCode mss_draminit_cloned(Target& i_target) rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS0); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P1_0x8001C21D0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS1); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P1_0x8001C21E0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS2); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP2_P1_0x8001C21F0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS3); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); } else if (rank_pair_group == 3) { @@ -669,25 +673,25 @@ ReturnCode mss_draminit_cloned(Target& i_target) rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS0); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P1_0x8001C31D0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS1); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P1_0x8001C31E0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS2); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP3_P1_0x8001C31F0301143F, data_buffer_64); rc_num = rc_num | data_buffer_64.reverse(); rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - FAPI_INF( "PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS3); + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); } } @@ -802,7 +806,7 @@ ReturnCode mss_rcd_load( ecmdDataBufferBase wen_1(1); rc_num = rc_num | wen_1.setBit(0); ecmdDataBufferBase cke_4(4); - rc_num = rc_num | cke_4.clearBit(0,4); + rc_num = rc_num | cke_4.setBit(0,4); ecmdDataBufferBase csn_8(8); rc_num = rc_num | csn_8.setBit(0,8); ecmdDataBufferBase odt_4(4); @@ -854,7 +858,7 @@ ReturnCode mss_rcd_load( if(rc) return rc; io_ccs_inst_cnt ++; - FAPI_INF( "+++++++++++++++++++++ LOADING RCD CONTROL WORDS FOR PORT %d +++++++++++++++++++++", i_port_number); + FAPI_INF( "+++++++++++++++++++++ LOADING RCD CONTROL WORDS FOR %s PORT %d +++++++++++++++++++++", i_target.toEcmdString(), i_port_number); for ( dimm_number = 0; dimm_number < MAX_NUM_DIMMS; dimm_number++) { @@ -866,7 +870,7 @@ ReturnCode mss_rcd_load( } else { - FAPI_INF( "RCD SETTINGS FOR PORT%d DIMM%d ", i_port_number, dimm_number); + FAPI_INF( "RCD SETTINGS FOR %s PORT%d DIMM%d ", i_target.toEcmdString(), i_port_number, dimm_number); FAPI_INF( "RCD Control Word: 0x%016llX", rcd_array[i_port_number][dimm_number]); if (rc_num) @@ -971,8 +975,6 @@ ReturnCode mss_mrs_load( uint32_t rc_num = 0; ecmdDataBufferBase data_buffer_64(64); - ecmdDataBufferBase address_pre_AMM_16(16); - ecmdDataBufferBase bank_pre_AMM_3(3); ecmdDataBufferBase address_16(16); ecmdDataBufferBase bank_3(3); ecmdDataBufferBase activate_1(1); @@ -990,7 +992,13 @@ ReturnCode mss_mrs_load( rc_num = rc_num | odt_4.setBit(0,4); ecmdDataBufferBase ddr_cal_type_4(4); + ecmdDataBufferBase csn_setup_8(8); + rc_num = rc_num | csn_setup_8.setBit(0,8); + ecmdDataBufferBase num_idles_16(16); + ecmdDataBufferBase num_idles_setup_16(16); + rc_num = rc_num | num_idles_setup_16.insertFromRight((uint32_t) 400, 0, 16); + ecmdDataBufferBase num_repeat_16(16); ecmdDataBufferBase data_20(20); ecmdDataBufferBase read_compare_1(1); @@ -1007,13 +1015,9 @@ ReturnCode mss_mrs_load( uint16_t MRS2 = 0; uint16_t MRS3 = 0; - uint16_t mirror_mode_ba = 0; - uint16_t mirror_mode_ad = 0; - - uint16_t num_ranks = 0; - FAPI_INF( "+++++++++++++++++++++ LOADING MRS SETTINGS FOR PORT %d +++++++++++++++++++++", i_port_number); + FAPI_INF( "+++++++++++++++++++++ LOADING MRS SETTINGS FOR %s PORT %d +++++++++++++++++++++", i_target.toEcmdString(), i_port_number); uint8_t num_ranks_array[2][2]; //[port][dimm] rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array); @@ -1027,6 +1031,9 @@ ReturnCode mss_mrs_load( rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim); if(rc) return rc; + uint8_t dram_2n_mode = 0; + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_2N_MODE_ENABLED, &i_target, dram_2n_mode); + if(rc) return rc; //Lines commented out in the following section are waiting for xml attribute adds //MRS0 @@ -1343,14 +1350,14 @@ ReturnCode mss_mrs_load( if (num_ranks == 0) { - FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d ", i_port_number, dimm_number, num_ranks); + FAPI_INF( " %s PORT%d DIMM%d not configured. Num_ranks: %d ", i_target.toEcmdString(), i_port_number, dimm_number, num_ranks); } else { // Rank 0-3 for ( rank_number = 0; rank_number < num_ranks; rank_number++) { - FAPI_INF( "MRS SETTINGS FOR PORT%d DIMM%d RANK%d", i_port_number, dimm_number, rank_number); + FAPI_INF( "MRS SETTINGS FOR %s PORT%d DIMM%d RANK%d", i_target.toEcmdString(), i_port_number, dimm_number, rank_number); rc_num = rc_num | csn_8.setBit(0,8); rc_num = rc_num | address_16.clearBit(0, 16); @@ -1470,82 +1477,79 @@ ReturnCode mss_mrs_load( // Setting the bank address if (mrs_number == 0) { - rc_num = rc_num | address_pre_AMM_16.insert(mrs2, 0, 16, 0); - rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS2_BA, 0, 1, 7); - rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS2_BA, 1, 1, 6); - rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS2_BA, 2, 1, 5); + rc_num = rc_num | address_16.insert(mrs2, 0, 16, 0); + rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 1, 1, 6); + rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 2, 1, 5); } else if ( mrs_number == 1) { - rc_num = rc_num | address_pre_AMM_16.insert(mrs3, 0, 16, 0); - rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS3_BA, 0, 1, 7); - rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS3_BA, 1, 1, 6); - rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS3_BA, 2, 1, 5); + rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0); + rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6); + rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5); } else if ( mrs_number == 2) { - rc_num = rc_num | address_pre_AMM_16.insert(mrs1, 0, 16, 0); - rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS1_BA, 0, 1, 7); - rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS1_BA, 1, 1, 6); - rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS1_BA, 2, 1, 5); + rc_num = rc_num | address_16.insert(mrs1, 0, 16, 0); + rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 1, 1, 6); + rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 2, 1, 5); } else if ( mrs_number == 3) { - rc_num = rc_num | address_pre_AMM_16.insert(mrs0, 0, 16, 0); - rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS0_BA, 0, 1, 7); - rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS0_BA, 1, 1, 6); - rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS0_BA, 2, 1, 5); + rc_num = rc_num | address_16.insert(mrs0, 0, 16, 0); + rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 1, 1, 6); + rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 2, 1, 5); + } + + if (rc_num) + { + FAPI_ERR( "mss_mrs_load: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; } if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_CDIMM) && (dimm_number == 1) && (is_sim == 0)) { - FAPI_INF( "ADDRESS MIRRORING ON PORT%d DIMM%d RANK%d", i_port_number, dimm_number, rank_number); - - rc_num = rc_num | address_pre_AMM_16.extractPreserve(&mirror_mode_ad, 0, 16, 0); - FAPI_INF( "PRE - MIRROR MODE ADDRESS: 0x%04X", mirror_mode_ad); - rc_num = rc_num | bank_pre_AMM_3.extractPreserve(&mirror_mode_ba, 0, 3, 0); - FAPI_INF( "PRE - MIRROR MODE BANK ADDRESS: 0x%04X", mirror_mode_ba); - - //Initialize address and bank address as the same pre mirror mode swizzle - rc_num = rc_num | address_16.insert(address_pre_AMM_16, 0, 16, 0); - rc_num = rc_num | bank_3.insert(bank_pre_AMM_3, 0, 3, 0); - - //Swap A3 and A4 - rc_num = rc_num | address_16.insert(address_pre_AMM_16, 4, 1, 3); - rc_num = rc_num | address_16.insert(address_pre_AMM_16, 3, 1, 4); - - //Swap A5 and A6 - rc_num = rc_num | address_16.insert(address_pre_AMM_16, 6, 1, 5); - rc_num = rc_num | address_16.insert(address_pre_AMM_16, 5, 1, 6); + rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3); + } - //Swap A7 and A8 - rc_num = rc_num | address_16.insert(address_pre_AMM_16, 8, 1, 7); - rc_num = rc_num | address_16.insert(address_pre_AMM_16, 7, 1, 8); + + if (dram_2n_mode == ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_TRUE) + { - //Swap BA0 and BA1 - rc_num = rc_num | bank_3.insert(bank_pre_AMM_3, 1, 1, 0); - rc_num = rc_num | bank_3.insert(bank_pre_AMM_3, 0, 1, 1); + // Send out to the CCS array a "setup" cycle + rc = mss_ccs_inst_arry_0( i_target, + io_ccs_inst_cnt, + address_16, + bank_3, + activate_1, + rasn_1, + casn_1, + wen_1, + cke_4, + csn_setup_8, + odt_4, + ddr_cal_type_4, + i_port_number); + if(rc) return rc; + rc = mss_ccs_inst_arry_1( i_target, + io_ccs_inst_cnt, + num_idles_setup_16, + num_repeat_16, + data_20, + read_compare_1, + rank_cal_4, + ddr_cal_enable_1, + ccs_end_1); + if(rc) return rc; - rc_num = rc_num | address_16.extractPreserve(&mirror_mode_ad, 0, 16, 0); - FAPI_INF( "POST - MIRROR MODE ADDRESS: 0x%04X", mirror_mode_ad); - rc_num = rc_num | bank_3.extractPreserve(&mirror_mode_ba, 0, 3, 0); - FAPI_INF( "POST - MIRROR MODE BANK ADDRESS: 0x%04X", mirror_mode_ba); + io_ccs_inst_cnt ++; } - else - { - // No need to worry about swizzle - rc_num = rc_num | address_16.insert(address_pre_AMM_16, 0, 16, 0); - rc_num = rc_num | bank_3.insert(bank_pre_AMM_3, 0, 3, 0); - } - if (rc_num) - { - FAPI_ERR( "mss_mrs_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - // Send out to the CCS array rc = mss_ccs_inst_arry_0( i_target, io_ccs_inst_cnt, diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C index 155f33f9e..cbb43ee54 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit_mc.C,v 1.34 2013/03/12 21:33:56 lapietra Exp $ +// $Id: mss_draminit_mc.C,v 1.35 2013/04/01 20:24:02 lapietra Exp $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -44,6 +44,7 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.35 | dcadiga |01-APR-13| Temp Fix For Parity Error on 32GB // 1.34 | dcadiga |12-MAR-13| Added spare cke disable as step 0 // 1.33 | dcadiga |04-FEB-13| For some reason the main procedure call was commented out in the last commit... commenting it back in // 1.32 | gollub |31-JAN-13| Uncommenting mss_unmask_maint_errors and mss_unmask_inband_errors @@ -130,7 +131,7 @@ ReturnCode mss_draminit_mc(Target& i_target) fapi::ReturnCode l_rc; //Commented back in by dcadiga l_rc = mss_draminit_mc_cloned(i_target); - + //FAPI_INF("DID NOT RUN DRAMINIT MC\n"); // If mss_unmask_maint_errors gets it's own bad rc, // it will commit the passed in rc (if non-zero), and return it's own bad rc. // Else if mss_unmask_maint_errors runs clean, @@ -184,6 +185,18 @@ ReturnCode mss_draminit_mc_cloned(Target& i_target) FAPI_ERR("---Error During IML Complete Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator()); return rc; } + //Temp Fix For Scom Parity + ecmdDataBufferBase parity_tmp_data_buffer_64(64); + rc = fapiGetScom(i_target, MBS_FIR_REG_0x02011400, parity_tmp_data_buffer_64); + rc_num = rc_num | parity_tmp_data_buffer_64.clearBit(8); + rc = fapiPutScom(i_target, MBS_FIR_REG_0x02011400, parity_tmp_data_buffer_64); + if(rc) + { + FAPI_ERR("---Error During Clear Parity Bit", uint32_t(rc), rc.getCreator()); + return rc; + } + + // Loop through the 2 MBA's for (uint32_t i=0; i < l_mbaChiplets.size(); i++) diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C index 0a1a2f7f9..04efb9d00 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit_training_advanced.C,v 1.26 2013/03/06 11:22:31 sasethur Exp $ +// $Id: mss_draminit_training_advanced.C,v 1.27 2013/04/09 11:08:44 lapietra Exp $ /* File is created by SARAVANAN SETHURAMAN on Thur 29 Sept 2011. */ //------------------------------------------------------------------------------ @@ -44,7 +44,7 @@ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- // 1.1 | sasethur |30-Sep-11| Initial draft. -// 1.2 | sasethur |18-Nov-11| Changed function names +// 1.2 | sasethur |18-Nov-11| Changed function names // 1.3 | sasethur |01-Dec-11| Added details on Vref shmoo, reg addresses // 1.4 | sasethur |29-Jan-12| Updated wr&rd vref, removed ecmd workarounds // 1.5 | sasethur |13-Feb-12| Updated register naming conventions @@ -62,11 +62,11 @@ // 1.20 | bellows |13-Nov-12| Updated for new SI attributes // 1.21 | sasethur |11-Nov-12| Updated for new SI attribute change, fw review comments // 1.22 | sasethur |07-Dec-12| Updated for FW review comments - multiple changes -// 1.23 | sasethur |14-Dec-12| Updated for FW review comments -// 1.24 | sasethur |17-Jan-13| Updated for mss_mcbist_common.C include file -// 1.25 | abhijsau |31-Jan-13| removed mss_mcbist_common.C include file , needs to be included while compiling -// 1.26 | abhijsau |06-Mar-13| fixed fw comment - +// 1.23 | sasethur |14-Dec-12| Updated for FW review comments +// 1.24 | sasethur |17-Jan-13| Updated for mss_mcbist_common.C include file +// 1.25 | abhijsau |31-Jan-13| Removed mss_mcbist_common.C include file , needs to be included while compiling +// 1.26 | abhijsau |06-Mar-13| Fixed fw comment +// 1.27 | sasethur |09-Apr-13| Updated for port in parallel and pass shmoo param // This procedure Schmoo's DRV_IMP, SLEW, VREF (DDR, CEN), RCV_IMP based on attribute from effective config procedure // DQ & DQS Driver impedance, Slew rate, WR_Vref shmoo would call only write_eye shmoo for margin calculation @@ -74,7 +74,7 @@ // Internal Vref controlled by this function & external vref platform to provide function we return value // Not supported -// DDR4, DIMM Types +// DDR4, DIMM Types //---------------------------------------------------------------------- // Includes - FAPI //---------------------------------------------------------------------- @@ -100,15 +100,15 @@ enum shmoo_param { PARAM_NONE = 0x00, DELAY_REG = 0x01, - DRV_IMP = 0x02, + DRV_IMP = 0x02, SLEW_RATE = 0x04, WR_VREF = 0x08, RD_VREF = 0x10, - RCV_IMP = 0x20 + RCV_IMP = 0x20 }; -extern "C" +extern "C" { using namespace fapi; @@ -117,66 +117,67 @@ fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_ta uint8_t i_pattern, uint8_t i_test_type); fapi::ReturnCode drv_imped_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, - shmoo_type_t i_shmoo_type_valid, - uint8_t i_pattern, uint8_t i_test_type); + shmoo_type_t i_shmoo_type_valid, + uint8_t i_pattern, uint8_t i_test_type); fapi::ReturnCode slew_rate_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, - shmoo_type_t i_shmoo_type_valid, + shmoo_type_t i_shmoo_type_valid, uint8_t i_pattern, uint8_t i_test_type); fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, - shmoo_type_t i_shmoo_type_valid, + shmoo_type_t i_shmoo_type_valid, uint8_t i_pattern, uint8_t i_test_type); fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, - shmoo_type_t i_shmoo_type_valid, + shmoo_type_t i_shmoo_type_valid, uint8_t i_pattern, uint8_t i_test_type); fapi::ReturnCode rcv_imp_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, - shmoo_type_t i_shmoo_type_valid, + shmoo_type_t i_shmoo_type_valid, uint8_t i_pattern, uint8_t i_test_type); fapi::ReturnCode delay_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, - shmoo_type_t i_shmoo_type_valid, + shmoo_type_t i_shmoo_type_valid, uint32_t *o_left_margin, uint32_t *o_right_margin, - uint8_t i_pattern, uint8_t i_test_type); + uint8_t i_pattern, uint8_t i_test_type, uint32_t i_shmoo_param); -void find_best_margin(shmoo_param i_shmoo_param_valid,uint32_t i_left[], - uint32_t i_right[], const uint8_t i_max, +void find_best_margin(shmoo_param i_shmoo_param_valid,uint32_t i_left[], + uint32_t i_right[], const uint8_t i_max, uint32_t i_param_nom, uint8_t& o_index); //----------------------------------------------------------------------------------- //Function name: mss_draminit_training_advanced() //Description: This function varies driver impedance, receiver impedance, slew, wr & rd vref //based on attribute definition and runs either mcbist/delay shmoo based on attribute -//Also calls unmask function mss_unmask_draminit_training_advanced_errors() -//Input : const fapi::Target MBA, i_pattern = pattern selection during mcbist @ lab, -// l_test type = test type selection during mcbist @ lab +//Also calls unmask function mss_unmask_draminit_training_advanced_errors() +//Input : const fapi::Target MBA, i_pattern = pattern selection during mcbist @ lab, +// l_test type = test type selection during mcbist @ lab // Default vlaues are Zero //----------------------------------------------------------------------------------- -fapi::ReturnCode mss_draminit_training_advanced(const fapi::Target & i_target_mba, - uint8_t i_pattern, +fapi::ReturnCode mss_draminit_training_advanced(const fapi::Target & i_target_mba, + uint8_t i_pattern, uint8_t i_test_type) { // const fapi::Target is centaur.mba - + i_pattern=13; + i_test_type=14; fapi::ReturnCode rc; - FAPI_INF(" pattern bit is %d and test_type_bit is %d",i_pattern,i_test_type); - + FAPI_INF(" pattern bit is %d and test_type_bit is %d",i_pattern,i_test_type); + rc = mss_draminit_training_advanced_cloned(i_target_mba,i_pattern,i_test_type); - if (rc) + if (rc) { FAPI_ERR("Advanced DRAM Init training procedure is Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); } - + // If mss_unmask_draminit_training_advanced_errors gets it's own bad rc, // it will commit the passed in rc (if non-zero), and return it's own bad rc. - // Else if mss_unmask_draminit_training_advanced_errors runs clean, + // Else if mss_unmask_draminit_training_advanced_errors runs clean, // it will just return the passed in rc. - + rc = mss_unmask_draminit_training_advanced_errors(i_target_mba, rc); - if (rc) + if (rc) { FAPI_ERR("Unmask Function is Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); return rc; @@ -200,42 +201,43 @@ fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_ta { //const fapi::Target is centaur.mba fapi::ReturnCode rc; - char procedure_name[32]; + char procedure_name[32]; sprintf(procedure_name, "mss_draminit_training_advanced"); FAPI_INF("+++++++ Executing %s +++++++", procedure_name); - + // Define attribute variables uint32_t l_attr_mss_freq_u32 = 0; - uint32_t l_attr_mss_volt_u32 = 0; + uint32_t l_attr_mss_volt_u32 = 0; uint8_t l_num_drops_per_port_u8 = 2; uint8_t l_num_ranks_per_dimm_u8array[MAX_PORT][MAX_DIMM] = {{0}}; - uint8_t __attribute__((unused) l_actual_dimm_size_u8 = 0; // HACK + uint8_t __attribute__((unused)) l_actual_dimm_size_u8 = 0; // SW198827 uint8_t l_port = 0; uint8_t l_dimm_type_u8 = 0; //default is set to CDIMM - uint32_t l_left_margin=0; - uint32_t l_right_margin=0; - + uint32_t l_left_margin=0; + uint32_t l_right_margin=0; + uint32_t l_shmoo_param=0; + // Define local variables uint8_t l_shmoo_type_valid_t=0; uint8_t l_shmoo_param_valid_t=0; - + //const fapi::Target is centaur fapi::Target l_target_centaur; - rc = fapiGetParentChip(i_target_mba, l_target_centaur); + rc = fapiGetParentChip(i_target_mba, l_target_centaur); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_u32); + rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_u32); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_attr_mss_volt_u32); + rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_attr_mss_volt_u32); if(rc) return rc; - - //const fapi::Target is centaur.mba - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, l_dimm_type_u8); + + //const fapi::Target is centaur.mba + rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, l_dimm_type_u8); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, l_num_drops_per_port_u8); + rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, l_num_drops_per_port_u8); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm_u8array); + rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm_u8array); if(rc) return rc; - + FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); FAPI_INF("freq = %d on %s.", l_attr_mss_freq_u32, l_target_centaur.toEcmdString()); FAPI_INF("volt = %d on %s.", l_attr_mss_volt_u32, l_target_centaur.toEcmdString()); @@ -244,49 +246,47 @@ fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_ta FAPI_INF("num_ranks_per_dimm = [%02d][%02d][%02d][%02d] on %s.", l_num_ranks_per_dimm_u8array[0][0],l_num_ranks_per_dimm_u8array[0][1], l_num_ranks_per_dimm_u8array[1][0],l_num_ranks_per_dimm_u8array[1][1], i_target_mba.toEcmdString()); FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); - if ( l_num_drops_per_port_u8 == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL ) + if ( l_num_drops_per_port_u8 == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL ) { l_actual_dimm_size_u8 = 2; } - else + else { l_actual_dimm_size_u8 = 1; } - - rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, l_shmoo_type_valid_t); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_PARAM_VALID, &i_target_mba, l_shmoo_param_valid_t); + + rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, l_shmoo_type_valid_t); + if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_PARAM_VALID, &i_target_mba, l_shmoo_param_valid_t); if(rc) return rc; - + shmoo_type_t l_shmoo_type_valid; shmoo_param l_shmoo_param_valid; l_shmoo_type_valid=(shmoo_type_t)l_shmoo_type_valid_t; l_shmoo_param_valid=(shmoo_param)l_shmoo_param_valid_t; - + FAPI_INF("+++++++++++++++++++++++++ Read Schmoo Attributes ++++++++++++++++++++++++++"); FAPI_INF("Schmoo param valid = 0x%x on %s", l_shmoo_param_valid, i_target_mba.toEcmdString()); FAPI_INF("Schmoo test valid = 0x%x on %s", l_shmoo_type_valid, i_target_mba.toEcmdString()); FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); - //Check for Shmoo Parameter, if anyof them is enabled then go into the loop else the procedure exit + //Check for Shmoo Parameter, if anyof them is enabled then go into the loop else the procedure exit - for ( l_port = 0; l_port < MAX_PORT; l_port += 1 ) - { if (( l_num_ranks_per_dimm_u8array[l_port][0] > 0 ) || (l_num_ranks_per_dimm_u8array[l_port][1] > 0)) { - if((l_shmoo_param_valid != PARAM_NONE) || (l_shmoo_type_valid != TEST_NONE)) + if((l_shmoo_param_valid != PARAM_NONE) || (l_shmoo_type_valid != TEST_NONE)) { if((l_shmoo_param_valid & DRV_IMP) != 0) - { - rc = drv_imped_shmoo(i_target_mba, l_port, l_shmoo_type_valid, i_pattern,i_test_type); + { + rc = drv_imped_shmoo(i_target_mba, l_port, l_shmoo_type_valid, i_pattern,i_test_type); if (rc) { FAPI_ERR("Driver Impedance Schmoo function is Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); return rc; } } - if((l_shmoo_param_valid & SLEW_RATE) !=0) + if((l_shmoo_param_valid & SLEW_RATE) !=0) { rc = slew_rate_shmoo(i_target_mba, l_port, l_shmoo_type_valid, i_pattern,i_test_type); if (rc) @@ -295,7 +295,7 @@ fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_ta return rc; } } - if((l_shmoo_param_valid & WR_VREF) != 0) + if((l_shmoo_param_valid & WR_VREF) != 0) { rc = wr_vref_shmoo(i_target_mba, l_port, l_shmoo_type_valid, i_pattern,i_test_type); if (rc) @@ -314,7 +314,7 @@ fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_ta } } if ((l_shmoo_param_valid & RCV_IMP) !=0) - { + { rc = rcv_imp_shmoo(i_target_mba, l_port, l_shmoo_type_valid, i_pattern,i_test_type); if (rc) { @@ -322,9 +322,9 @@ fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_ta return rc; } } - if (((l_shmoo_param_valid & DELAY_REG) != 0) || (l_shmoo_type_valid != TEST_NONE)) + if ((l_shmoo_param_valid & DELAY_REG) != 0) { - rc = delay_shmoo(i_target_mba, l_port, l_shmoo_type_valid, &l_left_margin, &l_right_margin,i_pattern,i_test_type); + rc = delay_shmoo(i_target_mba, l_port, l_shmoo_type_valid, &l_left_margin, &l_right_margin, i_pattern, i_test_type, l_shmoo_param); if (rc) { FAPI_ERR("Delay Schmoo Function is Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); @@ -332,7 +332,6 @@ fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_ta } } } - } } return rc; } @@ -366,7 +365,8 @@ fapi::ReturnCode drv_imped_shmoo(const fapi::Target & i_target_mba, uint8_t l_slew_rate_dq_dqs_schmoo[MAX_PORT] = {0}; uint32_t l_drv_imp_dq_dqs_schmoo[MAX_PORT] = {0}; uint8_t l_drv_imp_dq_dqs_nom_fc = 0; - //Temporary + uint8_t l_drv_imp_dq_dqs_in = 0; + //Temporary i_shmoo_type_valid = WR_EYE; //Hard coded, since no other schmoo is applicable for this parameter uint32_t l_left_margin_drv_imp_array[MAX_DRV_IMP] = {0}; uint32_t l_right_margin_drv_imp_array[MAX_DRV_IMP] = {0}; @@ -374,44 +374,45 @@ fapi::ReturnCode drv_imped_shmoo(const fapi::Target & i_target_mba, uint32_t l_right_margin = 0; uint8_t count = 0; uint8_t l_slew_type = 0; // Hard coded since this procedure will touch only DQ_DQS and not address - - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_drv_imp_dq_dqs_nom); + + rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_drv_imp_dq_dqs_nom); if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, l_slew_rate_dq_dqs); + rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, l_slew_rate_dq_dqs); if (rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO, &i_target_mba, l_drv_imp_dq_dqs_schmoo); if (rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO, &i_target_mba, l_slew_rate_dq_dqs_schmoo); if (rc) return rc; - + FAPI_INF("+++++++++++++++++Read DRIVER IMP Attributes values++++++++++++++++"); FAPI_INF("CEN_DRV_IMP_DQ_DQS[%d] = [%02d] Ohms, on %s", i_port, l_drv_imp_dq_dqs_nom[i_port], i_target_mba.toEcmdString()); FAPI_INF("CEN_DRV_IMP_DQ_DQS_SCHMOO[0] = [0x%x], CEN_DRV_IMP_DQ_DQS_SCHMOO[1] = [0x%x] on %s", l_drv_imp_dq_dqs_schmoo[0],l_drv_imp_dq_dqs_schmoo[1], i_target_mba.toEcmdString()); FAPI_INF("CEN_SLEW_RATE_DQ_DQS[0] = [%02d]V/ns , CEN_SLEW_RATE_DQ_DQS[1] = [%02d]V/ns on %s", l_slew_rate_dq_dqs[0],l_slew_rate_dq_dqs[1], i_target_mba.toEcmdString()); FAPI_INF("CEN_SLEW_RATE_DQ_DQS_SCHMOO[0] = [0x%x], CEN_SLEW_RATE_DQ_DQS_SCHMOO[1] = [0x%x] on %s", l_slew_rate_dq_dqs_schmoo[0],l_slew_rate_dq_dqs_schmoo[1], i_target_mba.toEcmdString()); FAPI_INF("++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); - + if(l_drv_imp_dq_dqs_schmoo[i_port] == 0) //Check for any of the bits enabled in the shmoo { FAPI_INF("DRIVER IMP Shmoo set to FAST Mode and won't do anything"); } else - { - for(index = 0; index< MAX_DRV_IMP; index+=1) + { + for(index = 0; index< MAX_DRV_IMP; index+=1) { - if (l_drv_imp_dq_dqs_schmoo[i_port] & MASK) + if (l_drv_imp_dq_dqs_schmoo[i_port] & MASK) { l_drv_imp_dq_dqs[i_port] = drv_imp_array[index]; FAPI_INF("Current Driver Impedance Value = %d Ohms", drv_imp_array[index]); FAPI_INF("Configuring Driver Impedance Registers:"); - rc = config_drv_imp(i_target_mba, i_port, l_drv_imp_dq_dqs[i_port]); + rc = config_drv_imp(i_target_mba, i_port, l_drv_imp_dq_dqs[i_port]); if (rc) return rc; + l_drv_imp_dq_dqs_in = l_drv_imp_dq_dqs[i_port]; FAPI_INF("Configuring Slew Rate Registers:"); - rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs[i_port], l_slew_rate_dq_dqs[i_port]); + rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs[i_port], l_slew_rate_dq_dqs[i_port]); if (rc) return rc; FAPI_INF("Calling Shmoo for finding Timing Margin:"); - rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, - &l_left_margin, &l_right_margin, i_pattern, i_test_type); + rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, + &l_left_margin, &l_right_margin, i_pattern, i_test_type, l_drv_imp_dq_dqs_in); if (rc) return rc; l_left_margin_drv_imp_array[index]= l_left_margin; l_right_margin_drv_imp_array[index]= l_right_margin; @@ -426,7 +427,7 @@ fapi::ReturnCode drv_imped_shmoo(const fapi::Target & i_target_mba, l_drv_imp_dq_dqs_nom_fc = l_drv_imp_dq_dqs_nom[i_port]; find_best_margin(DRV_IMP, l_left_margin_drv_imp_array, l_right_margin_drv_imp_array, MAX_DRV_IMP, l_drv_imp_dq_dqs_nom_fc, count); - + if (count >= MAX_DRV_IMP) { FAPI_ERR("Driver Imp new input(%d) out of bounds, (>= %d)", @@ -436,7 +437,7 @@ fapi::ReturnCode drv_imped_shmoo(const fapi::Target & i_target_mba, } else { - + if(i_port == 0) { l_drv_imp_dq_dqs_new[0] = drv_imp_array[count]; @@ -447,28 +448,28 @@ fapi::ReturnCode drv_imped_shmoo(const fapi::Target & i_target_mba, l_drv_imp_dq_dqs_new[1] = drv_imp_array[count]; l_drv_imp_dq_dqs_new[0] = l_drv_imp_dq_dqs_nom[0]; } - + if (l_drv_imp_dq_dqs_new[i_port] != l_drv_imp_dq_dqs_nom[i_port]) { FAPI_INF("Better Margin found on %d Ohms on %s", l_drv_imp_dq_dqs_new[i_port], i_target_mba.toEcmdString()); - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_drv_imp_dq_dqs_new); + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_drv_imp_dq_dqs_new); if (rc) return rc; FAPI_INF("Configuring New Driver Impedance Value to Registers:"); rc = config_drv_imp(i_target_mba, i_port, l_drv_imp_dq_dqs_new[i_port]); if (rc) return rc; - rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs_new[i_port], l_slew_rate_dq_dqs[i_port]); + rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs_new[i_port], l_slew_rate_dq_dqs[i_port]); if (rc) return rc; } else { - FAPI_INF("Nominal value will not be changed - Restoring the original values!"); + FAPI_INF("Nominal value will not be changed - Restoring the original values!"); rc = config_drv_imp(i_target_mba, i_port, l_drv_imp_dq_dqs_nom[i_port]); if (rc) return rc; - rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs_nom[i_port], l_slew_rate_dq_dqs[i_port]); + rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs_nom[i_port], l_slew_rate_dq_dqs[i_port]); if (rc) return rc; - } + } } - + FAPI_INF("++++ Driver impedance shmoo function executed successfully ++++"); } return rc; @@ -496,11 +497,12 @@ fapi::ReturnCode slew_rate_shmoo(const fapi::Target & i_target_mba, uint8_t l_slew_rate_dq_dqs[MAX_PORT] = {0}; uint8_t l_slew_rate_dq_dqs_nom[MAX_PORT] = {0}; uint8_t l_slew_rate_dq_dqs_nom_fc = 0; + uint8_t l_slew_rate_dq_dqs_in = 0; uint8_t l_slew_rate_dq_dqs_new[MAX_PORT] = {0}; uint32_t l_slew_rate_dq_dqs_schmoo[MAX_PORT] = {0}; uint8_t l_drv_imp_dq_dqs_nom[MAX_PORT] = {0}; i_shmoo_type_valid = WR_EYE; // Hard coded - Other shmoo type is not valid - Temporary - + uint8_t index = 0; uint8_t count = 0; uint32_t l_left_margin_slew_array[MAX_NUM_SLEW_RATES] = {0}; @@ -508,21 +510,21 @@ fapi::ReturnCode slew_rate_shmoo(const fapi::Target & i_target_mba, uint32_t l_left_margin = 0; uint32_t l_right_margin = 0; uint8_t l_slew_type = 0; // Hard coded since this procedure will touch only DQ_DQS and not address - + //Read Attributes - DRV IMP, SLEW, SLEW RATES values to be Schmoo'ed - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_drv_imp_dq_dqs_nom); + rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_drv_imp_dq_dqs_nom); if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, l_slew_rate_dq_dqs_nom); + rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, l_slew_rate_dq_dqs_nom); if (rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO, &i_target_mba, l_slew_rate_dq_dqs_schmoo); if (rc) return rc; - + FAPI_INF("+++++++++++++++++Read Slew Shmoo Attributes values+++++++++++++++"); FAPI_INF("CEN_DRV_IMP_DQ_DQS[0] = [%02d] Ohms, CEN_DRV_IMP_DQ_DQS[1] = [%02d] Ohms on %s", l_drv_imp_dq_dqs_nom[0],l_drv_imp_dq_dqs_nom[1], i_target_mba.toEcmdString()); FAPI_INF("CEN_SLEW_RATE_DQ_DQS[0] = [%02d]V/ns , CEN_SLEW_RATE_DQ_DQS[1] = [%02d]V/ns on %s", l_slew_rate_dq_dqs_nom[0],l_slew_rate_dq_dqs_nom[1], i_target_mba.toEcmdString()); FAPI_INF("CEN_SLEW_RATE_DQ_DQS_SCHMOO[0] = [0x%x], CEN_SLEW_RATE_DQ_DQS_SCHMOO[1] = [0x%x] on %s", l_slew_rate_dq_dqs_schmoo[0],l_slew_rate_dq_dqs_schmoo[1], i_target_mba.toEcmdString()); FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); - + if(l_slew_rate_dq_dqs_schmoo == 0) //Check for any of the bits enabled in the shmoo { FAPI_INF("Slew Rate Shmoo set to FAST Mode and won't do anything"); @@ -531,16 +533,17 @@ fapi::ReturnCode slew_rate_shmoo(const fapi::Target & i_target_mba, { for(index = 0; index < MAX_NUM_SLEW_RATES; index+=1) { - if (l_slew_rate_dq_dqs_schmoo[i_port] & MASK ) + if (l_slew_rate_dq_dqs_schmoo[i_port] & MASK ) { l_slew_rate_dq_dqs[i_port] = slew_rate_array[index]; FAPI_INF("Current Slew rate value is %d V/ns", slew_rate_array[index]); FAPI_INF("Configuring Slew registers:"); - rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs_nom[i_port], l_slew_rate_dq_dqs[i_port]); + rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs_nom[i_port], l_slew_rate_dq_dqs[i_port]); if (rc) return rc; + l_slew_rate_dq_dqs_in = l_slew_rate_dq_dqs[i_port]; FAPI_INF("Calling Shmoo for finding Timing Margin:"); - rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, - &l_left_margin, &l_right_margin, i_pattern, i_test_type); + rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, + &l_left_margin, &l_right_margin, i_pattern, i_test_type, l_slew_rate_dq_dqs_in); if (rc) return rc; l_left_margin_slew_array[index]= l_left_margin; l_right_margin_slew_array[index]= l_right_margin; @@ -564,38 +567,38 @@ fapi::ReturnCode slew_rate_shmoo(const fapi::Target & i_target_mba, } else { - + if(i_port == 0) { l_slew_rate_dq_dqs_new[0] = slew_rate_array[count]; - l_slew_rate_dq_dqs_new[1] = l_slew_rate_dq_dqs_nom[1]; + l_slew_rate_dq_dqs_new[1] = l_slew_rate_dq_dqs_nom[1]; } else { l_slew_rate_dq_dqs_new[1] = slew_rate_array[count]; - l_slew_rate_dq_dqs_new[0] = l_slew_rate_dq_dqs_nom[0]; + l_slew_rate_dq_dqs_new[0] = l_slew_rate_dq_dqs_nom[0]; } - - - + + + if (l_slew_rate_dq_dqs_new[i_port] != l_slew_rate_dq_dqs_nom[i_port]) { FAPI_INF("Better Margin found on Slew Rate: %d V/ns on %s", l_slew_rate_dq_dqs_new[i_port], i_target_mba.toEcmdString()); - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, l_slew_rate_dq_dqs_new); + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, l_slew_rate_dq_dqs_new); if (rc) return rc; FAPI_INF("Configuring New Slew Rate Value to Registers:"); - rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs_nom[i_port], l_slew_rate_dq_dqs_new[i_port]); + rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs_nom[i_port], l_slew_rate_dq_dqs_new[i_port]); if (rc) return rc; } else { - FAPI_INF("Nominal value will not be changed!"); + FAPI_INF("Nominal value will not be changed!"); FAPI_INF("Slew Rate: %d V/ns on %s", l_slew_rate_dq_dqs_nom[i_port], i_target_mba.toEcmdString()); } } FAPI_INF("++++ Slew Rate shmoo function executed successfully ++++"); } -return rc; +return rc; } //---------------------------------------------------------------------------------------------- @@ -620,28 +623,29 @@ fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba, uint32_t l_wr_dram_vref[MAX_PORT] = {0}; uint32_t l_wr_dram_vref_nom[MAX_PORT] = {0}; uint32_t l_wr_dram_vref_new[MAX_PORT] = {0}; - uint32_t l_wr_dram_vref_schmoo[MAX_PORT] = {0}; + uint32_t l_wr_dram_vref_schmoo[MAX_PORT] = {0}; uint32_t l_wr_dram_vref_nom_fc = 0; + uint32_t l_wr_dram_vref_in = 0; i_shmoo_type_valid = WR_EYE; // Hard coded - Temporary - + uint8_t index = 0; uint8_t count = 0; uint32_t l_left_margin = 0; uint32_t l_right_margin = 0; uint32_t l_left_margin_wr_vref_array[MAX_WR_VREF]= {0}; uint32_t l_right_margin_wr_vref_array[MAX_WR_VREF]= {0}; - + //Read the write vref attributes - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, l_wr_dram_vref_nom); + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, l_wr_dram_vref_nom); if (rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_VREF_SCHMOO, &i_target_mba, l_wr_dram_vref_schmoo); if (rc) return rc; - FAPI_INF("+++++++++++++++++DRAM VREF Read Shmoo Attributes values+++++++++++++++"); - FAPI_INF("DRAM_WR_VREF[0] = %d , DRAM_WR_VREF[0] = %d on %s", l_wr_dram_vref_nom[0], l_wr_dram_vref_nom[1],i_target_mba.toEcmdString()); - FAPI_INF("DRAM_WR_VREF_SCHMOO[0] = [%x],DRAM_WR_VREF_SCHMOO[0] = [%x] on %s", l_wr_dram_vref_schmoo[0], l_wr_dram_vref_schmoo[1],i_target_mba.toEcmdString()); + FAPI_INF("+++++++++++++++++DRAM VREF Shmoo Attributes Values+++++++++++++++"); + FAPI_INF("DRAM_WR_VREF[0] = %d , DRAM_WR_VREF[1] = %d on %s", l_wr_dram_vref_nom[0], l_wr_dram_vref_nom[1],i_target_mba.toEcmdString()); + FAPI_INF("DRAM_WR_VREF_SCHMOO[0] = [%x],DRAM_WR_VREF_SCHMOO[1] = [%x] on %s", l_wr_dram_vref_schmoo[0], l_wr_dram_vref_schmoo[1],i_target_mba.toEcmdString()); FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); - - + + if(l_wr_dram_vref_schmoo[i_port] == 0) { FAPI_INF("FAST Shmoo Mode: This function will not change any Write DRAM VREF settings"); @@ -650,15 +654,16 @@ fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba, { for(index = 0; index < MAX_WR_VREF; index+=1) { - if (l_wr_dram_vref_schmoo[i_port] & MASK) + if (l_wr_dram_vref_schmoo[i_port] & MASK) { FAPI_INF("Current Vref value is %dmV", wr_vref_array[index]); l_wr_dram_vref[i_port] = wr_vref_array[index]; - rc = config_wr_dram_vref(i_target_mba, i_port, l_wr_dram_vref[i_port]); + rc = config_wr_dram_vref(i_target_mba, i_port, l_wr_dram_vref[i_port]); if (rc) return rc; + l_wr_dram_vref_in = l_wr_dram_vref[i_port]; FAPI_INF(" Calling Shmoo for finding Timing Margin:"); - rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, - &l_left_margin, &l_right_margin, i_pattern, i_test_type); + rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, + &l_left_margin, &l_right_margin, i_pattern, i_test_type, l_wr_dram_vref_in); if (rc) return rc; l_left_margin_wr_vref_array[index]= l_left_margin; l_right_margin_wr_vref_array[index]= l_right_margin; @@ -683,7 +688,7 @@ fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba, } else { - + if(i_port == 0) { l_wr_dram_vref_new[0] = wr_vref_array_fitness[count]; @@ -694,21 +699,21 @@ fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba, l_wr_dram_vref_new[1] = wr_vref_array_fitness[count]; l_wr_dram_vref_new[0] = l_wr_dram_vref_nom[0]; } - + if(l_wr_dram_vref_new[i_port] != l_wr_dram_vref_nom[i_port]) { FAPI_INF("Best Margin Found on Vref : %d , %d mV on %s", count, wr_vref_array_fitness[count], i_target_mba.toEcmdString()); - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, l_wr_dram_vref_new); + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, l_wr_dram_vref_new); if (rc) return rc; FAPI_INF("Configuring New Vref Value to registers:"); - rc = config_wr_dram_vref(i_target_mba, i_port, l_wr_dram_vref_new[i_port]); - if (rc) return rc; + rc = config_wr_dram_vref(i_target_mba, i_port, l_wr_dram_vref_new[i_port]); + if (rc) return rc; } else { - FAPI_INF("Nominal value will not be changed!- Restoring the original values!"); - rc = config_wr_dram_vref(i_target_mba, i_port, l_wr_dram_vref_nom[i_port]); - if (rc) return rc; + FAPI_INF("Nominal value will not be changed!- Restoring the original values!"); + rc = config_wr_dram_vref(i_target_mba, i_port, l_wr_dram_vref_nom[i_port]); + if (rc) return rc; } } FAPI_INF("++++ Write Vref Shmoo function executed successfully ++++"); @@ -719,51 +724,52 @@ fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba, //---------------------------------------------------------------------------------------------- -// Function name: rd_vref_shmoo() -// Description: This function varies the Centaur IO vref in 16 steps -// Calls write eye shmoo function +// Function name: rd_vref_shmoo() +// Description: This function varies the Centaur IO vref in 16 steps +// Calls write eye shmoo function // Input param: const fapi::Target MBA, port = 0,1 // Shmoo type: MCBIST, WR_EYE, RD_EYE, WR_DQS, RD_DQS // Shmoo param: PARAM_NONE, DRV_IMP, SLEW_RATE, WR_VREF, RD_VREF, RCV_IMP // Shmoo Mode: FEW_ADDR, QUARTER_ADDR, HALF_ADDR, FULL_ADDR // i_pattern, i_test_type : Default = 0, mcbist lab function would use this arg //---------------------------------------------------------------------------------------------- - + fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, shmoo_type_t i_shmoo_type_valid, uint8_t i_pattern, - uint8_t i_test_type) + uint8_t i_test_type) { fapi::ReturnCode rc; uint32_t l_rd_cen_vref[MAX_PORT] = {0}; uint32_t l_rd_cen_vref_nom[MAX_PORT] = {0}; uint32_t l_rd_cen_vref_nom_fc = 0; + uint32_t l_rd_cen_vref_in = 0; uint32_t l_rd_cen_vref_new[MAX_PORT] ={0}; uint32_t l_rd_cen_vref_schmoo[MAX_PORT] = {0}; uint8_t index = 0; uint8_t count = 0; i_shmoo_type_valid = RD_EYE; // Hard coded - Temporary - + uint32_t l_left_margin = 0; uint32_t l_right_margin = 0; uint32_t l_left_margin_rd_vref_array[MAX_RD_VREF] = {0}; uint32_t l_right_margin_rd_vref_array[MAX_RD_VREF] = {0}; - - + + rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, l_rd_cen_vref_nom); if (rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RD_VREF_SCHMOO, &i_target_mba, l_rd_cen_vref_schmoo); if (rc) return rc; - + FAPI_INF("+++++++++++++++++CENTAUR VREF Read Shmoo Attributes values+++++++++++++++"); FAPI_INF("CEN_RD_VREF[0] = %d CEN_RD_VREF[1] = %d on %s", l_rd_cen_vref_nom[0],l_rd_cen_vref_nom[1], i_target_mba.toEcmdString()); FAPI_INF("CEN_RD_VREF_SCHMOO[0] = [%d], CEN_RD_VREF_SCHMOO[1] = [%d] on %s", l_rd_cen_vref_schmoo[0], l_rd_cen_vref_schmoo[1],i_target_mba.toEcmdString()); FAPI_INF("++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); - + if(l_rd_cen_vref_schmoo[i_port] == 0) { - FAPI_INF("FAST Shmoo Mode: This function will not change any Write DRAM VREF settings"); + FAPI_INF("FAST Shmoo Mode: This function will not change any Read Centaur VREF settings"); } else { @@ -775,8 +781,9 @@ fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba, FAPI_INF("Current Vref value is %dmV", rd_cen_vref_array[index]); FAPI_INF("Configuring Read Vref Registers:"); rc = config_rd_cen_vref(i_target_mba, i_port, l_rd_cen_vref[i_port]); if (rc) return rc; + l_rd_cen_vref_in = l_rd_cen_vref[i_port]; FAPI_INF(" Calling Shmoo function to find out Timing Margin:"); - rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, &l_left_margin, &l_right_margin,i_pattern,i_test_type); + rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, &l_left_margin, &l_right_margin,i_pattern,i_test_type, l_rd_cen_vref_in); if (rc) return rc; l_left_margin_rd_vref_array[index]= l_left_margin; l_right_margin_rd_vref_array[index]= l_right_margin; @@ -800,7 +807,7 @@ fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba, } else { - + if(i_port == 0) { l_rd_cen_vref_new[0] = rd_cen_vref_array_fitness[count]; @@ -811,20 +818,20 @@ fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba, l_rd_cen_vref_new[1] = rd_cen_vref_array_fitness[count]; l_rd_cen_vref_new[0] = l_rd_cen_vref_nom[0]; } - + if(l_rd_cen_vref_new[i_port] != l_rd_cen_vref_nom[i_port]) { FAPI_INF("Best Margin Found on Vref : %dmv , %dmV on %s", l_rd_cen_vref_new[i_port], rd_cen_vref_array_fitness[count], i_target_mba.toEcmdString()); - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, l_rd_cen_vref_new); + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, l_rd_cen_vref_new); if (rc) return rc; FAPI_INF("Configuring New Read Vref Value to Registers:"); - rc = config_rd_cen_vref(i_target_mba, i_port, l_rd_cen_vref_new[i_port]); + rc = config_rd_cen_vref(i_target_mba, i_port, l_rd_cen_vref_new[i_port]); if (rc) return rc; } else { - FAPI_INF("Nominal value will not be changed!- Restoring the original values!"); - rc = config_rd_cen_vref(i_target_mba, i_port, l_rd_cen_vref_nom[i_port]); + FAPI_INF("Nominal value will not be changed!- Restoring the original values!"); + rc = config_rd_cen_vref(i_target_mba, i_port, l_rd_cen_vref_nom[i_port]); if (rc) return rc; } } @@ -852,23 +859,24 @@ fapi::ReturnCode rcv_imp_shmoo(const fapi::Target & i_target_mba, uint8_t l_rcv_imp_dq_dqs[MAX_PORT] = {0}; uint8_t l_rcv_imp_dq_dqs_nom[MAX_PORT] = {0}; uint8_t l_rcv_imp_dq_dqs_nom_fc = 0; + uint8_t l_rcv_imp_dq_dqs_in = 0; uint8_t l_rcv_imp_dq_dqs_new[MAX_PORT] = {0}; uint32_t l_rcv_imp_dq_dqs_schmoo[MAX_PORT] = {0}; uint8_t index = 0; uint8_t count = 0; i_shmoo_type_valid = RD_EYE; //Hard coded since no other shmoo is applicable - Temporary - + uint32_t l_left_margin = 0; uint32_t l_right_margin = 0; uint32_t l_left_margin_rcv_imp_array[MAX_RCV_IMP] = {0}; uint32_t l_right_margin_rcv_imp_array[MAX_RCV_IMP] = {0}; - - + + rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, l_rcv_imp_dq_dqs_nom); if (rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO, &i_target_mba, l_rcv_imp_dq_dqs_schmoo); if (rc) return rc; - + FAPI_INF("+++++++++++++++++RECIVER IMP Read Shmoo Attributes values+++++++++++++++"); FAPI_INF("CEN_RCV_IMP_DQ_DQS[0] = %d , CEN_RCV_IMP_DQ_DQS[1] = %d on %s", l_rcv_imp_dq_dqs_nom[0],l_rcv_imp_dq_dqs_nom[1], i_target_mba.toEcmdString()); FAPI_INF("CEN_RCV_IMP_DQ_DQS_SCHMOO[0] = [%d], CEN_RCV_IMP_DQ_DQS_SCHMOO[1] = [%d], on %s", l_rcv_imp_dq_dqs_schmoo[0],l_rcv_imp_dq_dqs_schmoo[1], i_target_mba.toEcmdString()); @@ -888,9 +896,10 @@ fapi::ReturnCode rcv_imp_shmoo(const fapi::Target & i_target_mba, FAPI_INF("Current Receiver Impedance: %d Ohms ", rcv_imp_array[index]); FAPI_INF("Configuring Receiver impedance registers:"); rc = config_rcv_imp(i_target_mba, i_port, l_rcv_imp_dq_dqs[i_port]); if (rc) return rc; + l_rcv_imp_dq_dqs_in = l_rcv_imp_dq_dqs[i_port]; FAPI_INF("Calling Shmoo function to find out timing margin:"); - rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, - &l_left_margin, &l_right_margin, i_pattern, i_test_type); + rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, + &l_left_margin, &l_right_margin, i_pattern, i_test_type, l_rcv_imp_dq_dqs_in); if (rc) return rc; l_left_margin_rcv_imp_array[index]= l_left_margin; l_right_margin_rcv_imp_array[index]= l_right_margin; @@ -914,7 +923,7 @@ fapi::ReturnCode rcv_imp_shmoo(const fapi::Target & i_target_mba, } else { - + if(i_port == 0) { l_rcv_imp_dq_dqs_new[0] = rcv_imp_array[count]; @@ -925,25 +934,25 @@ fapi::ReturnCode rcv_imp_shmoo(const fapi::Target & i_target_mba, l_rcv_imp_dq_dqs_new[1] = rcv_imp_array[count]; l_rcv_imp_dq_dqs_new[0] = l_rcv_imp_dq_dqs_nom[0]; } - + if (l_rcv_imp_dq_dqs_new[i_port] != l_rcv_imp_dq_dqs_nom[i_port]) { FAPI_INF("Better Margin found on %d on %s", l_rcv_imp_dq_dqs_new[i_port], i_target_mba.toEcmdString()); - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, l_rcv_imp_dq_dqs_new); + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, l_rcv_imp_dq_dqs_new); if (rc) return rc; rc = config_rcv_imp(i_target_mba, i_port, l_rcv_imp_dq_dqs_new[i_port]); if (rc) return rc; } else { - FAPI_INF("Nominal value will not be changed!- Restoring the original values!"); + FAPI_INF("Nominal value will not be changed!- Restoring the original values!"); rc = config_rcv_imp(i_target_mba, i_port, l_rcv_imp_dq_dqs_nom[i_port]); if (rc) return rc; } } FAPI_INF("++++ Receiver Impdeance Shmoo function executed successfully ++++"); } -return rc; +return rc; } //------------------------------------------------------------------------------ @@ -953,7 +962,7 @@ return rc; // Shmoo type: MCBIST, WR_EYE, RD_EYE, WR_DQS, RD_DQS // Shmoo Mode: FEW_ADDR, QUARTER_ADDR, HALF_ADDR, FULL_ADDR // i_pattern, i_test_type : Default = 0, mcbist lab function would use this arg -// Output param: l_left_margin = Left Margin(Setup time), +// Output param: l_left_margin = Left Margin(Setup time), // l_right_margin = Right Margin (Hold time) in ps //------------------------------------------------------------------------------ @@ -962,14 +971,15 @@ fapi::ReturnCode delay_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, uint32_t *o_left_margin, uint32_t *o_right_margin, uint8_t i_pattern, - uint8_t i_test_type) + uint8_t i_test_type, + uint32_t i_shmoo_param) { fapi::ReturnCode rc; FAPI_INF(" Inside the delay shmoo " ); //Constructor CALL: generic_shmoo::generic_shmoo(uint8_t i_port, uint32_t shmoo_mask,shmoo_algorithm_t shmoo_algorithm) //generic_shmoo mss_shmoo=generic_shmoo(i_port,2,SEQ_LIN); generic_shmoo mss_shmoo=generic_shmoo(i_port,i_shmoo_type_valid,SEQ_LIN); - rc = mss_shmoo.run(i_target_mba, o_left_margin, o_right_margin,i_pattern,i_test_type); + rc = mss_shmoo.run(i_target_mba, o_left_margin, o_right_margin,i_pattern,i_test_type,i_shmoo_param); if(rc) { FAPI_ERR("Delay Schmoo Function is Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); @@ -1001,12 +1011,12 @@ void find_best_margin(shmoo_param i_shmoo_param_valid, uint32_t left_margin_nom = 0; uint32_t right_margin_nom = 0; uint32_t diff_margin_nom = 0; - uint32_t __attribute__((unused)) total_margin = 0; // HACK + uint32_t __attribute__((unused)) total_margin = 0; //SW198827 uint32_t diff_margin = 0; uint8_t index = 0; uint8_t index2 = 0; - - + + for(index = 0; index < i_max; index+=1) //send max from top function { if(i_shmoo_param_valid & DRV_IMP) @@ -1032,7 +1042,7 @@ void find_best_margin(shmoo_param i_shmoo_param_valid, } } else if(i_shmoo_param_valid & WR_VREF) - { + { if (wr_vref_array_fitness[index] == i_param_nom) { left_margin_nom = i_left[index]; @@ -1043,7 +1053,7 @@ void find_best_margin(shmoo_param i_shmoo_param_valid, } } else if(i_shmoo_param_valid & RD_VREF) - { + { if (rd_cen_vref_array_fitness[index] == i_param_nom) { left_margin_nom = i_left[index]; @@ -1054,17 +1064,17 @@ void find_best_margin(shmoo_param i_shmoo_param_valid, } } else if(i_shmoo_param_valid & RCV_IMP) - { + { if (rcv_imp_array[index] == i_param_nom) { left_margin_nom = i_left[index]; right_margin_nom = i_right[index]; diff_margin_nom = (i_left[index] >= i_right[index]) ? (i_left[index] - i_right[index]) : (i_right[index] - i_left[index]); FAPI_INF("Receiver Impedance value (NOM): %d Ohms Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]); - break; + break; } } - + } for(index2 = 0; index2 < i_max; index2+=1) { diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C index ddbb0108f..b29864630 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C @@ -20,14 +20,15 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_generic_shmoo.C,v 1.27 2013/01/22 17:31:26 sasethur Exp $ + +// $Id: mss_generic_shmoo.C,v 1.43 2013/04/11 15:06:18 bellows Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** // *!*************************************************************************** // *! FILENAME : mss_generic_shmoo.C -// *! TITLE : MSS Generic Shmoo Implementation +// *! TITLE : MSS Generic Shmoo Implementation // *! DESCRIPTION : Memory Subsystem Generic Shmoo -- abstraction for HB // *! CONTEXT : To make all shmoos share a common abstraction layer // *! @@ -39,19 +40,27 @@ //------------------------------------------------------------------------------ // Version:|Author: | Date: | Comment: // --------|--------|---------|-------------------------------------------------- -// 1.26 |abhijit |01/21/13 | fixed fw comments -// 1.25 |abhijit |01/21/13 | fixed the constructor definition +// 1.43 |bellows |04/11/13 | quick fix for firmware delivery. Uninitialized varialbles: i_mcbtest, i_mcbpatt +// 1.42 |abhijit |04/09/13 | added shmoo param +// 1.40 |abhijit |03/22/13 | Fixed boundary checks +// 1.38 |abhijit |03/19/13 | included spare byte and ECC and fixed printing for RD_EYE +// 1.36 |abhijit |03/19/13 | changed mcbist call position +// 1.35 |abhijit |03/16/13 | fixed clearing of error map regs for mba23 +// 1.32 |abhijit |03/12/13 | new parallel schmoo under dev +// 1.27 |abhijit |01/21/13 | fixed ISDIMM mapping need some workaround +// 1.26 |abhijit |01/21/13 | fixed fw comments +// 1.25 |abhijit |01/21/13 | fixed the constructor definition // 1.21 |sasethur|01/17/13 | Updated for sanity mcbist function // 1.20 |abhijit |01/11/13 | Updated for change in setup_mcbist function // 1.19 |aditya |01/07/13 | Updated for change in setup_mcbist function -// 1.18 |sasethur|14-DEC-12| Updated for change in access delay function -// 1.16 |sasethur|14-DEC-12| Updated for Warning -// 1.15 |abhijit |13-DEC-12| Updated for FW review comments +// 1.18 |sasethur|14-DEC-12| Updated for change in access delay function +// 1.16 |sasethur|14-DEC-12| Updated for Warning +// 1.15 |abhijit |13-DEC-12| Updated for FW review comments // 1.14 |abhijit |06-DEC-12| Fixed more FW review comments // 1.12 |abhijit |15-Nov-12| Fixed FW review comments // 1.11 |abhijit |29-Oct-12| added change for ISDIMM checker DQS. -// 1.9 |abhijit |22-Oct-12| added Write and read DQS. -// 1.8 |abhijit |15-Oct-12|Updated multiple changes +// 1.9 |abhijit |22-Oct-12| added Write and read DQS. +// 1.8 |abhijit |15-Oct-12|Updated multiple changes // 1.0 |varkeykv|27-Sep-11|Initial check in //------------------------------------------------------------------------------ #include <fapi.H> @@ -66,62 +75,71 @@ extern "C" { using namespace fapi; -// START IMPLEMENTATION OF generic_shmoo CLASS METHODS +// START IMPLEMENTATION OF generic_shmoo CLASS METHODS //! shmoo_mask - What shmoos do you want to run ... encoded as Hex 0x2,0x4,0x8,0x16 /*------------------------------------------------------------------------------ * constructor: generic_shmoo - * Description :Constructor used to initialize variables and do the initial settings + * Description :Constructor used to initialize variables and do the initial settings * - * Parameters: i_target: mba; iv_port: 0, 1 + * Parameters: i_target: mba; iv_port: 0, 1 * ---------------------------------------------------------------------------*/ -generic_shmoo:: generic_shmoo(uint8_t prt,shmoo_type_t shmoo_mask,shmoo_algorithm_t shmoo_algorithm) +generic_shmoo:: generic_shmoo(uint8_t addr,shmoo_type_t shmoo_mask,shmoo_algorithm_t shmoo_algorithm) { //this->shmoo_mask=shmoo_mask; //! Sets what Shmoos the caller wants to run this->algorithm=shmoo_algorithm ; - this->iv_port=prt ; - - - iv_MAX_RANKS=8; + this->iv_addr=addr ; + + + //iv_MAX_RANKS=8; iv_MAX_BYTES=10; iv_DQS_ON=0; iv_pattern=0; iv_test_type=0; iv_dmm_type=0; - - for(int i=0;i<iv_MAX_RANKS;++i) + iv_shmoo_param=0; + + for(int p=0;p<MAX_PORT;++p) + { + for(int i=0;i<iv_MAX_RANKS[p];++i) { valid_rank[i]=0; } - + } + + for(int p=0;p<MAX_PORT;++p) + { + iv_MAX_RANKS[p]=4; + } + FAPI_DBG("mss_generic_shmoo : constructor running for shmoo type %d",shmoo_mask); iv_shmoo_type = 0; SHMOO[iv_shmoo_type].static_knob.min_val=0; - SHMOO[iv_shmoo_type].static_knob.max_val=512; - - + SHMOO[iv_shmoo_type].static_knob.max_val=512; + + if(shmoo_mask & TEST_NONE) { FAPI_DBG("mss_generic_shmoo : WR_EYE selected %d",shmoo_mask); iv_shmoo_type = 0; SHMOO[0].static_knob.min_val=0; - SHMOO[0].static_knob.max_val=512; + SHMOO[0].static_knob.max_val=512; } - + if(shmoo_mask & WR_EYE) { FAPI_DBG("mss_generic_shmoo : WR_EYE selected %d",shmoo_mask); iv_shmoo_type = 0; SHMOO[0].static_knob.min_val=0; - SHMOO[0].static_knob.max_val=512; + SHMOO[0].static_knob.max_val=512; } if(shmoo_mask & RD_EYE) { FAPI_DBG("mss_generic_shmoo : RD_EYE selected %d",shmoo_mask); iv_shmoo_type = 2; - SHMOO[2].static_knob.min_val=0; + SHMOO[2].static_knob.min_val=2; SHMOO[2].static_knob.max_val=128; } - + if(shmoo_mask & WRT_DQS) //preet { FAPI_DBG("mss_generic_shmoo : WRT_DQS selected %d",shmoo_mask); @@ -130,38 +148,42 @@ generic_shmoo:: generic_shmoo(uint8_t prt,shmoo_type_t shmoo_mask,shmoo_algorith SHMOO[1].static_knob.min_val=0; SHMOO[1].static_knob.max_val=512; } - + if(shmoo_mask & RD_GATE) //preet { FAPI_DBG("mss_generic_shmoo : RD_EYE selected %d",shmoo_mask); - + iv_shmoo_type = 3; iv_DQS_ON = 1; - SHMOO[3].static_knob.min_val=0; + SHMOO[3].static_knob.min_val=2; SHMOO[3].static_knob.max_val=128; } - - for(int j=0;j<iv_MAX_RANKS;++j) + for(int i=0;i<MAX_PORT;++i) + { + for(int j=0;j<iv_MAX_RANKS[i];++j) { - init_multi_array(SHMOO[iv_shmoo_type].MBA.P[iv_port].S[j].K.nom_val,0); - init_multi_array(SHMOO[iv_shmoo_type].MBA.P[iv_port].S[j].K.lb_regval,SHMOO[iv_shmoo_type].static_knob.min_val); - init_multi_array(SHMOO[iv_shmoo_type].MBA.P[iv_port].S[j].K.rb_regval,SHMOO[iv_shmoo_type].static_knob.max_val); - init_multi_array(SHMOO[iv_shmoo_type].MBA.P[iv_port].S[j].K.total_margin,0); - init_multi_array(SHMOO[iv_shmoo_type].MBA.P[iv_port].S[j].K.right_margin_val,0); - init_multi_array(SHMOO[iv_shmoo_type].MBA.P[iv_port].S[j].K.left_margin_val,0); + init_multi_array(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.nom_val,0); + init_multi_array(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.lb_regval,SHMOO[iv_shmoo_type].static_knob.min_val); + init_multi_array(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.rb_regval,SHMOO[iv_shmoo_type].static_knob.max_val); + init_multi_array(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.total_margin,0); + init_multi_array(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.right_margin_val,0); + init_multi_array(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.left_margin_val,0); } - + } + if(iv_DQS_ON == 1) - { - for(int j=0;j<iv_MAX_RANKS;++j) //initialize values for DQS + { for(int i=0;i<MAX_PORT;++i) + { + for(int j=0;j<iv_MAX_RANKS[i];++j) //initialize values for DQS { - init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[iv_port].S[j].K.nom_val,0); - init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[iv_port].S[j].K.lb_regval,SHMOO[iv_shmoo_type].static_knob.min_val); - init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[iv_port].S[j].K.rb_regval,SHMOO[iv_shmoo_type].static_knob.max_val); - init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[iv_port].S[j].K.total_margin,0); - init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[iv_port].S[j].K.right_margin_val,0); - init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[iv_port].S[j].K.left_margin_val,0); + init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.nom_val,0); + init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.lb_regval,SHMOO[iv_shmoo_type].static_knob.min_val); + init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.rb_regval,SHMOO[iv_shmoo_type].static_knob.max_val); + init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.total_margin,0); + init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.right_margin_val,0); + init_multi_array_dqs(SHMOO[iv_shmoo_type].MBA.P[i].S[j].K.left_margin_val,0); } + } } } @@ -171,54 +193,38 @@ generic_shmoo:: generic_shmoo(uint8_t prt,shmoo_type_t shmoo_mask,shmoo_algorith * * Parameters: i_target: mba; iv_port: 0, 1 * ---------------------------------------------------------------------------*/ -fapi::ReturnCode generic_shmoo::run(const fapi::Target & i_target,uint32_t *o_right_min_margin,uint32_t *o_left_min_margin,uint8_t i_pattern,uint8_t i_test_type){ - fapi::ReturnCode rc; +fapi::ReturnCode generic_shmoo::run(const fapi::Target & i_target,uint32_t *o_right_min_margin,uint32_t *o_left_min_margin,uint8_t i_pattern,uint8_t i_test_type,uint32_t i_shmoo_param){ + fapi::ReturnCode rc; uint8_t num_ranks_per_dimm[2][2]; uint8_t l_attr_eff_dimm_type_u8=0; uint8_t l_attr_schmoo_test_type_u8=0; - uint8_t rank_pair=0; - uint16_t l_sp_mask=0x00ff; + //uint8_t l_val=2; + iv_shmoo_param=i_shmoo_param; + ecmdDataBufferBase l_data_buffer1_64(64); - uint32_t rc_num = 0; - + + rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_per_dimm); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, l_attr_eff_dimm_type_u8); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target, l_attr_schmoo_test_type_u8); if(rc) return rc; - iv_MAX_RANKS=num_ranks_per_dimm[iv_port][0]+num_ranks_per_dimm[iv_port][1]; + rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, l_attr_eff_dimm_type_u8); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target, l_attr_schmoo_test_type_u8); if(rc) return rc; + + iv_MAX_RANKS[0]=num_ranks_per_dimm[0][0]+num_ranks_per_dimm[0][1]; + iv_MAX_RANKS[1]=num_ranks_per_dimm[1][0]+num_ranks_per_dimm[1][1]; + iv_pattern=i_pattern; iv_test_type=i_test_type; - + if ( l_attr_eff_dimm_type_u8 == 0 ) { - iv_MAX_BYTES=8; + iv_MAX_BYTES=10; } else { - if(iv_port==0) - { - rc_num = rc_num | l_data_buffer1_64.insertFromRight(l_sp_mask,0,16); - if(rc_num) - { - FAPI_ERR( "mss_generic_shmoo: Error in run !"); - rc.setEcmdError(rc_num); - return rc; - } - } - else - { - rc_num = rc_num | l_data_buffer1_64.insertFromRight(l_sp_mask,16,16); - if(rc_num) - { - FAPI_ERR( "mss_generic_shmoo:"); - rc.setEcmdError(rc_num); - return rc; - } - } - rc = fapiPutScom(i_target,MBS_MCBIST01_MCBCMABQ_0x02011674,l_data_buffer1_64); if(rc) return rc; + iv_dmm_type=1; iv_MAX_BYTES=9; } - rc = mss_getrankpair(i_target,iv_port,0,&rank_pair,valid_rank);if(rc) return rc; + //rc = mss_getrankpair(i_target,iv_port,0,&rank_pair,valid_rank);if(rc) return rc; FAPI_DBG("mss_generic_shmoo : run() for shmoo type %d",shmoo_mask); // Check if all bytes/bits are in a pass condition initially .Otherwise quit if(l_attr_schmoo_test_type_u8 == 0){ @@ -226,29 +232,30 @@ fapi::ReturnCode generic_shmoo::run(const fapi::Target & i_target,uint32_t *o_ri return rc; } if(l_attr_schmoo_test_type_u8 == 1){ - rc=sanity_check(i_target); // Run MCBIST only when ATTR_EFF_SCHMOO_TEST_VALID is mcbist only + rc=sanity_check(i_target); // Run MCBIST only when ATTR_EFF_SCHMOO_TEST_VALID is mcbist only if(!rc.ok()) { FAPI_ERR("generic_shmoo::run MSS Generic Shmoo failed initial Sanity Check. Memory not in an all pass Condition"); - return rc; + return rc; } }else{ - // rc=sanity_check(i_target); // Run MCBIST by default before for every schmoo to check if memory is in good condition. + // rc=sanity_check(i_target); // Run MCBIST by default before for every schmoo to check if memory is in good condition. // if(!rc.ok()) // { // FAPI_ERR("generic_shmoo::run MSS Generic Shmoo failed initial Sanity Check. Memory not in an all pass Condition"); - // return rc; + // return rc; // } // If memory is OK then we continue to gather nominals and config values // Now Read nominal values for all knobs configured // FAPI_DBG("mss_generic_shmoo : run() :read nominal values "); rc=get_all_noms(i_target);if(rc) return rc; + rc=schmoo_setup_mcb(i_target);if(rc) return rc; //Find RIGHT BOUND OR SETUP BOUND rc=find_bound(i_target,RIGHT);if(rc) return rc; //Find LEFT BOUND OR HOLD BOUND rc=find_bound(i_target,LEFT);if(rc) return rc; - //Find the margins in Ps i.e setup margin ,hold margin,Eye width + //Find the margins in Ps i.e setup margin ,hold margin,Eye width rc=get_margin(i_target);if(rc) return rc; //It is used to find the lowest of setup and hold margin rc=get_min_margin(i_target,o_right_min_margin,o_left_min_margin);if(rc) return rc; @@ -261,94 +268,33 @@ fapi::ReturnCode generic_shmoo::run(const fapi::Target & i_target,uint32_t *o_ri * Function: sanity_check * Description : do intial mcbist check in nominal and report spd if any bad bit found * - * Parameters: i_target: mba; + * Parameters: i_target: mba; * ---------------------------------------------------------------------------*/ fapi::ReturnCode generic_shmoo::sanity_check(const fapi::Target & i_target){ fapi:: ReturnCode rc; mcbist_mode=QUARTER_SLOW; uint8_t l_mcb_status=0; - uint8_t l_rank = 0; + uint64_t l_time = 0x0000000000000000ull; uint8_t l_rank_valid = 0; - uint8_t l_byte = 0; - uint8_t l_nibble = 0; - uint8_t __attribute__((unused)) l_socket =0; // HACK - uint32_t rc_num = 0; - uint8_t __attribute__((unused)) l_dqBitmap[DIMM_DQ_RANK_BITMAP_SIZE]; // HACK - uint64_t l_original_start_address1 = 0x0000000000000000; - uint64_t l_original_end_address1 = 0x0000000000000000; - uint64_t l_original_start_address2 = 0x0000000000000000; - uint64_t l_original_end_address2 = 0x0000000000000000; - uint64_t l_start =0x0000000000000000ull; - uint64_t l_end = 0x0000000000000000ull; - uint64_t l_time = 0x0000000000000000ull; - ecmdDataBufferBase l_data_bufferx1_64(64); - ecmdDataBufferBase l_data_bufferx2_64(64); - ecmdDataBufferBase l_data_bufferx3_64(64); - ecmdDataBufferBase l_data_bufferx4_64(64); - - rc = fapiGetScom(i_target,MBA01_MCBIST_MCBSSARA0Q_0x030106d0,l_data_bufferx1_64); if(rc) return rc; - rc = fapiGetScom(i_target,MBA01_MCBIST_MCBSEARA0Q_0x030106d2,l_data_bufferx2_64); if(rc) return rc; - rc = fapiGetScom(i_target,MBA01_MCBIST_MCBSSARA1Q_0x030106d1,l_data_bufferx3_64); if(rc) return rc; - rc = fapiGetScom(i_target,MBA01_MCBIST_MCBSEARA1Q_0x030106d3,l_data_bufferx4_64); if(rc) return rc; - l_original_start_address1 = l_data_bufferx1_64.getDoubleWord (0); - l_original_end_address1 = l_data_bufferx2_64.getDoubleWord (0); - l_original_start_address2 = l_data_bufferx3_64.getDoubleWord (0); - l_original_end_address2 = l_data_bufferx4_64.getDoubleWord (0); - for(l_rank = 0; l_rank < iv_MAX_RANKS; l_rank++) - { - l_rank_valid=valid_rank[l_rank]; - - if(l_rank_valid<MAX_RANK_DIMM) - { - l_socket=0; - } - else - { - l_socket=1; - } + + + FAPI_INF(" entering set_up mcbist now and rank %d",l_rank_valid); - - rc = setup_mcbist(i_target, iv_port, MCBIST_2D_CUP_PAT8, CENSHMOO, UNMASK_ALL, 0,iv_pattern,iv_test_type,l_rank_valid,0,l_start,l_end);if(rc) return rc; //send shmoo mode to vary the address range - + + //rc = setup_mcbist(i_target, 0, MCBIST_2D_CUP_PAT8, CENSHMOO, UNMASK_ALL, 0,iv_pattern,iv_test_type,l_rank_valid,0,l_start,l_end,0);if(rc) return rc; //send shmoo mode to vary the address range + rc=schmoo_setup_mcb(i_target);if(rc) return rc; FAPI_INF(" starting mcbist now"); rc=start_mcb(i_target);if(rc) return rc; FAPI_INF(" polling mcbist now"); rc=poll_mcb(i_target,false,&l_mcb_status,l_time);if(rc) return rc; FAPI_INF(" checking error map "); - rc=mcb_error_map(i_target,mcbist_error_map,iv_port,l_rank_valid);if(rc) return rc; - for(l_byte = 0; l_byte < iv_MAX_BYTES; l_byte++) - { - for(l_nibble = 0; l_nibble < MAX_NIBBLES; l_nibble++) - { - if(mcbist_error_map[iv_port][l_rank_valid][l_byte][l_nibble] == 1) - { - if(l_nibble == 0) - { - l_dqBitmap[l_byte] = 0xf0; - } - else - { - l_dqBitmap[l_byte] = 0x0f; - } - //rc = dimmSetBadDqBitmap(i_target,iv_port,l_socket, l_rank_valid, l_dqBitmap);if(rc) return rc; - } - } - } - rc_num = l_data_bufferx1_64.setDoubleWord(0,l_original_start_address1);if (rc_num){FAPI_ERR( "Error in function sanity_check:");rc.setEcmdError(rc_num);return rc;} - rc_num = l_data_bufferx2_64.setDoubleWord(0,l_original_end_address1);if (rc_num){FAPI_ERR( "Error in function sanity_check:");rc.setEcmdError(rc_num);return rc;} - rc_num = l_data_bufferx3_64.setDoubleWord(0,l_original_start_address2);if (rc_num){FAPI_ERR( "Error in function sanity_check:");rc.setEcmdError(rc_num);return rc;} - rc_num = l_data_bufferx4_64.setDoubleWord(0,l_original_end_address2);if (rc_num){FAPI_ERR( "Error in function sanity_check:");rc.setEcmdError(rc_num);return rc;} - rc = fapiPutScom(i_target,MBA01_MCBIST_MCBSSARA0Q_0x030106d0,l_data_bufferx1_64); if(rc) return rc; - rc = fapiPutScom(i_target,MBA01_MCBIST_MCBSEARA0Q_0x030106d2,l_data_bufferx2_64); if(rc) return rc; - rc = fapiPutScom(i_target,MBA01_MCBIST_MCBSSARA1Q_0x030106d1,l_data_bufferx3_64); if(rc) return rc; - rc = fapiPutScom(i_target,MBA01_MCBIST_MCBSEARA1Q_0x030106d3,l_data_bufferx4_64); if(rc) return rc; - - } - + rc=mcb_error_map(i_target,mcbist_error_map,0,l_rank_valid);if(rc) return rc; + + if(l_mcb_status) { FAPI_ERR("generic_shmoo:sanity_check failed !! MCBIST failed on intial run , memory is not in good state aborting shmoo"); - FAPI_SET_HWP_ERROR(rc,RC_MSS_MCBIST_ERROR); + FAPI_SET_HWP_ERROR(rc,RC_MSS_MCBIST_ERROR); return rc; } @@ -358,116 +304,180 @@ fapi::ReturnCode generic_shmoo::sanity_check(const fapi::Target & i_target){ * Function: do_mcbist_test * Description : do mcbist check for error on particular nibble * - * Parameters: i_target: mba,iv_port 0/1 , rank 0-7 , byte 0-7, nibble 0/1, pass; + * Parameters: i_target: mba,iv_port 0/1 , rank 0-7 , byte 0-7, nibble 0/1, pass; * ---------------------------------------------------------------------------*/ -fapi::ReturnCode generic_shmoo::do_mcbist_test(const fapi::Target & i_target,uint8_t i_rank,uint8_t i_byte,uint8_t i_nibble,uint8_t &pass) +fapi::ReturnCode generic_shmoo::do_mcbist_test(const fapi::Target & i_target) { - mcbist_mode=QUARTER_SLOW; - uint8_t __attribute__((unused)) l_socket=0; // HACK - uint8_t l_mcb_status=0; - input_type l_input_type_e = ISDIMM_DQ; - uint8_t i_input_index_u8=0; - uint8_t l_val =0; + fapi::ReturnCode rc; + uint64_t l_time = 0x0000000000000000ull; uint32_t rc_num =0; - fapi::ReturnCode rc; - uint64_t l_original_start_address1 = 0x0000000000000000; - uint64_t l_original_end_address1 = 0x0000000000000000; - uint64_t l_original_start_address2 = 0x0000000000000000; - uint64_t l_original_end_address2 = 0x0000000000000000; - ecmdDataBufferBase l_data_bufferx1_64(64); - ecmdDataBufferBase l_data_bufferx2_64(64); - ecmdDataBufferBase l_data_bufferx3_64(64); - ecmdDataBufferBase l_data_bufferx4_64(64); - uint64_t l_start =0x0000000000000000ull; - uint64_t l_end = 0x0000000000000000ull; - uint64_t l_time = 0x0000000000000000ull; - rc = fapiGetScom(i_target,MBA01_MCBIST_MCBSSARA0Q_0x030106d0,l_data_bufferx1_64); if(rc) return rc; - rc = fapiGetScom(i_target,MBA01_MCBIST_MCBSEARA0Q_0x030106d2,l_data_bufferx2_64); if(rc) return rc; - rc = fapiGetScom(i_target,MBA01_MCBIST_MCBSSARA1Q_0x030106d1,l_data_bufferx3_64); if(rc) return rc; - rc = fapiGetScom(i_target,MBA01_MCBIST_MCBSEARA1Q_0x030106d3,l_data_bufferx4_64); if(rc) return rc; - l_original_start_address1 = l_data_bufferx1_64.getDoubleWord (0); - l_original_end_address1 = l_data_bufferx2_64.getDoubleWord (0); - l_original_start_address2 = l_data_bufferx3_64.getDoubleWord (0); - l_original_end_address2 = l_data_bufferx4_64.getDoubleWord (0); - - if(i_rank<4) - { - l_socket=0; - } - else - { - l_socket=1; - } - - - - rc = setup_mcbist(i_target, iv_port, ABLE_FIVE, CENSHMOO, UNMASK_ALL, 0,iv_pattern,iv_test_type,i_rank,0,l_start,l_end);if(rc) return rc; //send shmoo mode to vary the address range - + uint8_t l_mcb_status=0; + ecmdDataBufferBase l_data_buffer_64(64); + rc_num = l_data_buffer_64.flushTo0();if (rc_num){FAPI_ERR( "Error in function mcb_reset_trap:");rc.setEcmdError(rc_num);return rc;} + //PORT - A + rc = fapiPutScom(i_target,MBS_MCBIST01_MCBEMA1Q_0x0201166a,l_data_buffer_64); if(rc) return(rc); + rc = fapiPutScom(i_target,MBS_MCBIST01_MCBEMA2Q_0x0201166b,l_data_buffer_64); if(rc) return(rc); + rc = fapiPutScom(i_target,MBS_MCBIST01_MCBEMA3Q_0x0201166c,l_data_buffer_64); if(rc) return(rc); + + //PORT - B + rc = fapiPutScom(i_target,MBS_MCBIST01_MCBEMB1Q_0x0201166d,l_data_buffer_64); if(rc) return(rc); + rc = fapiPutScom(i_target,MBS_MCBIST01_MCBEMB2Q_0x0201166e,l_data_buffer_64); if(rc) return(rc); + rc = fapiPutScom(i_target,MBS_MCBIST01_MCBEMB3Q_0x0201166f,l_data_buffer_64); if(rc) return(rc); + + // MBS 23 + rc = fapiPutScom(i_target,0x0201176a,l_data_buffer_64); if(rc) return(rc); + rc = fapiPutScom(i_target,0x0201176b,l_data_buffer_64); if(rc) return(rc); + rc = fapiPutScom(i_target,0x0201176c,l_data_buffer_64); if(rc) return(rc); + + //PORT - B + rc = fapiPutScom(i_target,0x0201176d,l_data_buffer_64); if(rc) return(rc); + rc = fapiPutScom(i_target,0x0201176e,l_data_buffer_64); if(rc) return(rc); + rc = fapiPutScom(i_target,0x0201176f,l_data_buffer_64); if(rc) return(rc); + rc = start_mcb(i_target); if(rc) { - FAPI_ERR("generic_shmoo::do_mcbist_test: Start MCBIST failed !!"); - + FAPI_ERR("generic_shmoo::do_mcbist_test: Start MCBIST failed !!"); + return rc; } rc=poll_mcb(i_target,false,&l_mcb_status,l_time); if(rc) { - FAPI_ERR("generic_shmoo::do_mcbist_test: POLL MCBIST failed !!"); - + FAPI_ERR("generic_shmoo::do_mcbist_test: POLL MCBIST failed !!"); + return rc; } - rc=mcb_error_map(i_target,mcbist_error_map,iv_port,i_rank); + //FAPI_INF("\n abhijit is here 1 \n"); + return rc; + +} +/*------------------------------------------------------------------------------ + * Function: check_error_map + * Description : used by do_mcbist_test to check the error map for particular nibble + * + * Parameters: iv_port 0/1 , rank 0-7 , byte 0-7, nibble 0/1, pass; + * ---------------------------------------------------------------------------*/ +fapi::ReturnCode generic_shmoo::check_error_map(const fapi::Target & i_target,uint8_t port,uint8_t &pass) +{ + + fapi::ReturnCode rc; + uint8_t l_byte,l_rnk; + uint8_t l_nibble; + uint8_t l_byte_is; + uint8_t l_nibble_is; + uint8_t l_n=0; + pass=1; + uint8_t l_p=0; + input_type l_input_type_e = ISDIMM_DQ; + uint8_t i_input_index_u8=0; + uint8_t l_val =0; + uint8_t i_rp=0; + uint8_t rank=0; + uint8_t l_max_byte=10; + uint8_t l_max_nibble=20; + + if(iv_dmm_type==1) + { + l_max_byte=9; + l_max_nibble=18; + } + + // rc=mcb_error_map(i_target,mcbist_error_map,port,i_rank); + // if(rc) + // { + // FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); + + // return rc; + // } + + + for (l_p=0;l_p<MAX_PORT;l_p++){ + for (l_rnk=0;l_rnk<iv_MAX_RANKS[l_p];++l_rnk) + {// Byte loop + rc = mss_getrankpair(i_target,l_p,0,&i_rp,valid_rank);if(rc) return rc; + rank=valid_rank[l_rnk]; + rc=mcb_error_map(i_target,mcbist_error_map,port,rank); if(rc) { - FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); - + FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); + return rc; } - rc_num = l_data_bufferx1_64.setDoubleWord(0,l_original_start_address1);if (rc_num){FAPI_ERR( "Error in function do_mcbist_test:");rc.setEcmdError(rc_num);return rc;} - rc_num = l_data_bufferx2_64.setDoubleWord(0,l_original_end_address1);if (rc_num){FAPI_ERR( "Error in function do_mcbist_test:");rc.setEcmdError(rc_num);return rc;} - rc_num = l_data_bufferx3_64.setDoubleWord(0,l_original_start_address2);if (rc_num){FAPI_ERR( "Error in function do_mcbist_test:");rc.setEcmdError(rc_num);return rc;} - rc_num = l_data_bufferx4_64.setDoubleWord(0,l_original_end_address2);if (rc_num){FAPI_ERR( "Error in function do_mcbist_test:");rc.setEcmdError(rc_num);return rc;} - rc = fapiPutScom(i_target,MBA01_MCBIST_MCBSSARA0Q_0x030106d0,l_data_bufferx1_64); if(rc) return rc; - rc = fapiPutScom(i_target,MBA01_MCBIST_MCBSEARA0Q_0x030106d2,l_data_bufferx2_64); if(rc) return rc; - rc = fapiPutScom(i_target,MBA01_MCBIST_MCBSSARA1Q_0x030106d1,l_data_bufferx3_64); if(rc) return rc; - rc = fapiPutScom(i_target,MBA01_MCBIST_MCBSEARA1Q_0x030106d3,l_data_bufferx4_64); if(rc) return rc; - + l_n=0; + for(l_byte=0;l_byte<l_max_byte;++l_byte) + { + // if(l_byte==9){ + // if(iv_dmm_type==1) + // { + // continue; + // } + // } + //Nibble loop + for(l_nibble=0;l_nibble< MAX_NIBBLES;++l_nibble) + { if(iv_dmm_type==1) { - i_input_index_u8=8*i_byte+4*i_nibble; - rc=rosetta_map(i_target,iv_port,l_input_type_e,i_input_index_u8,0,l_val);if(rc) return rc; - i_byte=l_val/8; - i_nibble=l_val%4; - check_error_map(i_rank,i_byte,i_nibble,pass); - + i_input_index_u8=8*l_byte+4*l_nibble; + //FAPI_INF("\n ISDIMM input byte=%d and nibble=%d and bit returned is %d \n",l_byte,l_nibble,l_val); + rc=rosetta_map(i_target,l_p,l_input_type_e,i_input_index_u8,0,l_val);if(rc) return rc; + //FAPI_INF("\n ISDIMM input byte=%d and nibble=%d and bit returned is %d \n",l_byte,l_nibble,l_val); + l_byte_is=l_val/8; + + l_nibble_is=l_val%8; + if(l_nibble_is>3){ + l_nibble_is=1; + }else{ + l_nibble_is=0; + } + //FAPI_INF("\n the final byte and nibble is %d and %d for rank=%d \n",l_byte_is,l_nibble_is,i_rank); + if( mcbist_error_map [l_p][l_rnk][l_byte_is][l_nibble_is] == 1){ + //pass=0; + schmoo_error_map[l_p][rank][l_n]=1; + //FAPI_INF("We are in error and nibble is %d and rank is %d and port is %d \n",l_n,rank,l_p); } else { - check_error_map(i_rank,i_byte,i_nibble,pass); - + //schmoo_error_map[l_p][rank][l_n]=0; + //pass=0; + //FAPI_INF("We are in error2"); } - return rc; -} -/*------------------------------------------------------------------------------ - * Function: check_error_map - * Description : used by do_mcbist_test to check the error map for particular nibble - * - * Parameters: iv_port 0/1 , rank 0-7 , byte 0-7, nibble 0/1, pass; - * ---------------------------------------------------------------------------*/ -void generic_shmoo::check_error_map(uint8_t i_rank,uint8_t i_byte,uint8_t i_nibble,uint8_t &pass) -{ - - if( mcbist_error_map [iv_port][i_rank][i_byte][i_nibble] == 1){ - pass=0; - // FAPI_INF("We are in error1"); + + } else { + + + if( mcbist_error_map [l_p][l_rnk][l_byte][l_nibble] == 1){ + //pass=0; + schmoo_error_map[l_p][rank][l_n]=1; + //FAPI_INF("We are in error and nibble is %d and rank is %d and port is %d \n",l_n,rank,l_p); } else { - pass=1; + //schmoo_error_map[l_p][rank][l_n]=0; + //pass=0; //FAPI_INF("We are in error2"); } - + } + l_n++; + } + } + } + } + for (l_p=0;l_p<MAX_PORT;l_p++){ + for (l_rnk=0;l_rnk<iv_MAX_RANKS[l_p];++l_rnk) + {// Byte loop + rc = mss_getrankpair(i_target,l_p,0,&i_rp,valid_rank);if(rc) return rc; + rank=valid_rank[l_rnk]; + for (l_n=0; l_n<l_max_nibble;l_n++){ + if(schmoo_error_map[l_p][rank][l_n]==0){ + //FAPI_INF("\n the port=%d and nibble=%d and value for error map =%d \n",l_p,l_n,schmoo_error_map[l_p][rank][l_n]); + pass=0; + } + + } + } + } + return rc; } /*------------------------------------------------------------------------------ * Function: init_multi_array @@ -477,22 +487,22 @@ void generic_shmoo::check_error_map(uint8_t i_rank,uint8_t i_byte,uint8_t i_nib * ---------------------------------------------------------------------------*/ void generic_shmoo::init_multi_array(uint32_t (&array)[MAX_DQ][MAX_RPS],uint32_t init_val) { - + uint8_t l_byte,l_nibble,l_bit,l_rp; uint8_t l_dq=0; for (l_rp=0;l_rp<MAX_RPS;++l_rp) {// Byte loop - + for(l_byte=0;l_byte<iv_MAX_BYTES;++l_byte) { //Nibble loop for(l_nibble=0;l_nibble< MAX_NIBBLES;++l_nibble) - { + { //Bit loop for(l_bit=0;l_bit<MAX_BITS;++l_bit) - { + { l_dq=8*l_byte+4*l_nibble+l_bit; array[l_dq][l_rp]=init_val; - } + } } } } @@ -511,17 +521,17 @@ fapi::ReturnCode generic_shmoo::init_multi_array_dqs(uint32_t (&array)[MAX_DQ][M uint8_t l_dq=0; for (l_rp=0;l_rp<MAX_RPS;++l_rp) {// Byte loop - + for(l_byte=0;l_byte<iv_MAX_BYTES;++l_byte) { //Nibble loop for(l_nibble=0;l_nibble< MAX_NIBBLES;++l_nibble) - { + { //Bit loop for(l_bit=0;l_bit<MAX_BITS;++l_bit) - { + { l_dq=8*l_byte+4*l_nibble+l_bit; array[l_dq][l_rp]=init_val; - } + } } } } @@ -529,65 +539,68 @@ return rc; } /*------------------------------------------------------------------------------ * Function: get_all_noms - * Description : This function gets the nominal values for each DQ + * Description : This function gets the nominal values for each DQ * - * Parameters: Target:MBA + * Parameters: Target:MBA * ---------------------------------------------------------------------------*/ fapi::ReturnCode generic_shmoo::get_all_noms(const fapi::Target & i_target) { fapi::ReturnCode rc; - + uint8_t l_rnk,l_byte,l_nibble,l_bit; uint8_t i_rnk=0; uint8_t i_rp=0; uint32_t val=0; uint8_t l_dq=0; - + uint8_t l_p=0; + input_type_t l_input_type_e = WR_DQ; access_type_t l_access_type_e = READ ; FAPI_DBG("mss_generic_shmoo : get_all_noms : Reading in all nominal values"); - - + + if(iv_shmoo_type == 1) - { + { l_input_type_e = WR_DQS; - + } else if(iv_shmoo_type == 2) - { - + { + l_input_type_e = RD_DQ; - + } else if(iv_shmoo_type == 3) - { - + { + l_input_type_e = RD_DQS; - + } - - - for (l_rnk=0;l_rnk<iv_MAX_RANKS;++l_rnk) + + for (l_p=0;l_p<MAX_PORT;l_p++){ + for (l_rnk=0;l_rnk<iv_MAX_RANKS[l_p];++l_rnk) {// Byte loop + rc = mss_getrankpair(i_target,l_p,0,&i_rp,valid_rank);if(rc) return rc; i_rnk=valid_rank[l_rnk]; - rc = mss_getrankpair(i_target,iv_port,i_rnk,&i_rp,valid_rank);if(rc) return rc; + rc = mss_getrankpair(i_target,l_p,i_rnk,&i_rp,valid_rank);if(rc) return rc; for(l_byte=0;l_byte<iv_MAX_BYTES;++l_byte) { //Nibble loop for(l_nibble=0;l_nibble< MAX_NIBBLES;++l_nibble) - { + { //Bit loop for(l_bit=0;l_bit<MAX_BITS;++l_bit) - { + { l_dq=8*l_byte+4*l_nibble+l_bit; - - rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,i_rnk,l_input_type_e,l_dq,0,val);if(rc) return rc; - SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rnk].K.nom_val[l_dq][i_rp]=val; - FAPI_INF("Nominal Value for rank=%d and rank pair=%d and dq=%d is %d",i_rnk,i_rp,l_dq,val); - + + rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,i_rnk,l_input_type_e,l_dq,0,val);if(rc) return rc; + SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rnk].K.nom_val[l_dq][i_rp]=val; + FAPI_INF("Nominal Value for port=%d rank=%d and rank pair=%d and dq=%d is %d",l_p,i_rnk,i_rp,l_dq,val); + } } } } +} return rc; } @@ -597,251 +610,204 @@ fapi::ReturnCode generic_shmoo::get_all_noms(const fapi::Target & i_target) * * Parameters: Target:MBA,bound:RIGHT/LEFT,scenario:type of schmoo,iv_port:0/1,rank:0-7,byte:0-7,nibble:0/1,bit:0-3,pass, * ---------------------------------------------------------------------------*/ -fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t rank,uint8_t byte,uint8_t nibble,uint8_t bit,uint8_t pass,bool &flag) -{ +fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag) +{ fapi::ReturnCode rc; ecmdDataBufferBase data_buffer_64(64); ecmdDataBufferBase data_buffer_64_1(64); - uint32_t l_current_val=0; - uint32_t l_left_del=1; - uint32_t l_right_del=1; - uint32_t l_max_value=0; - uint32_t l_min_value=0; - uint16_t l_nibb_err_chk=2*byte+nibble; - uint32_t l_rd_cnt_A=0; - uint32_t l_rd_cnt_B=0; - uint32_t l_err_cnt_C=0; - uint32_t l_start_bit=0; - uint32_t rc_ecmd; - uint32_t l_length_buffer=7; - uint32_t l_delta=0; - uint32_t l_err_prblty=0; + + + uint8_t l_rp=0; input_type_t l_input_type_e = WR_DQ; uint8_t l_dq=0; access_type_t l_access_type_e = WRITE; - - - - l_dq=8*byte+4*nibble+bit; - - rc = mss_getrankpair(i_target,iv_port,rank,&l_rp,valid_rank);if(rc) return rc; - - + uint8_t l_n=0; + + uint8_t l_p=0; + uint16_t l_delay=0; + uint32_t __attribute__((unused)) l_max=0; //SW198827 + uint16_t l_max_limit=500; + uint8_t rank=0; + uint8_t l_rank=0; + uint8_t l_SCHMOO_NIBBLES=20; + uint8_t i_rp=0; + + if(iv_dmm_type==1) + { + l_SCHMOO_NIBBLES=18; + } + //rc = mss_getrankpair(i_target,iv_port,rank,&l_rp,valid_rank);if(rc) return rc; + + for (l_p=0;l_p<MAX_PORT;l_p++){ + for(int i=0;i<iv_MAX_RANKS[l_p];i++){ + rc = mss_getrankpair(i_target,l_p,0,&i_rp,valid_rank);if(rc) return rc; + rank=valid_rank[i]; + for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){ + schmoo_error_map[l_p][rank][l_n]=0; + } + } + } + if(scenario == 2) { l_input_type_e = RD_DQ; + l_max_limit=127; } - - - if(bound==LEFT) + + + if(bound==RIGHT) { - + if(algorithm==SEQ_LIN) { - l_min_value=SHMOO[scenario].static_knob.min_val; - for(l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp];((l_current_val >= l_left_del)&&(pass==1));l_current_val-=l_left_del) - { - FAPI_INF(" The current value inside left bound for dq=%d and rp=%d is %d ",l_dq,l_rp,l_current_val); - rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,1,l_current_val);if(rc) return rc; - rc=do_mcbist_test(i_target,rank,byte,nibble,pass); + + + for (l_delay=1;((pass==0));l_delay++){ + + for (l_p=0;l_p<MAX_PORT;l_p++){ + for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank) + { + l_dq=bit; + rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc; + rank=valid_rank[l_rank]; + rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc; + for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){ + + if(schmoo_error_map[l_p][rank][l_n]==0){ + + SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]+l_delay; + + FAPI_INF("\n value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]); + rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]);if(rc) return rc; + + } + + if(SHMOO[scenario].MBA.P[l_p].S[rank].K.rb_regval[l_dq][l_rp]>l_max_limit){ + schmoo_error_map[l_p][rank][l_n]=1; + } + + l_dq=l_dq+4; + + } + + + } + + } + rc=do_mcbist_test(i_target); if(rc) - { + { FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); return rc; } - } - if(flag) - { - pass=1; - for(l_current_val=l_current_val+10;((l_current_val>l_min_value)&&(pass==1));l_current_val--) - { - rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc; - rc = fapiGetScom(i_target,MBA01_MBA_PMU0Q_0x03010437,data_buffer_64); if(rc) return rc; - l_rd_cnt_A = data_buffer_64.getDoubleWord(0); - do - { - rc = fapiGetScom(i_target,MBA01_MBA_PMU0Q_0x03010437,data_buffer_64); if(rc) return rc; - l_rd_cnt_B = data_buffer_64.getDoubleWord(0); - if(iv_port==0) - { - if(l_nibb_err_chk<9) - { - rc = fapiGetScom(i_target,MBS_MCBIST01_MCB_ERRCNTA1Q_0x02011664,data_buffer_64_1); if(rc) return rc; - l_start_bit=l_nibb_err_chk*7; - rc_ecmd=data_buffer_64.extractToRight(&l_err_cnt_C,l_start_bit,l_length_buffer);if (rc_ecmd){ rc.setEcmdError(rc_ecmd); return rc;} - } - else - { - rc = fapiGetScom(i_target,MBS_MCBIST01_MCB_ERRCNTA2Q_0x02011665,data_buffer_64_1); if(rc) return rc; - l_nibb_err_chk=l_nibb_err_chk-9; - l_start_bit=l_nibb_err_chk*7; - rc_ecmd=data_buffer_64.extractToRight(&l_err_cnt_C,l_start_bit,l_length_buffer);if (rc_ecmd){ rc.setEcmdError(rc_ecmd); return rc;} - } - } - else - { - if(l_nibb_err_chk<9) - { - rc = fapiGetScom(i_target,MBS_MCBIST01_MCB_ERRCNTB1Q_0x02011667,data_buffer_64_1); if(rc) return rc; - l_start_bit=l_nibb_err_chk*7; - rc_ecmd=data_buffer_64.extractToRight(&l_err_cnt_C,l_start_bit,l_length_buffer);if (rc_ecmd){ rc.setEcmdError(rc_ecmd); return rc;} - } - else - { - rc = fapiGetScom(i_target,MBS_MCBIST01_MCB_ERRCNTB2Q_0x02011668,data_buffer_64_1); if(rc) return rc; - l_nibb_err_chk=l_nibb_err_chk-9; - l_start_bit=l_nibb_err_chk*7; - rc_ecmd=data_buffer_64.extractToRight(&l_err_cnt_C,l_start_bit,l_length_buffer);if (rc_ecmd){ rc.setEcmdError(rc_ecmd); return rc;} - } - } - if(l_rd_cnt_A>l_rd_cnt_B) - { - l_delta=l_rd_cnt_A-l_rd_cnt_B; - } - else - { - l_delta=l_rd_cnt_B-l_rd_cnt_A; - } - if(l_delta>read_counter_threshold) - { - l_err_prblty=l_err_cnt_C*read_counter_threshold; - l_err_prblty=l_err_prblty/l_delta; - if(l_err_prblty>error_threshold_count) - { - pass=0; - } - else - { - pass=1; - } - } - }while(l_delta<read_counter_threshold); - if(!pass) - { - SHMOO[scenario].MBA.P[iv_port].S[rank].K.lb_regval[l_dq][l_rp]=l_current_val; - } + + rc=check_error_map(i_target,l_p,pass); + if(rc) + { + FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); + return rc; + } + + } + + + for (l_p=0;l_p<MAX_PORT;l_p++){ + for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank) + { + l_dq=bit; + rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc; + rank=valid_rank[l_rank]; + rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc; + for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){ + rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]);if(rc) return rc; + l_dq=l_dq+4; + } } - } - - SHMOO[scenario].MBA.P[iv_port].S[rank].K.lb_regval[l_dq][l_rp]=l_current_val+l_left_del; - - - l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp]; - FAPI_INF(" the restoring nominal value for rank=%d dq=%d and rp=%d is %d",rank,l_dq,l_rp,l_current_val); - rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc; + } + } + } - } - if(bound==RIGHT) + + if(bound==LEFT) { if(algorithm==SEQ_LIN) { - l_max_value=SHMOO[scenario].static_knob.max_val; - for(l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp];((l_current_val<l_max_value)&&(pass==1));l_current_val+=l_right_del) - { - FAPI_INF(" The current value inside right bound dq=%d and rp=%d is %d ",l_dq,l_rp,l_current_val); - rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,1,l_current_val);if(rc) return rc; - rc=do_mcbist_test(i_target,rank,byte,nibble,pass); + + for (l_delay=1;(pass==0);l_delay++){ + + for (l_p=0;l_p<MAX_PORT;l_p++){ + for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank) + { + l_dq=bit; + rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc; + rank=valid_rank[l_rank]; + rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc; + for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){ + + l_max=SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]; + + + if(schmoo_error_map[l_p][rank][l_n]==0){ + SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]=SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]-l_delay; + //l_max=SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]; + FAPI_INF("\n left value of delay rank=%d for port=%d bit=%d is %d ",rank,l_p,l_dq,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]); + rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp]);if(rc) return rc; + + } + if(SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp] == 0){ + schmoo_error_map[l_p][rank][l_n] = 1; + } + + l_dq=l_dq+4; + + } + } + + } + rc=do_mcbist_test(i_target); if(rc) - { + { FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); return rc; } - } - - if(flag) - { - pass=1; - for(l_current_val=l_current_val-20;((l_current_val<l_max_value)&&(pass==1));l_current_val++) - { - rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc; - rc = fapiGetScom(i_target,MBA01_MBA_PMU0Q_0x03010437,data_buffer_64); if(rc) return rc; - l_rd_cnt_A = data_buffer_64.getDoubleWord(0); - do - { - rc = fapiGetScom(i_target,MBA01_MBA_PMU0Q_0x03010437,data_buffer_64); if(rc) return rc; - l_rd_cnt_B = data_buffer_64.getDoubleWord(0); - if(iv_port==0) - { - if(l_nibb_err_chk<9) - { - rc = fapiGetScom(i_target,MBS_MCBIST01_MCB_ERRCNTA1Q_0x02011664,data_buffer_64_1); if(rc) return rc; - l_start_bit=l_nibb_err_chk*7; - rc_ecmd=data_buffer_64.extractToRight(&l_err_cnt_C,l_start_bit,l_length_buffer);if (rc_ecmd){ rc.setEcmdError(rc_ecmd); return rc;} - } - else - { - rc = fapiGetScom(i_target,MBS_MCBIST01_MCB_ERRCNTA2Q_0x02011665,data_buffer_64_1); if(rc) return rc; - l_nibb_err_chk=l_nibb_err_chk-9; - l_start_bit=l_nibb_err_chk*7; - rc_ecmd=data_buffer_64.extractToRight(&l_err_cnt_C,l_start_bit,l_length_buffer);if (rc_ecmd){ rc.setEcmdError(rc_ecmd); return rc;} - } - } - else - { - if(l_nibb_err_chk<9) - { - rc = fapiGetScom(i_target,MBS_MCBIST01_MCB_ERRCNTB1Q_0x02011667,data_buffer_64_1); if(rc) return rc; - l_start_bit=l_nibb_err_chk*7; - rc_ecmd=data_buffer_64.extractToRight(&l_err_cnt_C,l_start_bit,l_length_buffer);if (rc_ecmd){ rc.setEcmdError(rc_ecmd); return rc;} - } - else - { - rc = fapiGetScom(i_target,MBS_MCBIST01_MCB_ERRCNTB2Q_0x02011668,data_buffer_64_1); if(rc) return rc; - l_nibb_err_chk=l_nibb_err_chk-9; - l_start_bit=l_nibb_err_chk*7; - rc_ecmd=data_buffer_64.extractToRight(&l_err_cnt_C,l_start_bit,l_length_buffer);if (rc_ecmd){ rc.setEcmdError(rc_ecmd); return rc;} - } - } - if(l_rd_cnt_A>l_rd_cnt_B) - { - l_delta=l_rd_cnt_A-l_rd_cnt_B; - } - else - { - l_delta=l_rd_cnt_B-l_rd_cnt_A; - } - if(l_delta>read_counter_threshold) - { - l_err_prblty=l_err_cnt_C*read_counter_threshold; - l_err_prblty=l_err_prblty/l_delta; - if(l_err_prblty>error_threshold_count) - { - pass=0; - } - else - { - pass=1; - } - } - }while(l_delta<read_counter_threshold); - if(!pass) - { - SHMOO[scenario].MBA.P[iv_port].S[rank].K.rb_regval[l_dq][l_rp]=l_current_val; - } - else - { - SHMOO[scenario].MBA.P[iv_port].S[rank].K.rb_regval[l_dq][l_rp]=l_current_val-l_right_del; - } + +rc=check_error_map(i_target,l_p,pass); + if(rc) + { + FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); + return rc; + } + + + } + + + for (l_p=0;l_p<MAX_PORT;l_p++){ + for (l_rank=0;l_rank<iv_MAX_RANKS[l_p];++l_rank) + { + l_dq=bit; + rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc; + rank=valid_rank[l_rank]; + rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc; + for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){ + rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[scenario].MBA.P[l_p].S[rank].K.nom_val[l_dq][l_rp]);if(rc) return rc; + l_dq=l_dq+4; + } } - } - - SHMOO[scenario].MBA.P[iv_port].S[rank].K.rb_regval[l_dq][l_rp]=l_current_val-l_right_del; - - FAPI_INF(" the right bound for dq=%d is %d ",l_dq,SHMOO[scenario].MBA.P[iv_port].S[rank].K.rb_regval[l_dq][l_rp]); - l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp]; - FAPI_INF(" the restoring nominal value for rank=%d dq=%d and rp=%d is %d",rank,l_dq,l_rp,l_current_val); - rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc; - + } + } + + } - } - return rc; + + return rc; } /*------------------------------------------------------------------------------ * Function: knob_update_dqs * Description : This is a key function is used to find right and left bound using new algorithm -- there is an option u can chose not to use it by setting a flag * * Parameters: Target:MBA,bound:RIGHT/LEFT,scenario:type of schmoo,iv_port:0/1,rank:0-7,byte:0-7,nibble:0/1,bit:0-3,pass, - * ---------------------------------------------------------------------------*/ + * --------------------------------------------------------------------------- fapi::ReturnCode generic_shmoo::knob_update_dqs(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t rank,uint8_t byte,uint8_t nibble,uint8_t bit,uint8_t pass) { fapi::ReturnCode rc; @@ -851,38 +817,38 @@ fapi::ReturnCode generic_shmoo::knob_update_dqs(const fapi::Target & i_target,bo data_buffer_64_1.flushTo0(); uint32_t l_current_val=0; uint32_t l_max_value=0; - uint32_t __attribute__((unused)) l_min_value=0; // HACK - + uint32_t l_min_value=0; + uint8_t l_rp=0; input_type_t l_input_type_e = WR_DQS; uint8_t l_dq=0; access_type_t l_access_type_e = WRITE; - - if(scenario == 1) + + if(scenario == 1) { l_input_type_e = WR_DQS; } - else if(scenario == 3) + else if(scenario == 3) { l_input_type_e = RD_DQS; } - + if(bound==LEFT) { - + if(algorithm==SEQ_LIN) { l_min_value=SHMOO[scenario].static_knob.min_val; FAPI_INF(" curr val in left above = %d and pass=%d ",l_current_val,pass); for(l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp];((l_current_val >= 20)&&(pass==1));l_current_val-=20) { - //use saurabh function for writing here + //use saurabh function for writing here FAPI_INF(" curr val in left = %d and pass=%d ",l_current_val,pass); rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,0,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc; - + rc=do_mcbist_test(i_target,rank,byte,nibble,pass); if(rc) - { + { FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); return rc; } @@ -894,25 +860,25 @@ fapi::ReturnCode generic_shmoo::knob_update_dqs(const fapi::Target & i_target,bo FAPI_INF(" left bound = %d ",SHMOO[scenario].MBA.P[iv_port].S[rank].K.rb_regval[l_dq][l_rp]); l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp]; rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,0,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc; - + } } - + else if(bound==RIGHT) { - + if(algorithm==SEQ_LIN) { l_max_value=SHMOO[scenario].static_knob.max_val; for(l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp];((l_current_val<l_max_value)&&(pass==1));l_current_val+=100) { - //use saurabh function for writing here + //use saurabh function for writing here FAPI_INF(" curr val = %d ",l_current_val); rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,0,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc; - + rc=do_mcbist_test(i_target,rank,byte,nibble,pass); if(rc) - { + { FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); return rc; } @@ -922,15 +888,15 @@ fapi::ReturnCode generic_shmoo::knob_update_dqs(const fapi::Target & i_target,bo SHMOO[scenario].MBA.P[iv_port].S[rank].K.rb_regval[l_dq][l_rp]=l_current_val; } l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp]; - + rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,0,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc; FAPI_INF(" right bound = %d ",SHMOO[scenario].MBA.P[iv_port].S[rank].K.rb_regval[l_dq][l_rp]); } - + } return rc; } - +*/ /*------------------------------------------------------------------------------ * Function: find_bound * Description : This function calls the knob_update for each DQ which is used to find bound that is left/right according to schmoo type @@ -938,56 +904,50 @@ fapi::ReturnCode generic_shmoo::knob_update_dqs(const fapi::Target & i_target,bo * Parameters: Target:MBA,bound:RIGHT/LEFT, * ---------------------------------------------------------------------------*/ fapi::ReturnCode generic_shmoo::find_bound(const fapi::Target & i_target,bound_t bound){ - uint8_t l_rnk,l_byte,l_nibble,l_bit; + uint8_t l_bit; fapi::ReturnCode rc; - - uint8_t i_rank=0; + + + uint8_t pass=0; bool flag=false; - - - + + + FAPI_INF("generic_shmoo::find_bound running find_bound function "); - - - for (l_rnk=0;l_rnk<iv_MAX_RANKS;++l_rnk) - {// Byte loop - i_rank=valid_rank[l_rnk]; - for(l_byte=0;l_byte<iv_MAX_BYTES;++l_byte) - { //Nibble loop - - for(l_nibble=0;l_nibble< MAX_NIBBLES;++l_nibble) - { - + + + + + //Bit loop for(l_bit=0;l_bit< MAX_BITS;++l_bit) { // preetham function here - - - if(iv_DQS_ON==1) - rc=knob_update_dqs(i_target,bound,iv_shmoo_type,i_rank,l_byte,l_nibble,l_bit,1);if(rc) return rc; - else - rc=knob_update(i_target,bound,iv_shmoo_type,i_rank,l_byte,l_nibble,l_bit,1,flag); if(rc) return rc; - } + + pass=0; + //FAPI_INF("\n abhijit is inside find bound 0 \n"); + rc=knob_update(i_target,bound,iv_shmoo_type,l_bit,pass,flag); if(rc) return rc; + } - } - } + + return rc; } //#ifdef char /*------------------------------------------------------------------------------ * Function: print_report - * Description : This function is used to print the information needed such as freq,voltage etc, and also the right,left and total margin + * Description : This function is used to print the information needed such as freq,voltage etc, and also the right,left and total margin * * Parameters: Target:MBA * ---------------------------------------------------------------------------*/ fapi::ReturnCode generic_shmoo::print_report(const fapi::Target & i_target) { fapi::ReturnCode rc; - + uint8_t l_rnk,l_byte,l_nibble,l_bit; uint8_t l_dq=0; uint8_t l_rp=0; + uint8_t l_p=0; uint8_t i_rank=0; uint8_t l_mbapos = 0; uint32_t l_attr_mss_freq_u32 = 0; @@ -996,71 +956,73 @@ fapi::ReturnCode generic_shmoo::print_report(const fapi::Target & i_target) uint8_t l_attr_eff_num_drops_per_port_u8 = 0; uint8_t l_attr_eff_dram_width_u8 = 0; fapi::Target l_target_centaur; - - + + rc = fapiGetParentChip(i_target, l_target_centaur); if(rc) return rc; - + rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_u32); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_attr_mss_volt_u32); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, l_attr_eff_dimm_type_u8); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target, l_attr_eff_num_drops_per_port_u8); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_attr_eff_dram_width_u8); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbapos);if(rc) return rc; - + FAPI_INF(" freq = %d on %s.", l_attr_mss_freq_u32, l_target_centaur.toEcmdString()); FAPI_INF("volt = %d on %s.", l_attr_mss_volt_u32, l_target_centaur.toEcmdString()); FAPI_INF("dimm_type = %d on %s.", l_attr_eff_dimm_type_u8, i_target.toEcmdString()); if ( l_attr_eff_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) { - FAPI_INF("It is a CDIMM"); + FAPI_INF("It is a CDIMM"); } else { - FAPI_INF("It is an ISDIMM"); + FAPI_INF("It is an ISDIMM"); } - FAPI_INF("num_drops_per_port = %d on %s.", l_attr_eff_num_drops_per_port_u8, i_target.toEcmdString()); - FAPI_INF("num_ranks = %d on %s.", iv_MAX_RANKS,i_target.toEcmdString()); - FAPI_INF("dram_width = %d on %s. \n\n", l_attr_eff_dram_width_u8, i_target.toEcmdString()); + //FAPI_INF("num_drops_per_port = %d on %s.", l_attr_eff_num_drops_per_port_u8, i_target.toEcmdString()); + //FAPI_INF("num_ranks = %d on %s.", iv_MAX_RANKS,i_target.toEcmdString()); + //FAPI_INF("dram_width = %d on %s. \n\n", l_attr_eff_dram_width_u8, i_target.toEcmdString()); FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); - FAPI_INF("Schmoo POS\tPort\tRank\tByte\tnibble\tbit\tNominal\t\tSetup_Limit\tHold_Limit\tWrD_Setup(ps)\tWrD_Hold(ps)\tEye_Width(ps)\tBitRate "); - - - - for (l_rnk=0;l_rnk<iv_MAX_RANKS;++l_rnk) - {// Byte loop + FAPI_INF("Schmoo POS\tPort\tRank\tByte\tnibble\tbit\tNominal\t\tSetup_Limit\tHold_Limit\tWrD_Setup(ps)\tWrD_Hold(ps)\tEye_Width(ps)\tBitRate\tVref_Multiplier "); + + + + + for (l_p=0;l_p<MAX_PORT;l_p++){ + for (l_rnk=0;l_rnk<iv_MAX_RANKS[l_p];++l_rnk) + { rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc; i_rank=valid_rank[l_rnk]; - rc = mss_getrankpair(i_target,iv_port,i_rank,&l_rp,valid_rank);if(rc) return rc; + rc = mss_getrankpair(i_target,l_p,i_rank,&l_rp,valid_rank);if(rc) return rc; for(l_byte=0;l_byte<iv_MAX_BYTES;++l_byte) { - + //Nibble loop for(l_nibble=0;l_nibble< MAX_NIBBLES;++l_nibble) { for(l_bit=0;l_bit< MAX_BITS;++l_bit) - { + { l_dq=8*l_byte+4*l_nibble+l_bit; if(iv_shmoo_type==0) { - FAPI_INF("WR_EYE %d\t%d\t%d\t%d\t%d\t%d\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\n ",iv_port,l_mbapos,i_rank,l_byte,l_nibble,l_bit,SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.nom_val[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.rb_regval[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.lb_regval[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.right_margin_val[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.left_margin_val[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.total_margin[l_dq][l_rp],l_attr_mss_freq_u32); + FAPI_INF("WR_EYE %d\t%d\t%d\t%d\t%d\t%d\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\n ",l_mbapos,l_p,i_rank,l_byte,l_nibble,l_bit,SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.nom_val[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.total_margin[l_dq][l_rp],l_attr_mss_freq_u32,iv_shmoo_param); } if(iv_shmoo_type==2) { - FAPI_INF("RD_EYE\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\n ",iv_port,l_mbapos,i_rank,l_byte,l_nibble,l_bit,SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.nom_val[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.rb_regval[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.lb_regval[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.right_margin_val[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.left_margin_val[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.total_margin[l_dq][l_rp],l_attr_mss_freq_u32); + FAPI_INF("RD_EYE %d\t%d\t%d\t%d\t%d\t%d\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\n ",l_mbapos,l_p,i_rank,l_byte,l_nibble,l_bit,SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.nom_val[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.total_margin[l_dq][l_rp],l_attr_mss_freq_u32,iv_shmoo_param); } - + } } } } - - + } + return rc; } //#endif /*------------------------------------------------------------------------------ * Function: get_margin - * Description : This function is used to get margin for setup,hold and total eye width in Ps by using frequency + * Description : This function is used to get margin for setup,hold and total eye width in Ps by using frequency * * Parameters: Target:MBA * ---------------------------------------------------------------------------*/ @@ -1073,95 +1035,240 @@ fapi::ReturnCode generic_shmoo::get_margin(const fapi::Target & i_target) uint64_t l_cyc = 1000000000000000ULL; uint8_t l_dq=0; uint8_t l_rp=0; + uint8_t l_p=0; uint8_t i_rank=0; uint64_t l_factor=0; uint64_t l_factor_ps=1000000000; - + //FAPI_INF(" the factor is % llu ",l_cyc); - + fapi::Target l_target_centaur; rc = fapiGetParentChip(i_target, l_target_centaur); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_margin_u32); if(rc) return rc; l_freq=l_attr_mss_freq_margin_u32/2; - l_cyc=l_cyc/l_freq;// converting to zepto to get more accurate data + l_cyc=l_cyc/l_freq;// converting to zepto to get more accurate data l_factor=l_cyc/128; //FAPI_INF("l_factor is % llu ",l_factor); - - - - for (l_rnk=0;l_rnk<iv_MAX_RANKS;++l_rnk) - {// Byte loop + + + + + for (l_p=0;l_p<MAX_PORT;l_p++){ + for (l_rnk=0;l_rnk<iv_MAX_RANKS[l_p];++l_rnk) + { + rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc; i_rank=valid_rank[l_rnk]; - rc = mss_getrankpair(i_target,iv_port,i_rank,&l_rp,valid_rank);if(rc) return rc; + rc = mss_getrankpair(i_target,l_p,i_rank,&l_rp,valid_rank);if(rc) return rc; for(l_byte=0;l_byte<iv_MAX_BYTES;++l_byte) { - + //Nibble loop for(l_nibble=0;l_nibble< MAX_NIBBLES;++l_nibble) { for(l_bit=0;l_bit< MAX_BITS;++l_bit) { l_dq=8*l_byte+4*l_nibble+l_bit; - //FAPI_INF(" the right bound = %d and nominal = %d",SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.rb_regval[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.nom_val[l_dq][l_rp]); - SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.right_margin_val[l_dq][l_rp]=((SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.rb_regval[l_dq][l_rp]-SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.nom_val[l_dq][l_rp])*l_factor)/l_factor_ps; - SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.left_margin_val[l_dq][l_rp]= ((SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.nom_val[l_dq][l_rp]-SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.lb_regval[l_dq][l_rp])*l_factor)/l_factor_ps;//((1/uint32_t_freq*1000000)/128); - SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.total_margin[l_dq][l_rp]=SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.right_margin_val[l_dq][l_rp]+SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.left_margin_val[l_dq][l_rp]; + //FAPI_INF(" the right bound = %d and nominal = %d",SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.nom_val[l_dq][l_rp]); + if(iv_shmoo_type==2) + { + if(SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq][l_rp] == 0){ + //FAPI_INF("\n abhijit saurabh is here and dq=%d \n",l_dq); + SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq][l_rp]=0; + SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq][l_rp]=SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq][l_rp]-2; + //FAPI_INF("\n the value of left bound after is %d \n",SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq][l_rp]); + } + } + SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq][l_rp]=SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq][l_rp]-1; + SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq][l_rp]=SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq][l_rp]+1; + SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq][l_rp]=((SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq][l_rp]-SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.nom_val[l_dq][l_rp])*l_factor)/l_factor_ps; + SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq][l_rp]= ((SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.nom_val[l_dq][l_rp]-SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq][l_rp])*l_factor)/l_factor_ps;//((1/uint32_t_freq*1000000)/128); + SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.total_margin[l_dq][l_rp]=SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq][l_rp]+SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq][l_rp]; } } } } - - + } + return rc; } /*------------------------------------------------------------------------------ * Function: get_min_margin - * Description : This function is used to get the minimum margin of all the schmoo margins + * Description : This function is used to get the minimum margin of all the schmoo margins * - * Parameters: Target:MBA,right minimum margin , left minimum margin, pass fail + * Parameters: Target:MBA,right minimum margin , left minimum margin, pass fail * ---------------------------------------------------------------------------*/ fapi::ReturnCode generic_shmoo::get_min_margin(const fapi::Target & i_target,uint32_t *o_right_min_margin,uint32_t *o_left_min_margin) { fapi::ReturnCode rc; - uint8_t l_rnk,l_byte,l_nibble,l_bit; + uint8_t l_rnk,l_byte,l_nibble,l_bit,i_rank; uint16_t l_temp_right=4800; uint16_t l_temp_left=4800; uint8_t l_dq=0; uint8_t l_rp=0; + uint8_t l_p=0; - - - - for (l_rnk=0;l_rnk<iv_MAX_RANKS;++l_rnk) - {// Byte loop + + + + for (l_p=0;l_p<MAX_PORT;l_p++){ + for (l_rnk=0;l_rnk<iv_MAX_RANKS[l_p];++l_rnk) + { + rc = mss_getrankpair(i_target,l_p,0,&l_rp,valid_rank);if(rc) return rc; + i_rank=valid_rank[l_rnk]; + rc = mss_getrankpair(i_target,l_p,i_rank,&l_rp,valid_rank);if(rc) return rc; for(l_byte=0;l_byte<iv_MAX_BYTES;++l_byte) { - + //Nibble loop for(l_nibble=0;l_nibble< MAX_NIBBLES;++l_nibble) { for(l_bit=0;l_bit< MAX_BITS;++l_bit) - { + { l_dq=8*l_byte+4*l_nibble+l_bit; - if(SHMOO[iv_shmoo_type].MBA.P[iv_port].S[l_rnk].K.right_margin_val[l_dq][l_rp]<l_temp_right) + if(SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq][l_rp]<l_temp_right) { - l_temp_right=SHMOO[iv_shmoo_type].MBA.P[iv_port].S[l_rnk].K.right_margin_val[l_dq][l_rp]; + l_temp_right=SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq][l_rp]; } - if(SHMOO[iv_shmoo_type].MBA.P[iv_port].S[l_rnk].K.left_margin_val[l_dq][l_rp]<l_temp_left) + if(SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq][l_rp]<l_temp_left) { - l_temp_left=SHMOO[iv_shmoo_type].MBA.P[iv_port].S[l_rnk].K.left_margin_val[l_dq][l_rp]; + l_temp_left=SHMOO[iv_shmoo_type].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq][l_rp]; } } } } + } } - - - // hacked for now till schmoo is running + + + // hacked for now till schmoo is running *o_right_min_margin=l_temp_right; *o_left_min_margin=l_temp_left; return rc; } + fapi::ReturnCode generic_shmoo:: schmoo_setup_mcb( const fapi::Target & i_target) +{ + + + uint8_t __attribute__((unused)) l_socket=0; //SW198827 + + //uint32_t rc_num =0; + uint8_t l_pattern=0; + uint8_t l_testtype=0; + uint8_t l_rank=0; + fapi::ReturnCode rc; + + uint64_t l_start =0x0000000000000000ull; + uint64_t l_end = 0x0000000000000000ull; + + + mcbist_test_mem i_mcbtest = CENSHMOO; // bellows: initialize to this type + mcbist_data_gen i_mcbpatt = ABLE_FIVE; // bellows: initialize to this data type + + if(l_rank<4) + { + l_socket=0; + } + else + { + l_socket=1; + } + + //send shmoo mode to vary the address range + + +l_pattern=iv_pattern; +FAPI_INF("value of pattern is %d",l_pattern); +switch(l_pattern) +{ +case 0 : i_mcbpatt = ABLE_FIVE;break; +case 1 : i_mcbpatt = USR_MODE;break; +case 2 : i_mcbpatt = ONEHOT;break; +case 3 : i_mcbpatt = DQ0_00011111_RESTALLONE;break; +case 4 : i_mcbpatt = DQ0_11100000_RESTALLZERO;break; +case 5 : i_mcbpatt = ALLZERO;break; +case 6 : i_mcbpatt = ALLONE;break; +case 7 : i_mcbpatt = BYTE_BURST_SIGNATURE;break; +case 8 : i_mcbpatt = BYTE_BURST_SIGNATURE_V1;break; +case 9 : i_mcbpatt = BYTE_BURST_SIGNATURE_V2;break; +case 10 : i_mcbpatt = BYTE_BURST_SIGNATURE_V3;break; +case 11 : i_mcbpatt = DATA_GEN_DELTA_I;break; +case 12 : i_mcbpatt = MCBIST_2D_CUP_PAT0;break; +case 13 : i_mcbpatt = MPR;break; +case 14 : i_mcbpatt = MPR03;break; +case 15 : i_mcbpatt = MPR25;break; +case 16 : i_mcbpatt = MPR47;break; +case 17 : i_mcbpatt = DELTA_I1;break; +case 18 : i_mcbpatt = MCBIST_2D_CUP_PAT1;break; +case 19 : i_mcbpatt = MHC_55;break; +case 20 : i_mcbpatt = MHC_DQ_SIM;break; +case 21 : i_mcbpatt = MCBIST_2D_CUP_PAT2;break; +case 22 : i_mcbpatt = MCBIST_2D_CUP_PAT3;break; +case 23 : i_mcbpatt = MCBIST_2D_CUP_PAT4;break; +case 24 : i_mcbpatt = MCBIST_2D_CUP_PAT5;break; +case 25 : i_mcbpatt = MCBIST_2D_CUP_PAT6;break; +case 26 : i_mcbpatt = MCBIST_2D_CUP_PAT7;break; +case 27 : i_mcbpatt = MCBIST_2D_CUP_PAT8;break; +case 28 : i_mcbpatt = MCBIST_2D_CUP_PAT9;break; +case 29 : i_mcbpatt = CWLPATTERN;break; +case 30 : i_mcbpatt = GREY1;break; +case 31 : i_mcbpatt = DC_ONECHANGE;break; +case 32 : i_mcbpatt = DC_ONECHANGEDIAG;break; +case 33 : i_mcbpatt = GREY2;break; +case 34 : i_mcbpatt = FIRST_XFER;break; +case 35 : i_mcbpatt = MCBIST_222_XFER;break; +case 36 : i_mcbpatt = MCBIST_333_XFER;break; +case 37 : i_mcbpatt = MCBIST_444_XFER;break; +case 38 : i_mcbpatt = MCBIST_555_XFER;break; +case 39 : i_mcbpatt = MCBIST_666_XFER;break; +case 40 : i_mcbpatt = MCBIST_777_XFER;break; +case 41 : i_mcbpatt = MCBIST_888_XFER;break; +case 42 : i_mcbpatt = FIRST_XFER_X4MODE;break; +case 43 : i_mcbpatt = MCBIST_LONG;break; +case 44 : i_mcbpatt = PSEUDORANDOM;break; +case 45 : i_mcbpatt = CASTLE;break; + +default : FAPI_INF("Wrong Data Pattern,so using default pattern"); +} +l_testtype=iv_test_type; +switch(l_testtype) +{ +case 0 : i_mcbtest = USER_MODE;break; +case 1 : i_mcbtest = CENSHMOO;break; +case 2 : i_mcbtest = SUREFAIL;break; +case 3 : i_mcbtest = MEMWRITE;break; +case 4 : i_mcbtest = MEMREAD;break; +case 5 : i_mcbtest = CBR_REFRESH;break; +case 6 : i_mcbtest = MCBIST_SHORT;break; +case 7 : i_mcbtest = SHORT_SEQ;break; +case 8 : i_mcbtest = DELTA_I;break; +case 9 : i_mcbtest = DELTA_I_LOOP;break; +case 10 : i_mcbtest = SHORT_RAND;break; +case 11 : i_mcbtest = LONG1;break; +case 12 : i_mcbtest = BUS_TAT;break; +case 13 : i_mcbtest = SIMPLE_FIX;break; +case 14 : i_mcbtest = SIMPLE_RAND;break; +case 15 : i_mcbtest = SIMPLE_RAND_2W;break; +case 16 : i_mcbtest = SIMPLE_RAND_FIXD;break; +case 17 : i_mcbtest = SIMPLE_RA_RD_WR;break; +case 18 : i_mcbtest = SIMPLE_RA_RD_R;break; +case 19 : i_mcbtest = SIMPLE_RA_FD_R;break; +case 20 : i_mcbtest = SIMPLE_RA_FD_R_INF;break; +case 21 : i_mcbtest = SIMPLE_SA_FD_R;break; +case 22 : i_mcbtest = SIMPLE_RA_FD_W;break; +case 23 : i_mcbtest = INFINITE;break; +case 24 : i_mcbtest = WR_ONLY;break; +case 25 : i_mcbtest = W_ONLY;break; +case 26 : i_mcbtest = R_ONLY;break; +case 27 : i_mcbtest = W_ONLY_RAND;break; +case 28 : i_mcbtest = R_ONLY_RAND;break; +case 29 : i_mcbtest = R_ONLY_MULTI;break; +default : FAPI_INF("Wrong Test_type,so using default test_type"); +} +rc = setup_mcbist(i_target, 0, i_mcbpatt, i_mcbtest, UNMASK_ALL, 0,iv_pattern,iv_test_type,0,0,l_start,l_end,iv_addr);if(rc) return rc; + +return rc; +} + }//Extern C diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.H index 609697507..df73008ee 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.H +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_generic_shmoo.H,v 1.11 2013/01/21 12:36:52 sasethur Exp $ +// $Id: mss_generic_shmoo.H,v 1.13 2013/04/09 12:18:47 lapietra Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -84,15 +84,17 @@ class generic_shmoo shmoo_algorithm_t algorithm; shmoo_mode mcbist_mode; uint8_t mcbist_error_map[MAX_PORT][MAX_RANK][MAX_BYTE][MAX_NIBBLES]; + uint8_t schmoo_error_map[MAX_PORT][MAX_RANK][20]; shmoo_type_t shmoo_mask; - uint8_t iv_port; - uint8_t iv_MAX_RANKS; + uint8_t iv_addr; + uint8_t iv_MAX_RANKS[MAX_PORT]; uint8_t iv_MAX_BYTES; uint8_t iv_pattern; uint8_t iv_test_type; uint8_t iv_dmm_type; uint8_t iv_DQS_ON; uint8_t iv_shmoo_type; + uint32_t iv_shmoo_param; uint8_t valid_rank[MAX_RANK]; @@ -103,22 +105,23 @@ class generic_shmoo enum bound_t { LEFT , RIGHT}; - generic_shmoo(uint8_t iv_port,shmoo_type_t shmoo_mask,shmoo_algorithm_t shmoo_algorithm);// Constructor + generic_shmoo(uint8_t iv_addr,shmoo_type_t shmoo_mask,shmoo_algorithm_t shmoo_algorithm);// Constructor generic_shmoo(){}; ~generic_shmoo(){}; // Destructor void init_multi_array(uint32_t (&array)[MAX_DQ][MAX_RPS],uint32_t init_val); //initialize multi dim arrays to known value fapi::ReturnCode init_multi_array_dqs(uint32_t (&array)[MAX_DQ][MAX_RPS],uint32_t init_val); fapi::ReturnCode get_all_noms(const fapi::Target & i_target); //! Read in all the Nominal values of the relevant knobs fapi::ReturnCode find_bound(const fapi::Target & i_target,bound_t); // generic Right bound - fapi::ReturnCode knob_update(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t rank,uint8_t byte,uint8_t nibble,uint8_t bit,uint8_t pass,bool &flag); // Increment or decrement the knob + fapi::ReturnCode knob_update(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag); // Increment or decrement the knob fapi::ReturnCode knob_update_dqs(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t rank,uint8_t byte,uint8_t nibble,uint8_t bit,uint8_t pass); fapi::ReturnCode print_report(const fapi::Target & i_target); // Print Shmoo report to file or STDOUT fapi::ReturnCode print_shmoo_parms(); fapi::ReturnCode get_margin(const fapi::Target & i_target); fapi::ReturnCode get_min_margin(const fapi::Target & i_target,uint32_t *o_right_min_margin,uint32_t *o_left_min_margin); - fapi::ReturnCode do_mcbist_test(const fapi::Target & i_target,uint8_t rank,uint8_t byte,uint8_t nibble,uint8_t &pass); - void check_error_map(uint8_t i_rank,uint8_t i_byte,uint8_t i_nibble,uint8_t &pass); + fapi::ReturnCode do_mcbist_test(const fapi::Target & i_target); + fapi::ReturnCode check_error_map(const fapi::Target & i_target,uint8_t port,uint8_t &pass); fapi::ReturnCode sanity_check(const fapi::Target & i_target); - fapi::ReturnCode run(const fapi::Target & i_target,uint32_t *right_min_margin,uint32_t *left_min_margin,uint8_t i_pattern,uint8_t i_test_type); + fapi::ReturnCode schmoo_setup_mcb( const fapi::Target & i_target); + fapi::ReturnCode run(const fapi::Target & i_target,uint32_t *right_min_margin,uint32_t *left_min_margin,uint8_t i_pattern,uint8_t i_test_type,uint32_t i_shmoo_param); }; #endif diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.C index 1bbc2145b..ffc4f3d69 100755 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_mcbist.C,v 1.29 2013/01/16 15:38:02 sasethur Exp $ +// $Id: mss_mcbist.C,v 1.37 2013/02/19 12:14:03 sasethur Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -38,8 +38,14 @@ //------------------------------------------------------------------------------ // Version:|Author: | Date: | Comment: // --------|--------|--------|-------------------------------------------------- -// 1.29 |aditya |01/11/16|Updated cfg_mcb_dgen function -// 1.28 |aditya |01/11/16|Updated cfg_mcb_dgen function +// 1.37 |aditya |02/19/13|updated testtypes +// 1.34 |aditya |02/13/13|updated testtypes +// 1.33 |aditya |02/12/13|updated testtypes +// 1.32 |aditya |02/11/13|updated testtypes +// 1.31 |aditya |02/06/13|Updated SIMPLE_RAND test_type +// 1.30 |aditya |01/30/13|Updated fw comments +// 1.29 |aditya |01/11/13|Updated cfg_mcb_dgen function +// 1.28 |aditya |01/11/13|Updated cfg_mcb_dgen function // 1.27 |aditya |01/11/13|Updated cfg_mcb_dgen function // 1.26 |aditya |01/07/13|Updated Review Comments // 1.25 |aditya |01/03/13| Updated FW Comments @@ -111,43 +117,43 @@ fapi::ReturnCode cfg_mcb_test_mem(const fapi::Target & i_target_mba,mcbist_test rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,R, 0,SF,FIX, 1,DEFAULT,FIX_ADDR,2); if(rc) return rc; rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,OPER_RAND,0,RF,FIX, 1,DEFAULT,FIX_ADDR,3); if(rc) return rc; - rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR1Q_0x030106a9,RW, 0,RF,RAND,0,DEFAULT,FIX_ADDR,0); if(rc) return rc; + rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR1Q_0x030106a9,RW, 0,RF,DATA_RF,0,DEFAULT,FIX_ADDR,0); if(rc) return rc; } else if (i_test_type == SIMPLE_RAND) { - rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,W, 0,SF,RAND,0,DEFAULT,FIX_ADDR,0); if(rc) return rc; - rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,R, 0,SF,RAND,1,DEFAULT,FIX_ADDR,1); if(rc) return rc; - rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,W, 0,RF,RAND,1,DEFAULT,FIX_ADDR,2); if(rc) return rc; - rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,R, 0,RF,RAND,1,DEFAULT,FIX_ADDR,3); if(rc) return rc; + rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,W, 0,SF,DATA_RF,0,DEFAULT,FIX_ADDR,0); if(rc) return rc; + rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,R, 0,SF,DATA_RF,0,DEFAULT,FIX_ADDR,1); if(rc) return rc; + rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,W, 0,RF,DATA_RF,0,DEFAULT,FIX_ADDR,2); if(rc) return rc; + rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,R, 0,RF,DATA_RF,1,DEFAULT,FIX_ADDR,3); if(rc) return rc; - rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR1Q_0x030106a9,RW, 4,RF,RAND,0,DEFAULT,FIX_ADDR,0); if(rc) return rc; + rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR1Q_0x030106a9,RW, 4,RF,DATA_RF,0,DEFAULT,FIX_ADDR,0); if(rc) return rc; } else if (i_test_type == WR_ONLY) { - rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,W, 0,SF,RAND,0,DEFAULT,FIX_ADDR,0); if(rc) return rc; - rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,R, 0,SF,RAND,1,DEFAULT,FIX_ADDR,1); if(rc) return rc; + rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,W, 0,SF,DATA_RF,0,DEFAULT,FIX_ADDR,0); if(rc) return rc; + rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,R, 0,SF,DATA_RF,1,DEFAULT,FIX_ADDR,1); if(rc) return rc; rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,W, 0,RF,FIX,0,DEFAULT,FIX_ADDR,2); if(rc) return rc; rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,OPER_RAND,0,RF,FIX,1,DEFAULT,FIX_ADDR,3); if(rc) return rc; - rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR1Q_0x030106a9,RW, 4,RF,RAND,0,DEFAULT,FIX_ADDR,0); if(rc) return rc; + rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR1Q_0x030106a9,RW, 4,RF,DATA_RF,0,DEFAULT,FIX_ADDR,0); if(rc) return rc; } else if (i_test_type == W_ONLY) { - rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,W, 0,SF,RAND,1,DEFAULT,FIX_ADDR,0); if(rc) return rc; + rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,W, 0,SF,DATA_RF,1,DEFAULT,FIX_ADDR,0); if(rc) return rc; rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,R, 0,SF,FIX, 1,DEFAULT,FIX_ADDR,1); if(rc) return rc; rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,W, 0,RF,FIX, 0,DEFAULT,FIX_ADDR,2); if(rc) return rc; rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,OPER_RAND,0,RF,FIX, 1,DEFAULT,FIX_ADDR,3); if(rc) return rc; - rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR1Q_0x030106a9,RW, 4,RF,RAND,0,DEFAULT,FIX_ADDR,0); if(rc) return rc; + rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR1Q_0x030106a9,RW, 4,RF,DATA_RF,0,DEFAULT,FIX_ADDR,0); if(rc) return rc; } else if (i_test_type == R_ONLY) { - rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,R, 0,SF,RAND,1,DEFAULT,FIX_ADDR,0); if(rc) return rc; + rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,R, 0,SF,DATA_RF,1,DEFAULT,FIX_ADDR,0); if(rc) return rc; rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,W, 0,RF,FIX, 0,DEFAULT,FIX_ADDR,2); if(rc) return rc; rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR0Q_0x030106a8,OPER_RAND,0,RF,FIX, 1,DEFAULT,FIX_ADDR,3); if(rc) return rc; - rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR1Q_0x030106a9,RW, 4,RF,RAND,0,DEFAULT,FIX_ADDR,0); if(rc) return rc; + rc = mcb_write_test_mem(i_target_mba,MBA01_MCBIST_MCBMR1Q_0x030106a9,RW, 4,RF,DATA_RF,0,DEFAULT,FIX_ADDR,0); if(rc) return rc; } else @@ -188,8 +194,8 @@ fapi::ReturnCode cfg_mcb_dgen(const fapi::Target & i_target_mba,mcbist_data_gen uint64_t l_spare = 0x0000000000000000ull; //uint64_t l_data = 0x0000000000000000ull; uint8_t l_rotnum = 0; - uint32_t l_mba01_mcb_pseudo_random[NINE] = { MBA01_MCBIST_MCBFD0Q_0x030106be,MBA01_MCBIST_MCBFD1Q_0x030106bf,MBA01_MCBIST_MCBFD2Q_0x030106c0,MBA01_MCBIST_MCBFD3Q_0x030106c1,MBA01_MCBIST_MCBFD4Q_0x030106c2, MBA01_MCBIST_MCBFD5Q_0x030106c3,MBA01_MCBIST_MCBFD6Q_0x030106c4,MBA01_MCBIST_MCBFD7Q_0x030106c5,MBA01_MCBIST_MCBFDQ_0x030106c6}; - uint32_t l_mba01_mcb_random[MAX_BYTE] = {MBA01_MCBIST_MCBRDS0Q_0x030106b2,MBA01_MCBIST_MCBRDS1Q_0x030106b3,MBA01_MCBIST_MCBRDS2Q_0x030106b4,MBA01_MCBIST_MCBRDS3Q_0x030106b5,MBA01_MCBIST_MCBRDS4Q_0x030106b6,MBA01_MCBIST_MCBRDS5Q_0x030106b7,MBA01_MCBIST_MCBRDS6Q_0x030106b8,MBA01_MCBIST_MCBRDS7Q_0x030106b9,MBA01_MCBIST_MCBRDS8Q_0x030106ba,MBA01_MCBIST_MCBDRSRQ_0x030106bc}; + uint32_t l_mba01_mcb_pseudo_random[MAX_BYTE] = { MBA01_MCBIST_MCBFD0Q_0x030106be,MBA01_MCBIST_MCBFD1Q_0x030106bf,MBA01_MCBIST_MCBFD2Q_0x030106c0,MBA01_MCBIST_MCBFD3Q_0x030106c1,MBA01_MCBIST_MCBFD4Q_0x030106c2, MBA01_MCBIST_MCBFD5Q_0x030106c3,MBA01_MCBIST_MCBFD6Q_0x030106c4,MBA01_MCBIST_MCBFD7Q_0x030106c5,MBA01_MCBIST_MCBFDQ_0x030106c6,MBA01_MCBIST_MCBFDSPQ_0x030106c7}; + uint32_t l_mba01_mcb_random[MAX_BYTE] = {MBA01_MCBIST_MCBRDS0Q_0x030106b2,MBA01_MCBIST_MCBRDS1Q_0x030106b3,MBA01_MCBIST_MCBRDS2Q_0x030106b4,MBA01_MCBIST_MCBRDS3Q_0x030106b5,MBA01_MCBIST_MCBRDS4Q_0x030106b6,MBA01_MCBIST_MCBRDS5Q_0x030106b7,MBA01_MCBIST_MCBRDS6Q_0x030106b8,MBA01_MCBIST_MCBRDS7Q_0x030106b9,MBA01_MCBIST_MCBRDS8Q_0x030106ba,0x030106bb}; uint8_t l_index,l_index1 = 0; uint32_t l_rand_32 = 0; @@ -272,8 +278,10 @@ rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var); if (rc_num){ FAPI_ERR( "c else if(i_datamode == ABLE_FIVE) { - l_var = 0xA5A5A5A5A5A5A5A5ull; - l_var1 =0x5A5A5A5A5A5A5A5Aull; + // l_var = 0x4B4B4B4B4B4B4B4Bull; + //l_var1 = 0x9696969696969696ull; + l_var = 0xA5A5A5A5A5A5A5A5ull; + l_var1 =0x5A5A5A5A5A5A5A5Aull; l_spare = 0xA55AA55AA55AA55Aull; rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;} @@ -321,7 +329,7 @@ rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var); if (rc_num){ FAPI_ERR( "c { // srand(2); FAPI_INF("Need to check the value of RAND_MAX for this compiler -- assuming 32bit of data is returned"); - for (l_index = 0; l_index< (MAX_BYTE-1) ; l_index++) + for (l_index = 0; l_index< (MAX_BYTE) ; l_index++) { //l_rand_32 = rand(); l_rand_32 = 0xFFFFFFFF;//Hard Coded Temporary Fix till random function is fixed @@ -528,16 +536,16 @@ rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var); if (rc_num){ FAPI_ERR( "c //Writing MBS 23 pattern registers for comparison mod - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD0Q_0x02011681, l_var_data_buffer_64); if(rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD1Q_0x02011682, l_var1_data_buffer_64); if(rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD2Q_0x02011683, l_var_data_buffer_64); if(rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD3Q_0x02011684, l_var1_data_buffer_64); if(rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD4Q_0x02011685, l_var_data_buffer_64); if(rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD5Q_0x02011686, l_var1_data_buffer_64); if(rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD6Q_0x02011687, l_var_data_buffer_64); if(rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD7Q_0x02011688, l_var1_data_buffer_64); if(rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDQ_0x02011689, l_spare_data_buffer_64); if(rc) return rc; - rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDSPQ_0x0201168A,l_spare_data_buffer_64); if(rc) return rc; + rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD0Q_0x02011781, l_var_data_buffer_64); if(rc) return rc; + rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD1Q_0x02011782, l_var1_data_buffer_64); if(rc) return rc; + rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD2Q_0x02011783, l_var_data_buffer_64); if(rc) return rc; + rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD3Q_0x02011784, l_var1_data_buffer_64); if(rc) return rc; + rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD4Q_0x02011785, l_var_data_buffer_64); if(rc) return rc; + rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD5Q_0x02011786, l_var1_data_buffer_64); if(rc) return rc; + rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD6Q_0x02011787, l_var_data_buffer_64); if(rc) return rc; + rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD7Q_0x02011788, l_var1_data_buffer_64); if(rc) return rc; + rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDQ_0x02011789, l_spare_data_buffer_64); if(rc) return rc; + rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDSPQ_0x0201178A,l_spare_data_buffer_64); if(rc) return rc; } diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H index e3464b2c5..f21a24f48 100755 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_mcbist.H,v 1.23 2013/01/16 15:16:29 sasethur Exp $ +// $Id: mss_mcbist.H,v 1.28 2013/02/14 12:04:04 billyz Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -38,7 +38,10 @@ //------------------------------------------------------------------------------- // Version:|Author: | Date: | Comment: // --------|--------|---------|-------------------------------------------------- -// 1.23 |aditya |01/11/16 |added a parameter to setup_mcbist function +// 1.27 |aditya |02/13/13 |updated testtypes +// 1.25 |aditya |02/12/13 |updated testtypes +// 1.24 |aditya |01/30/13 |Updated fw comments +// 1.23 |aditya |01/16/13 |added a parameter to setup_mcbist function // 1.22 |aditya |01/11/13 |added a parameter to setup_mcbist function // 1.21 |aditya |01/07/13 | Updated FW Review Comments // 1.20 |aditya |01/03/13 | Updated FW Comments @@ -76,7 +79,7 @@ using namespace fapi; /*const uint8_t MAX_PORT = 2; const uint8_t MAX_BYTE = 10; const uint8_t MAX_RANK = 8; -const uint8_t MAX_NIBBLE = 1;*/ +const uint8_t MAX_NIBBLE = 1;;;*/ enum mcbist_test_mem { @@ -109,7 +112,14 @@ enum mcbist_test_mem R_ONLY, W_ONLY_RAND, R_ONLY_RAND, - R_ONLY_MULTI + R_ONLY_MULTI, + SHORT, + SIMPLE_RAND_BARI, + W_R_INFINITE, + W_R_RAND_INFINITE, + R_INFINITE1, + R_INFINITE_RF, + MARCH }; enum mcbist_data_gen @@ -183,8 +193,8 @@ enum mcbist_data_mode RECCB, DEA, DRL, - DRR, - RAND + DRR + }; enum mcbist_addr_mode @@ -261,7 +271,7 @@ fapi::ReturnCode mcb_reset_trap(const fapi::Target & i_target_mba); fapi::ReturnCode cfg_mcb_dgen(const fapi::Target & i_target_mba,mcbist_data_gen i_datamode,uint8_t i_mcbrotate); fapi::ReturnCode cfg_byte_mask(const fapi::Target & i_target_mba,uint8_t i_rank,uint8_t i_port); fapi::ReturnCode start_mcb(const fapi::Target & i_target_mba); -fapi::ReturnCode setup_mcbist(const fapi::Target & i_target_mba, uint8_t i_port,mcbist_data_gen i_mcbpatt,mcbist_test_mem i_mcbtest,mcbist_byte_mask i_mcbbytemask,uint8_t i_mcbrotate,uint8_t i_pattern,uint8_t i_test_type,uint8_t i_rank,uint8_t i_bit32,uint64_t i_start,uint64_t i_end); +fapi::ReturnCode setup_mcbist(const fapi::Target & i_target_mba, uint8_t i_port,mcbist_data_gen i_mcbpatt,mcbist_test_mem i_mcbtest,mcbist_byte_mask i_mcbbytemask,uint8_t i_mcbrotate,uint8_t i_pattern,uint8_t i_test_type,uint8_t i_rank,uint8_t i_bit32,uint64_t i_start,uint64_t i_end,uint8_t new_address_map); fapi::ReturnCode cfg_mcb_addr(const fapi::Target & i_target_mba,uint8_t i_rank,uint8_t i_port,uint64_t i_start,uint64_t i_end); fapi::ReturnCode mcb_error_map_print(const fapi::Target & i_target_mba,uint8_t i_port,uint8_t i_rank,ecmdDataBufferBase & i_mcb_fail_320); } diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C new file mode 100644 index 000000000..2d59480c4 --- /dev/null +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C @@ -0,0 +1,991 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: mss_mcbist_address.C,v 1.9 2013/04/04 20:56:10 bellows Exp $ +// *!*************************************************************************** +// *! (C) Copyright International Business Machines Corp. 1997, 1998, 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *!*************************************************************************** +// *! FILENAME : mss_mcbist_address_default.C +// *! TITLE : +// *! DESCRIPTION : MCBIST procedures +// *! CONTEXT : +// *! +// *! OWNER NAME : preeragh@in.ibm.com +// *! BACKUP : +// *!*************************************************************************** +// CHANGE HISTORY: +//------------------------------------------------------------------------------- +// Version:|Author: | Date: | Comment: +// --------|--------|---------|-------------------------------------------------- +// 1.9 |bellows |04-Apr-13| Changed program to be Hostboot compliant +// 1.2 |bellows |03-Apr-13| Added Id and cleaned up a warning msg. +// 1.1 | |xx-Apr-13| Copied from original which is now known as mss_mcbist_address_default/_lab.C +//------------------------------------------------------------------------------ + +#include "mss_mcbist_address.H" +extern "C" +{ +using namespace fapi; + +#define MAX_STRING_LEN 80 +#define DELIMITERS "," + +fapi::ReturnCode address_generation(const fapi:: Target & i_target_mba,uint8_t i_port,mcbist_addr_mode i_addr_type,interleave_type i_add_inter_type,uint8_t i_rank,uint64_t &io_start_address, uint64_t &io_end_address) + +{ +fapi::ReturnCode rc; +uint8_t l_num_ranks_per_dimm[2][2]; +uint8_t l_num_master_ranks[2][2]; +uint8_t l_dram_gen=0; +uint8_t l_dram_banks=0; +uint8_t l_dram_rows=0; +uint8_t l_dram_cols=0; +uint8_t l_dram_density=0; +uint8_t l_dram_width=0; +uint8_t l_addr_inter=0; +uint8_t l_num_ranks_p0_dim0,l_num_ranks_p0_dim1,l_num_ranks_p1_dim0,l_num_ranks_p1_dim1; +uint8_t mr3_valid,mr2_valid,mr1_valid; +uint32_t __attribute__((unused)) rc_num; // SW198827 +char S0[] = "b"; +//char l_my_addr[MAX_STRING_LEN]; + +//Choose a default buffer for the below +//0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 +//MR0(MSB) MR1 MR2 MR3 BA0 BA1 BA2 BA3 C3 C4 C5 C6 C7 C8 C9 C10 C11 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 SL0(MSB) SL1 SL2 +ecmdDataBufferBase l_default_add_buffer(64); +ecmdDataBufferBase l_new_add_buffer(64); + + rc_num = l_default_add_buffer.flushTo0(); + rc_num = l_new_add_buffer.flushTo0(); + + +rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm); if(rc) return rc; +rc = FAPI_ATTR_GET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, &i_target_mba, l_num_master_ranks); if(rc) return rc; +rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target_mba, l_dram_gen); if(rc) return rc; +rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_BANKS, &i_target_mba, l_dram_banks); if(rc) return rc; +rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_ROWS, &i_target_mba, l_dram_rows); if(rc) return rc; +rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_COLS, &i_target_mba, l_dram_cols); if(rc) return rc; +rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DENSITY, &i_target_mba, l_dram_density); if(rc) return rc; +rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width); if(rc) return rc; +rc = FAPI_ATTR_GET(ATTR_MCBIST_ADDR_INTER, &i_target_mba, l_addr_inter); if(rc) return rc; + + +//------------------------------ Debug Stuff ------------------------------- +FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[0][0]); +FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[0][1]); +FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[1][0]); +FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[1][1]); +//------------------------------ Debug Stuff ------------------------------- + +FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p0_dim0 is %d ",l_num_master_ranks[0][0]); +FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p0_dim1 is %d ",l_num_master_ranks[0][1]); +FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p1_dim0 is %d ",l_num_master_ranks[1][0]); +FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM is l_num_master_p1_dim1 %d ",l_num_master_ranks[1][1]); + +//------------------------------------------------------------------------------- + +l_num_ranks_p0_dim0 = l_num_ranks_per_dimm[0][0]; +l_num_ranks_p0_dim1 = l_num_ranks_per_dimm[0][1]; +l_num_ranks_p1_dim0 = l_num_ranks_per_dimm[1][0]; +l_num_ranks_p1_dim1 = l_num_ranks_per_dimm[1][1]; + +//Initial all ranks are invalid +mr3_valid = 0; +mr2_valid = 0; +mr1_valid = 0; + +if( (l_num_ranks_p0_dim0 == 1 && l_num_ranks_p0_dim1 == 0) || (l_num_ranks_p1_dim0 == 1 && l_num_ranks_p1_dim1 == 0) ) //Single Rank case -- default0 + { + //do rank-only stuff for this + FAPI_INF("--- INSIDE 1R"); + l_addr_inter=3; + } + +else if ( (l_num_ranks_p0_dim0 == 1 && l_num_ranks_p0_dim1 == 1) || (l_num_ranks_p1_dim0 == 1 && l_num_ranks_p1_dim1 == 1) ) +{ + FAPI_INF("--- INSIDE p0d0 valid and p0d1 valid --- 0 4---- 2R"); + mr1_valid=1; +} + +else if ( (l_num_ranks_p0_dim0 == 2 && l_num_ranks_p0_dim1 == 0) || (l_num_ranks_p1_dim0 == 2 && l_num_ranks_p1_dim1 == 0) ) +{ + FAPI_INF("--- INSIDE p0d0 valid and p0d1 valid --- 0 1---- 2R"); + mr3_valid=1; +} +else if ((l_num_ranks_p0_dim0 == 2 && l_num_ranks_p0_dim1 == 2)|| (l_num_ranks_p1_dim0 == 2 && l_num_ranks_p1_dim1 == 2)) //Rank 01 and 45 case + { + FAPI_INF("--- INSIDE --- 2R 0145"); + mr3_valid = 1; + mr1_valid=1; + } + +else if((l_num_ranks_p0_dim0 == 4 && l_num_ranks_p0_dim1 == 0 )|| (l_num_ranks_p1_dim0 == 4 && l_num_ranks_p1_dim1 == 0 )) //Rank 0123 on single dimm case + { + mr3_valid = 1;mr2_valid = 1; + } + +else if ((l_num_ranks_p0_dim0 == 4 && l_num_ranks_p0_dim1 == 4) || (l_num_ranks_p1_dim0 == 4 && l_num_ranks_p1_dim1 == 4)) //Rank 0123 and 4567 case +{ + mr3_valid = 1; + mr2_valid = 1; + mr1_valid = 1; +} + +else + + { + FAPI_INF("-- Error ---- Check Config ----- "); + } + +FAPI_INF("ATTR_EFF_DRAM_GEN is %d ",l_dram_gen); +FAPI_INF("ATTR_EFF_DRAM_BANKS is %d ",l_dram_banks); +FAPI_INF("ATTR_EFF_DRAM_ROWS is %d ",l_dram_rows); +FAPI_INF("ATTR_EFF_DRAM_COLS is %d ",l_dram_cols); +FAPI_INF("ATTR_EFF_DRAM_DENSITY is %d ",l_dram_density); +FAPI_INF("ATTR_EFF_DRAM_WIDTH is %d ",l_dram_width); +FAPI_INF("ATTR_ADDR_INTER Mode is %d ",l_addr_inter); + + + +FAPI_INF("--- BANK-RANK Address interleave ---"); +rc = parse_addr(i_target_mba,S0,mr3_valid,mr2_valid,mr1_valid,l_dram_rows,l_dram_cols,l_addr_inter);if(rc) return rc; + + + +return rc; + +} + + +fapi::ReturnCode parse_addr(const fapi:: Target & i_target_mba, char addr_string[],uint8_t mr3_valid,uint8_t mr2_valid,uint8_t mr1_valid,uint8_t l_dram_rows,uint8_t l_dram_cols,uint8_t l_addr_inter) +{ +fapi::ReturnCode rc; +uint8_t i=37; + +uint8_t l_slave_rank = 0; +uint8_t l_value; +uint32_t l_value32 = 0; +uint32_t l_sbit,rc_num; +uint32_t l_start=0; +uint32_t l_len = 6; +uint64_t l_readscom_value = 0; +uint64_t l_end = 0; +uint64_t l_start_addr = 0; +uint8_t l_value_zero = 0; +uint8_t l_user_end_addr = 0; +ecmdDataBufferBase l_data_buffer_64(64); +ecmdDataBufferBase l_data_buffer_rd64(64); +uint8_t l_attr_addr_mode = 3; +uint8_t l_num_cols = 0; +uint8_t l_num_rows = 0; + + + +rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_ADDR_MODE, &i_target_mba, l_attr_addr_mode); if(rc) return rc; + +rc = FAPI_ATTR_GET(ATTR_MCBIST_ADDR_NUM_COLS, &i_target_mba, l_num_cols); if(rc) return rc; +rc = FAPI_ATTR_GET(ATTR_MCBIST_ADDR_NUM_ROWS, &i_target_mba, l_num_rows); if(rc) return rc; + +if(l_num_cols == 0) +{l_num_cols = l_dram_cols;} + +if(l_num_rows == 0 ) +{l_num_rows = l_dram_rows;} + + +//Set all the addr reg to 0 + +//Define Custom String + +//Set all Params based on the string. + +rc_num = l_data_buffer_64.flushTo0(); + + l_sbit = 0;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + i--; + + l_sbit = 54;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106c8,l_data_buffer_64); + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6); + rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + i--; + //FAPI_INF("Inside strcmp ba2"); + l_sbit = 48;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6); + rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + i--; + + //FAPI_INF("Inside strcmp ba3"); + l_sbit = 42;l_value =i; + //------- Enable these for DDR4 --- for now constant map to zero + rc = fapiGetScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + FAPI_INF("ba3 Invalid"); + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6); + rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + i++; + + + //FAPI_INF("Inside strcmp mr3"); + l_sbit = 18;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + if(mr3_valid==1) + { + + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + i--; + } + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + FAPI_INF("mr3 Invalid"); + i++; + } + + + + //FAPI_INF("Inside strcmp mr2"); + l_sbit = 12;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + if(mr2_valid==1) + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + FAPI_INF("Inside mr2 --- l_addr_inter"); + rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + i--; + } + + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + FAPI_INF("mr2 Invalid"); + i++; + } + + + + + //FAPI_INF("Inside strcmp mr1"); + l_sbit = 6;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + if(mr1_valid==1) + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + FAPI_INF("Inside mr1 --- l_addr_inter"); + rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + i--; + } + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + FAPI_INF("mr1 Invalid"); + i++; + } + + + + + + //FAPI_INF("Inside strcmp mr0"); + l_sbit = 0;l_value =i; + //------- Enable these for DDR4 --- for now constant map to zero + rc = fapiGetScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + i++; + //FAPI_INF("Value of i = %d",i); + FAPI_INF("mr0 Invalid\n"); + + + + //FAPI_INF("Inside strcmp cl3"); + l_sbit = 42;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + i++; + FAPI_INF("col2 Invalid"); + //FAPI_INF("Value of i = %d",i); + + + + + //FAPI_INF("Inside strcmp cl3"); + l_sbit = 36;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + if(l_num_cols >= 1) + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + i--; + } + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + FAPI_INF("Col 3 -- Invalid"); + i++; + } + + //FAPI_INF("Inside strcmp cl4"); + l_sbit = 30;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + if(l_num_cols >= 2) + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + i--; + + } + //FAPI_INF("Value of i = %d",i); + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + FAPI_INF("Col 4 -- Invalid"); + i++; + } + + + + //FAPI_INF("Inside strcmp cl5"); + l_sbit = 24;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + if(l_num_cols >= 3) + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + i--; + } + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + FAPI_INF("Col 5 -- Invalid"); + i++; + } + + //FAPI_INF("Inside strcmp cl6"); + l_sbit = 18;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + if(l_num_cols >= 4) + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + i--; + } + //FAPI_INF("Value of i = %d",i); + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + FAPI_INF("Col 6 -- Invalid"); + i++; + } + + + + //FAPI_INF("Inside strcmp cl7"); + l_sbit = 12;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + if(l_num_cols >= 5) + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + i--; + } + //FAPI_INF("Value of i = %d",i); + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + FAPI_INF("Col 7 -- Invalid"); + i++; + } + + + + //FAPI_INF("Inside strcmp cl8"); + l_sbit = 6;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + if(l_num_cols >= 6) + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + i--; + } + //FAPI_INF("Value of i = %d",i); + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + FAPI_INF("Col 8 -- Invalid"); + i++; + } + + + + //FAPI_INF("Inside strcmp cl9"); + l_sbit = 0;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + if(l_num_cols >= 7) + {rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc;i--;} + + + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106cb,l_data_buffer_64); if(rc) return rc; + FAPI_INF("Col 9 -- Invalid"); + i++; + } + + + + //FAPI_INF("Inside strcmp cl11"); + l_sbit = 54;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + if(l_num_cols >= 11) + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + i--; + + + } + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + FAPI_INF("Col 11 -- Invalid"); + i++; + + } + + //FAPI_INF("Value of i = %d",i); + + + + //FAPI_INF("Inside strcmp cl13"); + l_sbit = 48;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + if(l_num_cols >= 12) + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + i--; + } + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + FAPI_INF("Col 13 Invalid"); + i++; + } + //FAPI_INF("Value of i = %d",i); + + + + + + //FAPI_INF("Inside strcmp r0"); + l_sbit = 42;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + if(l_num_rows > 0 ) + {rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + i--; + } + //FAPI_INF("Value of i = %d",i); + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + FAPI_INF("row 0 -- Invalid"); + i++; + } + + + + //FAPI_INF("Inside strcmp r1"); + l_sbit = 36;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + if(l_num_rows > 1 ) + {rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + i--; + } + //FAPI_INF("Value of i = %d",i); + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + FAPI_INF("row 1 -- Invalid"); + i++; + } + + + + + //FAPI_INF("Inside strcmp r2"); + l_sbit = 30;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + if(l_num_rows > 2 ) + {rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + i--; + } + //FAPI_INF("Value of i = %d",i); + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + FAPI_INF("row 2 -- Invalid"); + i++; + } + + + + //FAPI_INF("Inside strcmp r3"); + l_sbit = 24;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + if(l_num_rows > 3 ) + {rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + i--; + } + //FAPI_INF("Value of i = %d",i); + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + FAPI_INF("row 3 -- Invalid"); + i++; + } + + + + //FAPI_INF("Inside strcmp r4"); + l_sbit = 18;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + if(l_num_rows > 4 ) + {rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + i--;} + //FAPI_INF("Value of i = %d",i); + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + FAPI_INF("row 4 -- Invalid"); + i++; + } + + + + + + //FAPI_INF("Inside strcmp r5"); + l_sbit = 12;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + if(l_num_rows > 5 ) + {rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + i--; + } + //FAPI_INF("Value of i = %d",i); + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + FAPI_INF("row 5 -- Invalid"); + i++; + } + + + + //FAPI_INF("Inside strcmp r6"); + l_sbit = 6;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + if(l_num_rows > 6 ) + {rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + i--; + } + //FAPI_INF("Value of i = %d",i); + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + FAPI_INF("row 6 -- Invalid"); + i++; + } + + + + //FAPI_INF("Inside strcmp r7"); + l_sbit = 0;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + if(l_num_rows > 7 ) + {rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + i--; + } + //FAPI_INF("Value of i = %d",i); + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106ca,l_data_buffer_64); if(rc) return rc; + FAPI_INF("row 7 -- Invalid"); + i++; + } + + + + //FAPI_INF("Inside strcmp r8"); + l_sbit = 54;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + if(l_num_rows > 8 ) + {rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + i--; + } + //FAPI_INF("Value of i = %d",i); + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + FAPI_INF("row 8 -- Invalid"); + i++; + } + + + + + //FAPI_INF("Inside strcmp r9"); + l_sbit = 48;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + if(l_num_rows > 9 ) + {rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + i--; + } + //FAPI_INF("Value of i = %d",i); + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + FAPI_INF("row 9 -- Invalid"); + i++; + } + + + + //FAPI_INF("Inside strcmp r10"); + l_sbit = 42;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + if(l_num_rows > 10 ) + {rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + i--; + } + //FAPI_INF("Value of i = %d",i); + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + FAPI_INF("row 10 -- Invalid"); + i++; + } + + + + //FAPI_INF("Inside strcmp r11"); + l_sbit = 36;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + if(l_num_rows > 11 ) + {rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + i--; + } + //FAPI_INF("Value of i = %d",i); + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + FAPI_INF("row 11 -- Invalid"); + i++; + } + + + + //FAPI_INF("Inside strcmp r12"); + l_sbit = 30;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + if(l_num_rows > 12 ) + {rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + i--; + } + //FAPI_INF("Value of i = %d",i); + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + FAPI_INF("row 12 -- Invalid"); + i++; + } + + + + //FAPI_INF("Inside strcmp r13"); + l_sbit = 24;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + if(l_num_rows > 13 ) + {rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + i--; + } + //FAPI_INF("Value of i = %d",i); + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + FAPI_INF("row 13 -- Invalid"); + i++; + } + + + + //FAPI_INF("Inside strcmp r14"); + l_sbit = 18;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + if(l_num_rows > 14 ) + {rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + i--; + } + //FAPI_INF("Value of i = %d",i); + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + FAPI_INF("row 14 -- Invalid"); + i++; + } + + + + //FAPI_INF("Inside strcmp r15"); + l_sbit = 12;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + if ( l_num_rows > 15 ) + { rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + i--; + } + else + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + FAPI_INF("row 15 -- Invalid"); + i++; + } + //FAPI_INF("Value of i = %d",i); + + + + //FAPI_INF("Inside strcmp r16 and l_dram_rows = %d",l_dram_rows); + l_sbit = 6;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + if ( l_dram_rows >= 17 ) + { + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + i--; + } + else + { + //FAPI_INF("r16 not used"); + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + FAPI_INF("Row 16 Invalid"); + rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc; + i++; + } + //FAPI_INF("Value of i = %d",i); + + + + //FAPI_INF("Inside strcmp sl2"); + l_sbit = 36;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + //------- Enable these for later --- for now constant map to zero + if (l_slave_rank==0) + {l_value =0;} + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + FAPI_INF("sl2 Invalid"); + i++; + //FAPI_INF("Value of i = %d",i); + + + + //FAPI_INF("Inside strcmp sl1"); + l_sbit = 30;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + //------- Enable these for later --- for now constant map to zero + if (l_slave_rank==0) + {l_value =0;} + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + i++; + FAPI_INF("sl1 Invalid"); + //FAPI_INF("Value of i = %d",i); + + + + //FAPI_INF("Inside strcmp sl0"); + l_sbit = 24;l_value =i; + rc = fapiGetScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + //------- Enable these for later --- for now constant map to zero + if (l_slave_rank==0) + {l_value =0;} + rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function parse_addr:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc; + FAPI_INF("sl0 Invalid"); + i++; + //FAPI_INF("Value of i = %d",i); + + + + + + + //------ Setting Start and end addr counters + +FAPI_INF("Debug - --------------- Setting Start and End Counters -----------\n"); +rc_num = l_data_buffer_rd64.flushTo0(); +rc = fapiPutScom(i_target_mba,0x030106d0,l_data_buffer_rd64); if(rc) return rc; +l_value = i+1; +FAPI_INF("Setting end_addr Value of i = %d",i); +rc_num = l_data_buffer_rd64.flushTo0(); + +//Calculate and set Valid bits for end_addr + +for(i=l_value;i <= 37;i++) + { rc_num = l_data_buffer_rd64.clearBit(i); + rc_num = l_data_buffer_rd64.setBit(i); + } + if (rc_num){FAPI_ERR( "Error in function addr_gen:");rc.setEcmdError(rc_num);return rc;} + +l_readscom_value = l_data_buffer_rd64.getDoubleWord (0); +FAPI_INF("Debug - Initial End addr for 0x030106d2 = %016llX",l_readscom_value); + +rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_ADDR_MODE, &i_target_mba, l_attr_addr_mode); if(rc) return rc; + +rc = FAPI_ATTR_GET(ATTR_MCBIST_START_ADDR, &i_target_mba, l_start_addr); if(rc) return rc; +FAPI_INF("User Defined ATTR - Start = %016llX",l_start_addr); + +rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_ADDR_MODE, &i_target_mba, l_attr_addr_mode); if(rc) return rc; +rc = FAPI_ATTR_GET(ATTR_MCBIST_END_ADDR, &i_target_mba, l_end); if(rc) return rc; + +FAPI_INF("User defined END ATTR - End Address = %016llX",l_end); + +rc = FAPI_ATTR_GET(ATTR_MCBIST_RANK, &i_target_mba, l_user_end_addr); if(rc) return rc; + +if(l_user_end_addr == 1) +{ + +//Setting start and end Temp + +rc_num = l_data_buffer_rd64.setDoubleWord(0,l_start_addr);if(rc_num) return rc; +rc = fapiPutScom(i_target_mba,0x030106d0,l_data_buffer_rd64); if(rc) return rc; +rc = fapiPutScom(i_target_mba,0x030106d1,l_data_buffer_rd64); if(rc) return rc; + +rc_num = l_data_buffer_rd64.setDoubleWord(0,l_end);if(rc_num) return rc; +rc = fapiPutScom(i_target_mba,0x030106d2,l_data_buffer_rd64); if(rc) return rc; +rc = fapiPutScom(i_target_mba,0x030106d3,l_data_buffer_rd64); if(rc) return rc; +} + +else +{ + +l_attr_addr_mode = 3; + +if(l_attr_addr_mode == 0) +{ + FAPI_INF("ATTR_EFF_SCHMOO_ADDR_MODE - %d ---- Few Address Mode --------",l_attr_addr_mode); + l_sbit = 32; + rc_num = l_data_buffer_rd64.flushTo0(); + l_start = 24; + l_len = 8; + l_value32 = 28; + rc_num=l_data_buffer_rd64.insert(l_value32,l_sbit,l_len,l_start); + rc = fapiPutScom(i_target_mba,0x030106d2,l_data_buffer_rd64); if(rc) return rc; + rc = fapiPutScom(i_target_mba,0x030106d3,l_data_buffer_rd64); if(rc) return rc; + l_readscom_value = l_data_buffer_rd64.getDoubleWord (0); + FAPI_INF("Debug - Final End addr for 0x030106d2 = %016llX",l_readscom_value); +} + +else if(l_attr_addr_mode == 1) +{ + FAPI_INF("ATTR_EFF_SCHMOO_ADDR_MODE - %d ---- QUARTER ADDRESSING Mode --------",l_attr_addr_mode); + l_readscom_value = l_readscom_value >> 2; + FAPI_INF("Debug - Final End addr for 0x030106d2 = %016llX",l_readscom_value); + rc_num = l_data_buffer_rd64.setDoubleWord(0,l_readscom_value);if(rc_num) return rc; + rc = fapiPutScom(i_target_mba,0x030106d2,l_data_buffer_rd64); if(rc) return rc; + rc = fapiPutScom(i_target_mba,0x030106d3,l_data_buffer_rd64); if(rc) return rc; + +} +else if(l_attr_addr_mode == 2) +{ + FAPI_INF("ATTR_EFF_SCHMOO_ADDR_MODE - %d ---- HALF ADDRESSING Mode --------",l_attr_addr_mode); + l_readscom_value = l_readscom_value >> 1; + FAPI_INF("Debug - Final End addr for 0x030106d2 = %016llX",l_readscom_value); + rc_num = l_data_buffer_rd64.setDoubleWord(0,l_readscom_value);if(rc_num) return rc; + rc = fapiPutScom(i_target_mba,0x030106d2,l_data_buffer_rd64); if(rc) return rc; + rc = fapiPutScom(i_target_mba,0x030106d3,l_data_buffer_rd64); if(rc) return rc; +} +else +{ + FAPI_INF("ATTR_EFF_SCHMOO_ADDR_MODE - %d ---- FULL Address Mode --------",l_attr_addr_mode); + FAPI_INF("Debug - Final End addr for 0x030106d2 = %016llX",l_readscom_value); + rc = fapiPutScom(i_target_mba,0x030106d2,l_data_buffer_rd64); if(rc) return rc; + rc = fapiPutScom(i_target_mba,0x030106d3,l_data_buffer_rd64); if(rc) return rc; +} + +} + +return rc; + +} +} diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H index 8016f3d1b..c81fc55fd 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H @@ -20,8 +20,9 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ +// $Id: mss_mcbist_address.H,v 1.3 2013/04/03 14:17:30 bellows Exp $ // *!*************************************************************************** -// *! (C) Copyright International Business Machines Corp. 1997, 1998 +// *! (C) Copyright International Business Machines Corp. 1997, 1998, 2013 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** // *!*************************************************************************** @@ -36,6 +37,7 @@ // CHANGE HISTORY: //------------------------------------------------------------------------------- // Version:|Author: | Date: | Comment: +// 1.3 |bellows |03-Apr-13| Added Id for firmware // --------|--------|---------|-------------------------------------------------- //------------------------------------------------------------------------------ #ifndef MSS_MCBIST_ADDRESS_H diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C index f98cf4289..54db45502 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_mcbist_common.C,v 1.17 2013/01/16 15:16:15 sasethur Exp $ +// $Id: mss_mcbist_common.C,v 1.36 2013/04/09 09:02:14 ppcaelab Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -38,7 +38,20 @@ //------------------------------------------------------------------------------ // Version:|Author: | Date: | Comment: // --------|--------|--------|-------------------------------------------------- -// 1.17 |aditya |01/11/16|Updated setup_mcbist function +// 1.36 |aditya |04/09/13|Updated cfg_byte_mask and setup_mcbist functions +// 1.35 |aditya |03/18/13|Updated cfg_byte_mask and error map functions +// 1.34 |aditya |03/15/13|Added ISDIMM error map +// 1.33 |aditya |03/06/13|Updated Error map and addressing +// 1.32 |aditya |02/27/13|removed Port looping +// 1.29 |aditya |02/19/13|Updated Testtypes and removed rank looping +// 1.26 |aditya |02/13/13|Modified Addressing +// 1.24 |aditya |02/12/13|Modified Addressing +// 1.23 |aditya |02/07/13|Added MBS23 registers +// 1.22 |abhijit |02/06/13|Updated cfg_byte_mask function +// 1.21 |abhijit |01/30/13|Updated cfg_byte_mask function +// 1.20 |aditya |01/30/13|Updated fw comments +// 1.18 |aditya |01/30/13|Updated fw comments +// 1.17 |aditya |01/16/13|Updated setup_mcbist function // 1.16 |aditya |01/11/13|Updated function headers // 1.15 |aditya |01/11/13|added parameters to setup_mcbist function // 1.14 |aditya |01/07/13|Updated Review Comments @@ -58,6 +71,7 @@ //This File mss_mcbist_common.C contains the definition of common procedures for the files mss_mcbist.C and mss_mcbist_lab.C //------------------------------------------------------------------------------ #include "mss_mcbist.H" +#include "mss_mcbist_address.H" #include <mss_access_delay_reg.H> #include <fapiTestHwpDq.H> #include <dimmBadDqBitmapFuncs.H> @@ -108,11 +122,12 @@ const uint64_t FOUR = 0x0000000000000004ull; // uint8_t i_rank Current Rank // ,uint8_t i_bit32 Flag to set bit 32 of register 02011674 //uint64_t i_start Flag to set start address -// uint64_t i_end Flag to set End address +// uint64_t i_end Flag to set End address +//uint8_t new_address_map Flag to Enable Custom Address Map //****************************************************************/ -fapi::ReturnCode setup_mcbist(const fapi::Target & i_target_mba, uint8_t i_port,mcbist_data_gen i_mcbpatt,mcbist_test_mem i_mcbtest,mcbist_byte_mask i_mcbbytemask,uint8_t i_mcbrotate,uint8_t i_pattern,uint8_t i_test_type,uint8_t i_rank,uint8_t i_bit32,uint64_t i_start,uint64_t i_end) +fapi::ReturnCode setup_mcbist(const fapi::Target & i_target_mba, uint8_t i_port,mcbist_data_gen i_mcbpatt,mcbist_test_mem i_mcbtest,mcbist_byte_mask i_mcbbytemask,uint8_t i_mcbrotate,uint8_t i_pattern,uint8_t i_test_type,uint8_t i_rank,uint8_t i_bit32,uint64_t i_start,uint64_t i_end,uint8_t new_address_map) { fapi::ReturnCode rc; @@ -123,8 +138,17 @@ fapi::ReturnCode setup_mcbist(const fapi::Target & i_target_mba, uint8_t i_port ecmdDataBufferBase l_data_bufferx2_64(64); ecmdDataBufferBase l_data_bufferx3_64(64); ecmdDataBufferBase l_data_bufferx4_64(64); + uint64_t io_start_address = 0; + uint64_t io_end_address = 0; + //uint8_t l_addr_inter=0; //ecmdDataBufferBase l_data_buffer_64_1(64); // FAPI_INF("Value of Start is %016llX and end %016llX ",i_start,i_end); + uint8_t l_index = 0; + uint8_t l_index1 = 0; + uint8_t l_flag = 0; + uint64_t scom_array[24] = {0x03010440,0x03010441,0x03010442,0x03010443,0x03010444,0x03010445,0x03010446,0x03010447,0x0201145E,0x0201145F,0x02011460,0x02011461,0x02011462,0x02011463,0x02011464,0x02011465,0x0201149E,0x0201149F,0x020114A0,0x020114A1,0x020114A2,0x020114A3,0x020114A4,0x020114A5}; + + rc = mcb_reset_trap(i_target_mba); if(rc) return rc; @@ -143,29 +167,55 @@ fapi::ReturnCode setup_mcbist(const fapi::Target & i_target_mba, uint8_t i_port rc = fapiPutScom(i_target_mba,0x02011774,l_data_buffer_64);if(rc) return rc; } + + +//FIFO work around for random data +//################################### +//# WRQ and RRQ set to FIFO mode OFF +//################################### +//#WRQ FIFO mode OFF + rc = fapiGetScom(i_target_mba,0x0301040d,l_data_buffer_64); if(rc) return rc; + rc_num = l_data_buffer_64.clearBit(5);if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} + + rc = fapiPutScom(i_target_mba,0x0301040d,l_data_buffer_64); if(rc) return rc; + +//#RRQ FIFO Mode OFF + rc = fapiGetScom(i_target_mba,0x0301040e,l_data_buffer_64); if(rc) return rc; + rc_num = l_data_buffer_64.setBit(6);if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} + + rc_num = l_data_buffer_64.setBit(7);if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} + + rc_num = l_data_buffer_64.setBit(8);if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} + + rc_num = l_data_buffer_64.setBit(9);if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} + + rc_num = l_data_buffer_64.setBit(10);if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} + + rc = fapiPutScom(i_target_mba,0x0301040e,l_data_buffer_64); if(rc) return rc; + +//End +//power bus ECC setting for random data + +//# MBA01_MBA_WRD_MODE - dsibale powerbus ECC checking and correction + rc = fapiGetScom(i_target_mba,0x03010449,l_data_buffer_64); if(rc) return rc; + rc_num = l_data_buffer_64.setBit(0);if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} + rc_num = l_data_buffer_64.setBit(1);if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} + rc_num = l_data_buffer_64.setBit(5);if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x03010449,l_data_buffer_64); if(rc) return rc; +//# MBS_ECC01_MBSECCQ - set EEC checking On but ECC correction OFF + rc = fapiGetScom(i_target_mba,0x0201144a,l_data_buffer_64); if(rc) return rc; + rc_num = l_data_buffer_64.clearBit(0);if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} + rc_num = l_data_buffer_64.setBit(1);if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x0201144a,l_data_buffer_64); if(rc) return rc; + + rc = fapiGetScom(i_target_mba,0x0201148a,l_data_buffer_64); if(rc) return rc; + rc_num = l_data_buffer_64.clearBit(0);if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} + rc_num = l_data_buffer_64.setBit(1);if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x0201148a,l_data_buffer_64); if(rc) return rc; + +//end of power bus ECC setting for random data - - - /* rc = fapiGetScom(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,l_data_buffer_64); if(rc) return rc; - rc_num = rc_num | l_data_buffer_64.flushTo0(); - rc_num = rc_num | l_data_buffer_64.setBit(18); - rc_num = rc_num | l_data_buffer_64.setBit(27); - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8, l_data_buffer_64); if(rc) return rc; - rc = fapiGetScom(i_target_mba, MBA01_MCBIST_MCBSEARA0Q_0x030106d2,l_data_buffer_64);if(rc) return rc; - rc_num = rc_num | l_data_buffer_64.setBit(36); - rc_num = rc_num | l_data_buffer_64.setBit(37); - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBSEARA0Q_0x030106d2,l_data_buffer_64); if(rc) return rc; - - rc = fapiGetScom(i_target_mba, MBA01_MCBIST_MCBSSARA0Q_0x030106d0,l_data_buffer_64); if(rc) return rc; - rc_num = rc_num | l_data_buffer_64.flushTo0(); - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBSSARA0Q_0x030106d0,l_data_buffer_64); if(rc) return rc; - - rc = fapiGetScom(i_target_mba, MBA01_MCBIST_MCBAGRAQ_0x030106d6,l_data_buffer_64); if(rc) return rc; - rc_num = rc_num | l_data_buffer_64.setBit(24); - rc_num = rc_num | l_data_buffer_64.clearBit(25); - rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBAGRAQ_0x030106d6, l_data_buffer_64); if(rc) return rc; - */ rc = fapiGetScom(i_target_mba,MBA01_CCS_MODEQ_0x030106a7, l_data_buffer_64); if(rc) return rc; rc_num = l_data_buffer_64.clearBit(29); if (rc_num){FAPI_ERR( "Error in function setup_mcb:");rc.setEcmdError(rc_num);return rc;} @@ -176,42 +226,59 @@ fapi::ReturnCode setup_mcbist(const fapi::Target & i_target_mba, uint8_t i_port rc_num = rc_num | l_data_buffer_64.flushTo0(); rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBSEARA0Q_0x030106d2,l_data_buffer_64); if(rc) return rc; */ - //rc = print_pattern(i_target_mba);if(rc)return rc; - if((i_test_type == 1) && (i_pattern == 1)) - { - FAPI_INF("User pattern and User test_type modes enabled"); - rc = cfg_mcb_dgen(i_target_mba,USR_MODE,i_mcbrotate); if(rc) return rc; - FAPI_INF("Inside setup mcbist Entering cfg_mcb_addr"); - rc = cfg_mcb_addr(i_target_mba,i_rank,i_port,i_start,i_end);if(rc) return rc; - rc = cfg_mcb_test_mem(i_target_mba,USER_MODE); if(rc) return rc; - } - else if(i_pattern == 1) - { - FAPI_INF("User pattern mode enabled"); - rc = cfg_mcb_dgen(i_target_mba,USR_MODE,i_mcbrotate); if(rc) return rc; - FAPI_INF("Inside setup mcbist Entering cfg_mcb_addr"); - rc = cfg_mcb_addr(i_target_mba,i_rank,i_port,i_start,i_end);if(rc) return rc; - rc = cfg_mcb_test_mem(i_target_mba,i_mcbtest); if(rc) return rc; - } - else if(i_test_type == 1) - { - FAPI_INF(" User test_type mode enabled"); - rc = cfg_mcb_dgen(i_target_mba,i_mcbpatt,i_mcbrotate); if(rc) return rc; - FAPI_INF("Inside setup mcbist Entering cfg_mcb_addr"); - rc = cfg_mcb_addr(i_target_mba,i_rank,i_port,i_start,i_end);if(rc) return rc; - rc = cfg_mcb_test_mem(i_target_mba,USER_MODE); if(rc) return rc; - } - else - { + + + for(l_index = 0;l_index < 24;l_index++) + { + + rc = fapiGetScom(i_target_mba,scom_array[l_index],l_data_buffer_64); if(rc) return rc; + + for(l_index1 = 0;l_index1 < 64;l_index1++) + { + if(l_data_buffer_64.isBitSet(l_index1)) + { + + l_flag = 1; + break; + + } + } + } + + if(l_flag == 1) + { + + FAPI_INF("WARNING: Bit Steering is enabled !!!"); + + } + else + { + FAPI_INF("steer mode is not enabled"); + } + rc = cfg_mcb_dgen(i_target_mba,i_mcbpatt,i_mcbrotate); if(rc) return rc; - FAPI_INF("Inside setup mcbist Entering cfg_mcb_addr"); - rc = cfg_mcb_addr(i_target_mba,i_rank,i_port,i_start,i_end);if(rc) return rc; + + rc = cfg_mcb_test_mem(i_target_mba,i_mcbtest); if(rc) return rc; - } - if(i_mcbbytemask != NONE) + + + //preet + //FAPI_INF("DEBUG-----Print----Address Gen "); + + //if (new_address_map == 1) + //{ + rc = address_generation(i_target_mba,i_port,SF,BANK_RANK,i_rank,io_start_address,io_end_address); + if(rc) {FAPI_INF("BAD - RC ADDR Generation\n");return rc;} + //} + + + + + + if(i_mcbbytemask != NONE) { - rc = cfg_byte_mask(i_target_mba,i_rank,i_port); if(rc) return rc; + rc = cfg_byte_mask(i_target_mba,0,i_port); if(rc) return rc; } @@ -236,15 +303,7 @@ fapi::ReturnCode mcb_reset_trap(const fapi::Target & i_target_mba) FAPI_INF("Function - mcb_reset_trap"); FAPI_INF("Using MCB Reset Trap Function -- This automatically resets error log RA, error counters, Status Reg and error map"); - rc = fapiGetScom(i_target_mba,MBA01_MCBIST_MCBCFGQ_0x030106e0,l_data_buffer_64);if(rc) return rc; - rc_num = l_data_buffer_64.setBit(60);if (rc_num){FAPI_ERR( "Error in function mcb_reset_trap:");rc.setEcmdError(rc_num);return rc;} - //rc = fapiDelay(DELAY_100US, DELAY_2000SIMCYCLES);if(rc) return rc; // wait 2000 simcycles (in sim mode) OR 100 uS (in hw mode) - rc = fapiPutScom(i_target_mba,MBA01_MCBIST_MCBCFGQ_0x030106e0,l_data_buffer_64);if(rc) return rc; - rc_num = l_data_buffer_64.clearBit(60);if (rc_num){FAPI_ERR( "Error in function mcb_reset_trap:");rc.setEcmdError(rc_num);return rc;} - rc = fapiPutScom(i_target_mba,MBA01_MCBIST_MCBCFGQ_0x030106e0,l_data_buffer_64);if(rc) return rc; - //rc = fapiDelay(DELAY_100US, DELAY_2000SIMCYCLES);if(rc) return rc; // wait 2000 simcycles (in sim mode) OR 100 uS (in hw mode) - rc_num = l_data_buffer_64.setBit(60);if (rc_num){FAPI_ERR( "Error in function mcb_reset_trap:");rc.setEcmdError(rc_num);return rc;} - rc = fapiPutScom(i_target_mba,MBA01_MCBIST_MCBCFGQ_0x030106e0,l_data_buffer_64);if(rc) return rc; + //Reset MCB Maintanence register FAPI_INF("Clearing the MCBIST Maintenance "); rc_num = l_data_buffer_64.flushTo0();if (rc_num){FAPI_ERR( "Error in function mcb_reset_trap:");rc.setEcmdError(rc_num);return rc;} @@ -259,7 +318,7 @@ fapi::ReturnCode mcb_reset_trap(const fapi::Target & i_target_mba) rc_num = l_data_buffer_64.clearBit(0,37);if (rc_num){FAPI_ERR( "Error in function mcb_reset_trap:");rc.setEcmdError(rc_num);return rc;} rc = fapiPutScom(i_target_mba,MBA01_MCBIST_RUNTIMECTRQ_0x030106b0,l_data_buffer_64);if(rc) return rc; - FAPI_INF("To clear Port error map registers of both port A and B"); + FAPI_INF("To clear Port error map registers "); rc_num = l_data_buffer_64.flushTo0();if (rc_num){FAPI_ERR( "Error in function mcb_reset_trap:");rc.setEcmdError(rc_num);return rc;} //PORT - A rc = fapiPutScom(i_target_mba,MBS_MCBIST01_MCBEMA1Q_0x0201166a,l_data_buffer_64); if(rc) return(rc); @@ -272,6 +331,27 @@ fapi::ReturnCode mcb_reset_trap(const fapi::Target & i_target_mba) rc = fapiPutScom(i_target_mba,MBS_MCBIST01_MCBEMB3Q_0x0201166f,l_data_buffer_64); if(rc) return(rc); + //MBS23 + //PORT - A + rc = fapiPutScom(i_target_mba,0x0201176a,l_data_buffer_64); if(rc) return(rc); + rc = fapiPutScom(i_target_mba,0x0201176b,l_data_buffer_64); if(rc) return(rc); + rc = fapiPutScom(i_target_mba,0x0201176c,l_data_buffer_64); if(rc) return(rc); + + //PORT - B + rc = fapiPutScom(i_target_mba,0x0201176d,l_data_buffer_64); if(rc) return(rc); + rc = fapiPutScom(i_target_mba,0x0201176e,l_data_buffer_64); if(rc) return(rc); + rc = fapiPutScom(i_target_mba,0x0201176f,l_data_buffer_64); if(rc) return(rc); + + rc = fapiPutScom(i_target_mba,0x02011672,l_data_buffer_64); if(rc) return(rc); + rc = fapiPutScom(i_target_mba,0x02011673,l_data_buffer_64); if(rc) return(rc); + rc = fapiPutScom(i_target_mba,0x02011674,l_data_buffer_64); if(rc) return(rc); + + rc = fapiPutScom(i_target_mba,0x02011772,l_data_buffer_64); if(rc) return(rc); + rc = fapiPutScom(i_target_mba,0x02011773,l_data_buffer_64); if(rc) return(rc); + rc = fapiPutScom(i_target_mba,0x02011774,l_data_buffer_64); if(rc) return(rc); + + + return rc; } @@ -287,11 +367,12 @@ fapi::ReturnCode mcb_reset_trap(const fapi::Target & i_target_mba) fapi::ReturnCode start_mcb(const fapi::Target & i_target_mba) { ecmdDataBufferBase l_data_buffer_64(64); + ecmdDataBufferBase l_data_buffer_trap_64(64); uint8_t l_num_ranks_per_dimm[2][2]; fapi::ReturnCode rc; uint32_t rc_num = 0; FAPI_INF("Function - start_mcb"); - + rc = fapiGetScom(i_target_mba,MBA01_MCBIST_MCBAGRAQ_0x030106d6,l_data_buffer_64); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm); if(rc) return rc; @@ -299,19 +380,19 @@ fapi::ReturnCode start_mcb(const fapi::Target & i_target_mba) if(l_num_ranks_per_dimm[0][0] > 0) { - FAPI_INF("Port AB configured, Socket 0 Configured"); + FAPI_INF(" Socket 0 Configured"); rc_num = l_data_buffer_64.setBit(24);if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} rc_num = l_data_buffer_64.clearBit(25);if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} } else if(l_num_ranks_per_dimm[0][1] > 0) { - FAPI_INF("Port AB configured, Socket 1 Configured"); + FAPI_INF(" Socket 1 Configured"); rc_num = l_data_buffer_64.clearBit(24);if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} rc_num = l_data_buffer_64.setBit(25);if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} } else if((l_num_ranks_per_dimm[0][0] > 0) && (l_num_ranks_per_dimm[0][1] > 0)) { - FAPI_INF("Port AB configured, Socket 0, 1 Configured"); + FAPI_INF(" Socket 0, 1 Configured"); rc_num = l_data_buffer_64.setBit(24);if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} rc_num = l_data_buffer_64.setBit(25);if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} } @@ -335,8 +416,12 @@ fapi::ReturnCode start_mcb(const fapi::Target & i_target_mba) return rc; } - rc_num = l_data_buffer_64.flushTo0();if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} + + + + rc_num = l_data_buffer_64.flushTo0();if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} rc_num = l_data_buffer_64.setBit(0);if (rc_num){FAPI_ERR( "Error in function start_mcb:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,MBA01_MCBIST_MCB_CNTLQ_0x030106db,l_data_buffer_64); if(rc) return rc; //rc = fapiDelay(DELAY_100US, DELAY_2000SIMCYCLES);if(rc) return rc; // wait 2000 simcycles (in sim mode) OR 100 uS (in hw mode) @@ -366,7 +451,8 @@ fapi::ReturnCode poll_mcb(const fapi::Target & i_target_mba,bool i_mcb_stop_on_ fapi::ReturnCode rc; // return value after each SCOM access/buffer modification uint32_t rc_num = 0; ecmdDataBufferBase l_data_buffer_64(64); - ecmdDataBufferBase l_data_buffer1_64(64); + ecmdDataBufferBase l_data_buffer1_64(64); + ecmdDataBufferBase l_data_buffer_trap_64(64); ecmdDataBufferBase l_stop_on_fail_buffer_64(64); //Current status of the MCB (done, fail, in progress) uint8_t l_mcb_done = 0; @@ -375,16 +461,15 @@ fapi::ReturnCode poll_mcb(const fapi::Target & i_target_mba,bool i_mcb_stop_on_ //Time out variables uint64_t l_mcb_timeout = 0; uint32_t l_count = 0; + // Clear to register to zero; - /*uint8_t l_out_4(8); - uint32_t l_out_20(20); - uint64_t l_out_40(40);*/ + FAPI_INF("Function Poll_MCBIST"); - if(i_time <= 0x0000000000000000) + if(i_time == 0x0000000000000000) { i_time = MCB_MAX_TIMEOUT; @@ -398,14 +483,19 @@ fapi::ReturnCode poll_mcb(const fapi::Target & i_target_mba,bool i_mcb_stop_on_ rc = fapiGetScom(i_target_mba,MBA01_MCBIST_MCB_CNTLSTATQ_0x030106dc,l_data_buffer_64); if(rc) return rc; if(l_data_buffer_64.isBitSet(0)) { - //FAPI_INF("MCBIST is in progress_inside poll_mcb"); + l_mcb_ip = 1; } if(l_data_buffer_64.isBitSet(1)) { FAPI_INF("MCBIST is done"); - l_mcb_ip = 0; + l_mcb_ip = 0; l_mcb_done = 1; + + rc = fapiGetScom(i_target_mba,MBA01_MCBIST_MCBCFGQ_0x030106e0,l_data_buffer_trap_64);if(rc) return rc; + rc_num = l_data_buffer_64.clearBit(60);if (rc_num){FAPI_ERR( "Error in function Poll_mcb:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,MBA01_MCBIST_MCBCFGQ_0x030106e0,l_data_buffer_trap_64);if(rc) return rc; + } if(l_data_buffer_64.isBitSet(2)) { @@ -424,6 +514,13 @@ fapi::ReturnCode poll_mcb(const fapi::Target & i_target_mba,bool i_mcb_stop_on_ { l_mcb_ip = 0; l_mcb_done = 1; + + rc = fapiGetScom(i_target_mba,MBA01_MCBIST_MCBCFGQ_0x030106e0,l_data_buffer_trap_64);if(rc) return rc; + rc_num = l_data_buffer_64.clearBit(60);if (rc_num){FAPI_ERR( "Error in function Poll_mcb:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,MBA01_MCBIST_MCBCFGQ_0x030106e0,l_data_buffer_trap_64);if(rc) return rc; + + + FAPI_INF("MCBIST Done"); rc_num = l_stop_on_fail_buffer_64.clearBit(62);if (rc_num){FAPI_ERR( "Error in function poll_mcb:");rc.setEcmdError(rc_num);return rc;} // Clearing bit 61 to avoid breaking after current subtest rc = fapiPutScom(i_target_mba,MBA01_MCBIST_MCBCFGQ_0x030106e0,l_stop_on_fail_buffer_64); if(rc) return rc; @@ -489,24 +586,6 @@ fapi::ReturnCode poll_mcb(const fapi::Target & i_target_mba,bool i_mcb_stop_on_ if (*o_mcb_status == 1) { FAPI_ERR( "poll_mcb:MCBIST failed"); - //rc = fapiGetScom(i_target_mba,0x03010665,l_data_buffer1_64); if(rc) return rc; - /*l_sbit = 0; - l_len = 4; - rc_num= rc_num | l_data_buffer1_64.extractToRight(&l_out_4,l_sbit,l_len); - l_sbit = 5; - l_len = 19; - rc_num= rc_num | l_data_buffer1_64.extractToRight(&l_out_20,l_sbit,l_len); - - - l_sbit = 25; - l_len = 39; - rc_num= rc_num | l_data_buffer1_64.extractToRight(&l_out_40,l_sbit,l_len); - - FAPI_ERR(" FAILURE DETAILS "); - - FAPI_ERR(" subtest_num(0:4) :%X",l_out_4 ); - FAPI_ERR(" cmd number :%05lX",l_out_20 ); - FAPI_ERR(" trap addr(0:38) :%08llX",l_out_40 );*/ FAPI_SET_HWP_ERROR(rc,RC_MSS_MCBIST_ERROR); return rc; } @@ -530,112 +609,109 @@ fapi::ReturnCode poll_mcb(const fapi::Target & i_target_mba,bool i_mcb_stop_on_ // uint8_t o_error_map[][8][10][2] Contains the error map //****************************************************************/ -fapi::ReturnCode mcb_error_map_print(const fapi::Target & i_target_mba,uint8_t i_port,uint8_t i_rank,ecmdDataBufferBase & l_mcb_fail_320) +fapi::ReturnCode mcb_error_map_print(const fapi::Target & i_target_mba,uint8_t i_port,uint8_t i_rank,ecmdDataBufferBase & l_mcb_fail_160) { ReturnCode rc; uint8_t l_num_ranks_per_dimm[MAX_PORT][MAX_PORT]; - uint8_t l_rankpair_table[MAX_RANK] = {0}; + uint8_t l_rankpair_table[MAX_RANK] ; uint8_t l_cur_rank =0; - uint8_t l_cur_dram =0; - uint8_t l_max_rank = 0; + uint16_t l_index0,l_index1,l_byte,l_nibble; + uint8_t l_max_rank = 0; uint8_t l_rank_pair = 0; char l_str1[200] = ""; - uint8_t l_index = 0; + ecmdDataBufferBase l_mcb(64); + i_rank = 0; + //uint64_t start; + //uint32_t rc_num; uint8_t l_mbaPosition = 0; + //uint8_t l_attr_eff_dimm_type_u8 = 0; + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbaPosition); - //uint8_t l_dimmtype = 0; - //rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, l_dimmtype); if(rc) return rc; - // if(l_dimmtype==1) - // { + rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm); if(rc) return rc; + l_max_rank=l_num_ranks_per_dimm[i_port][0]+l_num_ranks_per_dimm[i_port][1]; - // return rc; - // } - if(i_port == 0) + if(l_max_rank == 0) { - if(l_mbaPosition ==0) - { - FAPI_INF("################# PortA Error MAP #################\n"); - FAPI_INF("################# MBA01 ###########################\n"); + FAPI_INF(" NO RANK FOUND ON PORT %d ",i_port); + return rc; } else { - FAPI_INF("################# PortA Error MAP #################\n"); - FAPI_INF("################# MBA023 ###########################\n"); - } + for(l_cur_rank = 0;l_cur_rank < l_max_rank;l_cur_rank++) + { + i_rank = l_rankpair_table[l_cur_rank]; + if(i_rank>MAX_RANK) + { + break; + } + } } - if(i_port == 1) - { - if(l_mbaPosition ==0) + if(i_port == 0) { - FAPI_INF("################# PortB Error MAP #################\n"); - FAPI_INF("################# MBA01 ###########################\n"); + if(l_mbaPosition == 0) + { + FAPI_INF("################# MBA01 ###########################\n"); + FAPI_INF("################# PORT0 ERROR MAP #################\n"); + } + else + { + FAPI_INF("################# MBA23 ###########################\n"); + FAPI_INF("################# PORT0 ERROR MAP #################\n"); + } + } - else + else if(i_port == 1) { - FAPI_INF("################# PortB Error MAP #################\n"); - FAPI_INF("################# MBA023 ###########################\n"); - } + + if(l_mbaPosition ==0) + { + FAPI_INF("################# MBA01 ###########################\n"); + FAPI_INF("################# PORT1 ERROR MAP #################\n"); + } + else + { + FAPI_INF("################# MBA23 ###########################\n"); + FAPI_INF("################# PORT1 ERROR MAP #################\n"); + } } + + //FAPI_INF(" --------------------"); FAPI_INF("Byte 00112233445566778899"); - FAPI_INF(" --------------------"); - FAPI_INF("Nibble 00000000001111111111"); - FAPI_INF("Nibble 01234567890123456789"); - - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm); if(rc) return rc; - l_max_rank=l_num_ranks_per_dimm[i_port][0]+l_num_ranks_per_dimm[i_port][1]; - rc = mss_getrankpair(i_target_mba,i_port,0,&l_rank_pair,l_rankpair_table); if(rc) return rc; - - if(l_max_rank > MAX_RANK) - { - FAPI_ERR(" Maximum ranks available exceeded 8"); - FAPI_SET_HWP_ERROR(rc, RC_MSS_INPUT_ERROR); - - return rc; - } + FAPI_INF("Nibble 01010101010101010101"); + + rc = mss_getrankpair(i_target_mba,i_port,0,&l_rank_pair,l_rankpair_table); if(rc) return rc; for(l_cur_rank = 0;l_cur_rank < l_max_rank;l_cur_rank++) - { - if(i_rank == l_rankpair_table[l_cur_rank]) - { - sprintf(l_str1,"%-4s%d%5s","RANK",l_rankpair_table[l_cur_rank],""); - for(l_cur_dram = 0; l_cur_dram < MAX_DRAM; l_cur_dram++) + { + i_rank = l_rankpair_table[l_cur_rank]; + sprintf(l_str1,"%-4s%d%5s","RANK",i_rank,""); + for(l_byte = 0; l_byte < MAX_BYTE; l_byte++) { - - if(i_port == 1) - { - l_index = (l_rankpair_table[l_cur_rank])*(MAX_DRAM) + l_cur_dram + 160; - } - - if(i_port == 0) - { - l_index = (l_rankpair_table[l_cur_rank])*(MAX_DRAM) + l_cur_dram ; - } - - - - - if(l_mcb_fail_320.isBitSet(l_index)) - { - + for(l_nibble = 0; l_nibble < MAX_NIBBLES; l_nibble++) + { + + l_index0 = (i_rank*20) + (l_byte*2) + l_nibble; + // l_index1 = l_index0 + 160*(i_port); + l_index1 = l_index0; + if(l_mcb_fail_160.isBitSet(l_index1)) + { strcat(l_str1,"X"); } else - { - + { strcat(l_str1,"."); - } - } + } + } + } + FAPI_INF("%s",l_str1); + } + - - FAPI_INF("%s",l_str1); - break; - } - } return rc; } @@ -644,7 +720,6 @@ return rc; - /*****************************************************************/ // Funtion name : mcb_error_map // Description : Reads the nibblewise Error map registers into o_error_map @@ -661,31 +736,38 @@ fapi::ReturnCode mcb_error_map(const fapi::Target & i_target_mba, uint8_t o_er ecmdDataBufferBase l_mcbem2ab(64); ecmdDataBufferBase l_mcbem3ab(64); ecmdDataBufferBase l_data_buffer_64(64); - ecmdDataBufferBase l_data_buffer1_64(64); - ecmdDataBufferBase l_mcb_fail_320(320); - - - + ecmdDataBufferBase l_mcb_fail_320(320); + ecmdDataBufferBase l_mcb_fail_160(160); + ecmdDataBufferBase l_mcb_fail1_160(160); + ecmdDataBufferBase l_mcb(64); + + uint8_t l_max_rank0,l_max_rank1; + + //#################### fapi::Target i_target_centaur ; //#################### fapi::ReturnCode rc; uint32_t rc_num = 0; - //uint8_t l_cur_rank =0; - //uint8_t l_cur_dram =0; - uint8_t l_index0 = 0; - uint8_t l_index1 = 0; + uint16_t l_index0 = 0; + uint32_t l_index1 = 0; uint8_t l_port = 0; uint8_t l_rank = 0; uint8_t l_byte = 0; uint8_t l_nibble = 0; uint8_t l_num_ranks_per_dimm[MAX_PORT][MAX_PORT]; - // uint8_t l_max_rank = 0; - // uint8_t l_rankpair_table[MAX_RANK] = {0}; - //uint8_t l_rank_pair = 0; + //uint64_t start; uint8_t l_mbaPosition = 0; + uint8_t rank_pair,i_byte,i_nibble,i_input_index_u8,o_val,i_byte1,i_nibble1; + input_type l_input_type_e = ISDIMM_DQ; + uint8_t valid_rank[MAX_RANK] ; + char l_str[200] = ""; + uint8_t l_max_bytes=9; + uint8_t l_max_rank; + uint8_t l_attr_eff_dimm_type_u8; FAPI_INF("Function MCB_ERROR_MAP"); + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbaPosition); if(rc) { @@ -693,65 +775,88 @@ fapi::ReturnCode mcb_error_map(const fapi::Target & i_target_mba, uint8_t o_er } - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm); if(rc) return rc; + + l_max_rank0=l_num_ranks_per_dimm[0][0]+l_num_ranks_per_dimm[0][1]; + l_max_rank1=l_num_ranks_per_dimm[1][0]+l_num_ranks_per_dimm[1][1]; + rc = fapiGetParentChip(i_target_mba, i_target_centaur); if (rc) { FAPI_ERR("Error in getting Parent Chiplet"); return rc; } - - rc = fapiGetScom(i_target_centaur,MBS_MCBIST01_MCBEMA1Q_0x0201166a,l_mcbem1ab); if(rc) return rc; - rc_num = l_mcb_fail_320.insert(l_mcbem1ab,0,60,0);if (rc_num){FAPI_ERR( "Error in function mcb_error_map:");rc.setEcmdError(rc_num);return rc;} + + + if(l_mbaPosition == 0) + { + + + rc = fapiGetScom(i_target_centaur,MBS_MCBIST01_MCBEMA1Q_0x0201166a,l_mcbem1ab); if(rc) return rc; + rc_num = l_mcb_fail_160.insert(l_mcbem1ab,0,60,0);if (rc_num){FAPI_ERR( "Error in function mcb_error_map:");rc.setEcmdError(rc_num);return rc;} rc = fapiGetScom(i_target_centaur,MBS_MCBIST01_MCBEMA2Q_0x0201166b,l_mcbem2ab); if(rc) return rc; - rc_num = l_mcb_fail_320.insert(l_mcbem2ab,60,60,0);if (rc_num){FAPI_ERR( "Error in function mcb_error_map:");rc.setEcmdError(rc_num);return rc;} + rc_num = l_mcb_fail_160.insert(l_mcbem2ab,60,60,0);if (rc_num){FAPI_ERR( "Error in function mcb_error_map:");rc.setEcmdError(rc_num);return rc;} rc = fapiGetScom(i_target_centaur,MBS_MCBIST01_MCBEMA3Q_0x0201166c,l_mcbem3ab); if(rc) return rc; - rc_num = l_mcb_fail_320.insert(l_mcbem3ab,120,40,0);if (rc_num){FAPI_ERR( "Error in function mcb_error_map:");rc.setEcmdError(rc_num);return rc;} - - - //rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm); if(rc) return rc; - //l_max_rank=l_num_ranks_per_dimm[0][0]+l_num_ranks_per_dimm[0][1]; - // rc = mss_getrankpair(i_target_mba,i_port,0,&l_rank_pair,l_rankpair_table); if(rc) return rc; - - /*if(l_max_rank > MAX_RANK) - { - FAPI_ERR(" Maximum ranks available exceeded 8"); - FAPI_SET_HWP_ERROR(rc, RC_MSS_INPUT_ERROR); - return rc; - }*/ - if(i_port == 0) - { - - mcb_error_map_print( i_target_mba ,i_port, i_rank, l_mcb_fail_320); - - } + rc_num = l_mcb_fail_160.insert(l_mcbem3ab,120,40,0);if (rc_num){FAPI_ERR( "Error in function mcb_error_map:");rc.setEcmdError(rc_num);return rc;} rc = fapiGetScom(i_target_centaur,MBS_MCBIST01_MCBEMB1Q_0x0201166d,l_mcbem1ab); if(rc) return rc; - rc_num = l_mcb_fail_320.insert(l_mcbem1ab,160,60,0);if (rc_num){FAPI_ERR( "Error in function mcb_error_map:");rc.setEcmdError(rc_num);return rc;} + rc_num = l_mcb_fail1_160.insert(l_mcbem1ab,0,60,0);if (rc_num){FAPI_ERR( "Error in function mcb_error_map:");rc.setEcmdError(rc_num);return rc;} rc = fapiGetScom(i_target_centaur,MBS_MCBIST01_MCBEMB2Q_0x0201166e,l_mcbem2ab); if(rc) return rc; - rc_num = l_mcb_fail_320.insert(l_mcbem2ab,220,60,0);if (rc_num){FAPI_ERR( "Error in function mcb_error_map:");rc.setEcmdError(rc_num);return rc;} + rc_num = l_mcb_fail1_160.insert(l_mcbem2ab,60,60,0);if (rc_num){FAPI_ERR( "Error in function mcb_error_map:");rc.setEcmdError(rc_num);return rc;} rc = fapiGetScom(i_target_centaur,MBS_MCBIST01_MCBEMB3Q_0x0201166f,l_mcbem3ab); if(rc) return rc; - rc_num = l_mcb_fail_320.insert(l_mcbem3ab,280,40,0);if (rc_num){FAPI_ERR( "Error in function mcb_error_map:");rc.setEcmdError(rc_num);return rc;} - //Restore values - - if(i_port == 1) - { - mcb_error_map_print(i_target_mba, i_port, i_rank, l_mcb_fail_320); + rc_num = l_mcb_fail1_160.insert(l_mcbem3ab,120,40,0);if (rc_num){FAPI_ERR( "Error in function mcb_error_map:");rc.setEcmdError(rc_num);return rc;} } - //Need to check the DIMM plugged in and decide the rank? - Implement that. - - for (l_port = 0; l_port < MAX_PORT ; l_port++) + else if(l_mbaPosition==1) + { + + + rc = fapiGetScom(i_target_centaur,0x0201176a,l_mcbem1ab); if(rc) return rc; + rc_num = l_mcb_fail_160.insert(l_mcbem1ab,0,60,0);if (rc_num){FAPI_ERR( "Error in function mcb_error_map:");rc.setEcmdError(rc_num);return rc;} + rc = fapiGetScom(i_target_centaur,0x0201176b,l_mcbem2ab); if(rc) return rc; + rc_num = l_mcb_fail_160.insert(l_mcbem2ab,60,60,0);if (rc_num){FAPI_ERR( "Error in function mcb_error_map:");rc.setEcmdError(rc_num);return rc;} + rc = fapiGetScom(i_target_centaur,0x0201176c,l_mcbem3ab); if(rc) return rc; + rc_num = l_mcb_fail_160.insert(l_mcbem3ab,120,40,0);if (rc_num){FAPI_ERR( "Error in function mcb_error_map:");rc.setEcmdError(rc_num);return rc;} + rc = fapiGetScom(i_target_centaur,0x0201176d,l_mcbem1ab); if(rc) return rc; + rc_num = l_mcb_fail1_160.insert(l_mcbem1ab,0,60,0);if (rc_num){FAPI_ERR( "Error in function mcb_error_map:");rc.setEcmdError(rc_num);return rc;} + rc = fapiGetScom(i_target_centaur,0x0201176e,l_mcbem2ab); if(rc) return rc; + rc_num = l_mcb_fail1_160.insert(l_mcbem2ab,60,60,0);if (rc_num){FAPI_ERR( "Error in function mcb_error_map:");rc.setEcmdError(rc_num);return rc;} + rc = fapiGetScom(i_target_centaur,0x0201176f,l_mcbem3ab); if(rc) return rc; + rc_num = l_mcb_fail1_160.insert(l_mcbem3ab,120,40,0);if (rc_num){FAPI_ERR( "Error in function mcb_error_map:");rc.setEcmdError(rc_num);return rc;} + + } + + + for (l_port = 0; l_port < MAX_PORT ; l_port++) { - for(l_rank = 0; l_rank < MAX_RANK; l_rank++) + rc = mss_getrankpair(i_target_mba,l_port,0,&rank_pair,valid_rank);if(rc) return rc; + + if(l_port == 0) + { + l_max_rank = l_max_rank0; + } + else + { + l_max_rank = l_max_rank1; + } + + for(l_rank = 0; l_rank < l_max_rank; l_rank++) { + + + i_rank=valid_rank[l_rank]; + for(l_byte = 0; l_byte < MAX_BYTE; l_byte++) { for(l_nibble = 0; l_nibble < MAX_NIBBLES; l_nibble++) { - l_index0 = (l_rank*20) + (l_byte*2) + l_nibble; - l_index1 = l_index0 + 160*(l_port); - if((l_mcb_fail_320.isBitSet(l_index1))) + if(l_port == 0) + { + l_index0 = (i_rank*20) + (l_byte*2) + l_nibble; + //l_index1 = l_index0 + 160*(l_port); + l_index1 = l_index0; + + if((l_mcb_fail_160.isBitSet(l_index1))) { o_error_map[l_port][l_rank][l_byte][l_nibble] = 1; } @@ -759,22 +864,111 @@ fapi::ReturnCode mcb_error_map(const fapi::Target & i_target_mba, uint8_t o_er { o_error_map[l_port][l_rank][l_byte][l_nibble] = 0; } - + } + else if(l_port == 1) + { + + l_index0 = (i_rank*20) + (l_byte*2) + l_nibble; + //l_index1 = l_index0 + 160*(l_port); + l_index1 = l_index0; + if((l_mcb_fail1_160.isBitSet(l_index1))) + { + + o_error_map[l_port][l_rank][l_byte][l_nibble] = 1; + } + else + { + o_error_map[l_port][l_rank][l_byte][l_nibble] = 0; + + } + } } } } } - - /* rc = fapiGetScom(i_target_mba,0x03010665,l_data_buffer1_64); if(rc) return rc; - rc = fapiGetScom(i_target_mba,0x03010666,l_data_buffer1_64); if(rc) return rc; - rc = fapiGetScom(i_target_mba,0x03010667,l_data_buffer1_64); if(rc) return rc; - rc = fapiGetScom(i_target_mba,0x03010668,l_data_buffer1_64); if(rc) return rc; - rc = fapiGetScom(i_target_mba,0x03010669,l_data_buffer1_64); if(rc) return rc; - rc = fapiGetScom(i_target_mba,0x0301066a,l_data_buffer1_64); if(rc) return rc; - rc = fapiGetScom(i_target_mba,0x0301066b,l_data_buffer1_64); if(rc) return rc; - rc = fapiGetScom(i_target_mba,0x0301066c,l_data_buffer1_64); if(rc) return rc;*/ + rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, l_attr_eff_dimm_type_u8); if(rc) return rc; + //ISDIMM error map + //uint8_t l_max_ranks =8; + + if((l_attr_eff_dimm_type_u8 == 1) || (l_attr_eff_dimm_type_u8 == 3)) //Calling ISDIMM error mAP and LRDIMM + { + FAPI_INF("################# Error MAP for ISDIMM #################"); + for(l_port = 0; l_port < 2; l_port++) + { + if(l_port == 0) + { + l_max_rank = l_max_rank0; + } + else + { + l_max_rank = l_max_rank1; + } + if(l_max_rank == 0) + { + FAPI_INF(" NO RANKS FOUND ON PORT %d",l_port); + } + else + { + if(l_mbaPosition ==0) + { + FAPI_INF("################# MBA01 ###########################\n"); + FAPI_INF("################# PORT%d ERROR MAP #################\n",l_port); + } + else + { + FAPI_INF("################# MBA23 ###########################\n"); + FAPI_INF("################# PORT%d ERROR MAP #################\n",l_port); + } + //FAPI_INF(" ------------------"); + FAPI_INF("Byte 001122334455667788"); + FAPI_INF("Nibble 010101010101010101"); + for(l_rank = 0; l_rank < l_max_rank; l_rank++) + { + //FAPI_INF("Rank %d",i_rank); + rc = mss_getrankpair(i_target_mba,l_port,0,&rank_pair,valid_rank);if(rc) return rc; + i_rank=valid_rank[l_rank]; + sprintf(l_str,"%-4s%d%5s","RANK",i_rank,""); + for( i_byte = 0;i_byte < l_max_bytes ;i_byte++) + { + for (i_nibble = 0;i_nibble < 2;i_nibble++) + { + i_input_index_u8=(8*i_byte)+(4*i_nibble); + rc=rosetta_map(i_target_mba,l_port,l_input_type_e,i_input_index_u8,0,o_val);if(rc) return rc; + i_byte1=o_val/8; + i_nibble1=o_val%8; + if(i_nibble1>3){ + i_nibble1=1; + }else{ + i_nibble1=0; + } + if( o_error_map[l_port][l_rank][i_byte1][i_nibble1] == 1){ + + strcat(l_str,"X"); + } + else + { + + strcat(l_str,"."); + } + } + } + FAPI_INF("%s",l_str); + } + } + } + } + + else //Calling CDIMM error Map print + { + i_port = 0; + mcb_error_map_print( i_target_mba ,i_port, i_rank, l_mcb_fail_160); + i_port = 1; + mcb_error_map_print(i_target_mba, i_port, i_rank, l_mcb_fail1_160); + } + + //End return rc; } /*****************************************************************/ @@ -854,50 +1048,93 @@ fapi::ReturnCode mcb_write_test_mem(const fapi::Target & i_target_mba,const uin // uint8_t i_rank Current Rank // uint8_t i_port Current Port //****************************************************************/ + + + fapi::ReturnCode cfg_byte_mask(const fapi::Target & i_target_mba,uint8_t i_rank,uint8_t i_port) { - + uint32_t rc_num; + uint8_t l_port=0; uint8_t l_dimm=0; - ecmdDataBufferBase l_data_buffer1_64(64); + uint8_t l_rank=0; + uint8_t l_max_0 =0; + uint8_t l_max_1 =0; + fapi::ReturnCode rc; + uint8_t l_rnk=0; + uint8_t num_ranks_per_dimm[2][2]; + uint8_t l_MAX_RANKS=8; + uint8_t rank_pair=0; + uint64_t l_var = 0xFFFFFFFFFFFFFFFFull; + uint16_t l_spare = 0xFFFF; + ecmdDataBufferBase l_data_buffer1_64(64); + uint8_t valid_rank[l_MAX_RANKS]; + //rc = mss_getrankpair(i_target_mba,l_port,0,&rank_pair,valid_rank);if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, num_ranks_per_dimm); if(rc) return rc; + uint8_t l_mbaPosition = 0; + uint8_t l_attr_eff_dimm_type_u8 = 0; + rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, l_attr_eff_dimm_type_u8); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbaPosition); + + //l_attr_eff_dimm_type_u8=1; + + for(l_port=0;l_port<2;l_port++){ + l_MAX_RANKS=num_ranks_per_dimm[l_port][0]+num_ranks_per_dimm[l_port][1]; + rc = mss_getrankpair(i_target_mba,l_port,0,&rank_pair,valid_rank);if(rc) return rc; + + for(l_rank=0;l_rank< l_MAX_RANKS;l_rank++){ + l_rnk=valid_rank[l_rank]; + if (l_rnk == 255){ + continue ; + } + ecmdDataBufferBase l_data_buffer2_64(64); ecmdDataBufferBase l_data_buffer3_64(64); - - - fapi::ReturnCode rc; - uint32_t rc_num = 0; + + l_max_0 = num_ranks_per_dimm[0][0]+num_ranks_per_dimm[0][1]; + + l_max_1 = num_ranks_per_dimm[1][0]+num_ranks_per_dimm[1][1]; + +//SW198827 uint32_t __attribute__((unused)) rc_num = 0; - rc_num = l_data_buffer3_64.flushTo1();if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} + rc_num = l_data_buffer3_64.flushTo0();if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} uint8_t l_dqBitmap[DIMM_DQ_RANK_BITMAP_SIZE]; uint8_t l_dq[8]={0}; - uint8_t l_sp[2]={0}; - uint8_t l_index0=0; + uint16_t l_sp[2]={0}; + uint16_t l_index0=0; uint8_t l_index_sp=0; - uint16_t l_sp_mask=0xffff; + //uint16_t l_sp_mask=0x0000; + uint16_t l_sp_isdimm=0xff; + FAPI_INF("Function cfg_byte_mask"); - if(i_rank>3) + if(l_rnk>3) { l_dimm=1; - i_rank=4-i_rank; + l_rnk=l_rnk-4; } else { l_dimm=0; } - rc = dimmGetBadDqBitmap(i_target_mba, i_port, l_dimm, i_rank,l_dqBitmap);if(rc) return rc; + rc = dimmGetBadDqBitmap(i_target_mba, l_port, l_dimm, l_rnk,l_dqBitmap);if(rc) return rc; for ( l_index0 = 0; l_index0 < DIMM_DQ_RANK_BITMAP_SIZE; l_index0++) { if(l_index0<8) { l_dq[l_index0]=l_dqBitmap[l_index0]; - FAPI_INF("\n the bad dq=%x ",l_dqBitmap[l_index0]); + if(l_dqBitmap[l_index0]){ + FAPI_INF("\n the port=%d bad dq=%x on dq=%d",l_port,l_dqBitmap[l_index0],l_index0); + } } else { + if(l_dqBitmap[l_index0]){ + FAPI_INF("\n the port=%d bad dq=%x on dq=%d",l_port,l_dqBitmap[l_index0],l_index0); + } l_sp[l_index_sp]=l_dqBitmap[l_index0]; l_index_sp++; } @@ -905,352 +1142,136 @@ fapi::ReturnCode cfg_byte_mask(const fapi::Target & i_target_mba,uint8_t i_rank rc_num = l_data_buffer1_64.insertFromRight(l_dq,0,64);if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} - // rc_num = l_data_buffer2_64.insertFromRight(l_sp,0,16);if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} + //rc_num = l_data_buffer2_64.insertFromRight(l_sp,0,16);if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} - if(i_port == 0) + if(l_mbaPosition == 0) + { + if(l_port == 0) { + if((l_attr_eff_dimm_type_u8 == 1) || (l_attr_eff_dimm_type_u8 == 3)){ + rc_num = l_data_buffer2_64.insertFromRight(l_sp_isdimm,8,8);if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} + rc_num = l_data_buffer2_64.insertFromRight(l_sp,0,8);if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} + }else{ rc_num = l_data_buffer2_64.insertFromRight(l_sp,0,16);if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} - rc_num = l_data_buffer2_64.insertFromRight(l_sp_mask,16,16);if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} + } + //rc_num = l_data_buffer2_64.insertFromRight(l_sp_mask,16,16);if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} rc = fapiPutScom(i_target_mba,MBS_MCBIST01_MCBCMA1Q_0x02011672,l_data_buffer1_64); if(rc) return rc; rc = fapiPutScom(i_target_mba,MBS_MCBIST01_MCBCMABQ_0x02011674,l_data_buffer2_64); if(rc) return rc; - rc = fapiPutScom(i_target_mba,MBS_MCBIST01_MCBCMB1Q_0x02011673,l_data_buffer3_64); if(rc) return rc; + //rc = fapiPutScom(i_target_mba,MBS_MCBIST01_MCBCMB1Q_0x02011673,l_data_buffer3_64); if(rc) return rc; } else { + rc = fapiGetScom(i_target_mba,MBS_MCBIST01_MCBCMABQ_0x02011674,l_data_buffer2_64); if(rc) return rc; + //rc = fapiGetScom(i_target_mba,MBS_MCBIST01_MCBCMA1Q_0x02011672,l_data_buffer3_64); if(rc) return rc; + if((l_attr_eff_dimm_type_u8 == 1) || (l_attr_eff_dimm_type_u8 == 3)){ + rc_num = l_data_buffer2_64.insertFromRight(l_sp_isdimm,24,8);if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} + rc_num = l_data_buffer2_64.insertFromRight(l_sp,16,8);if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} + }else{ rc_num = l_data_buffer2_64.insertFromRight(l_sp,16,16);if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} - rc_num = l_data_buffer2_64.insertFromRight(l_sp_mask,0,16);if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} + } + + //rc_num = l_data_buffer2_64.insertFromRight(l_sp_mask,0,16);if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} rc = fapiPutScom(i_target_mba,MBS_MCBIST01_MCBCMB1Q_0x02011673,l_data_buffer1_64); if(rc) return rc; rc = fapiPutScom(i_target_mba,MBS_MCBIST01_MCBCMABQ_0x02011674,l_data_buffer2_64); if(rc) return rc; - rc = fapiPutScom(i_target_mba,MBS_MCBIST01_MCBCMA1Q_0x02011672,l_data_buffer3_64); if(rc) return rc; + //rc = fapiPutScom(i_target_mba,MBS_MCBIST01_MCBCMA1Q_0x02011672,l_data_buffer3_64); if(rc) return rc; } - - - return rc; -} -/*****************************************************************/ -// Funtion name : addr_gen_func -// Description : Based on the Schmoo Address Mode this function decides the address range on which MCBIST must operate -// Input Parameters : -// const fapi::Target & Centaur.mba -// mcbist_addr_mode i_addr_mode MCBIST address mode -// uint8_t i_attr_eff_schmoo_addr_mode Schmoo address mode -// Output Parameters : -// uint64_t &io_end_address End address of MCBIST -// uint64_t &io_start_address Start address of MCBIST -// uint8_t i_rank Current Rank -// uint8_t i_port Current Port -//****************************************************************/ - -fapi::ReturnCode addr_gen_func(const fapi::Target & i_target_mba, mcbist_addr_mode i_addr_mode, uint8_t i_attr_eff_schmoo_addr_mode ,uint64_t &io_end_address,uint64_t &io_start_address,uint8_t i_rank,uint8_t i_port) -{ - fapi::ReturnCode rc; - //uint8_t l_rank = 0; - // uint8_t l_cur_rank = 0; - uint8_t l_rankpair_table[8]; - FAPI_INF("Function mss_address_gen"); - uint64_t l_end_address = io_end_address; - uint64_t l_start_address = io_start_address; - uint64_t l_diff_address = 0; - uint64_t l_diff_address1 = 0; - uint64_t l_addr1 = 0; - uint64_t l_addr2 = 0; - uint8_t l_num_ranks_per_dimm[MAX_PORT][MAX_PORT]; - uint8_t l_max_rank = 0; - //uint8_t i_port = 0; - uint8_t l_rank_pair = 0; - //uint8_t i = 0; - uint8_t l_compare = 0; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm); if(rc) return rc; - l_max_rank=l_num_ranks_per_dimm[i_port][0]+l_num_ranks_per_dimm[i_port][1]; - rc = mss_getrankpair(i_target_mba,i_port,0,&l_rank_pair,l_rankpair_table); if(rc) return rc; - - //FAPI_INF("FLAG 111 value of start and end addr is %016llX and %016llX",io_start_address,io_end_address); - - if(l_max_rank > MAX_RANK) + }else { - FAPI_ERR(" Maximum ranks available exceeded 8"); - FAPI_SET_HWP_ERROR(rc, RC_MSS_INPUT_ERROR); - return rc; + if(l_port == 0) + { + if((l_attr_eff_dimm_type_u8 == 1) || (l_attr_eff_dimm_type_u8 == 3)){ + rc_num = l_data_buffer2_64.insertFromRight(l_sp_isdimm,8,8);if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} + rc_num = l_data_buffer2_64.insertFromRight(l_sp,0,8);if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} + }else{ + rc_num = l_data_buffer2_64.insertFromRight(l_sp,0,16);if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} + } + //rc_num = l_data_buffer2_64.insertFromRight(l_sp_mask,16,16);if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x02011772,l_data_buffer1_64); if(rc) return rc; + rc = fapiPutScom(i_target_mba,0x02011774,l_data_buffer2_64); if(rc) return rc; + //rc = fapiPutScom(i_target_mba,0x02011773,l_data_buffer3_64); if(rc) return rc; + } + else + { + rc = fapiGetScom(i_target_mba,0x02011774,l_data_buffer2_64); if(rc) return rc; + if((l_attr_eff_dimm_type_u8 == 1) || (l_attr_eff_dimm_type_u8 == 3)){ + rc_num = l_data_buffer2_64.insertFromRight(l_sp_isdimm,24,8);if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} + rc_num = l_data_buffer2_64.insertFromRight(l_sp,16,8);if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} + }else{ + rc_num = l_data_buffer2_64.insertFromRight(l_sp,16,16);if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} + } + + //rc_num = l_data_buffer2_64.insertFromRight(l_sp_mask,0,16);if (rc_num){FAPI_ERR( "Error in function cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;} + rc = fapiPutScom(i_target_mba,0x02011773,l_data_buffer1_64); if(rc) return rc; + rc = fapiPutScom(i_target_mba,0x02011774,l_data_buffer2_64); if(rc) return rc; + //rc = fapiPutScom(i_target_mba,0x02011772,l_data_buffer3_64); if(rc) return rc; + } + } + } } - /* for(l_cur_rank = 0;l_cur_rank < l_max_rank;l_cur_rank++) + + + + + + if(l_max_0 == 0) { - if(i_rank == l_rankpair_table[l_cur_rank]) + if(l_mbaPosition == 0) { - l_rank = l_cur_rank; - break; + rc = fapiGetScom(i_target_mba,0x02011672,l_data_buffer1_64); if(rc) return rc; + rc_num = l_data_buffer1_64.setDoubleWord(0,l_var); + rc = fapiPutScom(i_target_mba,0x02011672,l_data_buffer1_64); if(rc) return rc; + rc = fapiGetScom(i_target_mba,0x02011674,l_data_buffer1_64); if(rc) return rc; + rc_num = l_data_buffer1_64.insertFromRight(l_spare,0,16); + rc = fapiPutScom(i_target_mba,0x02011674,l_data_buffer1_64); if(rc) return rc; } - } */ - FAPI_INF("Shmoo Addressing mode is %d ",i_attr_eff_schmoo_addr_mode); - //l_cur_rank = 0; - - if(i_addr_mode == SF) - { - l_addr1 = l_start_address; - l_addr2 = l_end_address; - } - else if(i_addr_mode == SR) - { - l_addr1 = l_end_address; - l_addr2 = l_start_address; + else + { + + rc = fapiGetScom(i_target_mba,0x02011772,l_data_buffer1_64); if(rc) return rc; + rc_num = l_data_buffer1_64.setDoubleWord(0,l_var); + rc = fapiPutScom(i_target_mba,0x02011772,l_data_buffer1_64); if(rc) return rc; + rc = fapiGetScom(i_target_mba,0x02011774,l_data_buffer1_64); if(rc) return rc; + rc_num = l_data_buffer1_64.insertFromRight(l_spare,0,16); + rc = fapiPutScom(i_target_mba,0x02011774,l_data_buffer1_64); if(rc) return rc; + + } } - else + + if(l_max_1 == 0) { - FAPI_INF("Wrong Shmoo address mode"); - FAPI_SET_HWP_ERROR(rc, RC_MSS_INPUT_ERROR); - return rc; - } - - if(i_attr_eff_schmoo_addr_mode == FEW_ADDR) + if(l_mbaPosition == 0) { - // FAPI_INF("Value 0 of Start is %016llX and Diff %016llX",l_addr1,l_addr2); - - l_diff_address = l_addr2 - l_addr1; - - /*for(i=0;i<l_rank;i++) + + rc = fapiGetScom(i_target_mba,0x02011673,l_data_buffer1_64); if(rc) return rc; + rc_num = l_data_buffer1_64.setDoubleWord(0,l_var); + rc = fapiPutScom(i_target_mba,0x02011673,l_data_buffer1_64); if(rc) return rc; + rc = fapiGetScom(i_target_mba,0x02011674,l_data_buffer1_64); if(rc) return rc; + rc_num = l_data_buffer1_64.insertFromRight(l_spare,16,16); + rc = fapiPutScom(i_target_mba,0x02011674,l_data_buffer1_64); if(rc) return rc; + + } + else { - l_addr1 = l_addr1 + START_ADDRESS + l_diff_address; - }*/ - - //FAPI_INF("Value 1 of Start is %016llX and Diff %016llX",l_addr1,l_addr2); - //l_addr1 += (END_ADDRESS * l_rank); - //l_addr1 += ((START_ADDRESS + l_diff_address) * l_rank); - l_addr1 += ((START_ADDRESS + l_diff_address) * i_rank); - l_addr2 = l_addr1 + FEW_INTERVAL; - //FAPI_INF("Value 2 of Start is %016llX and Diff %016llX",l_addr1,l_addr2); + rc = fapiGetScom(i_target_mba,0x02011773,l_data_buffer1_64); if(rc) return rc; + rc_num = l_data_buffer1_64.setDoubleWord(0,l_var); + rc = fapiPutScom(i_target_mba,0x02011773,l_data_buffer1_64); if(rc) return rc; + rc = fapiGetScom(i_target_mba,0x02011774,l_data_buffer1_64); if(rc) return rc; + rc_num = l_data_buffer1_64.insertFromRight(l_spare,16,16); + rc = fapiPutScom(i_target_mba,0x02011774,l_data_buffer1_64); if(rc) return rc; - - } - - else if(i_attr_eff_schmoo_addr_mode == QUARTER_ADDR) - { - - - - l_diff_address = l_addr2 - l_addr1; - - if (l_diff_address >= (FOUR)) - { - l_diff_address1 = l_diff_address>>2; - - - - /*for(i=0;i<l_rank;i++) - { - l_addr1 = l_addr1 + START_ADDRESS + l_diff_address; - }*/ - //FAPI_INF("Value 3 of Start is %016llX and Diff %016llX",l_addr1,l_addr2); - - //l_addr1 += ((START_ADDRESS+l_diff_address) * l_rank); - //l_addr1 += ((START_ADDRESS + l_diff_address) * l_rank); - l_addr1 += ((START_ADDRESS + l_diff_address) * i_rank); - l_addr2 = l_addr1 + l_diff_address1; - - - //FAPI_INF("Value 4 of Start is %016llX and Diff %016llX",l_addr1,l_addr2); - } - - - } - else if(i_attr_eff_schmoo_addr_mode == HALF_ADDR) - { - - - - l_diff_address = l_addr2 - l_addr1; - l_compare = (FOUR)>>1; - - if (l_diff_address >= l_compare) - { - l_diff_address1 = l_diff_address>>1; - - //FAPI_INF("Value 5.1 of diff is %016llX and FOUR %016llX",l_diff_address,l_compare); - - /*for(i=0;i<l_rank;i++) - { - l_addr1 = l_addr1 + l_diff_address + START_ADDRESS; - } */ - //FAPI_INF("Value 5 of Start is %016llX and Diff %016llX",l_addr1,l_addr2); - //l_addr1 += ((START_ADDRESS+l_diff_address) * l_rank); - //l_addr1 += ((START_ADDRESS + l_diff_address) * l_rank); - l_addr1 += ((START_ADDRESS + l_diff_address) * i_rank); - l_addr2 = l_addr1 + l_diff_address1; - //FAPI_INF("Value 6 of Start is %016llX and Diff %016llX",l_addr1,l_addr2); - } } - - else if(i_attr_eff_schmoo_addr_mode == FULL_ADDR) - { - - l_diff_address = l_addr2 - l_addr1; - - /*for(i=0;i<l_rank;i++) - { - l_addr1 = l_addr1 + l_diff_address + START_ADDRESS; - - }*/ - - // l_addr1 += ((START_ADDRESS+l_diff_address) * l_rank); - // l_addr1 += ((START_ADDRESS + l_diff_address) * l_rank); - l_addr1 += ((START_ADDRESS + l_diff_address) * i_rank); - l_addr2 = l_addr1 + l_diff_address; - - } - - if(i_addr_mode == SF) - { - l_start_address = l_addr1 ; - l_end_address = l_addr2 ; - } - else if(i_addr_mode == SR) - { - l_end_address = l_addr1; - l_start_address = l_addr2; } - io_start_address = l_start_address; - io_end_address = l_end_address; - //FAPI_INF("Value of end_address is %016llX and start address %016llX",io_end_address,io_start_address); + return rc; } -//************************************************************************/ -// Funtion name : cfg_mcb_addr -// Description : Configures the address range of MCBIST -// Input Parameters : -// const fapi::Target & Centaur.mba -// uint8_t i_rank Current Rank Being Passed -// uint8_t i_port Current port -// uint64_t i_start Flag to set start address -// uint64_t i_end Flag to set end address -//************************************************************************/ -fapi::ReturnCode cfg_mcb_addr(const fapi::Target & i_target_mba,uint8_t rank,uint8_t i_port,uint64_t i_start,uint64_t i_end) -{ - fapi::ReturnCode rc; // return value after each SCOM access/buffer modification - uint32_t rc_num = 0; - - ecmdDataBufferBase l_data_buffer_64(64); - ecmdDataBufferBase l_data_buffer2_64(64); - - uint32_t io_value_u32 = 0x00000000; - uint32_t l_sbit = 38; - uint32_t l_len = 26; - uint32_t l_start = 0; - uint8_t l_attr_eff_schmoo_addr_mode = 0; - uint8_t l_num_ranks_per_dimm[MAX_PORT][MAX_PORT]; - uint64_t start_address = 0; - uint64_t end_address = 0; - - - - - - - rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_ADDR_MODE, &i_target_mba, l_attr_eff_schmoo_addr_mode); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm); if(rc) return rc; - FAPI_INF("Function cfg_mcb_addr"); - - - FAPI_INF("Num ranks per dimm :%d ", l_num_ranks_per_dimm[0][0]); - FAPI_INF("Num ranks per dimm :%d ", l_num_ranks_per_dimm[0][1]); - FAPI_INF("Num ranks per dimm :%d ", l_num_ranks_per_dimm[1][0]); - FAPI_INF("Num ranks per dimm :%d ", l_num_ranks_per_dimm[1][1]); - - //FAPI_INF("FLAG 111 value of start and end addr is %016llX and %016llX",i_start,i_end); - - - if( ( l_attr_eff_schmoo_addr_mode == FEW_ADDR) || ( l_attr_eff_schmoo_addr_mode == QUARTER_ADDR) ||( l_attr_eff_schmoo_addr_mode == HALF_ADDR) ||( l_attr_eff_schmoo_addr_mode == FULL_ADDR)) - { - - - - if(((l_num_ranks_per_dimm[0][0] != 0) || (l_num_ranks_per_dimm[1][0] != 0)) && (rank <=3)) - { - FAPI_INF("Slot 0 is configured\n"); - - rc = fapiGetScom(i_target_mba,MBA01_MCBIST_MCBSSARA0Q_0x030106d0,l_data_buffer_64); if(rc) return rc; - rc = fapiGetScom(i_target_mba,MBA01_MCBIST_MCBSEARA0Q_0x030106d2,l_data_buffer2_64); if(rc) return rc; - start_address = l_data_buffer_64.getDoubleWord (0); - end_address = l_data_buffer2_64.getDoubleWord (0); - if((i_start >= 0x0000000000000000) && (i_end > 0x0000000000000000) ) - { - //FAPI_INF("FLAG 111 value of start and end addr is %016llX and %016llX",i_start,i_end); - rc=addr_gen_func(i_target_mba,SF, l_attr_eff_schmoo_addr_mode,i_end,i_start,rank,i_port);if(rc)return rc; - start_address = i_start; - end_address = i_end; - FAPI_INF(" value of start and end addr is %016llX and %016llX",start_address,end_address); - } - else - { - FAPI_INF(" value of start and end addr is %016llX and %016llX",start_address,end_address); - rc=addr_gen_func(i_target_mba,SF, l_attr_eff_schmoo_addr_mode,end_address,start_address,rank,i_port);if(rc)return rc; - } - - - - - //rc_num=rc_num|l_data_buffer_64.insert(io_value_u32,l_sbit,l_len,l_start); - //rc_num=rc_num|l_data_buffer2_64.insert(io_value_u32,l_sbit,l_len,l_start); - rc_num = rc_num|l_data_buffer_64.setDoubleWord(0,start_address); - rc_num = rc_num| l_data_buffer2_64.setDoubleWord(0,end_address); - if (rc_num){FAPI_ERR( "Error in function cfg_mcb_addr:");rc.setEcmdError(rc_num);return rc;} - - - rc_num=l_data_buffer_64.insert(io_value_u32,l_sbit,l_len,l_start);if (rc_num){FAPI_ERR( "Error in function cfg_mcb_addr:");rc.setEcmdError(rc_num);return rc;} - rc_num=l_data_buffer2_64.insert(io_value_u32,l_sbit,l_len,l_start); if (rc_num){FAPI_ERR( "Error in function cfg_mcb_addr:");rc.setEcmdError(rc_num);return rc;} - - - FAPI_INF(" value of start and end addr is %016llX and %016llX",start_address,end_address); - rc = fapiPutScom(i_target_mba,MBA01_MCBIST_MCBSSARA0Q_0x030106d0,l_data_buffer_64); if(rc) return rc; - rc = fapiPutScom(i_target_mba,MBA01_MCBIST_MCBSEARA0Q_0x030106d2,l_data_buffer2_64); if(rc) return rc; - } - - if(((l_num_ranks_per_dimm[0][1] != 0) || (l_num_ranks_per_dimm[1][1] != 0)) && (rank >=4)) - { - FAPI_INF("Slot 1 is configured\n"); - - rc = fapiGetScom(i_target_mba,MBA01_MCBIST_MCBSSARA0Q_0x030106d0,l_data_buffer_64); if(rc) return rc; - rc = fapiGetScom(i_target_mba,MBA01_MCBIST_MCBSEARA0Q_0x030106d2,l_data_buffer2_64); if(rc) return rc; - start_address = l_data_buffer_64.getDoubleWord (0); - end_address = l_data_buffer2_64.getDoubleWord (0); - FAPI_INF(" value of start and end addr is %016llX and %016llX",start_address,end_address); - - - if((i_start >= 0x0000000000000000) && (i_end > 0x0000000000000000) ) - { - // FAPI_INF("FLAG 111 value of start and end addr is %016llX and %016llX",i_start,i_end); - rc=addr_gen_func(i_target_mba,SF, l_attr_eff_schmoo_addr_mode,i_end,i_start,rank,i_port); if(rc)return rc; - start_address = i_start; - end_address = i_end; - FAPI_INF(" value of start and end addr is %016llX and %016llX",start_address,end_address); - } - else - { - rc=addr_gen_func(i_target_mba,SF, l_attr_eff_schmoo_addr_mode,end_address,start_address,rank,i_port); if(rc)return rc; - } - rc_num = rc_num| l_data_buffer_64.setDoubleWord(0,start_address); - rc_num = rc_num|l_data_buffer2_64.setDoubleWord(0,end_address); - if (rc_num){FAPI_ERR( "Error in function cfg_mcb_addr:");rc.setEcmdError(rc_num);return rc;} - - rc_num=rc_num|l_data_buffer_64.insert(io_value_u32,l_sbit,l_len,l_start); - rc_num=rc_num|l_data_buffer2_64.insert(io_value_u32,l_sbit,l_len,l_start); - if (rc_num){FAPI_ERR( "Error in function cfg_mcb_addr:");rc.setEcmdError(rc_num);return rc;} - FAPI_INF(" value of start and end addr is %016llX and %016llX",start_address,end_address); - rc = fapiPutScom(i_target_mba,MBA01_MCBIST_MCBSSARA1Q_0x030106d1,l_data_buffer_64); if(rc) return rc; - rc = fapiPutScom(i_target_mba,MBA01_MCBIST_MCBSEARA1Q_0x030106d3,l_data_buffer2_64); if(rc) return rc; - } - - } - - - return rc; - -} diff --git a/src/usr/hwpf/hwp/dram_training/mss_funcs.C b/src/usr/hwpf/hwp/dram_training/mss_funcs.C index 4aa0fa551..f4e1b03a1 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_funcs.C +++ b/src/usr/hwpf/hwp/dram_training/mss_funcs.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_funcs.C,v 1.29 2012/11/19 21:18:40 jsabrow Exp $ +// $Id: mss_funcs.C,v 1.30 2013/04/09 23:33:09 jdsloat Exp $ /* File mss_funcs.C created by SLOAT JACOB D. (JAKE),2D3970 on Fri Apr 22 2011. */ //------------------------------------------------------------------------------ @@ -43,6 +43,7 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.30 | jdsloat | 04/09/13| Moved Address mirror mode sub function in from mss_draminit // 1.29 | jsabrow | 11/19/12| added CCS data loader: mss_ccs_load_data_pattern // 1.28 | bellows | 07/16/12|added in Id tag // 1.27 | divyakum | 3/22/12 | Fixed warnings from mss_execute_zq_cal function @@ -114,6 +115,69 @@ ReturnCode mss_ccs_set_end_bit( return rc; } +ReturnCode mss_address_mirror_swizzle( + Target& i_target, + uint32_t i_port, + uint32_t i_dimm, + uint32_t i_rank, + ecmdDataBufferBase& io_address, + ecmdDataBufferBase& io_bank + ) +{ + ReturnCode rc; + ReturnCode rc_buff; + uint32_t rc_num = 0; + ecmdDataBufferBase address_post_swizzle_16(16); + ecmdDataBufferBase bank_post_swizzle_3(3); + uint16_t mirror_mode_ba = 0; + uint16_t mirror_mode_ad = 0; + + FAPI_INF( "ADDRESS MIRRORING ON %s PORT%d DIMM%d RANK%d", i_target.toEcmdString(), i_port, i_dimm, i_rank); + + rc_num = rc_num | io_address.extractPreserve(&mirror_mode_ad, 0, 16, 0); + FAPI_INF( "PRE - MIRROR MODE ADDRESS: 0x%04X", mirror_mode_ad); + rc_num = rc_num | io_bank.extractPreserve(&mirror_mode_ba, 0, 3, 0); + FAPI_INF( "PRE - MIRROR MODE BANK ADDRESS: 0x%04X", mirror_mode_ba); + + //Initialize address and bank address as the same pre mirror mode swizzle + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 0, 16, 0); + rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 0, 3, 0); + + //Swap A3 and A4 + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 4, 1, 3); + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 3, 1, 4); + + //Swap A5 and A6 + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 6, 1, 5); + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 5, 1, 6); + + //Swap A7 and A8 + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 8, 1, 7); + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 7, 1, 8); + + //Swap BA0 and BA1 + rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 1, 1, 0); + rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 0, 1, 1); + + rc_num = rc_num | address_post_swizzle_16.extractPreserve(&mirror_mode_ad, 0, 16, 0); + FAPI_INF( "POST - MIRROR MODE ADDRESS: 0x%04X", mirror_mode_ad); + rc_num = rc_num | bank_post_swizzle_3.extractPreserve(&mirror_mode_ba, 0, 3, 0); + FAPI_INF( "POST - MIRROR MODE BANK ADDRESS: 0x%04X", mirror_mode_ba); + + //copy address and bank address back to the IO variables + rc_num = rc_num | io_address.insert(address_post_swizzle_16, 0, 16, 0); + rc_num = rc_num | io_bank.insert(bank_post_swizzle_3, 0, 3, 0); + + if (rc_num) + { + FAPI_ERR( "Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + + return rc; +} + ReturnCode mss_ccs_inst_arry_0( Target& i_target, uint32_t& io_instruction_number, diff --git a/src/usr/hwpf/hwp/dram_training/mss_funcs.H b/src/usr/hwpf/hwp/dram_training/mss_funcs.H index 685ed1ef1..b5af96fcd 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_funcs.H +++ b/src/usr/hwpf/hwp/dram_training/mss_funcs.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_funcs.H,v 1.13 2012/11/19 21:18:41 jsabrow Exp $ +// $Id: mss_funcs.H,v 1.14 2013/04/09 23:34:27 jdsloat Exp $ /* File mss_funcs.H created by SLOAT JACOB D. (JAKE),2D3970 on Fri Apr 22 2011. */ //------------------------------------------------------------------------------ @@ -43,6 +43,7 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.14 | jdsloat | 04/09/13| Moved Address mirror mode sub function in from mss_draminit // 1.13 | jsabrow | 11/19/12| added CCS data loader: mss_ccs_load_data_pattern // 1.12 | 07/16/12 | bellows | added in Id tag // 1.11 | 3/21/12 | divyakum| Added mss_execute_zq_cal function @@ -244,5 +245,17 @@ uint8_t mss_reverse_8bits(uint8_t i_number); fapi::ReturnCode mss_execute_zq_cal(fapi::Target& i_target, uint8_t i_port); +//----------------------------------------- +// mss_address_mirror_swizzle +// swizzle the address bus and bank address bus for address mirror mode +// Target = centaur.mba +//----------------------------------------- +fapi::ReturnCode mss_address_mirror_swizzle(fapi::Target& i_target, + uint32_t i_port, + uint32_t i_dimm, + uint32_t i_rank, + ecmdDataBufferBase& io_address, + ecmdDataBufferBase& io_bank); + #endif /* _MSS_FUNCS_H */ diff --git a/src/usr/hwpf/hwp/dram_training/mss_termination_control.C b/src/usr/hwpf/hwp/dram_training/mss_termination_control.C index c15ffa5ac..376ed2724 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_termination_control.C +++ b/src/usr/hwpf/hwp/dram_training/mss_termination_control.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_termination_control.C,v 1.18 2013/03/05 15:40:38 mwuu Exp $ +// $Id: mss_termination_control.C,v 1.20 2013/04/09 11:04:34 lapietra Exp $ /* File is created by SARAVANAN SETHURAMAN on Thur 29 Sept 2011. */ //------------------------------------------------------------------------------ @@ -43,14 +43,16 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- -// 1.18 | mwuu |25-Feb-13| Added return code per port for config slew FN -// 1.17 | mwuu |07-Feb-13| Improved the debug and trace messages. -// 1.16 | mwuu |24-Jan-13| Fixed cal_slew extraction of bits. -// 1.15 | mwuu |14-Jan-13| Altered error message for unsupported slew rate -// 1.14 | mwuu |14-Jan-13| Removed error messages from slew cal fail when +// 1.20 | sasethur |09-Apr-13| Changed wr_vref register settings as per ddr3spec +// 1.19 | sasethur |05-Apr-13| Updated for port in parallel +// 1.18 | mwuu |25-Feb-13| Added return code per port for config slew FN +// 1.17 | mwuu |07-Feb-13| Improved the debug and trace messages. +// 1.16 | mwuu |24-Jan-13| Fixed cal_slew extraction of bits. +// 1.15 | mwuu |14-Jan-13| Altered error message for unsupported slew rate +// 1.14 | mwuu |14-Jan-13| Removed error messages from slew cal fail when // | | | in SIM and using unsupported slew rates. -// 1.13 | mwuu |18-Dec-12| Took out initialization of array_rcs in declaration. -// 1.12 | mwuu |14-Dec-12| Updated additional fw review comments +// 1.13 | mwuu |18-Dec-12| Took out initialization of array_rcs in declaration. +// 1.12 | mwuu |14-Dec-12| Updated additional fw review comments // 1.11 | sasethur |07-Dec-12| Updated for fw review comments // 1.10 | mwuu |28-Nov-12| Added changes suggested from FW team. // 1.9 | mwuu |20-Nov-12| Changed warning status to not cause error. @@ -62,7 +64,7 @@ // 1.4 | mwuu |26-Oct-12| Added mss_slew_cal FN, not 100% complete // 1.3 | sasethur |26-Oct-12| Updated FW review comments - fapi::, const fapi:: Target // 1.2 | mwuu |17-Oct-12| Updated return codes to use common error, also -// updates to the slew function +// | | | updates to the slew function // 1.1 | sasethur |15-Oct-12| Functions defined & moved from training adv, // Menlo upated slew function @@ -136,8 +138,6 @@ fapi::ReturnCode config_drv_imp(const fapi::Target & i_target_mba, uint8_t i_por } } - if (i_port == 0) - { rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_0_0x800000780301143F, data_buffer); if(rc) return rc; @@ -179,10 +179,8 @@ fapi::ReturnCode config_drv_imp(const fapi::Target & i_target_mba, uint8_t i_por rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_4_0x800010790301143F, data_buffer); if(rc) return rc; - } - else // port = 1 - { - rc = fapiGetScom(i_target_mba, + + rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_0_0x800100780301143F, data_buffer); if(rc) return rc; rc_num = data_buffer.insertFromRight(enslice_drv,48,8); @@ -223,7 +221,6 @@ fapi::ReturnCode config_drv_imp(const fapi::Target & i_target_mba, uint8_t i_por rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_4_0x800110790301143F, data_buffer); if(rc) return rc; - } return rc; } @@ -303,8 +300,6 @@ fapi::ReturnCode config_rcv_imp(const fapi::Target & i_target_mba, uint8_t i_por } - if (i_port == 0) - { rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_0_0x8000007A0301143F, data_buffer); if(rc) return rc; @@ -346,10 +341,8 @@ fapi::ReturnCode config_rcv_imp(const fapi::Target & i_target_mba, uint8_t i_por rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_4_0x8000107B0301143F, data_buffer); if(rc) return rc; - } - else - { - rc = fapiGetScom(i_target_mba, + + rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_0_0x8001007A0301143F, data_buffer); if(rc) return rc; rc_num = data_buffer.insertFromRight(enslicepterm,48,8); @@ -390,7 +383,6 @@ fapi::ReturnCode config_rcv_imp(const fapi::Target & i_target_mba, uint8_t i_por rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_4_0x8001107B0301143F, data_buffer); if(rc) return rc; - } return rc; } @@ -504,8 +496,6 @@ fapi::ReturnCode config_slew_rate(const fapi::Target & i_target_mba, FAPI_DBG("port%u type=%u imp_idx=%u slew_idx=%u cal_slew=%u", i_port, i_slew_type, imp_idx, slew_idx, slew_cal_value); - if (i_port == 0) // port dq/dqs slew - { rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_0_0x800000750301143F, data_buffer); if(rc) return rc; @@ -533,9 +523,6 @@ fapi::ReturnCode config_slew_rate(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_4_0x800010750301143F, data_buffer); if(rc) return rc; - } - else // port 1 dq/dqs slew - { rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_0_0x800100750301143F, data_buffer); if(rc) return rc; @@ -563,7 +550,6 @@ fapi::ReturnCode config_slew_rate(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_4_0x800110750301143F, data_buffer); if(rc) return rc; - } // end port 1 DATA } // end DATA else // Slew type = ADR { @@ -640,8 +626,6 @@ fapi::ReturnCode config_slew_rate(const fapi::Target & i_target_mba, FAPI_DBG("port%u type=%u slew_idx=%u imp_idx=%u cal_slew=%u", i_port, i_slew_type, slew_idx, imp_idx, slew_cal_value); - if (i_port == 0) - { rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0_0x8000401A0301143F, data_buffer); if(rc) return rc; @@ -666,9 +650,6 @@ fapi::ReturnCode config_slew_rate(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR3_0x80004C1A0301143F, data_buffer); if(rc) return rc; - } - else // port 1 ADR slew - { rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR0_0x8001401A0301143F, data_buffer); if(rc) return rc; @@ -693,7 +674,6 @@ fapi::ReturnCode config_slew_rate(const fapi::Target & i_target_mba, rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR3_0x80014C1A0301143F, data_buffer); if(rc) return rc; - } // end port 1 ADR } // end ADR return rc; } @@ -718,7 +698,7 @@ fapi::ReturnCode config_wr_dram_vref(const fapi::Target & i_target_mba, uint8_t fapi::ReturnCode rc; uint32_t rc_num = 0; uint32_t pcvref = 0; - uint32_t i = 0; + uint32_t sign = 0; // For DDR3 vary from VDD*0.42 to VDD*575 // For DDR4 internal voltage is there this function is not required @@ -728,20 +708,85 @@ fapi::ReturnCode config_wr_dram_vref(const fapi::Target & i_target_mba, uint8_t FAPI_SET_HWP_ERROR(rc, RC_MSS_INVALID_FN_INPUT_ERROR); return rc; } - for(i=0; i< MAX_WR_VREF; i++) + + if(i_wr_dram_vref < 500) { - if (wr_vref_array[i] == i_wr_dram_vref) - { - pcvref = i; - break; - } + sign = 1; } - - if (i_port == 0) + else + { + sign = 0; + } + if((i_wr_dram_vref == 420) || (i_wr_dram_vref == 575)) + { + pcvref = 0xF; + } + else if((i_wr_dram_vref == 425) || (i_wr_dram_vref == 570)) + { + pcvref = 0x7; + } + else if((i_wr_dram_vref == 430) || (i_wr_dram_vref == 565)) + { + pcvref = 0xB; + } + else if((i_wr_dram_vref == 435) || (i_wr_dram_vref == 560)) + { + pcvref = 0x3; + } + else if((i_wr_dram_vref == 440) || (i_wr_dram_vref == 555)) { + pcvref = 0xD; + } + else if((i_wr_dram_vref == 445) || (i_wr_dram_vref == 550)) + { + pcvref = 0x5; + } + else if((i_wr_dram_vref == 450) || (i_wr_dram_vref == 545)) + { + pcvref = 0x9; + } + else if((i_wr_dram_vref == 455) || (i_wr_dram_vref == 540)) + { + pcvref = 0x1; + } + else if((i_wr_dram_vref == 460) || (i_wr_dram_vref == 535)) + { + pcvref = 0xE; + } + else if((i_wr_dram_vref == 465) || (i_wr_dram_vref == 530)) + { + pcvref = 0x6; + } + else if((i_wr_dram_vref == 470) || (i_wr_dram_vref == 525)) + { + pcvref = 0xA; + } + else if((i_wr_dram_vref == 475) || (i_wr_dram_vref == 520)) + { + pcvref = 0x2; + } + else if((i_wr_dram_vref == 480) || (i_wr_dram_vref == 515)) + { + pcvref = 0xC; + } + else if((i_wr_dram_vref == 485) || (i_wr_dram_vref == 510)) + { + pcvref = 0x4; + } + else if((i_wr_dram_vref == 490) || (i_wr_dram_vref == 505)) + { + pcvref = 0x8; + } + else if((i_wr_dram_vref == 495) || (i_wr_dram_vref == 500)) + { + pcvref = 0x0; + } + rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P0_0x8000C0150301143F, data_buffer); if(rc) return rc; - rc_num = rc_num | data_buffer.insertFromRight(pcvref,48,5); - rc_num = rc_num | data_buffer.insertFromRight(pcvref,53,5); + rc_num = rc_num | data_buffer.insertFromRight(sign,48,1); + rc_num = rc_num | data_buffer.insertFromRight(sign,53,1); + rc_num = rc_num | data_buffer.insertFromRight(pcvref,49,4); + rc_num = rc_num | data_buffer.insertFromRight(pcvref,54,4); if (rc_num) { FAPI_ERR( "config_wr_vref: Error in setting up buffer "); @@ -749,12 +794,10 @@ fapi::ReturnCode config_wr_dram_vref(const fapi::Target & i_target_mba, uint8_t return rc; } rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P0_0x8000C0150301143F, data_buffer); if(rc) return rc; - } - else - { - rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P1_0x8001C0150301143F, data_buffer); if(rc) return rc; - rc_num = rc_num | data_buffer.insertFromRight(pcvref,48,5); - rc_num = rc_num | data_buffer.insertFromRight(pcvref,53,5); + rc_num = rc_num | data_buffer.insertFromRight(sign,48,1); + rc_num = rc_num | data_buffer.insertFromRight(sign,53,1); + rc_num = rc_num | data_buffer.insertFromRight(pcvref,49,4); + rc_num = rc_num | data_buffer.insertFromRight(pcvref,54,4); if (rc_num) { FAPI_ERR( "config_wr_vref: Error in setting up buffer "); @@ -762,7 +805,6 @@ fapi::ReturnCode config_wr_dram_vref(const fapi::Target & i_target_mba, uint8_t return rc; } rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P1_0x8001C0150301143F, data_buffer); if(rc) return rc; - } return rc; } /*------------------------------------------------------------------------------ @@ -803,8 +845,6 @@ fapi::ReturnCode config_rd_cen_vref (const fapi::Target & i_target_mba, uint8_t } } - if (i_port == 0) - { rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_0_0x800000060301143F, data_buffer); if(rc) return rc; @@ -830,9 +870,6 @@ fapi::ReturnCode config_rd_cen_vref (const fapi::Target & i_target_mba, uint8_t rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_4_0x800010060301143F, data_buffer); if(rc) return rc; - } - else - { rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_0_0x800100060301143F, data_buffer); if(rc) return rc; @@ -858,7 +895,6 @@ fapi::ReturnCode config_rd_cen_vref (const fapi::Target & i_target_mba, uint8_t rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_4_0x800110060301143F, data_buffer); if(rc) return rc; - } return rc; } /*------------------------------------------------------------------------------ diff --git a/src/usr/hwpf/hwp/include/cen_scom_addresses.H b/src/usr/hwpf/hwp/include/cen_scom_addresses.H index 4a7790ca4..3865eeb7c 100755 --- a/src/usr/hwpf/hwp/include/cen_scom_addresses.H +++ b/src/usr/hwpf/hwp/include/cen_scom_addresses.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: cen_scom_addresses.H,v 1.54 2013/03/08 23:25:10 jdsloat Exp $ +// $Id: cen_scom_addresses.H,v 1.56 2013/04/04 20:32:53 jdsloat Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/cen_scom_addresses.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -44,6 +44,8 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.55 | jdsloat |04-Apr-13| Added DPHY01_DDRPHY_WC_CONFIG3 regs +// 1.54 | jdsloat |03-Apr-13| Fixed MR Sec shadow regs // 1.53 | jdsloat |08-Mar-13| Added MBA01_MBARPC0Q_0x03010434 // 1.52 | jdsloat |27-Feb-13| Fixed additional typos in READ TIMING REF // 1.51 | sglancy |27-Feb-13| Fixed typos in READ TIMING REF @@ -396,22 +398,22 @@ CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_PRI_RP3_P0_0x8000C31D0301143F, CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_PRI_RP3_P0_0x8000C31E0301143F, ULL(0x8000C31E0301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_PRI_RP3_P0_0x8000C31F0301143F, ULL(0x8000C31F0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP0_P0_0x8000C02C0301143F, ULL(0x8000C02C0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP0_P0_0x8000C02D0301143F, ULL(0x8000C02D0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP0_P0_0x8000C02E0301143F, ULL(0x8000C02E0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP0_P0_0x8000C02F0301143F, ULL(0x8000C02F0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP1_P0_0x8000C12C0301143F, ULL(0x8000C12C0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP1_P0_0x8000C12D0301143F, ULL(0x8000C12D0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP1_P0_0x8000C12E0301143F, ULL(0x8000C12E0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP1_P0_0x8000C12F0301143F, ULL(0x8000C12F0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP2_P0_0x8000C22C0301143F, ULL(0x8000C22C0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP2_P0_0x8000C22D0301143F, ULL(0x8000C22D0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP2_P0_0x8000C22E0301143F, ULL(0x8000C22E0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP2_P0_0x8000C22F0301143F, ULL(0x8000C22F0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP3_P0_0x8000C32C0301143F, ULL(0x8000C32C0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP3_P0_0x8000C32D0301143F, ULL(0x8000C32D0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP3_P0_0x8000C32E0301143F, ULL(0x8000C32E0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP3_P0_0x8000C32F0301143F, ULL(0x8000C32F0301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP0_P0_0x8000C0200301143F, ULL(0x8000C0200301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP0_P0_0x8000C0210301143F, ULL(0x8000C0210301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP0_P0_0x8000C0220301143F, ULL(0x8000C0220301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP0_P0_0x8000C0230301143F, ULL(0x8000C0230301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP1_P0_0x8000C1200301143F, ULL(0x8000C1200301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP1_P0_0x8000C1210301143F, ULL(0x8000C1210301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP1_P0_0x8000C1220301143F, ULL(0x8000C1220301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP1_P0_0x8000C1230301143F, ULL(0x8000C1230301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP2_P0_0x8000C2200301143F, ULL(0x8000C2200301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP2_P0_0x8000C2210301143F, ULL(0x8000C2210301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP2_P0_0x8000C2220301143F, ULL(0x8000C2220301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP2_P0_0x8000C2230301143F, ULL(0x8000C2230301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP3_P0_0x8000C3200301143F, ULL(0x8000C3200301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP3_P0_0x8000C3210301143F, ULL(0x8000C3210301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP3_P0_0x8000C3220301143F, ULL(0x8000C3220301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP3_P0_0x8000C3230301143F, ULL(0x8000C3230301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_PRI_RP0_P1_0x8001C01C0301143F, ULL(0x8001C01C0301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_PRI_RP0_P1_0x8001C01D0301143F, ULL(0x8001C01D0301143F) ); @@ -431,28 +433,31 @@ CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_PRI_RP3_P1_0x8001C31E0301143F, CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_PRI_RP3_P1_0x8001C31F0301143F, ULL(0x8001C31F0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP0_P1_0x8001C02C0301143F, ULL(0x8001C02C0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP0_P1_0x8001C02D0301143F, ULL(0x8001C02D0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP0_P1_0x8001C02E0301143F, ULL(0x8001C02E0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP0_P1_0x8001C02F0301143F, ULL(0x8001C02F0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP1_P1_0x8001C12C0301143F, ULL(0x8001C12C0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP1_P1_0x8001C12D0301143F, ULL(0x8001C12D0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP1_P1_0x8001C12E0301143F, ULL(0x8001C12E0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP1_P1_0x8001C12F0301143F, ULL(0x8001C12F0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP2_P1_0x8001C22C0301143F, ULL(0x8001C22C0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP2_P1_0x8001C22D0301143F, ULL(0x8001C22D0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP2_P1_0x8001C22E0301143F, ULL(0x8001C22E0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP2_P1_0x8001C22F0301143F, ULL(0x8001C22F0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP3_P1_0x8001C32C0301143F, ULL(0x8001C32C0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP3_P1_0x8001C32D0301143F, ULL(0x8001C32D0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP3_P1_0x8001C32E0301143F, ULL(0x8001C32E0301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP3_P1_0x8001C32F0301143F, ULL(0x8001C32F0301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP0_P1_0x8001C0200301143F, ULL(0x8001C0200301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP0_P1_0x8001C0210301143F, ULL(0x8001C0210301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP0_P1_0x8001C0220301143F, ULL(0x8001C0220301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP0_P1_0x8001C0230301143F, ULL(0x8001C0230301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP1_P1_0x8001C1200301143F, ULL(0x8001C1200301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP1_P1_0x8001C1210301143F, ULL(0x8001C1210301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP1_P1_0x8001C1220301143F, ULL(0x8001C1220301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP1_P1_0x8001C1230301143F, ULL(0x8001C1230301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP2_P1_0x8001C2200301143F, ULL(0x8001C2200301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP2_P1_0x8001C2210301143F, ULL(0x8001C2210301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP2_P1_0x8001C2220301143F, ULL(0x8001C2220301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP2_P1_0x8001C2230301143F, ULL(0x8001C2230301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP3_P1_0x8001C3200301143F, ULL(0x8001C3200301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP3_P1_0x8001C3210301143F, ULL(0x8001C3210301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP3_P1_0x8001C3220301143F, ULL(0x8001C3220301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP3_P1_0x8001C3230301143F, ULL(0x8001C3230301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, ULL(0x8000C0110301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, ULL(0x8001C0110301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, ULL(0x8000C0350301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, ULL(0x8001C0350301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F, ULL(0x8000CC050301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_WC_CONFIG3_P1_0x8001CC050301143F, ULL(0x8001CC050301143F) ); + //------------------------------------------------------------------------------ // DISABLE BIT SCOM ADDRESSES (DPHY REGISTERS) @@ -1573,6 +1578,12 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: cen_scom_addresses.H,v $ +Revision 1.56 2013/04/04 20:32:53 jdsloat +Added DPHY01_DDRPHY_WC_CONFIG3 regs + +Revision 1.55 2013/04/03 20:43:25 jdsloat +Fixed MR Sec shadow regs + Revision 1.54 2013/03/08 23:25:10 jdsloat added MBA01_MBARPC0Q_0x03010434 diff --git a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile index 6b7744182..914781166 100755 --- a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile +++ b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile @@ -1,8 +1,15 @@ -#-- $Id: cen_ddrphy.initfile,v 1.21 2013/02/08 00:32:24 mwuu Exp $ +#-- $Id: cen_ddrphy.initfile,v 1.23 2013/04/10 01:59:41 mwuu Exp $ +#-- $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/ +#-- centaur/working/procedures/ec_ind/scoms/cen_ddrphy.initfile,v $ +# #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.23|mwuu |04/09/13|Fixed typo ENUM for 2N mode. +#-- 1.22|mwuu |04/04/13|Updated tODTL definition when AL=0, added 2N support +# |changed for LRDIMM: RLO=6, WLO=-1; DDR4 UDIMM mem type +# |changed WC_CONFIG3 bit 48 drive dq on MRS #-- 1.21|mwuu |02/07/13|Updated PC_CSID register to default CS to high #-- 1.20|mwuu |01/16/13|Updated TWTR & TRTP define for FW_WR_RD field in # | | |WC_CONFIG0 and FW_RD_WR in WC_CONFIG2 in 0W spec. @@ -85,8 +92,8 @@ define def_is_sim = (SYS.ATTR_IS_SIMULATION == 1) ; define def_FAST_SIM_PC = 1 ; # for real HW uncomment, !!FIX once ATTR_EFF_DIMM_SPARE available [2][4][4] port, dimm, rank -define def_has_spare = (ATTR_EFF_DIMM_TYPE == 0) ; # CDIMM -define def_no_spare = (ATTR_EFF_DIMM_TYPE != 0) ; # others, ISDIMMs, LRDIMM, etc. +define def_has_spare = (ATTR_EFF_DIMM_TYPE == ENUM_ATTR_EFF_DIMM_TYPE_CDIMM) ; # CDIMM +define def_no_spare = (ATTR_EFF_DIMM_TYPE != ENUM_ATTR_EFF_DIMM_TYPE_CDIMM) ; # others, ISDIMMs, LRDIMM, etc. # ports 0,1 must have functional dimms to be valid define def_valid_p0 = (ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR >> 4); @@ -264,6 +271,12 @@ define def_cdi_spcke_ohm20_p1 = (ATTR_EFF_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_EFF_ define def_cdi_spcke_ohm30_p1 = (ATTR_EFF_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM30) ; # OHM30 = 0x1E (30) define def_cdi_spcke_ohm40_p1 = (ATTR_EFF_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40) ; # OHM40 = 0x28 (40) +# define for glacier1(1), glacier2=normal(0) +define def_is_type1 = ((ATTR_MSS_DQS_SWIZZLE_TYPE == 1) && (ATTR_EFF_DIMM_TYPE != ENUM_ATTR_EFF_DIMM_TYPE_CDIMM)) ; + +# define for 2 cycle addressing mode (2N) +define def_2N_mode = (ATTR_EFF_DRAM_2N_MODE_ENABLED == ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_TRUE) ; + # SIMPLIFY # ================================================================================ @@ -276,14 +289,16 @@ define def_TWTR_PLUS_OFF = (ATTR_EFF_DRAM_TWTR + 11) ; # change from +8 on reg s define def_TRTP_PLUS_AL = (ATTR_EFF_DRAM_TRTP + ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_AL + 3) ; define def_TRTP_PLUS_NOAL = (ATTR_EFF_DRAM_TRTP + 3) ; -# for ODT on/off time calculation +# for ODT on/off time calculation during write calibration # 2tCK = DDR4 feature for extended write preamble, should be defined by attribute if used. # tODTLON/OFF DDR3=CWL+AL-2, DDR4=CWL+AL-3 if using 2tCK, otherwise same as DDR3 formula #define def_AL = ((def_AL_ena)*(ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_AL)); #define def_tODTL_DDR3 = (ATTR_EFF_DRAM_CWL + def_AL - 2) ; # DDR3 # should not try to do the defines above... define def_tODTL_DDR3 = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_AL - 2) ; # DDR3 +define def_tODTL_DDR3_NOAL = (ATTR_EFF_DRAM_CWL - 2) ; # DDR3, no AL define def_tODTL_DDR4 = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_AL - 3) ; # DDR4 & 2tCK +define def_tODTL_DDR4_NOAL = (ATTR_EFF_DRAM_CWL - 3) ; # DDR4 & 2tCK, no AL # def_1PR = 1000*1000 / (FREQ / 2) # def_dqs_offset = (10 + ((def_p2p_jitter / 2) / def_1PR) + 1) # +1 for ceiling FN @@ -291,9 +306,6 @@ define def_tODTL_DDR4 = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_A define def_p2p_jitter = 2600 ; # DQS peak to peak jitter in ps define def_dqs_offset = (11 + ((def_p2p_jitter * CEN.ATTR_MSS_FREQ) / 4000000)) ; -# define for glacier1(1), glacier2=normal(0) -define def_is_type1 = ((ATTR_MSS_DQS_SWIZZLE_TYPE == 1) && (ATTR_EFF_DIMM_TYPE != ENUM_ATTR_EFF_DIMM_TYPE_CDIMM)) ; - #--------------------------------------------------------------------------------- # ===================================================================================================== @@ -394,21 +406,30 @@ scom 0x800(0,1)C00D0301143F { # # WLO is normally 0 except for RDIMM (RCD) configurations in which case it's set to 1 # DD0 = PORT_BUFFER_LATENCY 48:51 , 0x1 , (def_is_rdimm) ; # RDIMM + 48:51 , 0xF , (def_is_lrdimm) ; # LRDIMM set WLO=-1 48:51 , 0x0 , any ; # WLO=WRITE_LATENCY_OFFSET (2's complement -8 to 7) # # 9.4.12.2 RLO = READ_LATENCY_OFFSET (2's complement -8 to 7) {0=CDIMM, 1=RDIMM, 2=LRDIMM} 52:55 , 0x0 , (def_is_cdimm) ; # CDIMM 52:55 , 0x1 , (def_is_rdimm) ; # RDIMM - 52:55 , 0x2 , (def_is_lrdimm) ; # LRDIMM + 52:55 , 0x6 , (def_is_lrdimm) ; # LRDIMM 56 , 0b0 , any ; # MEMCTL_CIC_FAST 57 , 0b0 , any ; # MEMCTL_CTRN_IGNORE 58 , 0b0 , any ; # DISABLE_MEMCTL_CAL # Memory Type # # 59:61 , 000=DDR3/DDR4 CDIMM, DDR3 (001=RDIMM, 011=LRDIMM), DDR4 (101=RDIMM, 111=LRDIMM) - 59:61 , 0b000 , (def_is_cdimm) ; # CDIMM - 59:61 , 0b001 , ((def_is_rdimm) && (def_is_ddr3)) ; # DDR3 RDIMM - 59:61 , 0b011 , ((def_is_lrdimm) && (def_is_ddr3)) ; # DDR3 LRDIMM - 59:61 , 0b101 , ((def_is_rdimm) && (def_is_ddr4)) ; # DDR4 RDIMM - 59:61 , 0b111 , ((def_is_lrdimm) && (def_is_ddr4)) ; # DDR4 LRDIMM + 59 , 0b1 , (def_is_ddr4) ; # DDR4 + 59 , 0b0 , any ; # DDR3 + + 60 , 0b1 , (def_is_lrdimm) ; # LRDIMM + 60 , 0b0 , any ; # not LRDIMM + + 61 , 0b1 , ((def_is_lrdimm) || (def_is_rdimm)) ; # registered C/A + 61 , 0b0 , any ; # unbuffered C/A +# 59:61 , 0b000 , (def_is_cdimm) ; # CDIMM +# 59:61 , 0b001 , ((def_is_rdimm) && (def_is_ddr3)) ; # DDR3 RDIMM +# 59:61 , 0b011 , ((def_is_lrdimm) && (def_is_ddr3)) ; # DDR3 LRDIMM +# 59:61 , 0b101 , ((def_is_rdimm) && (def_is_ddr4)) ; # DDR4 RDIMM +# 59:61 , 0b111 , ((def_is_lrdimm) && (def_is_ddr4)) ; # DDR4 LRDIMM # 62 , 0b1 , any ; # DDR4 Latency Chicken SW # 63 , 0b0 , any ; # Retain_Percal_SW } @@ -3683,6 +3704,7 @@ scom 0x800(0,1)C8000301143F { # _P[0:1] # # min GPO = 5 + max(rndUp(System_delay)) - RLO + ADVANCE_RD_VALID + SPAM_EN # max GPO = 11 if in 2:1, 13 if in 4:1 + 48:51 , 0b0111 , (def_is_lrdimm) ; # GLOBAL_PHY_OFFSET LRDIMM set to 7 48:51 , 0b0101 , any ; # GLOBAL_PHY_OFFSET (GPO), ideally 2:1 max=11, 4:1 max=13 52 , 0b0 , any ; # ADVANCE_RD_VALID ask Yuen 53 , 0b0 , any ; # PER_DUTY_CYCLE_SW, 0=rd cmds 50% duty cycle during per.cal, 1=continuously @@ -3772,17 +3794,20 @@ scom 0x800(0,1)C8070301143F { # _P[0:1] # DPHY01_DDRPHY_SEQ_CONFIG0_P0 CTL 0x002 0x8000c4020301143f # PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.MPR_PATTERN_DATA_L2 scom 0x800(0,1)C4020301143F { # _P[0:1] - bits , scom_data ; -# 0:47 , 0x000000000000 ; # reserved - 48 , 0b0 ; # MPR_PATTERN_BIT - 49 , 0b0 ; # TWO_CYCLE_ADDR_EN (must be set to 0?) - 50:53 , 0b0000 ; # MR_MASK_EN (mode register[0:3] mask during calibration) - 54 , 0b0 ; # DELAYED_PARITY (only for DDR4, DDR3 don't care) - 55 , 0b0 ; # LRDIMM_CONTEXT - 56 , 0b0 ; # FORCE_RESERVED # for DDR4 - 57 , 0b0 ; # HALT_ROTATION, for DDR4 staggered pattern - 58 , 0b0 ; # FORCE_MPR -# 59:63 , 0b00000 ; # reserved + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48 , 0b0 , any ; # MPR_PATTERN_BIT +# # TWO_CYCLE_ADDR_EN + 49 , 0b1 , (def_2N_mode) ; # enable 2 cycle addr mode + 49 , 0b0 , any ; # disable 2 cycle addr mode + + 50:53 , 0b0000 , any ; # MR_MASK_EN (mode register[0:3] mask during calibration) + 54 , 0b0 , any ; # DELAYED_PARITY (only for DDR4, DDR3 don't care) + 55 , 0b0 , any ; # LRDIMM_CONTEXT + 56 , 0b0 , any ; # FORCE_RESERVED # for DDR4 + 57 , 0b0 , any ; # HALT_ROTATION, for DDR4 staggered pattern + 58 , 0b0 , any ; # FORCE_MPR +# 59:63 , 0b00000 , any ; # reserved } # --------------------------------------------------------------------------------------- @@ -3905,54 +3930,31 @@ scom 0x800(0,1)C4130301143F { # _P[0:1] # PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.MEM_TIMING_PARAM2_L2 # # TODTLON_OFF_CYCLES DDR3=CWL+AL-2 DDR4 if 2tCK, CWL+AL-3 -# define def_tODTL_DDR3_AL0 = def_tODTL_DDR3 - ATTR_EFF_DRAM_CL ; -# scom 0x800(0,1)C4140301143F { # _P[0:1] -# bits , scom_data , ATTR_EFF_DRAM_GEN , ATTR_EFF_DRAM_AL , expr ; -# 0:47 , 0x000000000000, any , any , any ; # reserved -# #--------------- DDR3 ------------------------------------------------------------------------- -# 48:51 , 0x3 , 1 , 0 , (def_tODTL_DDR3_AL0 <= 8) ; # 8 clks -# 48:51 , 0x4 , 1 , 0 , ((def_tODTL_DDR3_AL0 <= 16) && (def_tODTL_DDR3_AL0 > 8)) ; # 16 clks -# 48:51 , 0x5 , 1 , 0 , ((def_tODTL_DDR3_AL0 <= 32) && (def_tODTL_DDR3_AL0 > 16)) ; # 32 clks -# 48:51 , 0x6 , 1 , 0 , ((def_tODTL_DDR3_AL0 <= 64) && (def_tODTL_DDR3_AL0 > 32)) ; # 64 clks -# 48:51 , 0x3 , 1 , any , (def_tODTL_DDR3 <= 8) ; # 8 clks -# 48:51 , 0x4 , 1 , any , ((def_tODTL_DDR3 <= 16) && (def_tODTL_DDR3 > 8)) ; # 16 clks -# 48:51 , 0x5 , 1 , any , ((def_tODTL_DDR3 <= 32) && (def_tODTL_DDR3 > 16)) ; # 32 clks -# 48:51 , 0x6 , 1 , any , ((def_tODTL_DDR3 <= 64) && (def_tODTL_DDR3 > 32)) ; # 64 clks -# #--------------- DDR4 ------------------------------------------------------------------------- -# 48:51 , 0x3 , 2 , 0 , (def_tODTL_DDR4_AL0 <= 8) ; # 8 clks -# 48:51 , 0x4 , 2 , 0 , ((def_tODTL_DDR4_AL0 <= 16) && (def_tODTL_DDR4_AL0 > 8)) ; # 16 clks -# 48:51 , 0x5 , 2 , 0 , ((def_tODTL_DDR4_AL0 <= 32) && (def_tODTL_DDR4_AL0 > 16)) ; # 32 clks -# 48:51 , 0x6 , 2 , 0 , ((def_tODTL_DDR4_AL0 <= 64) && (def_tODTL_DDR4_AL0 > 32)) ; # 64 clks -# 48:51 , 0x3 , 2 , any , (def_tODTL_DDR4 <= 8) ; # 8 clks -# 48:51 , 0x4 , 2 , any , ((def_tODTL_DDR4 <= 16) && (def_tODTL_DDR4 > 8)) ; # 16 clks -# 48:51 , 0x5 , 2 , any , ((def_tODTL_DDR4 <= 32) && (def_tODTL_DDR4 > 16)) ; # 32 clks -# 48:51 , 0x6 , 2 , any , ((def_tODTL_DDR4 <= 64) && (def_tODTL_DDR4 > 32)) ; # 64 clks -# 48:51 , 0x0 , any , any , any ; # 0 clks -# # TRC_CYCLES -# 52:55 , 0x7 , ((ATTR_EFF_DRAM_TRC > 64) && (ATTR_EFF_DRAM_TRC <= 128)) ; # 2^7 = 128 clks -# 52:55 , 0x6 , ((ATTR_EFF_DRAM_TRC > 32) && (ATTR_EFF_DRAM_TRC <= 64)) ; # 2^6 = 64 clks -# 52:55 , 0x5 , ((ATTR_EFF_DRAM_TRC > 16) && (ATTR_EFF_DRAM_TRC <= 32)) ; # 2^5 = 32 clks -# 52:55 , 0x4 , ((ATTR_EFF_DRAM_TRC > 8) && (ATTR_EFF_DRAM_TRC <= 16)) ; # 2^4 = 16 clks -# 52:55 , 0x3 , (ATTR_EFF_DRAM_TRC <= 8) ; # 2^3 = 8 clks -# # TMRSC_CYCLES for RLDRAMs, set to 0 for everything else -# 56:59 , 0x0 , any ; -# # 60:63 , 0x0 , any ; # reserved -# } - +# scom 0x800(0,1)C4140301143F { # _P[0:1] bits , scom_data , expr ; # 0:47 , 0x000000000000, any ; # reserved # TODTLON_OFF_CYCLES DDR3=CWL+AL-2 DDR4 if 2tCK, CWL+AL-3 #--------------- DDR3 ------------------------------------------------------------------------- - 48:51 , 0x3 , ((def_is_ddr3) && (def_tODTL_DDR3 <= 8)) ; # 8 clks - 48:51 , 0x4 , ((def_is_ddr3) && (def_tODTL_DDR3 <= 16) && (def_tODTL_DDR3 > 8)) ; # 16 clks - 48:51 , 0x5 , ((def_is_ddr3) && (def_tODTL_DDR3 <= 32) && (def_tODTL_DDR3 > 16)) ; # 32 clks - 48:51 , 0x6 , ((def_is_ddr3) && (def_tODTL_DDR3 <= 64) && (def_tODTL_DDR3 > 32)) ; # 64 clks + 48:51 , 0x3 , ((def_is_ddr3) && (def_AL_ena) && (def_tODTL_DDR3 <= 8)) ; # 8 clks + 48:51 , 0x4 , ((def_is_ddr3) && (def_AL_ena) && (def_tODTL_DDR3 <= 16) && (def_tODTL_DDR3 > 8)) ; # 16 clks + 48:51 , 0x5 , ((def_is_ddr3) && (def_AL_ena) && (def_tODTL_DDR3 <= 32) && (def_tODTL_DDR3 > 16)) ; # 32 clks + 48:51 , 0x6 , ((def_is_ddr3) && (def_AL_ena) && (def_tODTL_DDR3 <= 64) && (def_tODTL_DDR3 > 32)) ; # 64 clks + #--------------- DDR3 and no AL --------------------------------------------------------------- + 48:51 , 0x3 , ((def_is_ddr3) && (def_AL_dis) && (def_tODTL_DDR3_NOAL <= 8)) ; # 8 clks + 48:51 , 0x4 , ((def_is_ddr3) && (def_AL_dis) && (def_tODTL_DDR3_NOAL <= 16) && (def_tODTL_DDR3_NOAL > 8)) ; # 16 clks + 48:51 , 0x5 , ((def_is_ddr3) && (def_AL_dis) && (def_tODTL_DDR3_NOAL <= 32) && (def_tODTL_DDR3_NOAL > 16)) ; # 32 clks + 48:51 , 0x6 , ((def_is_ddr3) && (def_AL_dis) && (def_tODTL_DDR3_NOAL <= 64) && (def_tODTL_DDR3_NOAL > 32)) ; # 64 clks #--------------- DDR4 ------------------------------------------------------------------------- - 48:51 , 0x3 , ((def_is_ddr4) && (def_tODTL_DDR4 <= 8)) ; # 8 clks - 48:51 , 0x4 , ((def_is_ddr4) && (def_tODTL_DDR4 <= 16) && (def_tODTL_DDR4 > 8)) ; # 16 clks - 48:51 , 0x5 , ((def_is_ddr4) && (def_tODTL_DDR4 <= 32) && (def_tODTL_DDR4 > 16)) ; # 32 clks - 48:51 , 0x6 , ((def_is_ddr4) && (def_tODTL_DDR4 <= 64) && (def_tODTL_DDR4 > 32)) ; # 64 clks + 48:51 , 0x3 , ((def_is_ddr4) && (def_AL_ena) && (def_tODTL_DDR4 <= 8)) ; # 8 clks + 48:51 , 0x4 , ((def_is_ddr4) && (def_AL_ena) && (def_tODTL_DDR4 <= 16) && (def_tODTL_DDR4 > 8)) ; # 16 clks + 48:51 , 0x5 , ((def_is_ddr4) && (def_AL_ena) && (def_tODTL_DDR4 <= 32) && (def_tODTL_DDR4 > 16)) ; # 32 clks + 48:51 , 0x6 , ((def_is_ddr4) && (def_AL_ena) && (def_tODTL_DDR4 <= 64) && (def_tODTL_DDR4 > 32)) ; # 64 clks + #--------------- DDR4 and no AL --------------------------------------------------------------- + 48:51 , 0x3 , ((def_is_ddr4) && (def_AL_dis) && (def_tODTL_DDR4_NOAL <= 8)) ; # 8 clks + 48:51 , 0x4 , ((def_is_ddr4) && (def_AL_dis) && (def_tODTL_DDR4_NOAL <= 16) && (def_tODTL_DDR4_NOAL > 8)) ; # 16 clks + 48:51 , 0x5 , ((def_is_ddr4) && (def_AL_dis) && (def_tODTL_DDR4_NOAL <= 32) && (def_tODTL_DDR4_NOAL > 16)) ; # 32 clks + 48:51 , 0x6 , ((def_is_ddr4) && (def_AL_dis) && (def_tODTL_DDR4_NOAL <= 64) && (def_tODTL_DDR4_NOAL > 32)) ; # 64 clks 48:51 , 0x0 , any ; # 0 clks # TRC_CYCLES # 52:55 , 0x7 , (def_is_sim) ; # match dials @@ -4080,8 +4082,7 @@ scom 0x800(0,1)CC020301143F { # _P[0:1] scom 0x800(0,1)CC050301143F { # _P[0:1] bits , scom_data , expr ; # 0:47 , 0x000000000000, any ; # reserved - 48 , 0b1 , (def_is_ddr4) ; # if DDR4, drive DQ pins in DATA_BIT_ENABLE1 - 48 , 0b0 , (def_not_ddr4) ; # if not DDR4, set to 0 + 48 , 0b0 , any ; # DDR4 ballot, drive DQ pins on MRS # !! need to review # MRS_CMD_DQ_ON determines the WL_per_DRAM_addr time. # WL_per_DRAM_addr = 10 + MRS_CMD_DQ_ON in 2:1 mode diff --git a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile index a83c5cd20..e30b0999c 100644 --- a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile +++ b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile @@ -1,8 +1,9 @@ -#-- $Id: mbs_def.initfile,v 1.28 2013/03/15 16:59:48 jmcgill Exp $ +#-- $Id: mbs_def.initfile,v 1.29 2013/04/08 15:52:55 yctschan Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.29 |tschang |04/08/13| added MBI cfg register initialization for Irving #-- 1.26 |tschang |03/13/13| changed cache interleave mode to have ATTR_MSS_CACHE_ENABLE as a condition #-- 1.25 |tschang |01/17/13| cache enabled when (ATTR_MSS_CACHE_ENABLE != 0) - enabled cache when 1/2 cache mode is choosen #-- 1.21 |tschang |10/23/12| disable interleaving when one or both MBA are disabled (partial good tests) @@ -395,6 +396,38 @@ define def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated = (def_mb #define def_01ATTR_EFF_MBA_POS = 0; # -MW not needed? #define def_23ATTR_EFF_MBA_POS = 1; # -MW not needed? +# YCT added for Irving +#--****************************************************************************** +#-- MBI Configuration Register +#--****************************************************************************** + scom 0x000000000201080A { + bits , scom_data ; + 0 , 0b0 ; # MBICFGQ_FORCE_CHANNEL_FAIL + 1 , 0b0 ; # MBICFGQ_REPLAY_CRC_DISABLE + 2 , 0b0 ; # MBICFGQ_REPLAY_NOACK_DISABLE + 3 , 0b0 ; # MBICFGQ_REPLAY_OUTOFORDER_DISABLE + 4 , 0b0 ; # MBICFGQ_FORCE_LFSR_REPLAY + 5 , 0b0 ; # MBICFGQ_CRC_CHECK_DISABLE + 6 , 0b0 ; # MBICFGQ_ECC_CHECK_DISABLE + 7 , 0b0 ; # MBICFGQ_START_FRAME_LOCK + 8 , 0b0 ; # MBICFGQ_FORCE_FRTL + 9 , 0b0 ; # MBICFGQ_AUTO_FRTL_DISABLE + 10:16, 0b0000000 ; # MBICFGQ_MANUAL_FRTL_VALUE + 17 , 0x0 ; # MBICFGQ_MANUAL_FRTL_DONE + 18 , 0b0 ; # MBICFGQ_ECC_CORRECT_DISABLE + 19 , 0b0 ; # MBICFGQ_SPARE1 + 20 , 0b0 ; # MBICFGQ_LANE_VOTING_BYPASS + 21:25, 0b00000 ; # MBICFGQ_BAD_LANE_VALUE + 26 , 0b0 ; # MBICFGQ_BAD_LANE_VOTING_DISABLE + 27:32, 0b010010 ; # MBICFGQ_NO_FORWARD_PROGRESS_TIMEOUT_VALUE (0x12 = 18 => 2ms) + 33:34, 0b00 ; # MBICFGQ_PERFORMANCE_DEGRADATION_PERCENT_SELECT + 35:36, 0b00 ; # MBICFGQ_CHANNEL_INITIALIZATION_STATE_MACHINE_TIMEOUT_VALUE + 37 , 0b0 ; # MBICFGQ_RESET_KEEPER + 38 , 0b0 ; # MBICFGQ_FAULT_LINE_ERROR_ENABLE + 39:43, 0b00000 ; # MBICFGQ_RESERVED + + } + ###################### # temp VBU settings # ###################### diff --git a/src/usr/hwpf/hwp/initfiles/p8.psi.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.psi.scom.initfile index dac39ed85..8f788af29 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.psi.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.psi.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: p8.psi.scom.initfile,v 1.2 2013/03/04 17:22:34 jmcgill Exp $ +#-- $Id: p8.psi.scom.initfile,v 1.3 2013/03/29 15:39:19 jmcgill Exp $ #------------------------------------------------------------------------------- #-- #-- (C) Copyright International Business Machines Corp. 2011 @@ -26,5 +26,5 @@ SyntaxVersion = 1 # PSI Host Bridge FIR Mask Register scom 0x02010903 { bits, scom_data; - 0:63, 0x9D03F9F800000000; + 0:63, 0x9D03FDF800000000; } diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C index 01ab2b3e0..99086973d 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_config_rank_group.C,v 1.8 2012/08/30 03:07:27 asaetow Exp $ +// $Id: mss_eff_config_rank_group.C,v 1.9 2013/04/01 20:08:03 asaetow Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_rank_group.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -46,7 +46,9 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- -// 1.9 | | | +// 1.10 | | | +// 1.9 | asaetow |01-APR-13| Added 32G CDIMM 1R dualdrop workaround. +// | | | NOTE: Normally primary_rank_group0=0, primary_rank_group1=4. // 1.8 | asaetow |29-AUG-12| Fixed variable init for rank_group to INVALID for PORT1. // 1.7 | asaetow |24-AUG-12| Fixed variable init for rank_group to INVALID. // 1.6 | asaetow |30-APR-12| Fixed "fapi::" for hostboot, added "const", renamed "i_target_mba", and changed comments. @@ -134,7 +136,25 @@ fapi::ReturnCode mss_eff_config_rank_group(const fapi::Target i_target_mba) { uint8_t quanternary_rank_group3_u8array[PORT_SIZE]; for (uint8_t cur_port = 0; cur_port < PORT_SIZE; cur_port += 1) { - if (dimm_type_u8 == LRDIMM) { + if ((dimm_type_u8 == CDIMM) && (num_ranks_per_dimm_u8array[cur_port][0] == 1) && (num_ranks_per_dimm_u8array[cur_port][1] == 1)) { + // NOTE: 32G CDIMM 1R dualdrop workaround, normally primary_rank_group0=0, primary_rank_group1=4. + primary_rank_group0_u8array[cur_port] = 0; + primary_rank_group1_u8array[cur_port] = INVALID; + primary_rank_group2_u8array[cur_port] = INVALID; + primary_rank_group3_u8array[cur_port] = INVALID; + secondary_rank_group0_u8array[cur_port] = 4; + secondary_rank_group1_u8array[cur_port] = INVALID; + secondary_rank_group2_u8array[cur_port] = INVALID; + secondary_rank_group3_u8array[cur_port] = INVALID; + tertiary_rank_group0_u8array[cur_port] = INVALID; + tertiary_rank_group1_u8array[cur_port] = INVALID; + tertiary_rank_group2_u8array[cur_port] = INVALID; + tertiary_rank_group3_u8array[cur_port] = INVALID; + quanternary_rank_group0_u8array[cur_port] = INVALID; + quanternary_rank_group1_u8array[cur_port] = INVALID; + quanternary_rank_group2_u8array[cur_port] = INVALID; + quanternary_rank_group3_u8array[cur_port] = INVALID; + } else if (dimm_type_u8 == LRDIMM) { // HERE: NOT correct, need to account for ATTR_EFF_DIMM_RANKS_CONFIGED for LRDIMMs /w multi master ranks primary_rank_group0_u8array[cur_port] = 0; primary_rank_group1_u8array[cur_port] = 4; diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C index ed3c8fb90..90c3e3009 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_config_shmoo.C,v 1.1 2013/02/26 12:38:20 lapietra Exp $ +// $Id: mss_eff_config_shmoo.C,v 1.2 2013/03/27 15:15:07 lapietra Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_shmoo.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -41,7 +41,7 @@ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- // 1.1 | sauchadh |26-Feb-13| Added MCBIST related attributes - +// 1.2 | sauchadh |13-Mar-13| Added Schmoo related attributes from mss_eff_config.C //---------------------------------------------------------------------- @@ -87,6 +87,51 @@ fapi::ReturnCode mss_eff_config_shmoo(const fapi::Target i_target_mba) { uint8_t addr_slave_rank_on=0; uint64_t adr_str_map=0; uint8_t addr_rand=0; + uint8_t shmoo_mode=0; + uint8_t shmoo_addr_mode=3; + uint8_t shmoo_param_valid=0; + uint8_t shmoo_test_valid=0; + uint8_t wr_eye_min_margin=0x46; + uint8_t rd_eye_min_margin=0x46; + uint8_t dqs_clk_min_margin=0x8c; + uint8_t rd_gate_min_margin=0x64; + uint8_t adr_cmd_min_margin=0x8c; + uint32_t cen_rd_vref_shmoo[2]; + cen_rd_vref_shmoo[0]=0x00000000; + cen_rd_vref_shmoo[1]=0x00000000; + uint32_t dram_wr_vref_schmoo[2]; + dram_wr_vref_schmoo[0]=0x00000000; + dram_wr_vref_schmoo[1]=0x00000000; + uint32_t cen_rcv_imp_dq_dqs_schmoo[2]; + cen_rcv_imp_dq_dqs_schmoo[0]=0x00000000; + cen_rcv_imp_dq_dqs_schmoo[1]=0x00000000; + uint32_t cen_drv_imp_dq_dqs_schmoo[2]; + cen_drv_imp_dq_dqs_schmoo[0]=0x00000000; + cen_drv_imp_dq_dqs_schmoo[1]=0x00000000; + uint8_t cen_drv_imp_cntl_schmoo[2]; + cen_drv_imp_cntl_schmoo[0]=0x00; + cen_drv_imp_cntl_schmoo[1]=0x00; + uint8_t cen_drv_imp_clk_schmoo[2]; + cen_drv_imp_clk_schmoo[0]=0x00; + cen_drv_imp_clk_schmoo[1]=0x00; + uint8_t cen_drv_imp_spcke_schmoo[2]; + cen_drv_imp_spcke_schmoo[0]=0x00; + cen_drv_imp_spcke_schmoo[1]=0x00; + uint8_t cen_slew_rate_dq_dqs_schmoo[2]; + cen_slew_rate_dq_dqs_schmoo[0]=0x00; + cen_slew_rate_dq_dqs_schmoo[1]=0x00; + uint8_t cen_slew_rate_cntl_schmoo[2]; + cen_slew_rate_cntl_schmoo[0]=0x00; + cen_slew_rate_cntl_schmoo[1]=0x00; + uint8_t cen_slew_rate_addr_schmoo[2]; + cen_slew_rate_addr_schmoo[0]=0x00; + cen_slew_rate_addr_schmoo[1]=0x00; + uint8_t cen_slew_rate_clk_schmoo[2]; + cen_slew_rate_clk_schmoo[0]=0x00; + cen_slew_rate_clk_schmoo[1]=0x00; + uint8_t cen_slew_rate_spcke_schmoo[2]; + cen_slew_rate_spcke_schmoo[0]=0x00; + cen_slew_rate_spcke_schmoo[1]=0x00; rc = FAPI_ATTR_SET(ATTR_MCBIST_PATTERN, &i_target_mba, datapattern); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_MCBIST_TEST_TYPE, &i_target_mba, testtype); if(rc) return rc; @@ -107,7 +152,28 @@ fapi::ReturnCode mss_eff_config_shmoo(const fapi::Target i_target_mba) { rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_SLAVE_RANK_ON, &i_target_mba, addr_slave_rank_on); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_STR_MAP, &i_target_mba, adr_str_map); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_RAND, &i_target_mba, addr_rand); if(rc) return rc; - + rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_MODE, &i_target_mba, shmoo_mode); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_ADDR_MODE, &i_target_mba, shmoo_addr_mode); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_PARAM_VALID, &i_target_mba, shmoo_param_valid); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, shmoo_test_valid); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_WR_EYE_MIN_MARGIN, &i_target_mba, wr_eye_min_margin); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_RD_EYE_MIN_MARGIN, &i_target_mba, rd_eye_min_margin); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_DQS_CLK_MIN_MARGIN, &i_target_mba, dqs_clk_min_margin); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_RD_GATE_MIN_MARGIN, &i_target_mba, rd_gate_min_margin); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_ADDR_CMD_MIN_MARGIN, &i_target_mba, adr_cmd_min_margin); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF_SCHMOO, &i_target_mba, cen_rd_vref_shmoo); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF_SCHMOO, &i_target_mba, dram_wr_vref_schmoo); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO, &i_target_mba, cen_rcv_imp_dq_dqs_schmoo); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO, &i_target_mba, cen_drv_imp_dq_dqs_schmoo); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CNTL_SCHMOO, &i_target_mba, cen_drv_imp_cntl_schmoo); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CLK_SCHMOO, &i_target_mba, cen_drv_imp_clk_schmoo); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_SPCKE_SCHMOO, &i_target_mba, cen_drv_imp_spcke_schmoo); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO, &i_target_mba, cen_slew_rate_dq_dqs_schmoo); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CNTL_SCHMOO, &i_target_mba, cen_slew_rate_cntl_schmoo); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_ADDR_SCHMOO, &i_target_mba, cen_slew_rate_addr_schmoo); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CLK_SCHMOO, &i_target_mba, cen_slew_rate_clk_schmoo); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_SPCKE_SCHMOO, &i_target_mba, cen_slew_rate_spcke_schmoo); if(rc) return rc; + FAPI_INF("%s on %s COMPLETE", PROCEDURE_NAME, i_target_mba.toEcmdString()); return rc; } diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C index dc5a8cba0..0c564c3b4 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_config_termination.C,v 1.15 2013/03/14 13:23:58 lapietra Exp $ +// $Id: mss_eff_config_termination.C,v 1.18 2013/04/10 16:31:47 lapietra Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_termination.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -42,7 +42,10 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- -// 1.15 | dcadiga |14-MAR-13| Fixed simulation issue +// 1.18 | dcadiga |10-APR-13| Added UDIMM for ICICLE DDR4, fixed DD0 Clk shift +// 1.17 | asaetow |26-MAR-13| Removed width check for RDIMM MBA0 4Rank 1333. +// 1.16 | dcadiga |25-MAR-13| Added in 2N Addressing Mode. +// 1.15 | dcadiga |14-MAR-13| Fixed simulation issue. // 1.14 | dcadiga |12-MAR-13| Code re-write for new dimms. Confirmed working on all systems // 1.13 | asaetow |19-FEB-12| Changed default SI value for CDIMM, turned of Rtt_NOM and disabled Rtt_WR for DIMM1. // 1.12 | asaetow |07-FEB-12| Added check for Centaur EC10 ADR Centerlane NWELL workaround. @@ -158,6 +161,7 @@ uint8_t attr_eff_cen_phase_rot_m1_cntl_csn2[PORT_SIZE]; uint8_t attr_eff_cen_phase_rot_m1_cntl_csn3[PORT_SIZE]; uint8_t attr_eff_cen_phase_rot_m1_cntl_odt0[PORT_SIZE]; uint8_t attr_eff_cen_phase_rot_m1_cntl_odt1[PORT_SIZE]; +uint8_t attr_eff_dram_2n_mode_enabled; /* const uint8_t valid_attrs[200] = { @@ -366,151 +370,160 @@ attr_eff_cen_phase_rot_m1_cntl_odt1[1] //Declare the different dimms here: //Cdimm rc_A uint32_t cdimm_rca_1r_1333_mba0[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,89,0,91,0,13,13,13,8,5,6,8,7,9,13,17,14,14,14,13,17,12,11,17,18,17,18,0,0,19,0,21,0,0,0,0,0,2,0,19,0,0,0,7,0,0,0,3,0,86,0,92,0,17,15,18,8,6,5,7,6,12,12,18,12,16,15,13,16,10,9,17,18,21,19,0,0,19,0,24,0,2,0,0,0,2,0,20,0,0,0,3,0,0,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,89,0,91,0,13,13,13,8,5,6,8,7,9,13,17,14,14,14,13,17,12,11,17,18,17,18,0,0,19,0,21,0,0,0,0,0,2,0,19,0,0,0,7,0,0,0,3,0,86,0,92,0,17,15,18,8,6,5,7,6,12,12,18,12,16,15,13,16,10,9,17,18,21,19,0,0,19,0,24,0,2,0,0,0,2,0,20,0,0,0,3,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t cdimm_rca_1r_1333_mba1[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,87,0,92,0,18,18,18,11,11,11,13,13,15,18,16,18,17,20,18,15,9,11,14,15,18,14,0,0,26,0,32,0,11,0,0,0,3,0,29,0,0,0,2,0,0,0,10,0,86,0,91,0,12,13,15,6,7,9,9,8,9,15,11,15,12,14,15,12,6,7,12,12,11,11,0,0,17,0,31,0,1,0,0,0,0,0,17,0,0,0,6,0,0,0,1,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,87,0,92,0,18,18,18,11,11,11,13,13,15,18,16,18,17,20,18,15,9,11,14,15,18,14,0,0,26,0,32,0,11,0,0,0,3,0,29,0,0,0,2,0,0,0,10,0,86,0,91,0,12,13,15,6,7,9,9,8,9,15,11,15,12,14,15,12,6,7,12,12,11,11,0,0,17,0,31,0,1,0,0,0,0,0,17,0,0,0,6,0,0,0,1,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t cdimm_rca_1r_1600_mba0[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,93,0,96,0,15,16,15,10,7,7,10,9,11,15,20,16,17,16,16,20,14,13,21,22,21,21,0,0,24,0,27,0,0,0,0,0,2,0,24,0,0,0,9,0,0,0,4,0,90,0,98,0,20,18,21,10,7,7,9,7,15,14,22,15,20,18,16,20,12,11,21,22,25,23,0,0,24,0,30,0,3,0,0,0,2,0,25,0,0,0,4,0,0,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,93,0,96,0,15,16,15,10,7,7,10,9,11,15,20,16,17,16,16,20,14,13,21,22,21,21,0,0,24,0,27,0,0,0,0,0,2,0,24,0,0,0,9,0,0,0,4,0,90,0,98,0,20,18,21,10,7,7,9,7,15,14,22,15,20,18,16,20,12,11,21,22,25,23,0,0,24,0,30,0,3,0,0,0,2,0,25,0,0,0,4,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t cdimm_rca_1r_1600_mba1[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,91,0,97,0,22,22,21,14,13,14,16,15,19,21,19,22,21,24,22,18,11,13,17,18,22,17,0,0,32,0,39,0,13,0,0,0,3,0,35,0,0,0,3,0,0,0,12,0,90,0,96,0,15,16,18,8,9,10,11,10,11,18,13,18,15,17,18,15,8,8,14,15,13,13,0,0,22,0,38,0,1,0,0,0,0,0,22,0,0,0,7,0,0,0,1,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,91,0,97,0,22,22,21,14,13,14,16,15,19,21,19,22,21,24,22,18,11,13,17,18,22,17,0,0,32,0,39,0,13,0,0,0,3,0,35,0,0,0,3,0,0,0,12,0,90,0,96,0,15,16,18,8,9,10,11,10,11,18,13,18,15,17,18,15,8,8,14,15,13,13,0,0,22,0,38,0,1,0,0,0,0,0,22,0,0,0,7,0,0,0,1,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t cdimm_rca_2r_1333_mba0[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,95,0,103,0,6,7,7,3,0,0,3,2,4,6,11,8,8,7,7,11,6,6,11,12,11,12,0,0,31,0,24,0,12,0,0,0,14,0,31,0,34,0,19,0,0,0,15,0,90,0,99,0,11,9,12,2,0,0,1,0,7,5,12,6,10,9,7,10,4,4,11,12,15,13,0,0,32,0,27,0,14,0,0,0,14,0,33,0,33,0,15,0,0,0,12,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,95,0,103,0,6,7,7,3,0,0,3,2,4,6,11,8,8,7,7,11,6,6,11,12,11,12,0,0,31,0,24,0,12,0,0,0,14,0,31,0,34,0,19,0,0,0,15,0,90,0,99,0,11,9,12,2,0,0,1,0,7,5,12,6,10,9,7,10,4,4,11,12,15,13,0,0,32,0,27,0,14,0,0,0,14,0,33,0,33,0,15,0,0,0,12,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t cdimm_rca_2r_1333_mba1[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,90,0,98,0,11,11,10,5,4,5,6,6,9,10,8,11,10,13,11,8,3,4,7,7,11,7,0,0,38,0,34,0,21,0,0,0,14,0,41,0,34,0,13,0,0,0,21,0,91,0,99,0,7,8,10,2,2,4,4,3,5,10,5,10,7,9,10,7,1,2,6,7,5,5,0,0,31,0,36,0,14,0,0,0,13,0,31,0,32,0,19,0,0,0,13,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,90,0,98,0,11,11,10,5,4,5,6,6,9,10,8,11,10,13,11,8,3,4,7,7,11,7,0,0,38,0,34,0,21,0,0,0,14,0,41,0,34,0,13,0,0,0,21,0,91,0,99,0,7,8,10,2,2,4,4,3,5,10,5,10,7,9,10,7,1,2,6,7,5,5,0,0,31,0,36,0,14,0,0,0,13,0,31,0,32,0,19,0,0,0,13,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t cdimm_rca_2r_1600_mba0[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,100,0,109,0,9,9,9,3,0,0,3,2,4,8,14,10,10,10,9,14,7,6,14,15,14,15,0,0,37,0,29,0,14,0,0,0,16,0,37,0,40,0,23,0,0,0,17,0,95,0,105,0,13,11,14,3,0,0,2,0,8,7,15,8,13,11,9,13,5,4,14,15,18,16,0,0,38,0,32,0,16,0,0,0,16,0,39,0,40,0,18,0,0,0,14,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,100,0,109,0,9,9,9,3,0,0,3,2,4,8,14,10,10,10,9,14,7,6,14,15,14,15,0,0,37,0,29,0,14,0,0,0,16,0,37,0,40,0,23,0,0,0,17,0,95,0,105,0,13,11,14,3,0,0,2,0,8,7,15,8,13,11,9,13,5,4,14,15,18,16,0,0,38,0,32,0,16,0,0,0,16,0,39,0,40,0,18,0,0,0,14,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t cdimm_rca_2r_1600_mba1[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,95,0,104,0,14,14,13,6,5,6,8,8,11,13,11,14,12,16,14,10,3,5,9,9,13,9,0,0,44,0,40,0,25,0,0,0,16,0,47,0,41,0,15,0,0,0,24,0,96,0,104,0,9,10,12,2,3,4,5,4,5,12,7,12,8,11,12,9,1,2,8,9,7,7,0,0,37,0,42,0,15,0,0,0,15,0,36,0,38,0,21,0,0,0,15,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,95,0,104,0,14,14,13,6,5,6,8,8,11,13,11,14,12,16,14,10,3,5,9,9,13,9,0,0,44,0,40,0,25,0,0,0,16,0,47,0,41,0,15,0,0,0,24,0,96,0,104,0,9,10,12,2,3,4,5,4,5,12,7,12,8,11,12,9,1,2,8,9,7,7,0,0,37,0,42,0,15,0,0,0,15,0,36,0,38,0,21,0,0,0,15,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; //Cdimm rc_A DD1.0 uint32_t cdimm_rca_1r_1333_mba0_DD10[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,57,0,59,0,64,0,0,0,0,0,0,0,0,0,0,0,64,64,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,54,0,60,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,64,0,64,0,0,0,0,0,0,0,0,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,57,0,59,0,64,0,0,0,0,0,0,0,0,0,0,0,64,64,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,54,0,60,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,64,0,64,0,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t cdimm_rca_1r_1333_mba1_DD10[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,55,0,60,0,0,64,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,54,0,59,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,64,0,0,0,0,0,0,0,64,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,55,0,60,0,0,64,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,54,0,59,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,64,0,0,0,0,0,0,0,64,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t cdimm_rca_1r_1600_mba0_DD10[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,61,0,64,0,64,0,0,0,0,0,0,0,0,0,0,0,64,64,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,58,0,66,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,64,0,64,0,0,0,0,0,0,0,0,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,61,0,64,0,64,0,0,0,0,0,0,0,0,0,0,0,64,64,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,58,0,66,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,64,0,64,0,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t cdimm_rca_1r_1600_mba1_DD10[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,59,0,65,0,0,64,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,7,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,0,64,58,0,64,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,6,0,64,0,0,0,64,0,0,0,0,0,0,0,64,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,59,0,65,0,0,64,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,7,0,0,0,0,0,0,0,3,0,0,0,0,0,0,0,0,64,58,0,64,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,6,0,64,0,0,0,64,0,0,0,0,0,0,0,64,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t cdimm_rca_2r_1333_mba0_DD10[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,71,0,64,0,0,0,0,0,0,0,0,0,0,0,64,64,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,58,0,67,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,64,0,64,0,1,0,1,0,0,0,0,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,71,0,64,0,0,0,0,0,0,0,0,0,0,0,64,64,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,0,0,0,0,0,58,0,67,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,64,0,64,0,1,0,1,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t cdimm_rca_2r_1333_mba1_DD10[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,58,0,66,0,0,64,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,6,0,2,0,0,0,0,0,0,0,9,0,2,0,0,0,0,0,0,64,59,0,67,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4,0,64,0,0,0,64,0,0,0,0,0,0,0,64,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,58,0,66,0,0,64,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,6,0,2,0,0,0,0,0,0,0,9,0,2,0,0,0,0,0,0,64,59,0,67,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4,0,64,0,0,0,64,0,0,0,0,0,0,0,64,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t cdimm_rca_2r_1600_mba0_DD10[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,68,0,77,0,64,0,0,0,0,0,0,0,0,0,0,0,64,64,0,0,64,0,0,0,0,0,0,0,5,0,0,0,0,0,0,0,0,0,5,0,8,0,0,0,0,0,0,0,63,0,73,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,64,0,64,0,7,0,8,0,0,0,0,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,68,0,77,0,64,0,0,0,0,0,0,0,0,0,0,0,64,64,0,0,64,0,0,0,0,0,0,0,5,0,0,0,0,0,0,0,0,0,5,0,8,0,0,0,0,0,0,0,63,0,73,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,64,0,64,0,7,0,8,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t cdimm_rca_2r_1600_mba1_DD10[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,72,0,0,64,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,12,0,8,0,0,0,0,0,0,0,15,0,9,0,0,0,0,0,0,64,64,0,72,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,5,0,10,0,64,0,0,0,64,0,4,0,6,0,0,0,64,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,72,0,0,64,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,12,0,8,0,0,0,0,0,0,0,15,0,9,0,0,0,0,0,0,64,64,0,72,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,5,0,10,0,64,0,0,0,64,0,4,0,6,0,0,0,64,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; //RDIMM A/B Ports MBA0 Glacier uint32_t rdimm_glacier_1600_r10_mba0[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,7,9,11,10,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,7,9,11,10,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t rdimm_glacier_1333_r20e_mba0[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,67,0,0,0,1,2,2,4,0,1,3,2,5,2,6,3,3,3,2,7,7,7,6,8,6,7,7,0,2,10,0,0,0,10,2,10,2,9,0,0,0,0,0,0,0,0,0,0,71,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,1,3,0,0,3,7,2,9,1,10,0,0,0,0,0,0,0,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,67,0,0,0,1,2,2,4,0,1,3,2,5,2,6,3,3,3,2,7,7,7,6,8,6,7,7,0,2,10,0,0,0,10,2,10,2,9,0,0,0,0,0,0,0,0,0,0,71,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,1,3,0,0,3,7,2,9,1,10,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t rdimm_glacier_1600_r20e_mba0[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,66,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,75,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,8,9,11,11,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,66,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,75,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,8,9,11,11,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t rdimm_glacier_1333_r20b_mba0[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,2,2,4,0,1,3,2,5,2,6,3,3,3,2,6,7,7,6,8,6,7,7,0,2,10,0,0,0,10,2,10,2,9,0,0,0,0,0,0,0,0,0,0,68,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,2,4,0,0,4,8,3,10,2,10,0,0,0,0,0,0,0,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,2,2,4,0,1,3,2,5,2,6,3,3,3,2,6,7,7,6,8,6,7,7,0,2,10,0,0,0,10,2,10,2,9,0,0,0,0,0,0,0,0,0,0,68,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,2,4,0,0,4,8,3,10,2,10,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t rdimm_glacier_1600_r20b_mba0[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,8,9,11,11,4,0,3,5,0,0,5,10,3,12,3,13,0,0,0,0,0,0,0,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,8,9,11,11,4,0,3,5,0,0,5,10,3,12,3,13,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t rdimm_glacier_1333_r40_mba0[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,4,1,1,4,3,5,2,7,3,4,3,3,7,7,7,7,8,7,8,7,0,3,11,0,0,1,11,3,11,3,10,0,0,0,0,0,0,0,0,0,0,71,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,2,4,0,0,4,8,3,10,3,11,0,0,0,0,0,0,0,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,4,1,1,4,3,5,2,7,3,4,3,3,7,7,7,7,8,7,8,7,0,3,11,0,0,1,11,3,11,3,10,0,0,0,0,0,0,0,0,0,0,71,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,2,4,0,0,4,8,3,10,3,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; //RDIMM C/D Ports MBA1 Glacier uint32_t rdimm_glacier_1333_r10_mba1[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,12,11,12,11,8,12,13,13,16,12,9,12,11,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,10,10,13,10,11,13,13,12,13,13,9,13,10,12,13,10,10,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,12,11,12,11,8,12,13,13,16,12,9,12,11,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,10,10,13,10,11,13,13,12,13,13,9,13,10,12,13,10,10,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t rdimm_glacier_1600_r10_mba1[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,10,2,0,0,13,2,12,5,4,2,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,12,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,10,2,0,0,13,2,12,5,4,2,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,12,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t rdimm_glacier_1333_r20e_mba1[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,0,0,12,11,12,11,8,12,13,13,16,12,9,12,11,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,73,0,0,0,10,10,13,11,11,13,13,12,13,13,9,13,10,12,13,10,10,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,0,0,12,11,12,11,8,12,13,13,16,12,9,12,11,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,73,0,0,0,10,10,13,11,11,13,13,12,13,13,9,13,10,12,13,10,10,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t rdimm_glacier_1600_r20e_mba1[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,77,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,9,1,0,0,13,2,12,5,4,1,0,0,0,0,0,0,0,0,0,0,77,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,13,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,3,11,0,0,0,0,0,0,0,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,77,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,9,1,0,0,13,2,12,5,4,1,0,0,0,0,0,0,0,0,0,0,77,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,13,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,3,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t rdimm_glacier_1333_r20b_mba1[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,12,10,12,11,8,11,13,13,16,12,9,12,10,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,10,10,13,10,10,13,13,12,13,13,8,13,10,12,13,10,9,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,12,10,12,11,8,11,13,13,16,12,9,12,10,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,10,10,13,10,10,13,13,12,13,13,8,13,10,12,13,10,9,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t rdimm_glacier_1600_r20b_mba1[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,14,13,15,14,10,14,16,17,21,15,11,15,13,17,15,9,11,13,8,10,14,7,11,0,10,1,0,0,13,2,12,5,4,1,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,16,10,16,12,15,17,12,12,12,11,12,9,9,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,14,13,15,14,10,14,16,17,21,15,11,15,13,17,15,9,11,13,8,10,14,7,11,0,10,1,0,0,13,2,12,5,4,1,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,16,10,16,12,15,17,12,12,12,11,12,9,9,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t rdimm_glacier_1066_r40_mba1[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,10,9,10,9,7,10,11,11,14,10,7,10,9,12,10,6,7,8,5,7,9,5,7,0,7,1,0,0,9,1,8,3,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,8,8,11,8,9,10,11,10,11,11,7,11,8,10,11,8,8,8,7,8,6,6,10,0,3,10,0,0,3,10,3,9,2,8,0,0,0,0,0,0,0,0,0,0 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,10,9,10,9,7,10,11,11,14,10,7,10,9,12,10,6,7,8,5,7,9,5,7,0,7,1,0,0,9,1,8,3,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,8,8,11,8,9,10,11,10,11,11,7,11,8,10,11,8,8,8,7,8,6,6,10,0,3,10,0,0,3,10,3,9,2,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t rdimm_glacier_1333_r11_mba1[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,69,0,18,17,18,17,14,18,19,19,22,18,15,18,17,20,18,13,15,16,13,14,17,12,15,0,11,5,0,0,14,5,13,7,7,5,11,2,0,0,3,3,5,3,8,2,73,0,69,0,16,16,19,16,17,19,19,18,19,19,15,19,16,18,19,16,16,16,15,16,14,14,18,0,7,15,0,0,7,15,7,14,6,13,4,12,0,0,9,14,9,11,4,11 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,69,0,18,17,18,17,14,18,19,19,22,18,15,18,17,20,18,13,15,16,13,14,17,12,15,0,11,5,0,0,14,5,13,7,7,5,11,2,0,0,3,3,5,3,8,2,73,0,69,0,16,16,19,16,17,19,19,18,19,19,15,19,16,18,19,16,16,16,15,16,14,14,18,0,7,15,0,0,7,15,7,14,6,13,4,12,0,0,9,14,9,11,4,11,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t rdimm_glacier_1600_r11_mba1[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,76,0,71,0,21,20,22,20,17,21,23,23,27,22,18,22,20,24,21,15,18,20,15,17,20,14,18,0,14,6,0,0,17,6,17,10,9,6,13,2,0,0,4,3,5,3,10,3,76,0,71,0,19,20,23,20,20,23,23,22,23,23,17,23,19,22,23,19,19,19,18,19,16,16,22,0,9,19,0,0,9,20,9,18,8,16,4,15,0,0,11,17,10,13,5,13 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,76,0,71,0,21,20,22,20,17,21,23,23,27,22,18,22,20,24,21,15,18,20,15,17,20,14,18,0,14,6,0,0,17,6,17,10,9,6,13,2,0,0,4,3,5,3,10,3,76,0,71,0,19,20,23,20,20,23,23,22,23,23,17,23,19,22,23,19,19,19,18,19,16,16,22,0,9,19,0,0,9,20,9,18,8,16,4,15,0,0,11,17,10,13,5,13,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t rdimm_glacier_1333_r22e_mba1[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,77,0,72,0,17,16,18,17,14,17,18,19,22,18,15,18,16,19,17,13,14,16,12,14,17,11,14,0,12,5,0,0,14,5,14,8,7,5,11,2,0,0,3,3,5,3,8,2,77,0,72,0,16,16,19,16,16,18,19,18,19,19,14,18,16,18,19,16,15,16,15,16,13,13,18,0,8,15,0,0,8,16,8,15,7,13,4,12,0,0,9,14,9,11,4,11 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,77,0,72,0,17,16,18,17,14,17,18,19,22,18,15,18,16,19,17,13,14,16,12,14,17,11,14,0,12,5,0,0,14,5,14,8,7,5,11,2,0,0,3,3,5,3,8,2,77,0,72,0,16,16,19,16,16,18,19,18,19,19,14,18,16,18,19,16,15,16,15,16,13,13,18,0,8,15,0,0,8,16,8,15,7,13,4,12,0,0,9,14,9,11,4,11,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t rdimm_glacier_1600_r22e_mba1[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,81,0,77,0,21,19,21,20,16,21,22,23,27,22,17,21,19,23,21,15,17,19,14,16,20,13,17,0,13,5,0,0,16,5,15,8,7,5,13,2,0,0,4,3,5,3,10,2,81,0,77,0,19,19,23,19,19,22,23,21,23,23,17,22,19,21,23,19,18,19,18,19,16,16,22,0,7,17,0,0,8,18,8,16,7,15,4,15,0,0,11,17,10,13,5,13 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,81,0,77,0,21,19,21,20,16,21,22,23,27,22,17,21,19,23,21,15,17,19,14,16,20,13,17,0,13,5,0,0,16,5,15,8,7,5,13,2,0,0,4,3,5,3,10,2,81,0,77,0,19,19,23,19,19,22,23,21,23,23,17,22,19,21,23,19,18,19,18,19,16,16,22,0,7,17,0,0,8,18,8,16,7,15,4,15,0,0,11,17,10,13,5,13,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t rdimm_glacier_1333_r22b_mba1[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,69,0,16,14,16,15,12,16,17,17,21,16,12,16,14,18,16,10,12,14,10,12,15,9,12,0,12,6,0,0,15,6,14,8,8,6,11,2,0,0,3,3,5,3,8,2,73,0,69,0,14,14,17,14,14,17,17,16,17,17,12,17,14,16,17,13,13,14,13,14,11,11,16,0,8,16,0,0,8,17,8,15,7,14,4,12,0,0,9,14,9,11,4,10 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,69,0,16,14,16,15,12,16,17,17,21,16,12,16,14,18,16,10,12,14,10,12,15,9,12,0,12,6,0,0,15,6,14,8,8,6,11,2,0,0,3,3,5,3,8,2,73,0,69,0,14,14,17,14,14,17,17,16,17,17,12,17,14,16,17,13,13,14,13,14,11,11,16,0,8,16,0,0,8,17,8,15,7,14,4,12,0,0,9,14,9,11,4,10,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t rdimm_glacier_1600_r22b_mba1[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,78,0,71,0,20,18,20,19,15,20,21,22,26,21,16,21,18,23,20,14,16,18,13,15,19,12,16,0,16,8,0,0,20,8,19,12,11,8,14,2,0,0,4,3,6,3,10,3,78,0,71,0,17,18,22,18,18,21,22,20,22,22,15,21,17,20,22,17,17,17,16,17,14,14,21,0,11,21,0,0,11,22,11,20,10,18,4,15,0,0,11,17,11,13,5,13 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0x20,0x20,0x00,0x00,0x80,0x80,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,0xA0,0x60,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,78,0,71,0,20,18,20,19,15,20,21,22,26,21,16,21,18,23,20,14,16,18,13,15,19,12,16,0,16,8,0,0,20,8,19,12,11,8,14,2,0,0,4,3,6,3,10,3,78,0,71,0,17,18,22,18,18,21,22,20,22,22,15,21,17,20,22,17,17,17,16,17,14,14,21,0,11,21,0,0,11,22,11,20,10,18,4,15,0,0,11,17,11,13,5,13,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; uint32_t rdimm_glacier_1066_r44_mba1[200] = -{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,0x20,0x20,0x20,0x20,0x80,0x80,0x80,0x80,0x20,0x20,0x20,0x20,0x80,0x80,0x80,0x80,0xA0,0x20,0x60,0x20,0xA0,0x80,0x90,0x80,0xA0,0x20,0x60,0x20,0xA0,0x80,0x90,0x80,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,74,0,68,0,15,14,15,14,12,15,16,16,19,15,12,15,14,17,15,11,12,14,10,12,14,9,12,0,12,7,0,0,15,7,14,9,9,7,9,1,0,0,3,2,4,3,7,2,74,0,68,0,13,14,16,14,14,16,16,15,16,16,12,16,13,15,16,13,13,13,12,13,11,11,15,0,9,15,0,0,9,16,9,15,8,14,3,10,0,0,8,12,7,9,3,9 +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,0x20,0x20,0x20,0x20,0x80,0x80,0x80,0x80,0x20,0x20,0x20,0x20,0x80,0x80,0x80,0x80,0xA0,0x20,0x60,0x20,0xA0,0x80,0x90,0x80,0xA0,0x20,0x60,0x20,0xA0,0x80,0x90,0x80,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,74,0,68,0,15,14,15,14,12,15,16,16,19,15,12,15,14,17,15,11,12,14,10,12,14,9,12,0,12,7,0,0,15,7,14,9,9,7,9,1,0,0,3,2,4,3,7,2,74,0,68,0,13,14,16,14,14,16,16,15,16,16,12,16,13,15,16,13,13,13,12,13,11,11,15,0,9,15,0,0,9,16,9,15,8,14,3,10,0,0,8,12,7,9,3,9,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +}; + +//UDIMM TEMP FOR JAKE ICICLE +uint32_t udimm_glacier_1600_r10_mba0[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,7,9,11,10,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE +}; + +uint32_t udimm_glacier_1600_r10_mba1[200] = +{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,10,2,0,0,13,2,12,5,4,2,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,12,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE }; @@ -722,9 +735,42 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { }//End CDIMM else{ //This is a UDIMM! - FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA0\n",l_mss_freq); - FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA1\n",l_mss_freq); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + if( l_target_mba_pos == 0 ){ + if ( l_mss_freq <= 1733 ) { // 1600Mbps + if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 8)){ + memcpy(base_var_array,udimm_glacier_1600_r10_mba0,200*sizeof(uint32_t)); + FAPI_INF("UDIMM ICICLE r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else{ + FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA0\n",l_mss_freq); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + + } + } + else{ + FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA0\n",l_mss_freq); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + } + else{ + if ( l_mss_freq <= 1733 ) { // 1600Mbps + if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 8)){ + memcpy(base_var_array,udimm_glacier_1600_r10_mba1,200*sizeof(uint32_t)); + FAPI_INF("UDIMM ICICLE r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else{ + FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA0\n",l_mss_freq); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + + } + } + else{ + FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA1\n",l_mss_freq); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + } + + }//End UDIMM @@ -740,7 +786,7 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { memcpy(base_var_array,rdimm_glacier_1333_r20b_mba0,200*sizeof(uint32_t)); FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } - else if((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 8)){ + else if((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){ memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,200*sizeof(uint32_t)); FAPI_INF("RDIMM r40 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } @@ -1124,6 +1170,8 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { attr_eff_cen_phase_rot_m1_cntl_csn3[1] = base_var_array[i++]; attr_eff_cen_phase_rot_m1_cntl_odt0[1] = base_var_array[i++]; attr_eff_cen_phase_rot_m1_cntl_odt1[1] = base_var_array[i++]; + attr_eff_dram_2n_mode_enabled = base_var_array[i++]; + //Now Setup the RCD - Done Here to Steal Code From Anuwats Version Of Eff Config Termination @@ -1271,6 +1319,9 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_csn3); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_odt0); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_odt1); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_2N_MODE_ENABLED, &i_target_mba, attr_eff_dram_2n_mode_enabled); if(rc) return rc; + + FAPI_INF("%s on %s COMPLETE", PROCEDURE_NAME, i_target_mba.toEcmdString()); return rc; |
