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| author | Dean Sanner <dsanner@us.ibm.com> | 2014-02-07 07:29:27 -0600 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-03-10 11:07:31 -0500 |
| commit | 333bb8c7bd7a29a688ddbe327a0b0543d422e402 (patch) | |
| tree | 01f51303dbbf98b6cb0bc4c139e9a064c22cbf35 /src/usr/hwpf | |
| parent | dd80c1a13def1a956cd88709f0e04e4b8c703ef1 (diff) | |
| download | talos-hostboot-333bb8c7bd7a29a688ddbe327a0b0543d422e402.tar.gz talos-hostboot-333bb8c7bd7a29a688ddbe327a0b0543d422e402.zip | |
Update HB memory map to match PHYP/Saph
Change-Id: I5c4c94e0fc6dee237ffe0a209d5d170cb20f02bd
CQ: SW247135
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/8924
Tested-by: Jenkins Server
Reviewed-by: MIKE J. JONES <mjjones@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf')
| -rw-r--r-- | src/usr/hwpf/plat/fapiPlatAttributeService.C | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/src/usr/hwpf/plat/fapiPlatAttributeService.C b/src/usr/hwpf/plat/fapiPlatAttributeService.C index ef6c493d6..cc2ad3f7f 100644 --- a/src/usr/hwpf/plat/fapiPlatAttributeService.C +++ b/src/usr/hwpf/plat/fapiPlatAttributeService.C @@ -867,8 +867,8 @@ fapi::ReturnCode fapiPlatGetProcPcieBarEnable ( phyp_mode = true; } - // BAR # 0 are the PCIE unit #'s - // BAR # 1 is reserved, should be DISabled (per Joe McGill) + // BAR # 0 are the PCIE Mem 64 + // BAR # 1 are the PCIE Mem 32 // BAR # 2 are the PHB REGS for( uint8_t u=0; u<3; u++ ) { @@ -881,7 +881,7 @@ fapi::ReturnCode fapiPlatGetProcPcieBarEnable ( else { o_pcieBarEnable[u][0] = l_isEnabled ; - o_pcieBarEnable[u][1] = PROC_BARS_DISABLE ; + o_pcieBarEnable[u][1] = l_isEnabled ; o_pcieBarEnable[u][2] = l_isEnabled ; } @@ -923,20 +923,23 @@ fapi::ReturnCode fapiPlatGetProcPcieBarBaseAddr ( else { // Pull the data out of the Hostboot attribute - uint64_t l_pciMem[4]; - l_pProcTarget->tryGetAttr<TARGETING::ATTR_PCI_BASE_ADDRS>( - l_pciMem); + uint64_t l_pciMem32[4]; + uint64_t l_pciMem64[4]; + l_pProcTarget->tryGetAttr<TARGETING::ATTR_PCI_BASE_ADDRS_32>( + l_pciMem32); + l_pProcTarget->tryGetAttr<TARGETING::ATTR_PCI_BASE_ADDRS_64>( + l_pciMem64); uint64_t l_phbRegs[4]; l_pProcTarget->tryGetAttr<TARGETING::ATTR_PHB_BASE_ADDRS>( l_phbRegs); - // BAR # 0 are the PCIE unit #'s - // BAR # 1 is disabled, set to 0 + // BAR # 0 are the PCIE mem 64 + // BAR # 1 are the PCIE mem 32 // BAR # 2 are the PHB REGS for ( uint8_t u=0; u < 3; u++ ) { - o_pcieBarBase[u][0] = l_pciMem[u]; - o_pcieBarBase[u][1] = 0; + o_pcieBarBase[u][0] = l_pciMem64[u]; + o_pcieBarBase[u][1] = l_pciMem32[u]; o_pcieBarBase[u][2] = l_phbRegs[u]; FAPI_DBG( "fapiPlatGetProcPcieBarBaseAddr: Unit %d : %p %p %p", @@ -967,12 +970,11 @@ fapi::ReturnCode fapiPlatGetProcPcieBarSize ( else { // NOTE: supported BAR0/1 sizes are from 64KB-1PB - // NOTE: BAR1 is disabled, set to 0 // NOTE: only supported BAR2 size is 4KB for ( uint8_t u=0; u < 3; u++ ) { o_pcieBarSize[u][0] = PCIE_BAR0_SIZE ; - o_pcieBarSize[u][1] = 0 ; + o_pcieBarSize[u][1] = PCIE_BAR1_SIZE ; o_pcieBarSize[u][2] = PCIE_BAR2_SIZE; FAPI_DBG( "fapiPlatGetProcPcieBarSize: Unit %d : %p %p %p", |
