diff options
| author | Thi Tran <thi@us.ibm.com> | 2013-04-23 14:31:45 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-04-24 09:12:17 -0500 |
| commit | 1431dbb451ab63db0d628bd24ac1d4cc4548d7f7 (patch) | |
| tree | fb1414e4ae4a1d237bcbcc0c9c11e244a6474740 /src/usr/hwpf | |
| parent | 9f992dec233540e053c2c520a2f07aa66cabd7be (diff) | |
| download | talos-hostboot-1431dbb451ab63db0d628bd24ac1d4cc4548d7f7.tar.gz talos-hostboot-1431dbb451ab63db0d628bd24ac1d4cc4548d7f7.zip | |
TULETA Bring Up - Updates for PLL for A, DMI locking 04/23i
SW196588
Change-Id: Ib4645e3630992c2d2f41f54050673e08f05b6591
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4179
Tested-by: Jenkins Server
Reviewed-by: Van H. Lee <vanlee@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf')
9 files changed, 1060 insertions, 897 deletions
diff --git a/src/usr/hwpf/hwp/nest_chiplets/makefile b/src/usr/hwpf/hwp/nest_chiplets/makefile index b9b826bce..03fbc7d64 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/makefile +++ b/src/usr/hwpf/hwp/nest_chiplets/makefile @@ -51,7 +51,8 @@ OBJS = nest_chiplets.o \ proc_a_x_pci_dmi_pll_setup.o \ proc_pcie_scominit.o \ proc_abus_scominit.o \ - proc_xbus_scominit.o + proc_xbus_scominit.o \ + proc_a_x_pci_dmi_pll_utils.o ## NOTE: add a new directory onto the vpaths when you add a new HWP VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C index c665d7ccc..a13da8498 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C @@ -20,8 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// -*- mode: C++; c-file-style: "linux"; -*- -// $Id: proc_a_x_pci_dmi_pll_initf.C,v 1.11 2013/01/24 16:34:45 jmcgill Exp $ +// $Id: proc_a_x_pci_dmi_pll_initf.C,v 1.13 2013/04/18 17:33:35 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_initf.C,v $ //------------------------------------------------------------------------------ // *| @@ -30,16 +29,15 @@ // *! *** IBM Confidential *** // *| // *! TITLE : proc_a_x_pci_dmi_pll_initf.C -// *! DESCRIPTION : Configure the PLLs +// *! DESCRIPTION : Scan PLL settings for A/X/PCI/DMI PLLs // *! // *! OWNER NAME : Ralph Koester Email: rkoester@de.ibm.com // *! -// *! The purpose of this procedure is to setup the PLLs +// *! The purpose of this procedure is to scan in runtime PLL settings +// *! for the X/A/PCIE/DMI PLLs // *! -// *! - prerequesit is that the PLLs run in bypass mode so far -// *! to bring-up the pervasive part of the chiplet (chiplet_init) -// *! - setup the tank PLLs by a load_ring of PLL config bits -// *! - release the RESET, check for the LOCK and release the bypass +// *! - prerequisite is that the PLLs are in bypass mode +// *! - setup the PLLs by a ring load of PLL config bits // *! //------------------------------------------------------------------------------ @@ -49,7 +47,7 @@ //------------------------------------------------------------------------------ #include "p8_scom_addresses.H" #include "proc_a_x_pci_dmi_pll_initf.H" -#include <fapi.H> +#include "proc_a_x_pci_dmi_pll_utils.H" using namespace fapi; @@ -58,12 +56,11 @@ using namespace fapi; // Constant definitions //------------------------------------------------------------------------------ -// Register values for using setpulse -const uint64_t OPCG_REG0_FOR_SETPULSE = 0x818C000000000000ull; -const uint64_t OPCG_REG2_FOR_SETPULSE = 0x0000000000002000ull; -const uint64_t OPCG_REG3_FOR_SETPULSE = 0x6000000000000000ull; -const uint64_t CLK_REGION_FOR_SETPULSE = 0x0010040000000000ull; +const uint32_t PB_BNDY_DMIPLL_RING_ADDR = 0x02030088; +const uint32_t AB_BNDY_PLL_RING_ADDR = 0x08030088; +const uint32_t PCI_BNDY_PLL_RING_ADDR = 0x09030088; +const uint32_t DMI_PLL_VCO_WORKAROUND_THRESHOLD_FREQ = 4800; //------------------------------------------------------------------------------ @@ -73,9 +70,10 @@ const uint64_t CLK_REGION_FOR_SETPULSE = 0x0010040000000000ull; extern "C" { + //------------------------------------------------------------------------------ // function: -// REAL PLL setup for X , A, PCIE, DMI +// Scan PLL settings for A/X/PCI/DMI PLLs // // parameters: i_target => chip target // i_startX => True to start X BUS PLL, else false @@ -84,624 +82,341 @@ extern "C" // i_startDMI => True to start DMI PLL, else false // returns: FAPI_RC_SUCCESS if operation was successful, else error //------------------------------------------------------------------------------ - fapi::ReturnCode proc_a_x_pci_dmi_pll_initf(const fapi::Target & i_target, - const bool i_startX, - const bool i_startA, - const bool i_startPCIE, - const bool i_startDMI) +fapi::ReturnCode proc_a_x_pci_dmi_pll_initf(const fapi::Target & i_target, + const bool i_startX, + const bool i_startA, + const bool i_startPCIE, + const bool i_startDMI) +{ + // data buffer to hold register values + ecmdDataBufferBase scom_data(64); + ecmdDataBufferBase ring_data; + uint8_t pcie_enable_attr; + uint8_t abus_enable_attr; + uint8_t is_simulation; + uint8_t lctank_pll_vco_workaround = 0; + uint32_t ring_length = 0; + uint8_t attrABRingData[80] ={0}; // Set to 80 bytes to match length in XML file, not actual scan ring length. + uint8_t attrDMIRingData[231]={0}; // Set to 231 bytes to match length in XML file, not actual scan ring length. + uint8_t attrPCIRingData[80] ={0}; // Set to 80 bytes to match length in XML file, not actual scan ring length. + + // return codes + uint32_t rc_ecmd = 0; + fapi::ReturnCode rc; + + // mark function entry + FAPI_INF("\n Parameter1, start_XBUS=%s\n Parameter2, start_ABUS=%s\n Parameter3, start_PCIE=%s\n Parameter4, start_DMI=%s \n" , + i_startX ? "true":"false", + i_startA ? "true":"false", + i_startPCIE ? "true":"false", + i_startDMI ? "true":"false"); + do { - // data buffer to hold register values - ecmdDataBufferBase scom_data(64); - ecmdDataBufferBase ring_data; - uint8_t pcie_enable_attr; - uint8_t abus_enable_attr; - uint32_t ring_length = 0; - uint8_t attrABRingData[80] ={0}; // Set to 80 bytes to match length in XML file, not actual scan ring length. - uint8_t attrDMIRingData[231]={0}; // Set to 231 bytes to match length in XML file, not actual scan ring length. - uint8_t attrPCIRingData[80] ={0}; // Set to 80 bytes to match length in XML file, not actual scan ring length. - - // return codes - uint32_t rc_ecmd = 0; - fapi::ReturnCode rc; - - - - // mark function entry - FAPI_INF("\n Parameter1, start_XBUS=%s\n Parameter2, start_ABUS=%s\n Parameter3, start_PCIE=%s\n Parameter4, start_DMI=%s \n" , - i_startX ? "true":"false", - i_startA ? "true":"false", - i_startPCIE ? "true":"false", - i_startDMI ? "true":"false"); - do + //------------// + // Workaround // + //------------// + rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, + NULL, + is_simulation); + if (!rc.ok()) { + FAPI_ERR("Error querying ATTR_IS_SIMULATION"); + break; + } - //------------// - // X Bus PLL // - //------------// - if (!i_startX) - { - FAPI_DBG("X BUS PLL not selected for setup in this routine."); - } - else + if (!is_simulation) + { + rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_LCTANK_PLL_VCO_BUG, + &i_target, + lctank_pll_vco_workaround); + if (!rc.ok()) { - FAPI_INF("This routine does not do X-BUS PLL setup at this time!."); - FAPI_INF("It is assumed that the X-BUS PLL is already set up in synchronous mode for use with the NEST logic."); + FAPI_ERR("Error querying Chip EC feature: ATTR_CHIP_EC_FEATURE_LCTANK_PLL_VCO_BUG"); + break; } - // end X-bus PLL setup + } + FAPI_DBG("lctank PLL VCO bug circumvention is %s", + (lctank_pll_vco_workaround ? "enabled" : "disabled")); + //------------// + // X Bus PLL // + //------------// + if (!i_startX) + { + FAPI_DBG("X BUS PLL not selected for setup in this routine."); + } + else + { + FAPI_INF("This routine does not do X-BUS PLL setup at this time!."); + FAPI_INF("It is assumed that the X-BUS PLL is already set up in synchronous mode for use with the NEST logic."); + } + // end X-bus PLL setup - //------------// - // A Bus PLL // - //------------// - // query ABUS partial good attribute - rc = FAPI_ATTR_GET(ATTR_PROC_A_ENABLE, - &i_target, - abus_enable_attr); - if (!rc.ok()) + //------------// + // A Bus PLL // + //------------// + + // query ABUS partial good attribute + rc = FAPI_ATTR_GET(ATTR_PROC_A_ENABLE, + &i_target, + abus_enable_attr); + if (!rc.ok()) + { + FAPI_ERR("Error querying ATTR_PROC_A_ENABLE"); + break; + } + + if (!i_startA) + { + FAPI_DBG("A BUS PLL not selected for setup in this routine."); + } + else if (abus_enable_attr != fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE) + { + FAPI_DBG("A BUS PLL setup skipped (partial good)."); + } + else + { + // Read the ring length attribute value. + rc = FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_LENGTH, &i_target, ring_length); + if (rc) { - FAPI_ERR("Error querying ATTR_PROC_A_ENABLE"); + FAPI_ERR("Failed to get attribute: ATTR_PROC_AB_BNDY_PLL_LENGTH."); break; } + FAPI_DBG("ATTR_PROC_AB_BNDY_PLL_LENGTH attribute is set to : %d.", ring_length); - if (!i_startA) + // Read the ring data attribute value. + rc = FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_DATA, &i_target, attrABRingData); + if (rc) { - FAPI_DBG("A BUS PLL not selected for setup in this routine."); + FAPI_ERR("Failed to get attribute: ATTR_PROC_AB_BNDY_PLL_DATA."); + break; } - else if (abus_enable_attr != fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE) + + // Set the ring_data buffer to the right length for the ring data + rc_ecmd |= ring_data.setBitLength(ring_length); + if (rc_ecmd) { - FAPI_DBG("A BUS PLL setup skipped (partial good)."); + FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; } - else - { - FAPI_DBG("Loading the config bits into A BUS PLL"); - - //--------------------------------------------------------------------------- - // Get ring data from cronus attribute and put it into eCmdDataBufferBase - //--------------------------------------------------------------------------- - - // Read the ring length attribute value. - rc = FAPI_ATTR_GET( ATTR_PROC_AB_BNDY_PLL_LENGTH, &i_target, ring_length); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_PROC_AB_BNDY_PLL_LENGTH."); - break; - } - FAPI_DBG("ATTR_PROC_AB_BNDY_PLL_LENGTH attribute is set to : %d.", ring_length); - - - // Read the ring data attribute value. - rc = FAPI_ATTR_GET( ATTR_PROC_AB_BNDY_PLL_DATA, &i_target, attrABRingData); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_PROC_AB_BNDY_PLL_DATA."); - break; - } - - - // Set the ring_data buffer to the right length for the ring data - rc_ecmd |= ring_data.setBitLength(ring_length); // This length needs to match the real scan length in the scandef file (Required for hostboot.) - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - - // Put the ring data from the attribute into the buffer - rc_ecmd |= ring_data.insert(attrABRingData, 0, ring_length, 0); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x loading scan chain attribute data into buffer.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - - - //------------------------------------------- - // Set the OPCG to generate the setpulse - //------------------------------------------ - // Write SCOM address=0x08030002 data=0x818C000000000000 unicast, write ABus OPCG Reg0 to generate setpulse - FAPI_DBG("Writing ABus OPCG Register 0 to 0x818C000000000000 to generate setpulse ..."); - rc_ecmd |= scom_data.setDoubleWord(0, OPCG_REG0_FOR_SETPULSE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write ABus OPCG Register 0.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, A_OPCG_CNTL0_0x08030002, scom_data); - if (rc) - { - FAPI_ERR("Error writing ABus OPCG Register0 0x08030002 to 0x818C000000000000 to generate setpulse."); - break; - } - - // Write SCOM address=0x08030004 data=0x0000000000002000 unicast, write ABus OPCG Reg2 to generate setpulse - FAPI_DBG("Writing ABus OPCG Register 2 to 0x0000000000002000 to generate setpulse ..."); - rc_ecmd |= scom_data.setDoubleWord(0, OPCG_REG2_FOR_SETPULSE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write ABus OPCG Register 2.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, A_OPCG_CNTL2_0x08030004, scom_data); - if (rc) - { - FAPI_ERR("Error writing ABus OPCG Register2 0x08030004 to 0x0000000000002000 to generate setpulse."); - break; - } - - // Write SCOM address=0x08030005 data=0x6000000000000000 unicast, write ABus OPCG Reg3 to generate setpulse - FAPI_DBG("Writing ABus OPCG Register 3 to 0x6000000000000000 to generate setpulse ..."); - rc_ecmd |= scom_data.setDoubleWord(0, OPCG_REG3_FOR_SETPULSE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write ABus OPCG Register 3.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, A_OPCG_CNTL3_0x08030005, scom_data); - if (rc) - { - FAPI_ERR("Error writing ABus OPCG Register3 0x08030005 to 0x6000000000000000 to generate setpulse."); - break; - } - - // Write SCOM address=0x08030006 data=0x0010040000000000 unicast, write ABus Clock Region Reg to generate setpulse - FAPI_DBG("Writing ABus OPCG Clock Region Register to 0x0010040000000000 to generate setpulse ..."); - rc_ecmd |= scom_data.setDoubleWord(0, CLK_REGION_FOR_SETPULSE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write ABus Clock Region Register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, A_CLK_REGION_0x08030006, scom_data); - if (rc) - { - FAPI_ERR("Error writing ABus Clock Region Register 0x08030006 to 0x0010040000000000 to generate setpulse."); - break; - } - - - //----------------------------------------------------- - // Scan new ring data into ab_bndy_pll scan ring. - //----------------------------------------------------- - rc = fapiPutRing(i_target, 0x08030088, ring_data, RING_MODE_SET_PULSE); - if (rc) - { - FAPI_ERR("fapiPutRing failed with rc = 0x%x", (uint32_t)rc); - break; - } - FAPI_DBG("Loading of the config bits for A-BUS PLL is done."); - - - - //------------------------------------------- - // Set the OPCG back to a good state - //------------------------------------------ - // Write SCOM address=0x08030005 data=0x0000000000000000 unicast, clear ABus OPCG Reg3 - FAPI_DBG("Writing ABus OPCG Register 3 to 0x0000000000000000 to clear setpulse ..."); - rc_ecmd |= scom_data.flushTo0(); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear ABus OPCG Register 3.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, A_OPCG_CNTL3_0x08030005, scom_data); - if (rc) - { - FAPI_ERR("Error writing ABus OPCG Register3 0x08030005 to 0x0000000000000000 to clear setpulse."); - break; - } - - // Write SCOM address=0x08030006 data=0x0000000000000000 unicast, clear ABus Clock Region Reg - FAPI_DBG("Writing ABus OPCG Clock Region Register to 0x0000000000000000 to clear setpulse ..."); - rc_ecmd |= scom_data.flushTo0(); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear ABus Clock Region Register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, A_CLK_REGION_0x08030006, scom_data); - if (rc) - { - FAPI_ERR("Error writing ABus Clock Region Register 0x08030006 to 0x0000000000000000 to clear setpulse."); - break; - } - - - FAPI_DBG("Loading of the config bits for A BUS PLL is done."); - FAPI_INF("Done setting up A-Bus PLL. "); - } // end A PLL - - - - //----------// - // DMI PLL // - //----------// - if (!i_startDMI) + // Put the ring data from the attribute into the buffer + rc_ecmd |= ring_data.insert(attrABRingData, 0, ring_length, 0); + if (rc_ecmd) { - FAPI_DBG("DMI PLL not selected for setup in this routine."); + FAPI_ERR("Error 0x%x loading scan chain attribute data into buffer.", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; } - else - { - FAPI_DBG("Loading the config bits into DMI PLL"); - //--------------------------------------------------------------------------- - // Get ring data from cronus attribute and put it into eCmdDataBufferBase - //--------------------------------------------------------------------------- - - // Read the ring length attribute value. - rc = FAPI_ATTR_GET( ATTR_PROC_PB_BNDY_DMIPLL_LENGTH, &i_target, ring_length); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_PROC_PB_BNDY_DMIPLL_LENGTH."); - break; - } - FAPI_DBG("ATTR_PROC_PB_BNDY_DMIPLL_LENGTH attribute is set to : %d.", ring_length); - - - // Read the ring data attribute value. - rc = FAPI_ATTR_GET( ATTR_PROC_PB_BNDY_DMIPLL_DATA, &i_target, attrDMIRingData); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_PROC_PB_BNDY_DMIPLL_DATA."); - break; - } - - - // Set the ring_data buffer to the right length for the ring data - rc_ecmd |= ring_data.setBitLength(ring_length); // This length needs to match the real scan length in the scandef file (Required for hostboot.) - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - - // Put the ring data from the attribute into the buffer - rc_ecmd |= ring_data.insert(attrDMIRingData, 0, ring_length, 0); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x loading scan chain attribute data into buffer.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - - - //------------------------------------------- - // Set the OPCG to generate the setpulse - //------------------------------------------ - // Write SCOM address=0x02030002 data=0x818C000000000000 unicast, write DMI OPCG Reg0 to generate setpulse - FAPI_DBG("Writing DMI OPCG Register 0 to 0x818C000000000000 to generate setpulse ..."); - rc_ecmd |= scom_data.setDoubleWord(0, OPCG_REG0_FOR_SETPULSE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write DMI OPCG Register 0.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, NEST_OPCG_CNTL0_0x02030002, scom_data); - if (rc) - { - FAPI_ERR("Error writing DMI OPCG Register0 0x02030002 to 0x818C000000000000 to generate setpulse."); - break; - } - - // Write SCOM address=0x02030004 data=0x0000000000002000 unicast, write DMI OPCG Reg2 to generate setpulse - FAPI_DBG("Writing DMI OPCG Register 2 to 0x0000000000002000 to generate setpulse ..."); - rc_ecmd |= scom_data.setDoubleWord(0, OPCG_REG2_FOR_SETPULSE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write DMI OPCG Register 2.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, NEST_OPCG_CNTL2_0x02030004, scom_data); - if (rc) - { - FAPI_ERR("Error writing DMI OPCG Register2 0x02030004 to 0x0000000000002000 to generate setpulse."); - break; - } - - // Write SCOM address=0x02030005 data=0x6000000000000000 unicast, write DMI OPCG Reg3 to generate setpulse - FAPI_DBG("Writing DMI OPCG Register 3 to 0x6000000000000000 to generate setpulse ..."); - rc_ecmd |= scom_data.setDoubleWord(0, OPCG_REG3_FOR_SETPULSE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write DMI OPCG Register 3.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, NEST_OPCG_CNTL3_0x02030005, scom_data); - if (rc) - { - FAPI_ERR("Error writing DMI OPCG Register3 0x02030005 to 0x6000000000000000 to generate setpulse."); - break; - } - - // Write SCOM address=0x02030006 data=0x0010040000000000 unicast, write DMI Clock Region Reg to generate setpulse - FAPI_DBG("Writing DMI OPCG Clock Region Register to 0x0010040000000000 to generate setpulse ..."); - rc_ecmd |= scom_data.setDoubleWord(0, CLK_REGION_FOR_SETPULSE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write DMI Clock Region Register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, NEST_CLK_REGION_0x02030006, scom_data); - if (rc) - { - FAPI_ERR("Error writing DMI Clock Region Register 0x02030006 to 0x0010040000000000 to generate setpulse."); - break; - } - - - - //----------------------------------------------------- - // Scan new ring data into pb_bndy_dmipll scan ring. - //----------------------------------------------------- - rc = fapiPutRing(i_target, 0x02030088, ring_data, RING_MODE_SET_PULSE); - if (rc) - { - FAPI_ERR("fapiPutRing failed with rc = 0x%x", (uint32_t)rc); - break; - } - FAPI_DBG("Loading of the config bits for DMI PLL is done."); - - - - //------------------------------------------- - // Set the OPCG back to a good state - //------------------------------------------ - // Write SCOM address=0x02030005 data=0x0000000000000000 unicast, clear DMI OPCG Reg3 - FAPI_DBG("Writing DMI OPCG Register 3 to 0x0000000000000000 to clear setpulse ..."); - rc_ecmd |= scom_data.flushTo0(); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear DMI OPCG Register 3.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, NEST_OPCG_CNTL3_0x02030005, scom_data); - if (rc) - { - FAPI_ERR("Error writing DMI OPCG Register3 0x02030005 to 0x0000000000000000 to clear setpulse."); - break; - } + // apply workaround for A PLL for all frequencies + bool a_lctank_pll_vco_workaround = (lctank_pll_vco_workaround != 0); + FAPI_DBG("A-Bus PLL VCO bug circumvention is %s", + (a_lctank_pll_vco_workaround ? "enabled" : "disabled")); + + // scan ab_bndy_pll ring with setpulse + FAPI_DBG("Loading the config bits into A BUS PLL"); + rc = proc_a_x_pci_dmi_pll_scan_pll( + i_target, + A_BUS_CHIPLET_0x08000000, + AB_BNDY_PLL_RING_ADDR, + ring_data, + a_lctank_pll_vco_workaround, + 278, + 279); + if (rc) + { + FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_pll"); + break; + } - // Write SCOM address=0x02030006 data=0x0000000000000000 unicast, clear DMI Clock Region Reg - FAPI_DBG("Writing DMI OPCG Clock Region Register to 0x0000000000000000 to clear setpulse ..."); - rc_ecmd |= scom_data.flushTo0(); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear DMI Clock Region Register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, NEST_CLK_REGION_0x02030006, scom_data); - if (rc) - { - FAPI_ERR("Error writing DMI Clock Region Register 0x02030006 to 0x0000000000000000 to clear setpulse."); - break; - } + FAPI_INF("Done setting up A-Bus PLL. "); + } // end A PLL - FAPI_INF("Done setting up DMI PLL. "); - } // end DMI PLL + //----------// + // DMI PLL // + //----------// + if (!i_startDMI) + { + FAPI_DBG("DMI PLL not selected for setup in this routine."); + } + else + { + // Read the ring length attribute value. + rc = FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_DMIPLL_LENGTH, &i_target, ring_length); + if (rc) + { + FAPI_ERR("Failed to get attribute: ATTR_PROC_PB_BNDY_DMIPLL_LENGTH."); + break; + } + FAPI_DBG("ATTR_PROC_PB_BNDY_DMIPLL_LENGTH attribute is set to : %d.", ring_length); - //-----------// - // PCIE PLL // - //-----------// - // query PCIE partial good attribute - rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_ENABLE, - &i_target, - pcie_enable_attr); - if (!rc.ok()) + // Read the ring data attribute value. + rc = FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_DMIPLL_DATA, &i_target, attrDMIRingData); + if (rc) { - FAPI_ERR("Error querying ATTR_PROC_PCIE_ENABLE"); + FAPI_ERR("Failed to get attribute: ATTR_PROC_PB_BNDY_DMIPLL_DATA."); break; } - if (!i_startPCIE) + // Set the ring_data buffer to the right length for the ring data + rc_ecmd |= ring_data.setBitLength(ring_length); + if (rc_ecmd) { - FAPI_DBG("PCIE PLL not selected for setup in this routine."); + FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; } - else if (pcie_enable_attr != fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE) + + // Put the ring data from the attribute into the buffer + rc_ecmd |= ring_data.insert(attrDMIRingData, 0, ring_length, 0); + if (rc_ecmd) { - FAPI_DBG("PCIE PLL setup skipped (partial good)."); + FAPI_ERR("Error 0x%x loading scan chain attribute data into buffer.", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; } - else - { - FAPI_DBG("Loading the config bits into PCIE BUS PLL"); - - //--------------------------------------------------------------------------- - // Get ring data from cronus attribute and put it into eCmdDataBufferBase - //--------------------------------------------------------------------------- - - // Read the ring length attribute value. - rc = FAPI_ATTR_GET( ATTR_PROC_PCI_BNDY_PLL_LENGTH, &i_target, ring_length); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_PROC_PCI_BNDY_PLL_LENGTH."); - break; - } - FAPI_DBG("ATTR_PROC_PCI_BNDY_PLL_LENGTH attribute is set to : %d.", ring_length); - - - // Read the ring data attribute value. - rc = FAPI_ATTR_GET( ATTR_PROC_PCI_BNDY_PLL_DATA, &i_target, attrPCIRingData); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_PROC_PCI_BNDY_PLL_DATA."); - break; - } - - // Set the ring_data buffer to the right length for the ring data - rc_ecmd |= ring_data.setBitLength(ring_length); // This length needs to match the real scan length in the scandef file (Required for hostboot.) - if (rc_ecmd) + // only apply DMI workaround if needed when frequency < 4800 MHz, + bool dmi_lctank_pll_vco_workaround = (lctank_pll_vco_workaround != 0); + uint32_t dmi_freq; + if (dmi_lctank_pll_vco_workaround) + { + // frequency reported via X attribute should be equivalent to DMI freq + // given that we are running NEST off of X-bus PLL (NEST=X/2) and + // DMI=NEST*2 + rc = FAPI_ATTR_GET(ATTR_FREQ_X, NULL, dmi_freq); + if (!rc.ok()) { - FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.", rc_ecmd); - rc.setEcmdError(rc_ecmd); + FAPI_ERR("Failed to get attribute: ATTR_FREQ_X"); break; } - - // Put the ring data from the attribute into the buffer - rc_ecmd |= ring_data.insert(attrPCIRingData, 0, ring_length, 0); - if (rc_ecmd) + if (dmi_freq >= DMI_PLL_VCO_WORKAROUND_THRESHOLD_FREQ) { - FAPI_ERR("Error 0x%x loading scan chain attribute data into buffer.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; + dmi_lctank_pll_vco_workaround = false; } + } + FAPI_DBG("DMI PLL VCO bug circumvention is %s", + (dmi_lctank_pll_vco_workaround ? "enabled" : "disabled")); + + // scan pb_bndy_dmipll ring with setpulse + FAPI_DBG("Loading the config bits into DMI PLL"); + rc = proc_a_x_pci_dmi_pll_scan_pll( + i_target, + NEST_CHIPLET_0x02000000, + PB_BNDY_DMIPLL_RING_ADDR, + ring_data, + dmi_lctank_pll_vco_workaround, + 580, + 581); + if (rc) + { + FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_pll"); + break; + } + FAPI_INF("Done setting up DMI PLL. "); + } // end DMI PLL - //------------------------------------------- - // Set the OPCG to generate the setpulse - //------------------------------------------ - // Write SCOM address=0x09030002 data=0x818C000000000000 unicast, write PCIE OPCG Reg0 to generate setpulse - FAPI_DBG("Writing PCIE OPCG Register 0 to 0x818C000000000000 to generate setpulse ..."); - rc_ecmd |= scom_data.setDoubleWord(0, OPCG_REG0_FOR_SETPULSE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write PCIE OPCG Register 0.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, PCIE_OPCG_CNTL0_0x09030002, scom_data); - if (rc) - { - FAPI_ERR("Error writing PCIE OPCG Register0 0x09030002 to 0x818C000000000000 to generate setpulse."); - break; - } - - // Write SCOM address=0x09030004 data=0x0000000000002000 unicast, write PCIE OPCG Reg2 to generate setpulse - FAPI_DBG("Writing PCIE OPCG Register 2 to 0x0000000000002000 to generate setpulse ..."); - rc_ecmd |= scom_data.setDoubleWord(0, OPCG_REG2_FOR_SETPULSE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write PCIE OPCG Register 2.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, PCIE_OPCG_CNTL2_0x09030004, scom_data); - if (rc) - { - FAPI_ERR("Error writing PCIE OPCG Register2 0x09030004 to 0x0000000000002000 to generate setpulse."); - break; - } - // Write SCOM address=0x09030005 data=0x6000000000000000 unicast, write PCIE OPCG Reg3 to generate setpulse - FAPI_DBG("Writing PCIE OPCG Register 3 to 0x6000000000000000 to generate setpulse ..."); - rc_ecmd |= scom_data.setDoubleWord(0, OPCG_REG3_FOR_SETPULSE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write PCIE OPCG Register 3.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, PCIE_OPCG_CNTL3_0x09030005, scom_data); - if (rc) - { - FAPI_ERR("Error writing PCIE OPCG Register3 0x09030005 to 0x6000000000000000 to generate setpulse."); - break; - } - - // Write SCOM address=0x09030006 data=0x0010040000000000 unicast, write PCIE Clock Region Reg to generate setpulse - FAPI_DBG("Writing PCIE OPCG Clock Region Register to 0x0010040000000000 to generate setpulse ..."); - rc_ecmd |= scom_data.setDoubleWord(0, CLK_REGION_FOR_SETPULSE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write PCIE Clock Region Register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, PCIE_CLK_REGION_0x09030006, scom_data); - if (rc) - { - FAPI_ERR("Error writing PCIE Clock Region Register 0x09030006 to 0x0010040000000000 to generate setpulse."); - break; - } + //-----------// + // PCIE PLL // + //-----------// + // query PCIE partial good attribute + rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_ENABLE, + &i_target, + pcie_enable_attr); + if (!rc.ok()) + { + FAPI_ERR("Error querying ATTR_PROC_PCIE_ENABLE"); + break; + } + if (!i_startPCIE) + { + FAPI_DBG("PCIE PLL not selected for setup in this routine."); + } + else if (pcie_enable_attr != fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE) + { + FAPI_DBG("PCIE PLL setup skipped (partial good)."); + } + else + { + FAPI_DBG("Loading the config bits into PCIE BUS PLL"); - //----------------------------------------------------- - // Scan new ring data into pci_bndy_pll scan ring. - //----------------------------------------------------- - rc = fapiPutRing(i_target, 0x09030088, ring_data, RING_MODE_SET_PULSE); - if (rc) - { - FAPI_ERR("fapiPutRing failed with rc = 0x%x", (uint32_t)rc); - break; - } - FAPI_DBG("Loading of the config bits for PCIE PLL is done."); + // Read the ring length attribute value. + rc = FAPI_ATTR_GET(ATTR_PROC_PCI_BNDY_PLL_LENGTH, &i_target, ring_length); + if (rc) + { + FAPI_ERR("Failed to get attribute: ATTR_PROC_PCI_BNDY_PLL_LENGTH."); + break; + } + FAPI_DBG("ATTR_PROC_PCI_BNDY_PLL_LENGTH attribute is set to : %d.", ring_length); + // Read the ring data attribute value. + rc = FAPI_ATTR_GET(ATTR_PROC_PCI_BNDY_PLL_DATA, &i_target, attrPCIRingData); + if (rc) + { + FAPI_ERR("Failed to get attribute: ATTR_PROC_PCI_BNDY_PLL_DATA."); + break; + } + // Set the ring_data buffer to the right length for the ring data + rc_ecmd |= ring_data.setBitLength(ring_length); + if (rc_ecmd) + { + FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } - //------------------------------------------- - // Set the OPCG back to a good state - //------------------------------------------ - // Write SCOM address=0x09030005 data=0x0000000000000000 unicast, clear PCIE OPCG Reg3 - FAPI_DBG("Writing PCIE OPCG Register 3 to 0x0000000000000000 to clear setpulse ..."); - rc_ecmd |= scom_data.flushTo0(); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear PCIE OPCG Register 3.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, PCIE_OPCG_CNTL3_0x09030005, scom_data); - if (rc) - { - FAPI_ERR("Error writing PCIE OPCG Register3 0x09030005 to 0x0000000000000000 to clear setpulse."); - break; - } + // Put the ring data from the attribute into the buffer + rc_ecmd |= ring_data.insert(attrPCIRingData, 0, ring_length, 0); + if (rc_ecmd) + { + FAPI_ERR("Error 0x%x loading scan chain attribute data into buffer.", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } - // Write SCOM address=0x09030006 data=0x0000000000000000 unicast, clear PCIE Clock Region Reg - FAPI_DBG("Writing PCIE OPCG Clock Region Register to 0x0000000000000000 to clear setpulse ..."); - rc_ecmd |= scom_data.flushTo0(); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear PCIE Clock Region Register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom( i_target, PCIE_CLK_REGION_0x09030006, scom_data); - if (rc) - { - FAPI_ERR("Error writing PCIE Clock Region Register 0x09030006 to 0x0000000000000000 to clear setpulse."); - break; - } + // scan pci_bndy_pll ring with setpulse + rc = proc_a_x_pci_dmi_pll_scan_pll( + i_target, + PCIE_CHIPLET_0x09000000, + PCI_BNDY_PLL_RING_ADDR, + ring_data, + false, + 0x0, + 0x0); + if (rc) + { + FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_pll"); + break; + } + FAPI_INF("Done setting up PCIE PLL."); + } // end PCIE PLL - FAPI_INF("Done setting up PCIE PLL. "); - } // end PCIE PLL + } while (0); // end do - } while (0); // end do + // mark function exit + FAPI_INF("Exit"); + return rc; +} // end FAPI procedure proc_a_x_pci_dmi_pll_initf - // mark function exit - FAPI_INF("Exit"); - return rc; - } // end FAPI procedure proc_a_x_pci_dmi_pll_initf } // extern "C" @@ -710,6 +425,12 @@ extern "C" This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: proc_a_x_pci_dmi_pll_initf.C,v $ +Revision 1.13 2013/04/18 17:33:35 jmcgill +qualify workaround for DMI bus based on frequency + +Revision 1.12 2013/04/17 22:38:38 jmcgill +implement A/DMI PLL workaround for SW194943, reorganize code to use common subroutines for PLL scan/setup + Revision 1.11 2013/01/24 16:34:45 jmcgill fix comment as well... diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.H b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.H index bf8d13879..5efeb3d1e 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.H +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_a_x_pci_dmi_pll_initf.H,v 1.2 2012/08/14 18:32:44 mfred Exp $ +// $Id: proc_a_x_pci_dmi_pll_initf.H,v 1.3 2013/04/17 22:38:40 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_initf.H,v $ //------------------------------------------------------------------------------ // *| @@ -29,7 +29,7 @@ // *! *** IBM Confidential *** // *| // *! TITLE : proc_a_x_pci_dmi_pll_initf.H -// *! DESCRIPTION : Start the VAR OSCs / Config the TANK PLLs & lock +// *! DESCRIPTION : Scan PLL settings for A/X/PCI/DMI PLLs // *! // *! OWNER NAME : Ralph Koester Email: rkoester@de.ibm.com // *! @@ -45,6 +45,10 @@ #include <fapi.H> //------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ // Structure definitions //------------------------------------------------------------------------------ @@ -60,13 +64,13 @@ extern "C" { /** - * @brief Start variable Oscillator + * @brief Scan PLL settings for A/X/PCI/DMI PLLs * * @param[in] i_target Reference to target - * @param[in] i_startX True if x_bus PLL should be started, else false - * @param[in] i_startA True if A PLL should be started, else false - * @param[in] i_startPCIE True if PCIE PLL should be started, else false - * @param[in] i_startDMI True if DMI PLL should be started, else false + * @param[in] i_startX True if x_bus PLL should be initalized, else false + * @param[in] i_startA True if A PLL should be initalized, else false + * @param[in] i_startPCIE True if PCIE PLL should be initalized, else false + * @param[in] i_startDMI True if DMI PLL should be initalized, else false * * @return ReturnCode */ diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C index b824ff03a..c8cd63957 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C @@ -20,8 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// -*- mode: C++; c-file-style: "linux"; -*- -// $Id: proc_a_x_pci_dmi_pll_setup.C,v 1.10 2013/01/25 19:30:22 mfred Exp $ +// $Id: proc_a_x_pci_dmi_pll_setup.C,v 1.11 2013/04/17 22:38:42 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_setup.C,v $ //------------------------------------------------------------------------------ // *| @@ -30,16 +29,12 @@ // *! *** IBM Confidential *** // *| // *! TITLE : proc_a_x_pci_dmi_pll_setup.C -// *! DESCRIPTION : Configure the PLLs +// *! DESCRIPTION : Initialize and lock A/X/PCI/DMI PLLs // *! // *! OWNER NAME : Ralph Koester Email: rkoester@de.ibm.com // *! -// *! The purpose of this procedure is to setup the PLLs -// *! -// *! - prerequesit is that the PLLs run in bypass mode so far -// *! to bring-up the pervasive part of the chiplet (chiplet_init) -// *! - setup the tank PLLs by a load_ring of PLL config bits -// *! - release the RESET, check for the LOCK and release the bypass +// *! The purpose of this procedure is to initialize (remove from reset/bypass) +// *! and lock the X/A/PCIE/DMI PLLs // *! //------------------------------------------------------------------------------ @@ -49,22 +44,7 @@ //------------------------------------------------------------------------------ #include "p8_scom_addresses.H" #include "proc_a_x_pci_dmi_pll_setup.H" - - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -// GP3 register bit/field definitions -const uint8_t GP3_PLL_TEST_ENABLE = 3; -const uint8_t GP3_PLL_RESET = 4; -const uint8_t GP3_PLL_BYPASS = 5; -const uint8_t FSI_GP4_PLL_TEST_BYPASS1 = 22; -const uint8_t PLLLOCK = 0; -const uint8_t PLLLOCK2 = 1; - - - +#include "proc_a_x_pci_dmi_pll_utils.H" //------------------------------------------------------------------------------ @@ -76,7 +56,7 @@ extern "C" //------------------------------------------------------------------------------ // function: -// REAL PLL setup for X , A, PCIE, DMI +// Initialize and lock A/X/PCI/DMI PLLs // // parameters: i_target => chip target // i_startX => True to start X BUS PLL, else false @@ -95,15 +75,11 @@ extern "C" ecmdDataBufferBase gp_data(64); // return codes - uint32_t rc_ecmd = 0; fapi::ReturnCode rc; // locals - const uint32_t max = 50; // Set to maximum number of times to poll for PLL each lock - uint32_t timeout = 0; - uint32_t num = 0; - uint8_t pcie_enable_attr; - uint8_t abus_enable_attr; + uint8_t pcie_enable_attr; + uint8_t abus_enable_attr; // mark function entry FAPI_INF("Entry1, start_XBUS=%s\n, Entry2, start_ABUS=%s\n, Entry3, start_PCIE=%s\n, Entry4, start_DMI=%s \n" , @@ -114,34 +90,6 @@ extern "C" do { - - //---------------------------// - // Common code for all PLLs // - //---------------------------// - - FAPI_INF("FSI GP4 bit 22: Clear pll_test_bypass1."); - rc = fapiGetScom(i_target, MBOX_FSIGP4_0x00050013, gp_data); - if (rc) - { - FAPI_ERR("Error reading FSI GP4 register ."); - break; - } - rc_ecmd |= gp_data.clearBit(FSI_GP4_PLL_TEST_BYPASS1); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up data buffer to clear FSI_GP4_PLL_TEST_BYPASS1", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, MBOX_FSIGP4_0x00050013, gp_data); - if (rc) - { - FAPI_ERR("fapiPutScom error (MBOX_FSIGP4_0x00050013)"); - break; - } - - - //------------// // X Bus PLL // //------------// @@ -183,95 +131,20 @@ extern "C" else { FAPI_DBG("Starting PLL setup for A BUS PLL ..."); - - FAPI_INF("ABUS GP3: Release PLL test enable of ABUS chiplet. "); - rc_ecmd |= gp_data.flushTo1(); - rc_ecmd |= gp_data.clearBit(GP3_PLL_TEST_ENABLE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up data buffer to clear GP3_PLL_TEST_ENABLE", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, A_GP3_AND_0x080F0013, gp_data); - if (rc) + rc = proc_a_x_pci_dmi_pll_release_pll( + i_target, + A_BUS_CHIPLET_0x08000000, + true); + if (!rc.ok()) { - FAPI_ERR("fapiPutScom error (A_GP3_AND_0x080F0013)"); + FAPI_ERR("Error from proc_a_x_pci_dmi_pll_release_pll"); break; } - - - FAPI_INF("ABUS GP3: Release PLL reset of ABUS chiplet "); - rc_ecmd |= gp_data.flushTo1(); - rc_ecmd |= gp_data.clearBit(GP3_PLL_RESET); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up data buffer to clear GP3_PLL_RESET", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, A_GP3_AND_0x080F0013, gp_data); - if (rc) - { - FAPI_ERR("fapiPutScom error (A_GP3_AND_0x080F0013)"); - break; - } - - - - FAPI_INF("ABUS GP3: Release PLL bypass of A-BUS "); - rc_ecmd |= gp_data.flushTo1(); - rc_ecmd |= gp_data.clearBit(GP3_PLL_BYPASS); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up data buffer to clear GP3_PLL_BYPASS", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, A_GP3_AND_0x080F0013, gp_data); - if (rc) - { - FAPI_ERR("fapiPutScom error (A_GP3_AND_0x080F0013)"); - break; - } - - - - FAPI_INF("CHIPLET PLLLK: Check the PLL lock of A-BUS "); - num = 0; - do - { - num++; - if ( num > max ) - { - timeout = 1; - break; - } - rc = fapiGetScom(i_target, A_PLLLOCKREG_0x080F0019, gp_data); - if (rc) - { - FAPI_ERR("fapiGetScom error (A_PLLLOCKREG_0x080F0019)"); - break; - } - // sleep (10); // not accurate anymore for P8 - } while ( !timeout && !gp_data.isBitSet(PLLLOCK) ); // Poll until PLL is locked or max count is reached. - if (rc) break; // Go to end of proc if error found inside polling loop. - if (timeout) - { - FAPI_ERR("Timed out polling for pll-lock PLLLOCK_ABUS 0x%X ", gp_data.getWord(0) ); - FAPI_SET_HWP_ERROR(rc, RC_PROC_A_X_PCI_DMI_PLL_SETUP_ABUS_PLL_NO_LOCK); - break; - } - FAPI_INF("A-Bus PLL is locked."); - - - FAPI_INF("Done setting up A-Bus PLL. "); } // end A PLL - //----------// // DMI PLL // //----------// @@ -282,99 +155,20 @@ extern "C" else { FAPI_DBG("Starting PLL setup for DMI PLL ..."); - - - FAPI_INF("NEST GP3: Release PLL test enable for DMI PLL."); - rc_ecmd |= gp_data.flushTo1(); - rc_ecmd |= gp_data.clearBit(GP3_PLL_TEST_ENABLE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up data buffer to clear GP3_PLL_TEST_ENABLE", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, NEST_GP3_AND_0x020F0013, gp_data); - if (rc) - { - FAPI_ERR("fapiPutScom error (NEST_GP3_AND_0x020F0013)"); - break; - } - - - - FAPI_INF("NEST GP3: Release PLL reset for DMI PLL."); - rc_ecmd |= gp_data.flushTo1(); - rc_ecmd |= gp_data.clearBit(GP3_PLL_RESET); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up data buffer to clear GP3_PLL_RESET", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, NEST_GP3_AND_0x020F0013, gp_data); - if (rc) - { - FAPI_ERR("fapiPutScom error (NEST_GP3_AND_0x020F0013)"); - break; - } - - - - FAPI_INF("NEST GP3: Release PLL bypass of for DMI PLL."); - rc_ecmd |= gp_data.flushTo1(); - rc_ecmd |= gp_data.clearBit(GP3_PLL_BYPASS); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up data buffer to clear GP3_PLL_BYPASS", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, NEST_GP3_AND_0x020F0013, gp_data); - if (rc) + rc = proc_a_x_pci_dmi_pll_release_pll( + i_target, + NEST_CHIPLET_0x02000000, + true); + if (!rc.ok()) { - FAPI_ERR("fapiPutScom error (NEST_GP3_AND_0x020F0013)"); + FAPI_ERR("Error from proc_a_x_pci_dmi_pll_release_pll"); break; } - - - FAPI_INF("CHIPLET PLLLK: Check the PLL lock of DMI PLL."); - num = 0; - do - { - num++; - if ( num > max ) - { - timeout = 1; - break; - } - rc = fapiGetScom(i_target, PB_PLLLOCKREG_0x020F0019, gp_data); - if (rc) - { - FAPI_ERR("fapiGetScom error (PB_PLLLOCKREG_0x020F0019)"); - break; - } - // sleep (10); // not accurate anymore for P8 - - // Check two lock bits because there are two DMI PLLs in Venice. Unused bit defaults to '1' in Murano. - } while ( !timeout && ( !gp_data.isBitSet(PLLLOCK) || !gp_data.isBitSet(PLLLOCK2) ) ); // Poll until PLL is locked or max count is reached. - - if (rc) break; // Go to end of proc if error found inside polling loop. - if (timeout) - { - FAPI_ERR("Timed out polling for pll-lock PLLLOCK_DMI 0x%X ", gp_data.getWord(0) ); - FAPI_SET_HWP_ERROR(rc, RC_PROC_A_X_PCI_DMI_PLL_SETUP_DMI_PLL_NO_LOCK); - break; - } - FAPI_INF("DMI PLL is locked."); - - - FAPI_INF("Done setting up DMI PLL. "); } // end DMI PLL - //-----------// // PCIE PLL // //-----------// @@ -400,90 +194,15 @@ extern "C" else { FAPI_DBG("Starting PLL setup for PCIE PLL ..."); - - FAPI_INF("PCIE GP3: Release PLL test enable of PCIE chiplet. "); - rc_ecmd |= gp_data.flushTo1(); - rc_ecmd |= gp_data.clearBit(GP3_PLL_TEST_ENABLE); - if (rc_ecmd) + rc = proc_a_x_pci_dmi_pll_release_pll( + i_target, + PCIE_CHIPLET_0x09000000, + true); + if (!rc.ok()) { - FAPI_ERR("Error 0x%x setting up data buffer to clear GP3_PLL_TEST_ENABLE", rc_ecmd); - rc.setEcmdError(rc_ecmd); + FAPI_ERR("Error from proc_a_x_pci_dmi_pll_release_pll"); break; } - rc = fapiPutScom(i_target, PCIE_GP3_AND_0x090F0013, gp_data); - if (rc) - { - FAPI_ERR("fapiPutScom error (PCIE_GP3_AND_0x090F0013)"); - break; - } - - - - FAPI_INF("PCIE GP3: Release PLL reset of PCIE chiplet "); - rc_ecmd |= gp_data.flushTo1(); - rc_ecmd |= gp_data.clearBit(GP3_PLL_RESET); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up data buffer to clear GP3_PLL_RESET", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, PCIE_GP3_AND_0x090F0013, gp_data); - if (rc) - { - FAPI_ERR("fapiPutScom error (PCIE_GP3_AND_0x090F0013)"); - break; - } - - - - FAPI_INF("PCIE GP3: Release PLL bypass of PCIE-BUS "); - // 24july2012 mfred moved this before checking PLL lock as this is required for analog PLLs. - rc_ecmd |= gp_data.flushTo1(); - rc_ecmd |= gp_data.clearBit(GP3_PLL_BYPASS); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up data buffer to clear GP3_PLL_BYPASS", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, PCIE_GP3_AND_0x090F0013, gp_data); - if (rc) - { - FAPI_ERR("fapiPutScom error (PCIE_GP3_AND_0x090F0013)"); - break; - } - - - - FAPI_INF("CHIPLET PLLLK: Check the PLL lock of PCIE-BUS "); - num = 0; - do - { - num++; - if ( num > max ) - { - timeout = 1; - break; - } - rc = fapiGetScom(i_target, PCIE_PLLLOCKREG_0x090F0019, gp_data); - if (rc) - { - FAPI_ERR("fapiGetScom error (PCIE_PLLLOCKREG_0x090F0019)"); - break; - } - // sleep (10); // not accurate anymore for P8 - } while ( !timeout && !gp_data.isBitSet(PLLLOCK) ); // Poll until PLL is locked or max count is reached. - if (rc) break; // Go to end of proc if error found inside polling loop. - if (timeout) - { - FAPI_ERR("Timed out polling for pll-lock PLLLOCK_PCIE 0x%X ", gp_data.getWord(0) ); - FAPI_SET_HWP_ERROR(rc, RC_PROC_A_X_PCI_DMI_PLL_SETUP_PCIE_PLL_NO_LOCK); - break; - } - FAPI_INF("PCIE PLL is locked."); - - FAPI_INF("Done setting up PCIE PLL. "); } // end PCIE PLL @@ -504,6 +223,9 @@ extern "C" This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: proc_a_x_pci_dmi_pll_setup.C,v $ +Revision 1.11 2013/04/17 22:38:42 jmcgill +implement A/DMI PLL workaround for SW194943, reorganize code to use common subroutines for PLL scan/setup + Revision 1.10 2013/01/25 19:30:22 mfred Release PLLs from bypass before checking for PLL lock. Also, check for two lock bits on DMI PLL to support Venice. diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H index eab1ccfd1..4e43cdd99 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_a_x_pci_dmi_pll_setup.H,v 1.4 2012/08/14 18:32:48 mfred Exp $ +// $Id: proc_a_x_pci_dmi_pll_setup.H,v 1.5 2013/04/17 22:38:44 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_setup.H,v $ //------------------------------------------------------------------------------ // *| @@ -29,7 +29,7 @@ // *! *** IBM Confidential *** // *| // *! TITLE : proc_a_x_pci_dmi_pll_setup.H -// *! DESCRIPTION : Start the VAR OSCs / Config the TANK PLLs & lock +// *! DESCRIPTION : Initialize and lock A/X/PCI/DMI PLLs // *! // *! OWNER NAME : Ralph Koester Email: rkoester@de.ibm.com // *! @@ -60,7 +60,7 @@ extern "C" { /** - * @brief Start variable Oscillator + * @brief Initialize and lock A/X/PCI/DMI PLLs * * @param[in] i_target Reference to target * @param[in] i_startX True if x_bus PLL should be started, else false diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C new file mode 100644 index 000000000..4c8a82a95 --- /dev/null +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C @@ -0,0 +1,474 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_a_x_pci_dmi_pll_utils.C,v 1.1 2013/04/17 22:36:32 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_utils.C,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2012 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : proc_a_x_pci_dmi_pll_utils.C +// *! DESCRIPTION : Configure the PLLs +// *! +// *! OWNER NAME : Ralph Koester Email: rkoester@de.ibm.com +// *! +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include "p8_scom_addresses.H" +#include "proc_a_x_pci_dmi_pll_utils.H" +#include <fapi.H> + +using namespace fapi; + + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_MAX_LOCK_POLLS = 50; + +// OPCG/Clock Region Register values +const uint64_t OPCG_REG0_FOR_SETPULSE = 0x818C000000000000ull; +const uint64_t OPCG_REG2_FOR_SETPULSE = 0x0000000000002000ull; +const uint64_t OPCG_REG3_FOR_SETPULSE = 0x6000000000000000ull; +const uint64_t CLK_REGION_FOR_SETPULSE = 0x0010040000000000ull; + +// GP3 Register field/bit definitions +const uint8_t GP3_PLL_TEST_ENABLE_BIT = 3; +const uint8_t GP3_PLL_RESET_BIT = 4; +const uint8_t GP3_PLL_BYPASS_BIT = 5; + +// PLL Lock Register field/bit definitions +const uint8_t PLL_LOCK_REG_LOCK_START_BIT = 0; +const uint8_t PLL_LOCK_REG_LOCK_END_BIT = 3; + + +//------------------------------------------------------------------------------ +// Function definition +//------------------------------------------------------------------------------ + +extern "C" +{ + + +//------------------------------------------------------------------------------ +// function: +// Scan PLL boundary ring with setpulse +// +// parameters: i_target => chip target +// i_chiplet_base_scom_addr => aligned base address of chiplet SCOM +// address space +// i_pll_ring_addr => PLL ring address +// i_pll_ring_data => data buffer containing full PLL ring +// content +// returns: FAPI_RC_SUCCESS if operation was successful, else error +//------------------------------------------------------------------------------ + +fapi::ReturnCode proc_a_x_pci_dmi_pll_scan_bndy( + const fapi::Target& i_target, + const uint32_t i_chiplet_base_scom_addr, + const uint32_t i_pll_ring_addr, + ecmdDataBufferBase& i_pll_ring_data) +{ + // data buffer to hold SCOM data + ecmdDataBufferBase data(64); + + // return codes + uint32_t rc_ecmd = 0; + fapi::ReturnCode rc; + + // mark function entry + FAPI_DBG("Start"); + + do + { + //------------------------------------------- + // Set the OPCG to generate the setpulse + //------------------------------------------ + + FAPI_DBG("Writing OPCG Register 0 to generate setpulse ..."); + rc_ecmd |= data.setDoubleWord(0, OPCG_REG0_FOR_SETPULSE); + if (rc_ecmd) + { + FAPI_ERR("Error 0x%x setting up ecmd data buffer to write OPCG Register 0.", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + rc = fapiPutScom(i_target, i_chiplet_base_scom_addr | GENERIC_OPCG_CNTL0_0x00030002, data); + if (!rc.ok()) + { + FAPI_ERR("Error writing OPCG Register0 to generate setpulse."); + break; + } + + FAPI_DBG("Writing OPCG Register 2 to generate setpulse ..."); + rc_ecmd |= data.setDoubleWord(0, OPCG_REG2_FOR_SETPULSE); + if (rc_ecmd) + { + FAPI_ERR("Error 0x%x setting up ecmd data buffer to write OPCG Register 2.", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + rc = fapiPutScom(i_target, i_chiplet_base_scom_addr | GENERIC_OPCG_CNTL2_0x00030004, data); + if (rc) + { + FAPI_ERR("Error writing OPCG Register2 to generate setpulse."); + break; + } + + FAPI_DBG("Writing OPCG Register 3 to generate setpulse ..."); + rc_ecmd |= data.setDoubleWord(0, OPCG_REG3_FOR_SETPULSE); + if (rc_ecmd) + { + FAPI_ERR("Error 0x%x setting up ecmd data buffer to write OPCG Register 3.", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + rc = fapiPutScom(i_target, i_chiplet_base_scom_addr | GENERIC_OPCG_CNTL3_0x00030005, data); + if (rc) + { + FAPI_ERR("Error writing OPCG Register3 to generate setpulse."); + break; + } + + FAPI_DBG("Writing OPCG Clock Region Register to generate setpulse ..."); + rc_ecmd |= data.setDoubleWord(0, CLK_REGION_FOR_SETPULSE); + if (rc_ecmd) + { + FAPI_ERR("Error 0x%x setting up ecmd data buffer to write Clock Region Register.", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + rc = fapiPutScom(i_target, i_chiplet_base_scom_addr | GENERIC_CLK_REGION_0x00030006, data); + if (rc) + { + FAPI_ERR("Error writing Clock Region Register to generate setpulse."); + break; + } + + //----------------------------------------------------- + // Scan new ring data into boundary scan ring + //----------------------------------------------------- + rc = fapiPutRing(i_target, i_pll_ring_addr, i_pll_ring_data, RING_MODE_SET_PULSE); + if (rc) + { + FAPI_ERR("fapiPutRing failed with rc = 0x%x", (uint32_t)rc); + break; + } + FAPI_DBG("Loading of the config bits for PLL is done."); + + + //----------------------------------------------------- + // Set the OPCG back to a good state + //----------------------------------------------------- + + FAPI_DBG("Writing OPCG Register 3 to clear setpulse ..."); + rc_ecmd |= data.flushTo0(); + if (rc_ecmd) + { + FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear OPCG Register 3.", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + rc = fapiPutScom(i_target, i_chiplet_base_scom_addr | GENERIC_OPCG_CNTL3_0x00030005, data); + if (rc) + { + FAPI_ERR("Error writing OPCG Register3 to clear setpulse."); + break; + } + + FAPI_DBG("Writing OPCG Clock Region Register to clear setpulse ..."); + rc_ecmd |= data.flushTo0(); + if (rc_ecmd) + { + FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear Clock Region Register.", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + rc = fapiPutScom(i_target, i_chiplet_base_scom_addr | GENERIC_CLK_REGION_0x00030006, data); + if (rc) + { + FAPI_ERR("Error writing Clock Region Register to clear setpulse."); + break; + } + + } while(0); + + + // mark function entry + FAPI_DBG("End"); + + return rc; +} + + +//------------------------------------------------------------------------------ +// function: +// Scan PLL ring to establish runtime state +// +// parameters: i_target => chip target +// i_chiplet_base_scom_addr => aligned base address of chiplet SCOM +// address space +// i_pll_ring_addr => PLL ring address +// i_pll_ring_data => data buffer containing full PLL ring +// content +// i_lctank_pll_vco_workaround => enable 2-pass scan workaround for +// lctank PLL vco runaway issue +// i_ccalload_ring_offset => ring offset for ccalload PLL control +// bit (used only if workaround +// is true) +// i_ccalfmin_ring_offset => ring offset for ccalfmin PLL control +// bit (used only if workaround +// is true) +// returns: FAPI_RC_SUCCESS if operation was successful, else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_a_x_pci_dmi_pll_scan_pll( + const fapi::Target& i_target, + const uint32_t i_chiplet_base_scom_addr, + const uint32_t i_pll_ring_addr, + ecmdDataBufferBase& i_pll_ring_data, + const bool i_lctank_pll_vco_workaround, + const uint32_t i_ccalload_ring_offset, + const uint32_t i_ccalfmin_ring_offset) +{ + // return codes + uint32_t rc_ecmd = 0; + fapi::ReturnCode rc; + uint8_t scan_count = 1; + + // mark function entry + FAPI_DBG("Start"); + + do + { + // modify ring for first scan if workaround is engaged + if (i_lctank_pll_vco_workaround) + { + rc_ecmd |= i_pll_ring_data.setBit(i_ccalload_ring_offset); + rc_ecmd |= i_pll_ring_data.setBit(i_ccalfmin_ring_offset); + if (rc_ecmd) + { + FAPI_ERR("Error 0x%x setting up data buffer to enable lctank PLL vco workaround (scan = %d)", rc_ecmd, scan_count); + rc.setEcmdError(rc_ecmd); + break; + } + } + + // scan with setpulse + rc = proc_a_x_pci_dmi_pll_scan_bndy( + i_target, + i_chiplet_base_scom_addr, + i_pll_ring_addr, + i_pll_ring_data); + if (!rc.ok()) + { + FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy (scan = %d)", scan_count); + break; + } + scan_count++; + + // release PLL & re-scan if workaround is engaged + if (i_lctank_pll_vco_workaround) + { + rc = proc_a_x_pci_dmi_pll_release_pll( + i_target, + i_chiplet_base_scom_addr, + false); + if (!rc.ok()) + { + FAPI_ERR("Error from proc_a_x_pci_dmi_pll_release_pll"); + break; + } + + rc_ecmd |= i_pll_ring_data.setBit(i_ccalload_ring_offset); + rc_ecmd |= i_pll_ring_data.clearBit(i_ccalfmin_ring_offset); + if (rc_ecmd) + { + FAPI_ERR("Error 0x%x setting up data buffer to enable lctank PLL vco workaround (scan = %d)", rc_ecmd, scan_count); + rc.setEcmdError(rc_ecmd); + break; + } + + // scan with setpulse + rc = proc_a_x_pci_dmi_pll_scan_bndy( + i_target, + i_chiplet_base_scom_addr, + i_pll_ring_addr, + i_pll_ring_data); + if (!rc.ok()) + { + FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy (scan = %d)", scan_count); + break; + } + } + } while(0); + + // mark function entry + FAPI_DBG("End"); + + return rc; +} + + +//------------------------------------------------------------------------------ +// function: +// Release PLL from test mode/bypass/reset and optionally check for lock +// +// parameters: i_target => chip target +// i_chiplet_base_scom_addr => aligned base address of chiplet SCOM +// address space +// i_check_lock => check for PLL lock? +// returns: FAPI_RC_SUCCESS if operation was successful, else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_a_x_pci_dmi_pll_release_pll( + const fapi::Target& i_target, + const uint32_t i_chiplet_base_scom_addr, + const bool i_check_lock) +{ + // data buffer to hold SCOM data + ecmdDataBufferBase data(64); + + // return codes + uint32_t rc_ecmd = 0; + fapi::ReturnCode rc; + + // mark function entry + FAPI_DBG("Start"); + + do + { + FAPI_DBG("Release PLL test enable"); + rc_ecmd |= data.flushTo1(); + rc_ecmd |= data.clearBit(GP3_PLL_TEST_ENABLE_BIT); + if (rc_ecmd) + { + FAPI_ERR("Error 0x%x setting up data buffer to clear GP3 PLL test enable", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + rc = fapiPutScom(i_target, i_chiplet_base_scom_addr | GENERIC_GP3_AND_0x000F0013, data); + if (rc) + { + FAPI_ERR("Error writing GP3 to clear PLL test enable"); + break; + } + + FAPI_DBG("Release PLL reset"); + rc_ecmd |= data.flushTo1(); + rc_ecmd |= data.clearBit(GP3_PLL_RESET_BIT); + if (rc_ecmd) + { + FAPI_ERR("Error 0x%x setting up data buffer to clear GP3 PLL reset", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + rc = fapiPutScom(i_target, i_chiplet_base_scom_addr | GENERIC_GP3_AND_0x000F0013, data); + if (rc) + { + FAPI_ERR("Error writing GP3 to clear PLL reset"); + break; + } + + FAPI_DBG("Release PLL bypass"); + // 24july2012 mfred moved this before checking PLL lock as this is required for analog PLLs. + rc_ecmd |= data.flushTo1(); + rc_ecmd |= data.clearBit(GP3_PLL_BYPASS_BIT); + if (rc_ecmd) + { + FAPI_ERR("Error 0x%x setting up data buffer to clear GP3 PLL bypass", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + rc = fapiPutScom(i_target, i_chiplet_base_scom_addr | GENERIC_GP3_AND_0x000F0013, data); + if (rc) + { + FAPI_ERR("Error writing GP3 to clear PLL bypass"); + break; + } + + if (i_check_lock) + { + FAPI_DBG("Checking for PLL lock..."); + uint32_t num = 0; + bool timeout = false; + + // poll until PLL is locked or max count is reached + do + { + num++; + if (num > PROC_A_X_PCI_DMI_PLL_UTILS_MAX_LOCK_POLLS) + { + timeout = 1; + break; + } + rc = fapiGetScom(i_target, i_chiplet_base_scom_addr | GENERIC_PLLLOCKREG_0x000F0019, data); + if (rc) + { + FAPI_ERR("Error reading PLL lock register"); + break; + } + } while (!timeout && + !data.isBitSet(PLL_LOCK_REG_LOCK_START_BIT, + (PLL_LOCK_REG_LOCK_END_BIT- + PLL_LOCK_REG_LOCK_START_BIT+1))); + if (rc) + { + break; + } + if (timeout) + { + FAPI_ERR("Timed out polling for PLL lock"); + const uint8_t LOCK_STATUS = data.getByte(0); + if (i_chiplet_base_scom_addr == NEST_CHIPLET_0x02000000) + { + FAPI_SET_HWP_ERROR(rc, RC_PROC_A_X_PCI_DMI_PLL_SETUP_DMI_PLL_NO_LOCK); + } + else if (i_chiplet_base_scom_addr == A_BUS_CHIPLET_0x08000000) + { + FAPI_SET_HWP_ERROR(rc, RC_PROC_A_X_PCI_DMI_PLL_SETUP_ABUS_PLL_NO_LOCK); + } + else if (i_chiplet_base_scom_addr == PCIE_CHIPLET_0x09000000) + { + FAPI_SET_HWP_ERROR(rc, RC_PROC_A_X_PCI_DMI_PLL_SETUP_ABUS_PLL_NO_LOCK); + } + break; + } + else + { + FAPI_DBG("PLL is locked."); + } + } + } while(0); + + // mark function entry + FAPI_DBG("End"); + return rc; +} + + +} // extern "C" diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.H b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.H new file mode 100644 index 000000000..9d0f5a8a8 --- /dev/null +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.H @@ -0,0 +1,104 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_a_x_pci_dmi_pll_utils.H,v 1.1 2013/04/17 22:36:34 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_utils.H,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2012 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : proc_a_x_pci_dmi_pll_utils.H +// *! DESCRIPTION : A/X/PCI/DMI PLL utility functions +// *! +// *! OWNER NAME : Ralph Koester Email: rkoester@de.ibm.com +// *! +//------------------------------------------------------------------------------ + +#ifndef _PROC_A_X_PCI_DMI_PLL_UTILS_H_ +#define _PROC_A_X_PCI_DMI_PLL_UTILS_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <fapi.H> + + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +extern "C" +{ + + +//------------------------------------------------------------------------------ +// function: +// Scan PLL ring to establish runtime state +// +// parameters: i_target => chip target +// i_chiplet_base_scom_addr => aligned base address of chiplet SCOM +// address space +// i_pll_ring_addr => PLL ring address +// i_pll_ring_data => data buffer containing full PLL ring +// content +// i_lctank_pll_vco_workaround => enable 2-pass scan workaround for +// lctank PLL vco runaway issue +// i_ccalload_ring_offset => ring offset for ccalload PLL control +// bit (used only if workaround +// is true) +// i_ccalfmin_ring_offset => ring offset for ccalfmin PLL control +// bit (used only if workaround +// is true) +// returns: FAPI_RC_SUCCESS if operation was successful, else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_a_x_pci_dmi_pll_scan_pll( + const fapi::Target& i_target, + const uint32_t i_chiplet_base_scom_addr, + const uint32_t i_pll_ring_addr, + ecmdDataBufferBase& i_pll_ring_data, + const bool i_lctank_pll_vco_workaround, + const uint32_t i_ccalload_ring_offset, + const uint32_t i_ccalfmin_ring_offset); + + +//------------------------------------------------------------------------------ +// function: +// Release PLL from test mode/bypass/reset and optionally check for lock +// +// parameters: i_target => chip target +// i_chiplet_base_scom_addr => aligned base address of chiplet SCOM +// address space +// i_check_lock => check for PLL lock? +// returns: FAPI_RC_SUCCESS if operation was successful, else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_a_x_pci_dmi_pll_release_pll( + const fapi::Target& i_target, + const uint32_t i_chiplet_base_scom_addr, + const bool i_check_lock); + + +} // extern "C" + +#endif // _PROC_A_X_PCI_DMI_PLL_UTILS_H_ diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup_errors.xml b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup_errors.xml index 2325f2758..f3edcf8ce 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup_errors.xml +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> <!-- --> <!-- p1 --> <!-- --> @@ -20,21 +20,24 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- Halt codes for proc_a_x_pci_cmi_pll_setup --> +<!-- Halt codes for proc_a_x_pci_dmi_pll_setup --> <hwpErrors> <!-- ******************************************************************** --> <hwpError> <rc>RC_PROC_A_X_PCI_DMI_PLL_SETUP_ABUS_PLL_NO_LOCK</rc> + <ffdc>LOCK_STATUS</ffdc> <description>A_Bus PLL failed to lock.</description> </hwpError> <!-- ******************************************************************** --> <hwpError> <rc>RC_PROC_A_X_PCI_DMI_PLL_SETUP_DMI_PLL_NO_LOCK</rc> + <ffdc>LOCK_STATUS</ffdc> <description>DMI PLL failed to lock.</description> </hwpError> <!-- ******************************************************************** --> <hwpError> <rc>RC_PROC_A_X_PCI_DMI_PLL_SETUP_PCIE_PLL_NO_LOCK</rc> + <ffdc>LOCK_STATUS</ffdc> <description>PCIE PLL failed to lock.</description> </hwpError> </hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_chip_ec_feature.xml b/src/usr/hwpf/hwp/proc_chip_ec_feature.xml index 8edceccf9..71436fc80 100644 --- a/src/usr/hwpf/hwp/proc_chip_ec_feature.xml +++ b/src/usr/hwpf/hwp/proc_chip_ec_feature.xml @@ -30,8 +30,8 @@ <chip> <name>ENUM_ATTR_NAME_MURANO</name> <ec> - <value>0x10</value> - <test>EQUAL</test> + <value>0x20</value> + <test>LESS_THAN</test> </ec> </chip> </chipEcFeature> @@ -127,4 +127,138 @@ </chip> </chipEcFeature> </attribute> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_CAPP_HANG_CONTROL_ON_SCOM</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Returns if a chip contains SCOM configuration for CAPP unit PB hang recovrery controls. True if: + Murano EC 0x20 or greater + Venice EC 0x10 or greater + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_MURANO</name> + <ec> + <value>0x20</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_VENICE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_RECAL_DFE_ENABLE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + True if: + Murano EC 0x20 or greater + Venice EC 0x10 or greater + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_MURANO</name> + <ec> + <value>0x20</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_VENICE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_RECAL_DDC_ENABLE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + True if: + Murano EC 0x20 or greater + Venice EC 0x10 or greater + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_MURANO</name> + <ec> + <value>0x20</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_VENICE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_RECAL_CTLE_ENABLE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + True if: + Murano EC 0x20 or greater + Venice EC 0x10 or greater + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_MURANO</name> + <ec> + <value>0x20</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_VENICE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_LCTANK_PLL_VCO_BUG</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + True if: + Murano EC less than 0x20 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_MURANO</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_XBUS_DLL_SLOW_MURANO</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + True if: + Murano EC less than 0x12 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_MURANO</name> + <ec> + <value>0x12</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> </attributes> |
