SW256281: INITPROC: HWP: cen_ddrphy.inifile phy training optimization

Change-Id: Iea9f07175f564e090196e1c96f4c88eb19e0657d
CQ:SW256281
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10282
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10284
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

1 files changed, 73 insertions, 17 deletions

diff --git a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile
index f619acbfc..fbcb19431 100755
--- a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile
+++ b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile
@@ -1,4 +1,4 @@
-#-- $Id: cen_ddrphy.initfile,v 1.31 2014/03/11 16:13:37 mwuu Exp $
+#-- $Id: cen_ddrphy.initfile,v 1.32 2014/03/26 13:49:01 asaetow Exp $
 #-- $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
 #--          centaur/working/procedures/ec_ind/scoms/cen_ddrphy.initfile,v $
 #
@@ -6,6 +6,10 @@
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#  1.32     |mwuu    |03/25/14|Changed PERCAL_PWR_DIS
+#		in RD_DIA_CONFIG5, CONSEQ_PASS in RC_CONFIG2, BIG/SMALL_STEP in WC_CONFIG1,
+#		FW_RD_WR in WC_CONFIG2, 8 DQS_OFFSET, FW_WR_RD 32
+#               NOTE: Backed off RD_DIA_CONFIG3, scom reg seems to get zeroed out when written, under investigation.
 #	    1.31|mwuu    |03/11/14|Changed DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S0
 #			|		 |		  |VCO bits 60:63 to match the DP18 PLL of 700MHz,
 #			|		 |		  |Changed LRDIMM settings GPO, WLO to use attributes
@@ -315,9 +319,14 @@ define def_AL_ena	= (ATTR_EFF_DRAM_AL != 0);
 define def_AL_dis	= (ATTR_EFF_DRAM_AL == 0);
 
 # for calculating FW_RD_WR delay...  NOTE: AL could be disabled(=0)
-define def_TWTR_PLUS_OFF = (ATTR_EFF_DRAM_TWTR + 11)	;	# change from +8 on reg spec
-define def_TRTP_PLUS_AL	= (ATTR_EFF_DRAM_TRTP + ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_AL + 3)	;
-define def_TRTP_PLUS_NOAL = (ATTR_EFF_DRAM_TRTP + 3)	;
+#define def_TWTR_PLUS_OFF = (ATTR_EFF_DRAM_TWTR + 11)	;	# change from +8 on reg spec
+#define def_TRTP_PLUS_AL	= (ATTR_EFF_DRAM_TRTP + ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_AL + 3)	;
+#define def_TRTP_PLUS_NOAL = (ATTR_EFF_DRAM_TRTP + 3)	;
+
+# AL={1,2};	max (TWTR + 8, TRTP + CL + AL + GPO) new formula from SWyatt
+define def_TWTR_PLUS_OFF = (ATTR_EFF_DRAM_TWTR + 8)	;
+define def_TRTP_PLUS_AL	= (ATTR_EFF_DRAM_TRTP + ATTR_EFF_DRAM_CL + ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_AL + ATTR_VPD_GPO[0])	;
+define def_TRTP_PLUS_NOAL = (ATTR_EFF_DRAM_TRTP + ATTR_EFF_DRAM_CL + ATTR_VPD_GPO[0])	;
 
 # for ODT on/off time calculation during write calibration
 # 2tCK = DDR4 feature for extended write preamble, should be defined by attribute if used.
@@ -334,7 +343,8 @@ define def_tODTL_DDR4_NOAL	= (ATTR_EFF_DRAM_CWL - 3)	;	# DDR4 & 2tCK, no AL
 # def_dqs_offset 	= (10 + ((def_p2p_jitter / 2) / def_1PR) + 1)	# +1 for ceiling FN
 #define def_p2p_jitter		=	240										;	# DQS peak to peak jitter in ps
 define def_p2p_jitter		=	2600									;	# DQS peak to peak jitter in ps
-define def_dqs_offset		=	(11 + (((def_p2p_jitter) * CEN.ATTR_MSS_FREQ) / 4000000))	;
+#define def_dqs_offset		=	(11 + (((def_p2p_jitter) * CEN.ATTR_MSS_FREQ) / 4000000))	;
+define def_dqs_offset		= 	8				;	# SWyatt
 
 #---------------------------------------------------------------------------------
 
@@ -3183,10 +3193,43 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 # PHYW.PHYX.GEN_DP#0.DPX.HC.HC.RDDP18WRAP.SL#3.RDDP18DQS_MAC.DQSLOGIC.R0DQSCDLY_L2
 #
 
+## ---------------------------------------------------------------------------------------
+## DP18 Read Diagnostic Configuration 3 Register		default=0x0806	!! need to set this?
+##
+## DDRPHY_DP18_RD_DIA_CONFIG3		0x06D		0x8000006d0301143f
+#scom 0x800(0,1)0C6D0301143F {	# broadcast all instances
+#	bits	,	scom_data	,	expr				;
+##	0:47	,	0x000000000000,	any					;	# reserved
+##	48:55	,	0x08		,	any					;	# DP18_0_DESIRED_EDGE_CNTR_TARGET_HIGH(0:7) default
+#	48:55	,	0x0C		,	any					;	# DP18_0_DESIRED_EDGE_CNTR_TARGET_HIGH(0:7) SWyatt
+##	56:63	,	0x06		,	any					;	# DP18_0_DESIRED_EDGE_CNTR_TARGET_HIGH(0:7) default
+#	56:63	,	0x08		,	any					;	# DP18_0_DESIRED_EDGE_CNTR_TARGET_HIGH(0:7) SWyatt
+#}
+
 # ---------------------------------------------------------------------------------------
-# DP18 Read Diagnostic Configuration 3 Register		default=0x0806	!! need to set this?
+# DP18 Read Diagnostic Configuration 5 Register		default=0x0000
 #
-# DDRPHY_DP18_RD_DIA_CONFIG3		0x06D		0x8000
+# DDRPHY_DP18_RD_DIA_CONFIG5		0x012		0x800000120301143f
+scom 0x800(0,1)3C120301143F {	# broadcast all instances
+	bits	,	scom_data	,	expr				;
+#	0:47	,	0x000000000000,	any					;	# reserved
+#	48		,	0b0			,	any					;	#0 DYN_POWER_CNTL_EN
+#	49		,	0b0			,	(def_is_sim)		;	#1 DYN_MCTERM_CNTL_EN
+#	50		,	0b0			,	(def_is_sim)		;	#2 DYN_RX_GATE_CNTL_EN
+#	51		,	0b0			,	(def_is_sim)		;	#3 CALGATE_ON
+#	52		,	0b0			,	(def_is_sim)		;	#4 PER_RDCLK_UPDATE_DISABLE
+#	53:54	,	0b00		,	(def_is_sim)		;	#5 DQS_PIPE_FIX_DIS
+#	55		,	0b0			,	(def_is_sim)		;	#6 DD2_DQS_FIX_DIS
+#	56		,	0b0			,	any					;	#7 DL_FORCE_ON
+#	57		,	0b0			,	any					;	#8 BLFIFO_DIS
+#	58		,	0b0			,	any					;	#9 WTRFL_AVE_DIS
+#	59		,	0b0			,	any					;	#A PERCAL_PWR_DIS	default
+	59		,	0b1			,	any					;	#B PERCAL_PWR_DIS	SWyatt
+#	60		,	0b0			,	any					;	#C LOOPBACK_FIX_EN
+#	61		,	0b0			,	any					;	#D LOOPBACK_DLY12
+#	62		,	0b0			,	any					;	#E DD2_WTRFL_SYNC_DIS
+#	63		,	0b0			,	any					;	#F FORCE_FIFO_CAPTURE
+}
 
 # ---------------------------------------------------------------------------------------
 # Initial calibration sequence Config0 register		default=0	sim = 0xBF2?
@@ -3846,8 +3889,10 @@ scom 0x800(0,1)C8020301143F {	# _P[0:1]
 	bits	,	scom_data	,	expr			;
 #	0:47	,	0x000000000000,	any				;	# reserved
 #	48:52	,	0b00000		,	(def_is_sim)	;	# CONSEQ_PASS	sim value
-	48:52	,	0b00110		,	(def_is_bl8)	;	# CONSEQ_PASS	6 min for BL8
-	48:52	,	0b01100		,	any				;	# CONSEQ_PASS	12 min for BL4, or OTF
+	48:52	,	0b01000		,	(def_is_bl8)	;	# CONSEQ_PASS	8 from SWyatt
+#	48:52	,	0b00110		,	(def_is_bl8)	;	# CONSEQ_PASS	6 min for BL8
+#	48:52	,	0b01100		,	any				;	# CONSEQ_PASS	12 min for BL4, or OTF
+	48:52	,	0b01111		,	any				;	# CONSEQ_PASS	16 min for BL4, or OTF
 #	53:56	,	0b0000		,	any				;	# reserved
 	# 00 = compare beats 1:4, 01 = compare beats 3:6,	10 = compare beats 5:8, 11 = compare all 8 beats
 #	57:58	,	0b00		,	(def_is_sim)	;	# BURST_WINDOW, compare beats 1-4 (legacy, if SIM)
@@ -4119,7 +4164,7 @@ scom 0x800(0,1)CC000301143F {	# _P[0:1]
 
 	# FW_WR_RD [same formula as RD_WR? max(tWTR+11,AL+tRTP+3), ATTR_EFF_DRAM_AL(0,1,2)]
 	57:62	,	0b000000			,	(def_is_sim)							;   # is this max?
-	57:62	,	0b010001			,	any										;	# same as dd0, 17 clocks
+	57:62	,	0b100000			,	any										;	# dd0 = 17 clocks, now 32 from SWyatt
 
 	# AL={1,2};	max (TWTR + 11, TRTP + AL + 3)
 #	57:62	,	(def_TWTR_PLUS_OFF)	,	(def_AL_ena && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_AL) )	;	# TWTR + 11
@@ -4141,8 +4186,10 @@ scom 0x800(0,1)CC010301143F {	# _P[0:1]
 #	0:47	,	0x000000000000,	any				;	# reserved
 # !! need to review
 	48:51	,	0b1100		,	(def_is_sim)	;	# BIG_STEP = 12	(changed from default for SIM)
-	48:51	,	0b0010		,	any				;	# BIG_STEP = 2	(default)
-	52:54	,	0b001		,	any				;	# SMALL_STEP = 1	(!! recommend setting to 0)
+	48:51	,	0b0000		,	any				;	# BIG_STEP = 0	SWyatt
+#	48:51	,	0b0010		,	any				;	# BIG_STEP = 2	(default)
+	52:54	,	0b000		,	any				;	# SMALL_STEP = 0 (default)	SWyatt
+#	52:54	,	0b001		,	any				;	# SMALL_STEP = 1	(!! recommend setting to 0)
 	55:60	,	0b101010	,	any				;	# WR_PRE_DLY = 42
 #	61:63	,	0b000		,	any				;	# reserved
 }
@@ -4157,15 +4204,24 @@ scom 0x800(0,1)CC020301143F {	# _P[0:1]
 #	0:47	,	0x000000000000		,	any				;	# reserved
 	48:51	,	0x3					,	(def_is_sim)	;	# NUM_VALID_SAMPLES = 3 (changed from defaults)
 	48:51	,	0x5					,	any				;	# NUM_VALID_SAMPLES = 5 (defaults)
-
+# --------------------------
+	# FW_RD_WR = max(tWTR+8,CL+AL+GPO+tRTP), AL=ATTR_EFF_DRAM_CL-ATTR_EFF_DRAM_AL when ATTR_EFF_DRAM_AL != 0   SWyatt
+	# AL={1,2};	max (TWTR + 8, TRTP + CL + AL + GPO)
+	52:57	,	(def_TWTR_PLUS_OFF)	,	(def_AL_ena && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_AL) )	;	# TWTR + 8
+	52:57	,	(def_TRTP_PLUS_AL)	,	(def_AL_ena && (def_TWTR_PLUS_OFF < def_TRTP_PLUS_AL) )		;	# TRTP + CL + CL-AL + GPO
+
+	# AL=0, 	max (TWTR + 8, TRTP + CL + GPO)
+	52:57	,	(def_TWTR_PLUS_OFF)	,	(def_AL_dis && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_NOAL) )	;	# TWTR + 8
+	52:57	,	(def_TRTP_PLUS_NOAL),	(def_AL_dis && (def_TWTR_PLUS_OFF < def_TRTP_PLUS_NOAL)	)	;	# TRTP + CL + GPO
+# --------------------------
 	# FW_RD_WR = max(tWTR+11,AL+tRTP+3), AL=ATTR_EFF_DRAM_CL-ATTR_EFF_DRAM_AL when ATTR_EFF_DRAM_AL != 0
 	# AL={1,2};	max (TWTR + 11, TRTP + AL + 3)
-	52:57	,	(def_TWTR_PLUS_OFF)	,	(def_AL_ena && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_AL) )	;	# TWTR + 11
-	52:57	,	(def_TRTP_PLUS_AL)	,	(def_AL_ena && (def_TWTR_PLUS_OFF < def_TRTP_PLUS_AL) )		;	# TRTP + AL + 3
+#	52:57	,	(def_TWTR_PLUS_OFF)	,	(def_AL_ena && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_AL) )	;	# TWTR + 11
+#	52:57	,	(def_TRTP_PLUS_AL)	,	(def_AL_ena && (def_TWTR_PLUS_OFF < def_TRTP_PLUS_AL) )		;	# TRTP + AL + 3
 
 	# AL=0, 	max (TWTR + 11, TRTP + 3)
-	52:57	,	(def_TWTR_PLUS_OFF)	,	(def_AL_dis && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_NOAL) )	;	# TWTR + 11
-	52:57	,	(def_TRTP_PLUS_NOAL),	(def_AL_dis && (def_TWTR_PLUS_OFF < def_TRTP_PLUS_NOAL)	)	;	# TRTP + 3
+#	52:57	,	(def_TWTR_PLUS_OFF)	,	(def_AL_dis && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_NOAL) )	;	# TWTR + 11
+#	52:57	,	(def_TRTP_PLUS_NOAL),	(def_AL_dis && (def_TWTR_PLUS_OFF < def_TRTP_PLUS_NOAL)	)	;	# TRTP + 3
 
 #	58:61	,	0b00000				,	any				;	# reserved
 	# DD2_FIX_DIS