INITPROC: Hostboot - FW612231 Watchdog msg

Change-Id: I34dba93de4a77e26616bc3a4367ffdfeabbd28c9
CMVC-Prereq:FW612231
CQ:FW612231
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7006
Tested-by: Jenkins Server
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

4 files changed, 210 insertions, 13 deletions

diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H
index 0bc9d64a5..ec9b01059 100644
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp.H,v 1.11 2013/09/26 18:14:06 jmcgill Exp $
+// $Id: proc_build_smp.H,v 1.12 2013/10/18 21:36:02 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp.H,v $
 //------------------------------------------------------------------------------
 // *|
@@ -158,7 +158,7 @@ struct proc_build_smp_node
     proc_fab_smp_node_id node_id;
 };
 
-// core floor/nest frequency ratio cutpoints
+// core floor/nest frequency ratio cutpoints (epsilon)
 enum proc_build_smp_core_floor_ratio
 {
     PROC_BUILD_SMP_CORE_FLOOR_RATIO_8_8 = 0,
@@ -169,6 +169,26 @@ enum proc_build_smp_core_floor_ratio
     PROC_BUILD_SMP_CORE_FLOOR_RATIO_2_8 = 5
 };
 
+// core floor/nest frequency ratio cutpoints (CPU delay)
+const uint8_t PROC_BUILD_SMP_CPU_DELAY_NUM_SETPOINTS = 13;
+
+enum proc_build_smp_cpu_delay
+{
+    PROC_BUILD_SMP_CPU_DELAY_4800_2400 = 0,
+    PROC_BUILD_SMP_CPU_DELAY_4431_2400 = 1,
+    PROC_BUILD_SMP_CPU_DELAY_4114_2400 = 2,
+    PROC_BUILD_SMP_CPU_DELAY_3840_2400 = 3,
+    PROC_BUILD_SMP_CPU_DELAY_3600_2400 = 4,
+    PROC_BUILD_SMP_CPU_DELAY_3338_2400 = 5,
+    PROC_BUILD_SMP_CPU_DELAY_3200_2400 = 6,
+    PROC_BUILD_SMP_CPU_DELAY_3032_2400 = 7,
+    PROC_BUILD_SMP_CPU_DELAY_2880_2400 = 8,
+    PROC_BUILD_SMP_CPU_DELAY_2743_2400 = 9,
+    PROC_BUILD_SMP_CPU_DELAY_2618_2400 = 10,
+    PROC_BUILD_SMP_CPU_DELAY_2504_2400 = 11,
+    PROC_BUILD_SMP_CPU_DELAY_2400_2400 = 12
+};
+
 // structure to encapsulate system epsilon configuration
 struct proc_build_smp_eps_cfg
 {
@@ -203,9 +223,14 @@ struct proc_build_smp_system
     uint32_t freq_a;
     uint32_t freq_x;
     uint32_t freq_core_floor;
+    uint32_t freq_core_nom;
+    uint32_t freq_core_ceiling;
     uint32_t freq_pcie;
     // core floor/pb frequency ratio
     proc_build_smp_core_floor_ratio core_floor_ratio;
+    // CPU ratios
+    proc_build_smp_cpu_delay nom_cpu_delay;
+    proc_build_smp_cpu_delay full_cpu_delay;
 
     // program async boundary crossings to safe mode
     bool async_safe_mode;
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C
index 52f019a1b..3d7938537 100644
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C
@@ -1273,7 +1273,8 @@ fapi::ReturnCode proc_build_smp_set_sconfig_we5(
 
     do
     {
-        rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_CENT5_VER2,
+//@thi - Patch this per Joe's suggestion
+        rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_WE5_VER2,
                            &(i_smp_chip.chip->this_chip),
                            ver2);
         if (!rc.ok())
diff --git a/src/usr/hwpf/hwp/initfiles/p8.pe.phase2.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.pe.phase2.scom.initfile
index ff41d660a..b575995e6 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.pe.phase2.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.pe.phase2.scom.initfile
@@ -1,4 +1,4 @@
-#-- $Id: p8.pe.phase2.scom.initfile,v 1.3 2013/04/19 14:30:07 jmcgill Exp $
+#-- $Id: p8.pe.phase2.scom.initfile,v 1.4 2013/11/01 00:37:33 jmcgill Exp $
 #-------------------------------------------------------------------------------
 #--
 #-- (C) Copyright International Business Machines Corp. 2011
@@ -27,14 +27,19 @@ define def_nest_freq_r0 = (SYS.ATTR_FREQ_PB >= 2200);
 define def_nest_freq_r1 = ((SYS.ATTR_FREQ_PB <= 1700) && (SYS.ATTR_FREQ_PB < 2200));
 define def_nest_freq_r2 = (SYS.ATTR_FREQ_PB < 1700);
 
+define enable_enh_ive_ordering = (ATTR_CHIP_EC_FEATURE_ENABLE_IVE_PERFORMANCE_ORDERING != 0);
+define enable_dmar_ooo         = (ATTR_CHIP_EC_FEATURE_ENABLE_PCI_DMAR_OOO != 0);
+
 #--------------------------------------------------------------------------------
 #-- SCOM initializations
 #--------------------------------------------------------------------------------
 
 #-- PBCQ Mode Control Register
 scom 0x02012(0,4,8)0B {
-    bits,    scom_data;
-    26,      0b1;                                                   #-- enable enhanced IVE performance ordering
+    bits,    scom_data,    expr;
+    12,      0b1,          any;                                     #-- disable group scope on TCE read requests
+    26,      0b1,          (enable_enh_ive_ordering);               #-- enable enhanced IVE performance ordering only where supported (HW226407)
+    27,      0b1,          any;                                     #-- force IVE write operations to system scope
 }
 
 #-- PCI Hardware Configuration 0 Register
@@ -46,6 +51,12 @@ scom 0x02012(0,4,8)18 {
     17,      0b1;                                                   #-- disable out-of-order store behavior
 }
 
+#-- PCI Hardware Configuration 1 Register
+scom 0x02012(0,4,8)19 {
+    bits,    scom_data,    expr;
+    22,      0b1,          (enable_dmar_ooo);                       #-- enable OOO DMA read only where supported (HW223650)
+}
+
 #-- PCI Nest Clock Trace Control Register
 scom 0x02012(0,4,8)0D {
     bits,    scom_data;
@@ -62,7 +73,6 @@ scom 0x09012(0,4,8)0F {
     6:8,     0b011,        (def_nest_freq_r0);                      #-- Maximum Ch2 command credit given to ETU
     6:8,     0b010,        (def_nest_freq_r1 || def_nest_freq_r2);
     9:11,    0b000,        any;                                     #-- Maximum Ch3 command credit given to ETU
-    12:13,   0b10,         (def_nest_freq_r0 || def_nest_freq_r1);  #-- Overcommit of inbound speed matching buffer
-    12:13,   0b11,         (def_nest_freq_r2);
+    12:13,   0b11,         any;                                     #-- Overcommit of inbound speed matching buffer (HW245629)
     30:31,   0b11,         any;                                     #-- enable PCI clock tracing w/ ETU as default
 }
diff --git a/src/usr/hwpf/hwp/proc_chip_ec_feature.xml b/src/usr/hwpf/hwp/proc_chip_ec_feature.xml
index 08b9a9a70..73290df8f 100644
--- a/src/usr/hwpf/hwp/proc_chip_ec_feature.xml
+++ b/src/usr/hwpf/hwp/proc_chip_ec_feature.xml
@@ -20,7 +20,7 @@
 <!-- Origin: 30                                                             -->
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
-<!-- $Id: proc_chip_ec_feature.xml,v 1.29 2013/10/11 14:34:44 thi Exp $ -->
+<!-- $Id: proc_chip_ec_feature.xml,v 1.37 2013/10/31 16:02:44 jmcgill Exp $ -->
 <!-- Defines the attributes that are based on EC level -->
 <attributes>
   <attribute>
@@ -169,7 +169,7 @@
     <id>ATTR_CHIP_EC_FEATURE_CAPP_HANG_CONTROL_ON_SCOM</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Returns if a chip contains SCOM configuration for CAPP unit PB hang recovrery controls.  True if:
+      Returns if a chip contains SCOM configuration for CAPP unit PB hang recovery controls.  True if:
         Murano EC 0x20 or greater
         Venice EC 0x10 or greater
     </description>
@@ -191,10 +191,35 @@
     </chipEcFeature>
   </attribute>
   <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_CAPP_PROD</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Returns if a chip contains production CAPP logic function
+        Murano EC 0x20 or greater
+        Venice EC 0x20 or greater
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_MURANO</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_VENICE</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_NX_HANG_CONTROL_ON_SCOM</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Returns if a chip contains SCOM configuration for NX unit PB hang recovrery controls.  True if:
+      Returns if a chip contains SCOM configuration for NX unit PB hang recovery controls.  True if:
         Murano EC 0x20 or greater
         Venice EC 0x20 or greater
     </description>
@@ -377,7 +402,7 @@
     <id>ATTR_CHIP_EC_FEATURE_ADU_PBINIT_LAUNCH_BUG</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      True if: 
+      True if:
         Murano EC less than 0x20
         Venice EC less than 0x20
     </description>
@@ -474,9 +499,10 @@
     </chipEcFeature>
   </attribute>
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_CENT5_VER2</id>
+    <id>ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_WE5_VER2</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
+      Specifies layout of WE5 serial chain
       True if:
         Murano EC greater than or equal to 0x20
         Venice EC greater than or equal to 0x20
@@ -499,6 +525,74 @@
     </chipEcFeature>
   </attribute>
   <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_C8_VER3</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Specifies layout of C8 serial chain
+      True if:
+        Murano/Venice EC greater than or equal to 0x20
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_MURANO</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_VENICE</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_C8_VER2</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Specifies layout of C8 serial chain
+      True if:
+        Venice EC equal to 0x10
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_VENICE</name>
+        <ec>
+          <value>0x10</value>
+          <test>EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_C10_VER2</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Specifies layout of C10 serial chain
+      True if:
+        Murano/Venice EC greater than or equal to 0x20
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_MURANO</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_VENICE</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
@@ -672,4 +766,71 @@
       </chip>
     </chipEcFeature>
   </attribute>
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_OCC_CE_FIR_DISABLE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      True if:
+        Murano EC less than 0x20
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_MURANO</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>      
+    </chipEcFeature>
+  </attribute>
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_ENABLE_IVE_PERFORMANCE_ORDERING</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      True if:
+        Murano EC greater than or equal to 0x20
+        Venice
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_MURANO</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>      
+      <chip>
+        <name>ENUM_ATTR_NAME_VENICE</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>      
+    </chipEcFeature>
+  </attribute>
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_ENABLE_PCI_DMAR_OOO</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      True if:
+        Murano EC greater than or equal to 0x20
+        Venice
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_MURANO</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>      
+      <chip>
+        <name>ENUM_ATTR_NAME_VENICE</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>      
+    </chipEcFeature>
+  </attribute>
 </attributes>