INITPROC: Hostboot - SW238939 Centaur scan ring changes

Change-Id: I8159adf805a9f92324742cbe5728b5697f8edd31
CQ:SW238939
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7850
Tested-by: Jenkins Server
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

5 files changed, 111 insertions, 29 deletions

diff --git a/src/usr/hwpf/hwp/bus_training/io_dccal.C b/src/usr/hwpf/hwp/bus_training/io_dccal.C
index 8176bc21a..d6a95ac6d 100644
--- a/src/usr/hwpf/hwp/bus_training/io_dccal.C
+++ b/src/usr/hwpf/hwp/bus_training/io_dccal.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_dccal.C,v 1.29 2013/12/04 10:35:50 jaswamin Exp $
+// $Id: io_dccal.C,v 1.30 2013/12/10 14:39:02 mfred Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -741,7 +741,7 @@ ReturnCode io_dccal(const Target& target){
         }
         rc = proc_a_x_pci_dmi_pll_scan_bndy(target,
                                             TP_CHIPLET_0x01000000,
-                                            TP_BNDY_PLL_RING_ADDR,
+                                            MEMB_TP_BNDY_PLL_RING_ADDR,
                                             ring_data,
                                             true);
         if (rc)
@@ -782,7 +782,7 @@ ReturnCode io_dccal(const Target& target){
 
         rc = proc_a_x_pci_dmi_pll_scan_bndy(target,
                                             TP_CHIPLET_0x01000000,
-                                            TP_BNDY_PLL_RING_ADDR,
+                                            MEMB_TP_BNDY_PLL_RING_ADDR,
                                             ring_data,
                                             true);
         if (rc)
diff --git a/src/usr/hwpf/hwp/bus_training/io_run_training.C b/src/usr/hwpf/hwp/bus_training/io_run_training.C
index 279475e61..7d5de49f8 100644
--- a/src/usr/hwpf/hwp/bus_training/io_run_training.C
+++ b/src/usr/hwpf/hwp/bus_training/io_run_training.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_run_training.C,v 1.51 2013/11/25 07:10:38 varkeykv Exp $
+// $Id: io_run_training.C,v 1.53 2013/12/20 08:32:10 varkeykv Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -89,7 +89,7 @@ ReturnCode io_training_set_pll_post_wiretest(const Target& target){
                                &target,
                                chip_unit);
      
-            if (!rc.ok())
+            if (rc)
             {
                 FAPI_ERR("Error retreiving MCS chiplet number!");
                 return rc;
@@ -133,16 +133,26 @@ ReturnCode io_training_set_pll_post_wiretest(const Target& target){
         //}
               
 	    rc_ecmd |= ring_data.setBitLength(ring_length);
-            
-            rc_ecmd |=fapiGetRing(parent_target,PB_BNDY_DMIPLL_RING_ADDR ,ring_data,RING_MODE_SET_PULSE); 
-            FAPI_DBG("PFD bit to be cleared for DMI unit %d is %d",chip_unit,proc_dmi_cupll_pfd360_offset[chip_unit]);
-            ring_data.clearBit(proc_dmi_cupll_pfd360_offset[chip_unit]);
-            // Now 
-        if (rc_ecmd)
+         if (rc_ecmd)
         {
             rc.setEcmdError(rc_ecmd);
             return(rc);
         }
+            
+          rc =fapiGetRing(parent_target,PB_BNDY_DMIPLL_RING_ADDR ,ring_data,RING_MODE_SET_PULSE);
+          if (rc)
+          {
+              FAPI_ERR("Error performing GetRing operation on PB_BNDY_DMIPLL");
+              return(rc);
+          }
+            FAPI_DBG("PFD bit to be cleared for DMI unit %d is %d",chip_unit,proc_dmi_cupll_pfd360_offset[chip_unit]);
+          rc_ecmd |= ring_data.clearBit(proc_dmi_cupll_pfd360_offset[chip_unit]);
+              // Now 
+          if (rc_ecmd)
+          {
+              rc.setEcmdError(rc_ecmd);
+              return(rc);
+          }
         rc = proc_a_x_pci_dmi_pll_scan_bndy(parent_target,
                                             NEST_CHIPLET_0x02000000,
                                             PB_BNDY_DMIPLL_RING_ADDR,
@@ -194,11 +204,21 @@ ReturnCode io_training_set_pll_post_wiretest(const Target& target){
      
         FAPI_DBG("Ring length is %d",ring_length);
 	    rc_ecmd |= ring_data.setBitLength(ring_length);
+       if (rc_ecmd)
+        {
+            rc.setEcmdError(rc_ecmd);
+            return(rc);
+        }
             
-           rc_ecmd |=fapiGetRing(target,TP_BNDY_PLL_RING_ADDR ,ring_data,RING_MODE_SET_PULSE); 
+           rc=fapiGetRing(target,MEMB_TP_BNDY_PLL_RING_ADDR ,ring_data,RING_MODE_SET_PULSE);
+          if (rc)
+          {
+              FAPI_ERR("Get ring error on MEMB ");
+              return(rc);
+          }
 	   // rc_ecmd |= ring_data.insert(pb_bndy_dmipll_data, 0, ring_length, 0);		// -- put data into ecmd buffer
             FAPI_DBG("PFD bit to be cleared for centaur is %d",memb_dmi_cupll_pfd360_offset);
-            ring_data.clearBit(memb_dmi_cupll_pfd360_offset);
+             rc_ecmd |=ring_data.clearBit(memb_dmi_cupll_pfd360_offset);
             
 	    //rc_ecmd |= ring_data.insert(tp_bndy_pll_data, 0, ring_length, 0);		// -- put data into ecmd buffer
         if (rc_ecmd)
@@ -208,7 +228,7 @@ ReturnCode io_training_set_pll_post_wiretest(const Target& target){
         }
         rc = proc_a_x_pci_dmi_pll_scan_bndy(target,
                                             TP_CHIPLET_0x01000000,
-                                            TP_BNDY_PLL_RING_ADDR,
+                                            MEMB_TP_BNDY_PLL_RING_ADDR,
                                             ring_data,
                                             true);
         if (rc)
@@ -278,15 +298,25 @@ ReturnCode io_training_set_pll_post_wiretest(const Target& target){
         //    return(rc);
         //}
             rc_ecmd |= ring_data.setBitLength(ring_length);
-            rc_ecmd |=fapiGetRing(parent_target,AB_BNDY_PLL_RING_ADDR ,ring_data,RING_MODE_SET_PULSE); 
+          if (rc_ecmd)
+          {
+              rc.setEcmdError(rc_ecmd);
+              return(rc);
+          }
+            rc =fapiGetRing(parent_target,AB_BNDY_PLL_RING_ADDR ,ring_data,RING_MODE_SET_PULSE);
+               if (rc)
+               {
+                   FAPI_ERR("GetRing error on AB ring");
+                   return(rc);
+               }
             FAPI_DBG("PFD bit to be cleared for Abus number %d is %d",chip_unit,proc_abus_cupll_pfd360_offset[chip_unit]);
-            ring_data.clearBit(proc_abus_cupll_pfd360_offset[chip_unit]);
+            rc_ecmd|=ring_data.clearBit(proc_abus_cupll_pfd360_offset[chip_unit]);
 
-        if (rc_ecmd)
-        {
-            rc.setEcmdError(rc_ecmd);
-            return(rc);
-        }
+          if (rc_ecmd)
+          {
+              rc.setEcmdError(rc_ecmd);
+              return(rc);
+          }
         rc = proc_a_x_pci_dmi_pll_scan_bndy(parent_target,
                                             A_BUS_CHIPLET_0x08000000,
                                             AB_BNDY_PLL_RING_ADDR,
diff --git a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.C b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.C
index 63207af42..804f2e82a 100644
--- a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.C
+++ b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_mem_pll_initf.C,v 1.9 2013/11/15 16:29:56 mfred Exp $
+// $Id: cen_mem_pll_initf.C,v 1.10 2013/12/10 03:41:34 mfred Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_pll_initf.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -87,6 +87,8 @@ const uint64_t OPCG_REG2_FOR_SETPULSE  = 0x0000000000002000ull;
 const uint64_t OPCG_REG3_FOR_SETPULSE  = 0x6000000000000000ull;
 const uint64_t CLK_REGION_FOR_SETPULSE = 0x0010040000000000ull;
 
+const uint32_t MEMB_TP_BNDY_PLL_RING_ADDR  = 0x01030088;
+
 // Pervasive LFIR Register field/bit definitions
 const uint8_t PERV_LFIR_SCAN_COLLISION_BIT = 3;
 
@@ -207,7 +209,7 @@ fapi::ReturnCode cen_load_pll_ring_from_buffer(const fapi::Target & i_target,
         //------------------------------------------------
         //  Scan new ring data into tp_pll_bndy scan ring.
         //------------------------------------------------
-        rc = fapiPutRing(i_target, 0x00030088, i_scan_ring_data, RING_MODE_SET_PULSE);
+        rc = fapiPutRing(i_target, MEMB_TP_BNDY_PLL_RING_ADDR, i_scan_ring_data, RING_MODE_SET_PULSE);
         if (rc)
         {
             FAPI_ERR("fapiPutRing failed with rc = 0x%x", (uint32_t)rc);
@@ -512,6 +514,9 @@ fapi::ReturnCode cen_mem_pll_initf(const fapi::Target & i_target)
 This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 $Log: cen_mem_pll_initf.C,v $
+Revision 1.10  2013/12/10 03:41:34  mfred
+Make changes to support TP_BNDY scan chain addresses changing to chiplet 1 for zSeries.
+
 Revision 1.9  2013/11/15 16:29:56  mfred
 Changes made by Mike Jones for gerrit review, mostly for improved error handling.
 
diff --git a/src/usr/hwpf/hwp/include/cen_scom_addresses.H b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
index a8130a2cf..c91c309a3 100755
--- a/src/usr/hwpf/hwp/include/cen_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_scom_addresses.H,v 1.65 2013/11/05 20:33:31 bellows Exp $
+// $Id: cen_scom_addresses.H,v 1.67 2013/12/16 19:38:35 dsanner Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/cen_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -231,6 +231,7 @@ CONST_UINT64_T( TP_TRACE_DATA_LO_0x01010441            , ULL(0x01010441) );
 //------------------------------------------------------------------------------
 // MBI
 CONST_UINT64_T( MBI_FIR_0x02010800                     , ULL(0x02010800) );
+CONST_UINT64_T( MBI_FIR_AND_0x02010801                 , ULL(0x02010801) );
 CONST_UINT64_T( MBI_FIRMASK_0x02010803                 , ULL(0x02010803) );
 CONST_UINT64_T( MBI_FIRACT0_0x02010806                 , ULL(0x02010806) );
 CONST_UINT64_T( MBI_FIRACT1_0x02010807                 , ULL(0x02010807) );
@@ -559,6 +560,34 @@ CONST_UINT64_T( DPHY01_DDRPHY_PC_PER_ZCAL_CONFIG_P1_0x8001C00F0301143F,
 CONST_UINT64_T( DPHY01_DDRPHY_PC_POWERDOWN_1_P0_0x8000C0100301143F,              ULL(0x8000C0100301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_PC_POWERDOWN_1_P1_0x8001C0100301143F,              ULL(0x8001C0100301143F) );
 
+CONST_UINT64_T( DPHY23_DDRPHY_PC_POWERDOWN_1_P0_0x8000C0100301183F,              ULL(0x8000C0100301183F) );
+CONST_UINT64_T( DPHY23_DDRPHY_PC_POWERDOWN_1_P1_0x8001C0100301183F,              ULL(0x8001C0100301183F) );
+//------------------------------------------------------------------------------
+// Delay Line Power control Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_0_0x8000006f0301143f,              ULL(0x8000006f0301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_1_0x8000046f0301143f,              ULL(0x8000046f0301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_2_0x8000086f0301143f,              ULL(0x8000086f0301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_3_0x80000c6f0301143f,              ULL(0x80000c6f0301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_4_0x8000106f0301143f,              ULL(0x8000106f0301143f) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_0_0x8001006f0301143f,              ULL(0x8001006f0301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_1_0x8001046f0301143f,              ULL(0x8001046f0301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_2_0x8001086f0301143f,              ULL(0x8001086f0301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_3_0x80010c6f0301143f,              ULL(0x80010c6f0301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_4_0x8001106f0301143f,              ULL(0x8001106f0301143f) );
+
+CONST_UINT64_T( DPHY23_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_0_0x8000006f0301183f,              ULL(0x8000006f0301183f) );
+CONST_UINT64_T( DPHY23_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_1_0x8000046f0301183f,              ULL(0x8000046f0301183f) );
+CONST_UINT64_T( DPHY23_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_2_0x8000086f0301183f,              ULL(0x8000086f0301183f) );
+CONST_UINT64_T( DPHY23_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_3_0x80000c6f0301183f,              ULL(0x80000c6f0301183f) );
+CONST_UINT64_T( DPHY23_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P0_4_0x8000106f0301183f,              ULL(0x8000106f0301183f) );
+                                                                                                               
+CONST_UINT64_T( DPHY23_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_0_0x8001006f0301183f,              ULL(0x8001006f0301183f) );
+CONST_UINT64_T( DPHY23_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_1_0x8001046f0301183f,              ULL(0x8001046f0301183f) );
+CONST_UINT64_T( DPHY23_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_2_0x8001086f0301183f,              ULL(0x8001086f0301183f) );
+CONST_UINT64_T( DPHY23_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_3_0x80010c6f0301183f,              ULL(0x80010c6f0301183f) );
+CONST_UINT64_T( DPHY23_DDRPHY_DP18_DELAY_LINE_PWR_CTL_P1_4_0x8001106f0301183f,              ULL(0x8001106f0301183f) );
 //------------------------------------------------------------------------------
 //      MBA Fault Isolation Register
 //------------------------------------------------------------------------------
@@ -1745,6 +1774,17 @@ CONST_UINT64_T( DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P1_2_0x800108120301143F , ULL(
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P1_3_0x80010C120301143F , ULL(0x80010C120301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P1_4_0x800110120301143F,  ULL(0x800110120301143F) );
 
+CONST_UINT64_T( DPHY23_DDRPHY_DP18_RD_DIA_CONFIG5_P0_0_0x800000120301183F , ULL(0x800000120301183F) );
+CONST_UINT64_T( DPHY23_DDRPHY_DP18_RD_DIA_CONFIG5_P0_1_0x800004120301183F , ULL(0x800004120301183F) );
+CONST_UINT64_T( DPHY23_DDRPHY_DP18_RD_DIA_CONFIG5_P0_2_0x800008120301183F , ULL(0x800008120301183F) );
+CONST_UINT64_T( DPHY23_DDRPHY_DP18_RD_DIA_CONFIG5_P0_3_0x80000C120301183F , ULL(0x80000C120301183F) );
+CONST_UINT64_T( DPHY23_DDRPHY_DP18_RD_DIA_CONFIG5_P0_4_0x800010120301183F , ULL(0x800010120301183F) );
+                                                                                               
+CONST_UINT64_T( DPHY23_DDRPHY_DP18_RD_DIA_CONFIG5_P1_0_0x800100120301183F , ULL(0x800100120301183F) );
+CONST_UINT64_T( DPHY23_DDRPHY_DP18_RD_DIA_CONFIG5_P1_1_0x800104120301183F , ULL(0x800104120301183F) );
+CONST_UINT64_T( DPHY23_DDRPHY_DP18_RD_DIA_CONFIG5_P1_2_0x800108120301183F , ULL(0x800108120301183F) );
+CONST_UINT64_T( DPHY23_DDRPHY_DP18_RD_DIA_CONFIG5_P1_3_0x80010C120301183F , ULL(0x80010C120301183F) );
+CONST_UINT64_T( DPHY23_DDRPHY_DP18_RD_DIA_CONFIG5_P1_4_0x800110120301183F,  ULL(0x800110120301183F) );
 
 
 
@@ -1757,6 +1797,12 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: cen_scom_addresses.H,v $
+Revision 1.67  2013/12/16 19:38:35  dsanner
+Fix compile error for proc_mpipl_clear_xstop.C
+
+Revision 1.66  2013/12/16 10:16:45  sasethur
+added power control registers
+
 Revision 1.65  2013/11/05 20:33:31  bellows
 Added MBI_CRCSYN
 
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.H b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.H
index 4a0c8e0a1..d1f1a0ab7 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.H
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_a_x_pci_dmi_pll_utils.H,v 1.2 2013/09/30 16:09:57 jmcgill Exp $
+// $Id: proc_a_x_pci_dmi_pll_utils.H,v 1.3 2013/12/10 02:50:34 mfred Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_utils.H,v $
 //------------------------------------------------------------------------------
 // *|
@@ -49,10 +49,11 @@
 // Constant definitions
 //------------------------------------------------------------------------------
 
-const uint32_t TP_BNDY_PLL_RING_ADDR    = 0x00030088;
-const uint32_t PB_BNDY_DMIPLL_RING_ADDR = 0x02030088;
-const uint32_t AB_BNDY_PLL_RING_ADDR    = 0x08030088;
-const uint32_t PCI_BNDY_PLL_RING_ADDR   = 0x09030088;
+const uint32_t TP_BNDY_PLL_RING_ADDR      = 0x00030088;
+const uint32_t MEMB_TP_BNDY_PLL_RING_ADDR = 0x01030088;
+const uint32_t PB_BNDY_DMIPLL_RING_ADDR   = 0x02030088;
+const uint32_t AB_BNDY_PLL_RING_ADDR      = 0x08030088;
+const uint32_t PCI_BNDY_PLL_RING_ADDR     = 0x09030088;
 
 const uint32_t DMI_PLL_VCO_WORKAROUND_THRESHOLD_FREQ = 4800;