Matching Tagged versions for memory HWPs

Change-Id: Icb9c98d71237e6c53b1a9a8af4fac0c95eced58b
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2911
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

21 files changed, 4302 insertions, 1245 deletions

diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_memdiag/mss_maint_cmds.C b/src/usr/hwpf/hwp/dram_initialization/mss_memdiag/mss_maint_cmds.C
index 038ac5864..877dd9a2c 100644
--- a/src/usr/hwpf/hwp/dram_initialization/mss_memdiag/mss_maint_cmds.C
+++ b/src/usr/hwpf/hwp/dram_initialization/mss_memdiag/mss_maint_cmds.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_maint_cmds.C,v 1.16 2012/11/21 21:21:08 gollub Exp $
+// $Id: mss_maint_cmds.C,v 1.17 2012/12/19 15:48:48 gollub Exp $
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -54,6 +54,7 @@
 //   1.15  | 11/08/12 | gollub  | Added timebase steer cleanup
 //         |          |         | Updates to traces.
 //   1.16  | 11/21/12 | gollub  | Updates from review.
+//   1.17  | 12/19/12 | gollub  | Added UE isolation
 
 //------------------------------------------------------------------------------
 //    Includes
@@ -106,7 +107,7 @@ const uint8_t MSS_X4_ECC_STEER_OPTIONS =              36;
 /**
  * @brief Max 8 patterns
  */ 
-const uint8_t MSS_MAX_PATTERNS =                      8;
+const uint8_t MSS_MAX_PATTERNS =                      9;
 
 
 namespace mss_MemConfig
@@ -183,6 +184,14 @@ static const uint32_t mss_markStoreRegs[8][2]={
     {MBS_ECC0_MBMS6_0x02011451,    MBS_ECC1_MBMS6_0x02011491},
     {MBS_ECC0_MBMS7_0x02011452,    MBS_ECC1_MBMS7_0x02011492}};
 
+static const uint32_t mss_mbstr[2]={
+    // port0/1                   port2/3
+    MBS01_MBSTRQ_0x02011655,     MBS23_MBSTRQ_0x02011755};
+
+static const uint32_t mss_mbmmr[2]={
+    // port0/1                   port2/3
+    MBS_ECC0_MBMMRQ_0x0201145B,  MBS_ECC1_MBMMRQ_0x0201149B};
+    
 static const uint32_t mss_readMuxRegs[8][2]={
     // port0/1                     port2/3
     {MBS_ECC0_MBSBS0_0x0201145E,   MBS_ECC1_MBSBS0_0x0201149E},
@@ -344,6 +353,27 @@ static const uint8_t mss_eccSpareIndex_to_symbol[MSS_X4_ECC_STEER_OPTIONS]={
 // TODO: Update with actual patterns from Luis Lastras when they are ready
 static const uint32_t mss_maintBufferData[MSS_MAX_PATTERNS][16][2]={
 
+// PATTERN_0 DEBUG
+/*
+   {{0x00000000, 0x10000000},
+    {0x01000000, 0x11000000},
+    {0x02000000, 0x12000000},
+    {0x03000000, 0x13000000},
+    {0x04000000, 0x14000000},
+    {0x05000000, 0x15000000},
+    {0x06000000, 0x16000000},
+    {0x07000000, 0x17000000},
+    {0x08000000, 0x18000000},
+    {0x09000000, 0x19000000},
+    {0x0a000000, 0x1a000000},
+    {0x0b000000, 0x1b000000},
+    {0x0c000000, 0x1c000000},
+    {0x0d000000, 0x1d000000},
+    {0x0e000000, 0x1e000000},
+    {0x0f000000, 0x1f000000}},
+*/
+
+
 // PATTERN_0
    {{0x00000000, 0x00000000},
     {0x00000000, 0x00000000},
@@ -486,7 +516,26 @@ static const uint32_t mss_maintBufferData[MSS_MAX_PATTERNS][16][2]={
     {0x33333333, 0x33333333},
     {0x33333333, 0x33333333},
     {0x33333333, 0x33333333},
-    {0x33333333, 0x33333333}}};
+    {0x33333333, 0x33333333}},
+
+// PATTERN_8: random seed
+   {{0x12345678, 0x87654321},
+    {0x12345678, 0x87654321},
+    {0x12345678, 0x87654321},
+    {0x12345678, 0x87654321},
+    {0x12345678, 0x87654321},
+    {0x12345678, 0x87654321},
+    {0x12345678, 0x87654321},
+    {0x12345678, 0x87654321},
+    {0x12345678, 0x87654321},
+    {0x12345678, 0x87654321},
+    {0x12345678, 0x87654321},
+    {0x12345678, 0x87654321},
+    {0x12345678, 0x87654321},
+    {0x12345678, 0x87654321},
+    {0x12345678, 0x87654321},
+    {0x12345678, 0x87654321}}};
+
 
 
 // TODO: Update with actual patterns from Luis Lastras when they are ready
@@ -494,54 +543,120 @@ static const uint8_t mss_65thByte[MSS_MAX_PATTERNS][4]={
 
 // bit1=tag0_2, bit2=tag1_3, bit3=MDI
 
-// PATTERN_0
+// PATTERN_0 - verified
    {0x00,   // 1st 64B of cachline: tag0=0, tag1=0, MDI=0
     0x00,   // 1st 64B of cachline: tag2=0, tag3=0, MDI=0
     0x00,   // 2nd 64B of cachline: tag0=0, tag1=0, MDI=0
     0x00},  // 2nd 64B of cachline: tag2=0, tag3=0, MDI=0
 
-// PATTERN_1
-   {0x70,   // 1st 64B of cachline: tag0=1, tag1=1, MDI=1
+// PATTERN_1 - verified
+   {0xF0,   // 1st 64B of cachline: tag0=1, tag1=1, MDI=1
     0x70,   // 1st 64B of cachline: tag2=1, tag3=1, MDI=1
-    0x70,   // 2nd 64B of cachline: tag0=1, tag1=1, MDI=1
+    0xF0,   // 2nd 64B of cachline: tag0=1, tag1=1, MDI=1
     0x70},  // 2nd 64B of cachline: tag2=1, tag3=1, MDI=1
 
-// PATTERN_2
+// PATTERN_2 - verified
    {0x70,   // 1st 64B of cachline: tag0=1, tag1=1, MDI=1
     0x00,   // 1st 64B of cachline: tag2=0, tag3=0, MDI=0
     0x70,   // 2nd 64B of cachline: tag0=1, tag1=1, MDI=1
     0x00},  // 2nd 64B of cachline: tag2=0, tag3=0, MDI=0
 
-// PATTERN_3
-   {0x00,   // 1st 64B of cachline: tag0=0, tag1=0, MDI=0
+// PATTERN_3 - verified
+   {0x80,   // 1st 64B of cachline: tag0=0, tag1=0, MDI=0
     0x70,   // 1st 64B of cachline: tag2=1, tag3=1, MDI=1
-    0x00,   // 2nd 64B of cachline: tag0=0, tag1=0, MDI=0
+    0x80,   // 2nd 64B of cachline: tag0=0, tag1=0, MDI=0
     0x70},  // 2nd 64B of cachline: tag2=1, tag3=1, MDI=1
 
-// PATTERN_4
-   {0x30,   // 1st 64B of cachline: tag0=0, tag1=1, MDI=1
-    0x50,   // 1st 64B of cachline: tag2=1, tag3=0, MDI=1
-    0x20,   // 2nd 64B of cachline: tag0=0, tag1=1, MDI=0
+// PATTERN_4 - verified
+   {0xB0,   // 1st 64B of cachline: tag0=0, tag1=1, MDI=1
+    0xD0,   // 1st 64B of cachline: tag2=1, tag3=0, MDI=1
+    0xA0,   // 2nd 64B of cachline: tag0=0, tag1=1, MDI=0
     0x40},  // 2nd 64B of cachline: tag2=1, tag3=0, MDI=0
 
-// PATTERN_5
-   {0x60,   // 1st 64B of cachline: tag0=1, tag1=0, MDI=0
+// PATTERN_5 - verified
+   {0xE0,   // 1st 64B of cachline: tag0=1, tag1=0, MDI=0
     0x20,   // 1st 64B of cachline: tag2=0, tag3=1, MDI=0
     0x50,   // 2nd 64B of cachline: tag0=1, tag1=0, MDI=1
     0x30},  // 2nd 64B of cachline: tag2=0, tag3=1, MDI=1
 
-// PATTERN_6
+// PATTERN_6 - verified
    {0x70,   // 1st 64B of cachline: tag0=1, tag1=1, MDI=1
-    0x40,   // 1st 64B of cachline: tag2=1, tag3=0, MDI=0
+    0xC0,   // 1st 64B of cachline: tag2=1, tag3=0, MDI=0
     0x60,   // 2nd 64B of cachline: tag0=1, tag1=1, MDI=0
     0x50},  // 2nd 64B of cachline: tag2=1, tag3=0, MDI=1
 
-// PATTERN_7
+// PATTERN_7 - verified
+   {0x20,   // 1st 64B of cachline: tag0=0, tag1=1, MDI=0
+    0x70,   // 1st 64B of cachline: tag2=1, tag3=1, MDI=1
+    0x30,   // 2nd 64B of cachline: tag0=0, tag1=1, MDI=1
+    0xE0},  // 2nd 64B of cachline: tag2=1, tag3=1, MDI=0
+
+// PATTERN_8: random seed
    {0x20,   // 1st 64B of cachline: tag0=0, tag1=1, MDI=0
     0x70,   // 1st 64B of cachline: tag2=1, tag3=1, MDI=1
     0x30,   // 2nd 64B of cachline: tag0=0, tag1=1, MDI=1
     0x60}}; // 2nd 64B of cachline: tag2=1, tag3=1, MDI=0
 
+// TODO: Update with actual patterns from Luis Lastras when they are ready
+static const uint32_t mss_ECC[MSS_MAX_PATTERNS][4]={
+
+// bit 4:15 ECC_c6_c5_c4, bit 16:31 ECC_c3_c2_c1_c0
+
+// PATTERN_0 - verified
+   {0x00000000,   // 1st 64B of cachline
+    0x00000000,   // 1st 64B of cachline
+    0x00000000,   // 2nd 64B of cachline
+    0x00000000},  // 2nd 64B of cachline
+
+// PATTERN_1 - verified
+   {0x0DA49500,   // 1st 64B of cachline
+    0x0234A60E,   // 1st 64B of cachline
+    0x0DA49500,   // 2nd 64B of cachline
+    0x0234A60E},  // 2nd 64B of cachline
+
+// PATTERN_2 - verified
+   {0x08A0AB54,   // 1st 64B of cachline
+    0x05CD9A13,   // 1st 64B of cachline
+    0x08A0AB54,   // 2nd 64B of cachline
+    0x05CD9A13},  // 2nd 64B of cachline
+
+// PATTERN_3 - verified
+   {0x05043E54,   // 1st 64B of cachline
+    0x07F93C1D,   // 1st 64B of cachline
+    0x05043E54,   // 2nd 64B of cachline
+    0x07F93C1D},  // 2nd 64B of cachline
+
+// PATTERN_4 - verified
+   {0x021C0F3D,   // 1st 64B of cachline
+    0x04332068,   // 1st 64B of cachline
+    0x0C33F1DA,   // 2nd 64B of cachline
+    0x0FF3F7AF},  // 2nd 64B of cachline
+
+// PATTERN_5 - verified
+   {0x04CA8334,   // 1st 64B of cachline
+    0x04F3D0DA,   // 1st 64B of cachline
+    0x019764DA,   // 2nd 64B of cachline
+    0x0DC751A1},  // 2nd 64B of cachline
+    
+// PATTERN_6 - verified
+   {0x0CF6B55C,   // 1st 64B of cachline
+    0x08CCE671,   // 1st 64B of cachline
+    0x02D94BBB,   // 2nd 64B of cachline
+    0x030C31B6},  // 2nd 64B of cachline
+    
+// PATTERN_7 - verified
+   {0x09150CD1,   // 1st 64B of cachline
+    0x0F9D48C9,   // 1st 64B of cachline
+    0x073AF236,   // 2nd 64B of cachline
+    0x045D9F0E},  // 2nd 64B of cachline
+    
+// PATTERN_8: random
+   {0x00000000,   // 1st 64B of cachline
+    0x00000000,   // 1st 64B of cachline
+    0x00000000,   // 2nd 64B of cachline
+    0x00000000}}; // 2nd 64B of cachline
+
+
 
 //------------------------------------------------------------------------------
 // Parent class
@@ -594,6 +709,7 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck()
     ecmdDataBufferBase l_mbaxcr(64);
     ecmdDataBufferBase l_ccs_modeq(64);
     ecmdDataBufferBase l_mbsecc(64);
+    ecmdDataBufferBase l_mbmct(64);
 
     FAPI_INF("ENTER mss_MaintCmd::preConditionCheck()");
 
@@ -632,13 +748,28 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck()
     // Read MBSECC
     l_rc = fapiGetScom(iv_targetCentaur, mss_mbsecc[iv_mbaPosition], l_mbsecc);
     if(l_rc) return l_rc;
-
+    
+    // Read MBMCT[0:4], cmd type, for FFDC
+    l_rc = fapiGetScom(iv_target, MBA01_MBMCTQ_0x0301060A, l_mbmct);
+    if(l_rc) return l_rc;
+    
 
     // Check for MBMCCQ[0], maint_cmd_start, to be reset by hw.
     if (l_mbmccq.isBitSet(0))
     {
+
+        FAPI_ERR("MBMCCQ[0]: maint_cmd_start not reset by hw.");
+         
+        // Calling out MBA target high, deconfig, gard
+        const fapi::Target & MBA = iv_target;
+        // FFDC: Capture register we are checking
+        ecmdDataBufferBase & MBMCC = l_mbmccq;
+        // FFDC: Capture command type we are trying to run
+        const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType;
+        // FFDC: MBMCT[0:4] contains the cmd type previously run
+        ecmdDataBufferBase & MBMCT = l_mbmct;  
+        
         // Create new log
-        FAPI_ERR("MCMCCQ[0]: maint_cmd_start not reset by hw.");
         FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_START_NOT_RESET);
     }
 
@@ -648,8 +779,18 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck()
         // Log previous error before creating new log
         if (l_rc) fapiLogError(l_rc);
 
+        FAPI_ERR("MBMCCQ[1]: maint_cmd_stop not reset by hw.");
+        
+        // Calling out MBA target high, deconfig, gard
+        const fapi::Target & MBA = iv_target;
+        // FFDC: Capture register we are checking
+        ecmdDataBufferBase & MBMCC = l_mbmccq;
+        // FFDC: Capture command type we are trying to run
+        const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType;
+        // FFDC: MBMCT[0:4] contains the cmd type previously run
+        ecmdDataBufferBase & MBMCT = l_mbmct;  
+        
         // Create new log
-        FAPI_ERR("MCMCCQ[1]: maint_cmd_stop not reset by hw.");
         FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_STOP_NOT_RESET);
     }
 
@@ -659,8 +800,19 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck()
         // Log previous error before creating new log
         if (l_rc) fapiLogError(l_rc);
 
-        // Create new log
         FAPI_ERR("MBMSRQ[0]: Can't start new cmd if previous cmd still in progress.");
+
+        // TODO: Calling out FW high
+        // Calling out MBA target low, deconfig, gard
+        const fapi::Target & MBA = iv_target;
+        // FFDC: Capture register we are checking
+        ecmdDataBufferBase & MBMSR = l_mbmsrq;
+        // FFDC: Capture command type we are trying to run
+        const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType;
+        // FFDC: MBMCT[0:4] contains the cmd type previously run
+        ecmdDataBufferBase & MBMCT = l_mbmct;  
+
+        // Create new log
         FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_CMD_IN_PROGRESS);
     }
 
@@ -670,8 +822,15 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck()
         // Log previous error before creating new log
         if (l_rc) fapiLogError(l_rc);
 
-        // Create new log
         FAPI_ERR("MBAXCRn[0:3] = 0, meaning no memory configured behind this MBA.");
+
+        // TODO: Calling out FW high
+        // FFDC: MBA target
+        const fapi::Target & MBA = iv_target;
+        // FFDC: Capture register we are checking
+        ecmdDataBufferBase & MBAXCR = l_mbaxcr;
+
+        // Create new log
         FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_NO_MEM_CNFG);
     }
 
@@ -681,8 +840,17 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck()
         // Log previous error before creating new log
         if (l_rc) fapiLogError(l_rc);
 
-        // Create new log
         FAPI_ERR("CCS_MODEQ[29] = 1, meaning mux set for CCS instead of mainline.");
+
+        // TODO: Calling out FW high
+        // FFDC: MBA target
+        const fapi::Target & MBA = iv_target;
+        // FFDC: Capture register we are checking
+        ecmdDataBufferBase & CCS_MODE = l_ccs_modeq;
+        // FFDC: Capture command type we are trying to run
+        const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType;
+
+        // Create new log
         FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_CCS_MUX_NOT_MAINLINE);
     }
 
@@ -692,8 +860,17 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck()
         // Log previous error before creating new log
         if (l_rc) fapiLogError(l_rc);
 
-        // Create new log
         FAPI_ERR("MBSECC[0] = 1, meaning ECC check/correct disabled.");
+
+        // TODO: Calling out FW high
+        // FFDC: MBA target
+        const fapi::Target & MBA = iv_target;
+        // FFDC: Capture register we are checking
+        ecmdDataBufferBase & MBSECC = l_mbsecc;
+        // FFDC: Capture command type we are trying to run
+        const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType;
+
+        // Create new log
         FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_ECC_DISABLED);
     }
 
@@ -844,7 +1021,7 @@ fapi::ReturnCode mss_MaintCmd::loadStopCondMask()
         l_ecmd_rc |= l_mbasctlq.setBit(6);
 
     // Stop on retry CE ETE
-    if ( 0 != (iv_stopCondition & STOP_ON_RETRY_CE) )
+    if ( 0 != (iv_stopCondition & STOP_ON_RETRY_CE_ETE) )
         l_ecmd_rc |= l_mbasctlq.setBit(7);
 
     // Stop on MPE
@@ -898,10 +1075,6 @@ fapi::ReturnCode mss_MaintCmd::startMaintCmd()
 
     FAPI_INF("ENTER mss_MaintCmd::startMaintCmd()");
 
-    // DEBUG - should be no special attentions before we start cmd
-    l_rc = fapiGetScom(iv_target, MBA01_MBSPAQ_0x03010611, l_data);
-    if(l_rc) return l_rc;
-
     l_rc = fapiGetScom(iv_target, MBA01_MBMCCQ_0x0301060B, l_data);
     if(l_rc) return l_rc;
 
@@ -926,7 +1099,8 @@ fapi::ReturnCode mss_MaintCmd::postConditionCheck()
     fapi::ReturnCode l_rc;
     ecmdDataBufferBase l_mbmccq(64);
     ecmdDataBufferBase l_mbafirq(64);
-
+    ecmdDataBufferBase l_mbmct(64);
+    
     FAPI_INF("ENTER mss_MaintCmd::postConditionCheck()");
 
     // Read MBMCCQ
@@ -937,11 +1111,25 @@ fapi::ReturnCode mss_MaintCmd::postConditionCheck()
     l_rc = fapiGetScom(iv_target, MBA01_MBAFIRQ_0x03010600, l_mbafirq);
     if(l_rc) return l_rc;
     
+    // Read MBMCT[0:4], cmd type, for FFDC
+    l_rc = fapiGetScom(iv_target, MBA01_MBMCTQ_0x0301060A, l_mbmct);
+    if(l_rc) return l_rc;    
+    
     // Check for MBMCCQ[0], maint_cmd_start, to be reset by hw.
     if (l_mbmccq.isBitSet(0))
     {
+        FAPI_ERR("MBMCCQ[0]: maint_cmd_start not reset by hw.");
+        
+        // Calling out MBA target high, deconfig, gard
+        const fapi::Target & MBA = iv_target;
+        // FFDC: Capture register we are checking
+        ecmdDataBufferBase & MBMCC = l_mbmccq;
+        // FFDC: Capture command type we are trying to run
+        const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType;
+        // FFDC: MBMCT[0:4] contains the cmd type set in hw
+        ecmdDataBufferBase & MBMCT = l_mbmct;  
+        
         // Create new log
-        FAPI_ERR("MCMCCQ[0]: maint_cmd_start not reset by hw.");
         FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_START_NOT_RESET);
     }
 
@@ -951,8 +1139,19 @@ fapi::ReturnCode mss_MaintCmd::postConditionCheck()
         // Log previous error before creating new log
         if (l_rc) fapiLogError(l_rc);
 
-        // Create new log
         FAPI_ERR("MBAFIRQ[0], invalid_maint_cmd.");
+        
+        // TODO: Calling out FW high
+        // FFDC: MBA target
+        const fapi::Target & MBA = iv_target;
+        // FFDC: Capture register we are checking
+        ecmdDataBufferBase & MBAFIR = l_mbafirq;
+        // FFDC: Capture command type we are trying to run
+        const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType;
+        // FFDC: MBMCT[0:4] contains the cmd type set in hw
+        ecmdDataBufferBase & MBMCT = l_mbmct;  
+        
+        // Create new log        
         FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_CMD);
     }
 
@@ -962,8 +1161,20 @@ fapi::ReturnCode mss_MaintCmd::postConditionCheck()
         // Log previous error before creating new log
         if (l_rc) fapiLogError(l_rc);
 
-        // Create new log
         FAPI_ERR("MBAFIRQ[1], cmd started with invalid_maint_address.");
+
+        // TODO: Calling out FW high
+        // FFDC: MBA target
+        const fapi::Target & MBA = iv_target;
+        // FFDC: Capture register we are checking
+        ecmdDataBufferBase & MBAFIR = l_mbafirq;
+        // FFDC: Capture command type we are trying to run
+        const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType;
+        // FFDC: MBMCT[0:4] contains the cmd type set in hw
+        ecmdDataBufferBase & MBMCT = l_mbmct;
+        // NOTE: List of additional FFDC regs specified in memory_errors.xml        
+        
+        // Create new log
         FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_ADDR);
     }
 
@@ -1019,9 +1230,19 @@ fapi::ReturnCode mss_MaintCmd::pollForMaintCmdComplete()
 
     if (count == loop_limit)
     {
-        // Create new log
         FAPI_ERR("Maint cmd timeout.");
-        FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_CMD_TIMEOUT);
+        
+        // TODO: Calling out FW high
+        // Calling out MBA target low, deconfig, gard
+        const fapi::Target & MBA = iv_target;
+        // FFDC: Capture command type we are trying to run
+        const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType;
+        // Specify CENTAUR target so we can read some FFDC regs from MBS
+        const fapi::Target & CENTAUR = iv_targetCentaur;
+        // NOTE: List of additional FFDC regs specified in memory_errors.xml        
+
+        // Create new log
+        FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_CMD_TIMEOUT);        
     }
     else
     {
@@ -1156,39 +1377,44 @@ fapi::ReturnCode mss_MaintCmd::loadPattern(PatternIndex i_initPattern)
     FAPI_INF("ENTER mss_MaintCmd::loadPattern()");
 
     static const uint32_t maintBufferDataRegs[2][16][2]={
-    // port0/1
+    // port0
    {{MAINT0_MBS_MAINT_BUFF0_DATA0_0x0201160A, MAINT0_MBS_MAINT_BUFF0_DATA_ECC0_0x02011612},
-    {MAINT0_MBS_MAINT_BUFF0_DATA1_0x0201160B, MAINT0_MBS_MAINT_BUFF0_DATA_ECC1_0x02011613},
-    {MAINT0_MBS_MAINT_BUFF0_DATA2_0x0201160C, MAINT0_MBS_MAINT_BUFF0_DATA_ECC2_0x02011614},
-    {MAINT0_MBS_MAINT_BUFF0_DATA3_0x0201160D, MAINT0_MBS_MAINT_BUFF0_DATA_ECC3_0x02011615},
-    {MAINT0_MBS_MAINT_BUFF1_DATA0_0x0201161A, MAINT0_MBS_MAINT_BUFF1_DATA_ECC0_0x02011622},
-    {MAINT0_MBS_MAINT_BUFF1_DATA1_0x0201161B, MAINT0_MBS_MAINT_BUFF1_DATA_ECC1_0x02011623},
-    {MAINT0_MBS_MAINT_BUFF1_DATA2_0x0201161C, MAINT0_MBS_MAINT_BUFF1_DATA_ECC2_0x02011624},
-    {MAINT0_MBS_MAINT_BUFF1_DATA3_0x0201161D, MAINT0_MBS_MAINT_BUFF1_DATA_ECC3_0x02011625},
     {MAINT0_MBS_MAINT_BUFF2_DATA0_0x0201162A, MAINT0_MBS_MAINT_BUFF2_DATA_ECC0_0x02011632},
+    {MAINT0_MBS_MAINT_BUFF0_DATA1_0x0201160B, MAINT0_MBS_MAINT_BUFF0_DATA_ECC1_0x02011613},
     {MAINT0_MBS_MAINT_BUFF2_DATA1_0x0201162B, MAINT0_MBS_MAINT_BUFF2_DATA_ECC1_0x02011633},
+    {MAINT0_MBS_MAINT_BUFF0_DATA2_0x0201160C, MAINT0_MBS_MAINT_BUFF0_DATA_ECC2_0x02011614},
     {MAINT0_MBS_MAINT_BUFF2_DATA2_0x0201162C, MAINT0_MBS_MAINT_BUFF2_DATA_ECC2_0x02011634},
+    {MAINT0_MBS_MAINT_BUFF0_DATA3_0x0201160D, MAINT0_MBS_MAINT_BUFF0_DATA_ECC3_0x02011615},
     {MAINT0_MBS_MAINT_BUFF2_DATA3_0x0201162D, MAINT0_MBS_MAINT_BUFF2_DATA_ECC3_0x02011635},
+
+    // port1
+    {MAINT0_MBS_MAINT_BUFF1_DATA0_0x0201161A, MAINT0_MBS_MAINT_BUFF1_DATA_ECC0_0x02011622},
     {MAINT0_MBS_MAINT_BUFF3_DATA0_0x0201163A, MAINT0_MBS_MAINT_BUFF3_DATA_ECC0_0x02011642},
+    {MAINT0_MBS_MAINT_BUFF1_DATA1_0x0201161B, MAINT0_MBS_MAINT_BUFF1_DATA_ECC1_0x02011623},
     {MAINT0_MBS_MAINT_BUFF3_DATA1_0x0201163B, MAINT0_MBS_MAINT_BUFF3_DATA_ECC1_0x02011643},
+    {MAINT0_MBS_MAINT_BUFF1_DATA2_0x0201161C, MAINT0_MBS_MAINT_BUFF1_DATA_ECC2_0x02011624},
     {MAINT0_MBS_MAINT_BUFF3_DATA2_0x0201163C, MAINT0_MBS_MAINT_BUFF3_DATA_ECC2_0x02011644},
+    {MAINT0_MBS_MAINT_BUFF1_DATA3_0x0201161D, MAINT0_MBS_MAINT_BUFF1_DATA_ECC3_0x02011625},
     {MAINT0_MBS_MAINT_BUFF3_DATA3_0x0201163D, MAINT0_MBS_MAINT_BUFF3_DATA_ECC3_0x02011645}},
-    // port2/3
+
+    // port2
    {{MAINT1_MBS_MAINT_BUFF0_DATA0_0x0201170A, MAINT1_MBS_MAINT_BUFF0_DATA_ECC0_0x02011712},
-    {MAINT1_MBS_MAINT_BUFF0_DATA1_0x0201170B, MAINT1_MBS_MAINT_BUFF0_DATA_ECC1_0x02011713},
-    {MAINT1_MBS_MAINT_BUFF0_DATA2_0x0201170C, MAINT1_MBS_MAINT_BUFF0_DATA_ECC2_0x02011714},
-    {MAINT1_MBS_MAINT_BUFF0_DATA3_0x0201170D, MAINT1_MBS_MAINT_BUFF0_DATA_ECC3_0x02011715},
-    {MAINT1_MBS_MAINT_BUFF1_DATA0_0x0201171A, MAINT1_MBS_MAINT_BUFF1_DATA_ECC0_0x02011722},
-    {MAINT1_MBS_MAINT_BUFF1_DATA1_0x0201171B, MAINT1_MBS_MAINT_BUFF1_DATA_ECC1_0x02011723},
-    {MAINT1_MBS_MAINT_BUFF1_DATA2_0x0201171C, MAINT1_MBS_MAINT_BUFF1_DATA_ECC2_0x02011724},
-    {MAINT1_MBS_MAINT_BUFF1_DATA3_0x0201171D, MAINT1_MBS_MAINT_BUFF1_DATA_ECC3_0x02011725},
     {MAINT1_MBS_MAINT_BUFF2_DATA0_0x0201172A, MAINT1_MBS_MAINT_BUFF2_DATA_ECC0_0x02011732},
+    {MAINT1_MBS_MAINT_BUFF0_DATA1_0x0201170B, MAINT1_MBS_MAINT_BUFF0_DATA_ECC1_0x02011713},
     {MAINT1_MBS_MAINT_BUFF2_DATA1_0x0201172B, MAINT1_MBS_MAINT_BUFF2_DATA_ECC1_0x02011733},
+    {MAINT1_MBS_MAINT_BUFF0_DATA2_0x0201170C, MAINT1_MBS_MAINT_BUFF0_DATA_ECC2_0x02011714},
     {MAINT1_MBS_MAINT_BUFF2_DATA2_0x0201172C, MAINT1_MBS_MAINT_BUFF2_DATA_ECC2_0x02011734},
+    {MAINT1_MBS_MAINT_BUFF0_DATA3_0x0201170D, MAINT1_MBS_MAINT_BUFF0_DATA_ECC3_0x02011715},
     {MAINT1_MBS_MAINT_BUFF2_DATA3_0x0201172D, MAINT1_MBS_MAINT_BUFF2_DATA_ECC3_0x02011735},
+
+    // port3
+    {MAINT1_MBS_MAINT_BUFF1_DATA0_0x0201171A, MAINT1_MBS_MAINT_BUFF1_DATA_ECC0_0x02011722},
     {MAINT1_MBS_MAINT_BUFF3_DATA0_0x0201173A, MAINT1_MBS_MAINT_BUFF3_DATA_ECC0_0x02011742},
+    {MAINT1_MBS_MAINT_BUFF1_DATA1_0x0201171B, MAINT1_MBS_MAINT_BUFF1_DATA_ECC1_0x02011723},
     {MAINT1_MBS_MAINT_BUFF3_DATA1_0x0201173B, MAINT1_MBS_MAINT_BUFF3_DATA_ECC1_0x02011743},
+    {MAINT1_MBS_MAINT_BUFF1_DATA2_0x0201171C, MAINT1_MBS_MAINT_BUFF1_DATA_ECC2_0x02011724},
     {MAINT1_MBS_MAINT_BUFF3_DATA2_0x0201173C, MAINT1_MBS_MAINT_BUFF3_DATA_ECC2_0x02011744},
+    {MAINT1_MBS_MAINT_BUFF1_DATA3_0x0201171D, MAINT1_MBS_MAINT_BUFF1_DATA_ECC3_0x02011725},
     {MAINT1_MBS_MAINT_BUFF3_DATA3_0x0201173D, MAINT1_MBS_MAINT_BUFF3_DATA_ECC3_0x02011745}}};
 
 
@@ -1204,6 +1430,8 @@ fapi::ReturnCode mss_MaintCmd::loadPattern(PatternIndex i_initPattern)
     ecmdDataBufferBase l_data(64);
     ecmdDataBufferBase l_ecc(64);
     ecmdDataBufferBase l_65th(64);
+    ecmdDataBufferBase l_mbmmr(64);
+    ecmdDataBufferBase l_mbsecc(64);
     uint32_t loop = 0;
 
     FAPI_INF("pattern = 0x%.8X 0x%.8X",
@@ -1213,16 +1441,22 @@ fapi::ReturnCode mss_MaintCmd::loadPattern(PatternIndex i_initPattern)
     //----------------------------------------------------
     // Load the data: 16 loops x 64bits = 128B cacheline
     //----------------------------------------------------
+    FAPI_INF("Load the data: 16 loops x 64bits = 128B cacheline");
 
     // Set bit 9 so that hw will generate the fabric ECC.
     // This is an 8B ECC protecting the data moving on internal buses in
     // the Centaur.
     l_ecmd_rc |= l_ecc.flushTo0();
     l_ecmd_rc |= l_ecc.setBit(9);
+    if(l_ecmd_rc)
+    {
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }
 
     for(loop=0; loop<16; loop++ )
     {
-        // A write to MAINT_BUFFx_DATAy will not update until the corresponding
+        // A write to MAINT_BUFFx_DATAy will not update until the corresponding 
         // MAINT_BUFFx_DATA_ECCy is written to.
         l_ecmd_rc |= l_data.insert(mss_maintBufferData[i_initPattern][loop][0], 0, 32, 0);
         l_ecmd_rc |= l_data.insert(mss_maintBufferData[i_initPattern][loop][1], 32, 32, 0);
@@ -1232,7 +1466,7 @@ fapi::ReturnCode mss_MaintCmd::loadPattern(PatternIndex i_initPattern)
             return l_rc;
         }
         l_rc = fapiPutScom(iv_targetCentaur, maintBufferDataRegs[iv_mbaPosition][loop][0], l_data);
-        if(l_rc) return l_rc;
+        if(l_rc) return l_rc;   
 
         l_rc = fapiPutScom(iv_targetCentaur, maintBufferDataRegs[iv_mbaPosition][loop][1], l_ecc);
         if(l_rc) return l_rc;
@@ -1241,6 +1475,7 @@ fapi::ReturnCode mss_MaintCmd::loadPattern(PatternIndex i_initPattern)
     //----------------------------------------------------
     // Load the 65th byte: 4 loops to fill in the two 65th bytes in cacheline
     //----------------------------------------------------
+    FAPI_INF("Load the 65th byte: 4 loops to fill in the two 65th bytes in the cacheline");
 
     l_ecmd_rc |= l_65th.flushTo0();
 
@@ -1264,7 +1499,40 @@ fapi::ReturnCode mss_MaintCmd::loadPattern(PatternIndex i_initPattern)
 
         l_rc = fapiPutScom(iv_targetCentaur, maintBuffer65thRegs[loop][iv_mbaPosition], l_65th);
         if(l_rc) return l_rc;
+    }  
+
+    //----------------------------------------------------
+    // Save i_initPattern in unused maint mark reg
+    // so we know what pattern was used when we do 
+    // UE isolation
+    //----------------------------------------------------
+
+    // No plans to use maint mark, but make sure it's disabled to be safe
+    l_rc = fapiGetScom(iv_targetCentaur, mss_mbsecc[iv_mbaPosition], l_mbsecc);
+    if(l_rc) return l_rc;
+    l_ecmd_rc |= l_mbsecc.clearBit(4);
+    if(l_ecmd_rc)
+    {
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
     }
+    l_rc = fapiPutScom(iv_targetCentaur, mss_mbsecc[iv_mbaPosition], l_mbsecc);
+    if(l_rc) return l_rc;
+
+
+    l_ecmd_rc |= l_mbmmr.flushTo0();
+    // Store i_initPattern, with range 0-8, in MBMMR bits 4-7
+    l_ecmd_rc |= l_mbmmr.insert((uint8_t)i_initPattern, 4, 4, 8-4);
+    if(l_ecmd_rc)
+    {
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }
+    l_rc = fapiPutScom(iv_targetCentaur, mss_mbmmr[iv_mbaPosition] , l_mbmmr);
+    if(l_rc) return l_rc;
+
+
+
 
     FAPI_INF("EXIT mss_MaintCmd::loadPattern()");
 
@@ -1356,7 +1624,18 @@ fapi::ReturnCode mss_MaintCmd::loadSpeed(TimeBaseSpeed i_speed)
         // Make sure it's non-zero, to avoid divide by 0
         if (l_ddr_freq == 0)
         {
-            FAPI_SET_HWP_ERROR(l_rc, RC_MSS_UNSUPPORTED_FREQ_CALCULATED);
+            FAPI_ERR("ATTR_MSS_FREQ set to zero so can't calculate scrub rate.");
+                        
+            // TODO: Calling out FW high
+            // FFDC: MBA target
+            const fapi::Target & MBA = iv_target;
+            // FFDC: Capture l_ddr_freq
+            uint32_t DDR_FREQ = l_ddr_freq;
+            // FFDC: Capture command type we are trying to run
+            const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType;
+
+            // Create new log            
+            FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_ZERO_DDR_FREQ);
             return l_rc;
         }
         
@@ -1831,6 +2110,9 @@ fapi::ReturnCode mss_SuperFastRead::setupAndExecuteCmd()
     // Make sure maint logic in valid state to run new cmd
     l_rc = preConditionCheck(); if(l_rc) return l_rc;
 
+    // Setup required to trap UE actual data needed for IPL UE isolation
+    l_rc = ueTrappingSetup(); if(l_rc) return l_rc;
+
     // Load cmd type: MBMCTQ
     l_rc = loadCmdType(); if(l_rc) return l_rc;
 
@@ -1905,6 +2187,70 @@ fapi::ReturnCode mss_SuperFastRead::setupAndExecuteCmd()
 
 }
 
+fapi::ReturnCode mss_SuperFastRead::ueTrappingSetup()
+{
+
+    FAPI_INF("ENTER mss_SuperFastRead::ueTrappingSetup()");
+
+    fapi::ReturnCode l_rc;
+
+    static const uint32_t maintBufferDataRegs[2][2][2]={
+    // port0/1
+    {{MAINT0_MBS_MAINT_BUFF0_DATA0_0x0201160A, MAINT0_MBS_MAINT_BUFF0_DATA_ECC0_0x02011612},
+     {MAINT0_MBS_MAINT_BUFF0_DATA4_0x0201160E, MAINT0_MBS_MAINT_BUFF0_DATA_ECC4_0x02011616}},
+    // port2/3
+    {{MAINT1_MBS_MAINT_BUFF0_DATA0_0x0201170A, MAINT1_MBS_MAINT_BUFF0_DATA_ECC0_0x02011712},
+     {MAINT1_MBS_MAINT_BUFF0_DATA4_0x0201170E, MAINT1_MBS_MAINT_BUFF0_DATA_ECC4_0x02011716}}};
+
+    uint32_t l_ecmd_rc = 0;
+    ecmdDataBufferBase l_data(64);
+    ecmdDataBufferBase l_ecc(64);
+    ecmdDataBufferBase l_mbstr(64);
+    uint32_t loop = 0;
+
+    // Set bit 9 so that hw will generate the fabric ECC.
+    // This is an 8B ECC protecting the data moving on internal buses in
+    // the Centaur.
+    l_ecmd_rc |= l_ecc.flushTo0();
+    l_ecmd_rc |= l_ecc.setBit(9);
+
+
+    for(loop=0; loop<2; loop++ )
+    {
+        // Load unique pattern into both halves of the maint buffer,
+        // so we can tell which half contains a trapped UE.
+        l_ecmd_rc |= l_data.insert(0xFACEB00C, 0, 32, 0);
+        l_ecmd_rc |= l_data.insert(0xD15C0DAD, 32, 32, 0);
+        if(l_ecmd_rc)
+        {
+            l_rc.setEcmdError(l_ecmd_rc);
+            return l_rc;
+        }
+        l_rc = fapiPutScom(iv_targetCentaur, maintBufferDataRegs[iv_mbaPosition][loop][0], l_data);
+        if(l_rc) return l_rc;
+
+        // A write to MAINT_BUFFx_DATAy will not update until the corresponding
+        // MAINT_BUFFx_DATA_ECCy is written to.
+        l_rc = fapiPutScom(iv_targetCentaur, maintBufferDataRegs[iv_mbaPosition][loop][1], l_ecc);
+        if(l_rc) return l_rc;
+    }
+
+
+    // Enable UE trapping
+    l_rc = fapiGetScom(iv_targetCentaur, mss_mbstr[iv_mbaPosition], l_mbstr);
+    if(l_rc) return l_rc;
+    l_mbstr.setBit(59);
+    l_rc = fapiPutScom(iv_targetCentaur, mss_mbstr[iv_mbaPosition], l_mbstr);
+    if(l_rc) return l_rc;
+
+
+    FAPI_INF("EXIT mss_SuperFastRead::ueTrappingSetup()");
+
+    return l_rc;
+}
+
+
+
 fapi::ReturnCode mss_SuperFastRead::stopCmd()
 {
 
@@ -1930,6 +2276,7 @@ fapi::ReturnCode mss_SuperFastRead::cleanupCmd()
     FAPI_INF("ENTER mss_SuperFastRead::cleanupCmd()");
 
     fapi::ReturnCode l_rc;
+    ecmdDataBufferBase l_mbstr(64);
 
     // Clear maintenance command complete attention, scrub stats, etc...
 
@@ -1940,8 +2287,16 @@ fapi::ReturnCode mss_SuperFastRead::cleanupCmd()
     l_rc = fapiPutScom(iv_target, MBA01_MBA_RRQ0Q_0x0301040E, iv_saved_MBA_RRQ0);
     if(l_rc) return l_rc;
 
-    FAPI_INF("EXIT mss_SuperFastRead::cleanupCmd()");
+    // Disable UE trapping
+    l_rc = fapiGetScom(iv_targetCentaur, mss_mbstr[iv_mbaPosition], l_mbstr);
+    if(l_rc) return l_rc;
+    l_mbstr.clearBit(59);
+    l_rc = fapiPutScom(iv_targetCentaur, mss_mbstr[iv_mbaPosition], l_mbstr);
+    if(l_rc) return l_rc;
 
+
+    FAPI_INF("EXIT mss_SuperFastRead::cleanupCmd()");
+    
     return l_rc;
 }
 
@@ -2165,6 +2520,7 @@ fapi::ReturnCode mss_Display::setupAndExecuteCmd()
     {
         l_rc = fapiGetScom(iv_target, maintBufferReadDataRegs[loop], l_data);
         if(l_rc) return l_rc;
+        FAPI_INF("0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1));
     }
 
     //----------------------------------------------------
@@ -2176,6 +2532,7 @@ fapi::ReturnCode mss_Display::setupAndExecuteCmd()
     {
         l_rc = fapiGetScom(iv_target, maintBufferRead65thByteRegs[loop], l_data);
         if(l_rc) return l_rc;
+        FAPI_INF("0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1));
     }
 
     // Collect FFDC
@@ -2636,8 +2993,15 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target,
     if(l_rc) return l_rc;
     if (l_data.isBitClear(0,4))
     {
-        // Create new log.
         FAPI_ERR("MBAXCRn[0:3] = 0, meaning no memory configured behind this MBA.");
+
+        // TODO: Calling out FW high
+        // FFDC: MBA target
+        const fapi::Target & MBA = i_target;
+        // FFDC: Capture register we are checking
+        ecmdDataBufferBase & MBAXCR = l_data;
+
+        // Create new log.
         FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_NO_MEM_CNFG);
         return l_rc;
     }
@@ -2704,8 +3068,15 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target,
     }
     else
     {
-        // Create new log. 
         FAPI_ERR("Invalid l_dramSize = %d or l_dramWidth = %d in MBAXCRn.", l_dramSize, l_dramWidth );
+
+        // TODO: Calling out FW high
+        // FFDC: MBA target
+        const fapi::Target & MBA = i_target;
+        // FFDC: Capture register we are checking
+        ecmdDataBufferBase & MBAXCR = l_data;
+        
+        // Create new log.        
         FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_DRAM_SIZE_WIDTH);
         return l_rc;
     }
@@ -2742,8 +3113,15 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target,
 
     if ((l_end_master_rank == 0x0f) || (l_end_slave_rank == 0x0f))
     {
-        // Create new log.
         FAPI_ERR("MBAXCRn configured with unsupported combination of l_configType, l_configSubType, l_slotConfig");
+
+        // TODO: Calling out FW high
+        // FFDC: MBA target
+        const fapi::Target & MBA = i_target;
+        // FFDC: Capture register we are checking
+        ecmdDataBufferBase & MBAXCR = l_data;
+
+        // Create new log.
         FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_DIMM_CNFG);
         return l_rc;
     }
@@ -2986,9 +3364,20 @@ fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target,
     }
     else if (l_dramWidth == mss_MemConfig::X4)
     {
-        // Create new log. 
         FAPI_ERR("l_symbolMarkGalois invalid: symbol mark not allowed in x4 mode.");
-        FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_NO_X4_SYMBOL);
+
+        // TODO: Calling out FW high
+        // FFDC: MBA target
+        const fapi::Target & MBA = i_target;
+        // FFDC: DRAM width
+        uint8_t DRAM_WIDTH = l_dramWidth;
+        // FFDC: Capure i_rank;
+        uint8_t RANK = i_rank;
+        // FFDC: Capture markstore
+        ecmdDataBufferBase & MARKSTORE = l_markstore;
+
+        // Create new log.
+        FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_X4_SYMBOL_ON_READ);
         return l_rc;
     }
     else // Converted from galois field to symbol index
@@ -3005,8 +3394,19 @@ fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target,
 
         if ( MSS_SYMBOLS_PER_RANK <= o_symbolMark )
         {
-            // Create new log. 
             FAPI_ERR("Invalid galois field in markstore.");
+
+            // TODO: Calling out FW high
+            // FFDC: MBA target
+            const fapi::Target & MBA = i_target;
+            // FFDC: DRAM width
+            uint8_t DRAM_WIDTH = l_dramWidth;
+            // FFDC: Capure i_rank;
+            uint8_t RANK = i_rank;
+            // FFDC: Capture markstore
+            ecmdDataBufferBase & MARKSTORE = l_markstore;
+
+            // Create new log. 
             FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_MARKSTORE);
             return l_rc;
         }
@@ -3049,8 +3449,19 @@ fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target,
 
         if ( MSS_SYMBOLS_PER_RANK <= o_chipMark )
         {
-            // Create new log. 
             FAPI_ERR("Invalid galois field in markstore.");
+
+            // TODO: Calling out FW high
+            // FFDC: MBA target
+            const fapi::Target & MBA = i_target;
+            // FFDC: DRAM width
+            uint8_t DRAM_WIDTH = l_dramWidth;
+            // FFDC: Capure i_rank;
+            uint8_t RANK = i_rank;
+            // FFDC: Capture markstore
+            ecmdDataBufferBase & MARKSTORE = l_markstore;
+
+            // Create new log. 
             FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_MARKSTORE);
             return l_rc;
         }
@@ -3120,15 +3531,41 @@ fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target,
     }
     else if ( l_dramWidth == mss_MemConfig::X4 )
     {
-        // Create new log.
         FAPI_ERR("i_symbolMark invalid: symbol mark not allowed in x4 mode.");
-        FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_NO_X4_SYMBOL);
+
+        // TODO: Calling out FW high
+        // FFDC: MBA target
+        const fapi::Target & MBA = i_target;
+        // FFDC: DRAM width
+        uint8_t DRAM_WIDTH = l_dramWidth;
+        // FFDC: Capure i_rank;
+        uint8_t RANK = i_rank;
+        // FFDC: Capure i_symbolMark;
+        uint8_t SYMBOL_MARK = i_symbolMark;
+        // FFDC: Capure i_chipMark;
+        uint8_t CHIP_MARK = i_chipMark;
+
+        // Create new log.
+        FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_X4_SYMBOL_ON_WRITE);
         return l_rc;
     }
     else if ( MSS_SYMBOLS_PER_RANK <= i_symbolMark )
     {
-        // Create new log.
         FAPI_ERR("i_symbolMark invalid: symbol index out of range.");
+
+        // TODO: Calling out FW high
+        // FFDC: MBA target
+        const fapi::Target & MBA = i_target;
+        // FFDC: DRAM width
+        uint8_t DRAM_WIDTH = l_dramWidth;
+        // FFDC: Capure i_rank;
+        uint8_t RANK = i_rank;
+        // FFDC: Capure i_symbolMark;
+        uint8_t SYMBOL_MARK = i_symbolMark;
+        // FFDC: Capure i_chipMark;
+        uint8_t CHIP_MARK = i_chipMark;
+
+        // Create new log.
         FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_INDEX);
         return l_rc;
     }
@@ -3142,29 +3579,68 @@ fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target,
     // Get l_chipMarkGalois
     if (i_chipMark == MSS_INVALID_SYMBOL) // No chip mark
     {
-    l_chipMarkGalois = 0x00;
+        l_chipMarkGalois = 0x00;
     }
     else if ( MSS_SYMBOLS_PER_RANK <= i_chipMark )
     {
-        // Create new log. 
         FAPI_ERR("i_chipMark invalid: symbol index out of range.");
+
+        // TODO: Calling out FW high
+        // FFDC: MBA target
+        const fapi::Target & MBA = i_target;
+        // FFDC: DRAM width
+        uint8_t DRAM_WIDTH = l_dramWidth;
+        // FFDC: Capure i_rank;
+        uint8_t RANK = i_rank;
+        // FFDC: Capure i_symbolMark;
+        uint8_t SYMBOL_MARK = i_symbolMark;
+        // FFDC: Capure i_chipMark;
+        uint8_t CHIP_MARK = i_chipMark;
+
+        // Create new log. 
         FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_INDEX);
         return l_rc;
     }
     else if ((l_dramWidth == mss_MemConfig::X8) && (i_chipMark % 4) )
     {
-        // Create new log.
         FAPI_ERR("i_chipMark invalid: not first symbol index of a x8 chip.");
+
+        // TODO: Calling out FW high
+        // FFDC: MBA target
+        const fapi::Target & MBA = i_target;
+        // FFDC: DRAM width
+        uint8_t DRAM_WIDTH = l_dramWidth;
+        // FFDC: Capure i_rank;
+        uint8_t RANK = i_rank;
+        // FFDC: Capure i_symbolMark;
+        uint8_t SYMBOL_MARK = i_symbolMark;
+        // FFDC: Capure i_chipMark;
+        uint8_t CHIP_MARK = i_chipMark;
+
+        // Create new log.
         FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_CHIP_INDEX);
         return l_rc;
 
     }
     else if ((l_dramWidth == mss_MemConfig::X4) && (i_chipMark % 2) )
     {
-        // Create new log.
         FAPI_ERR("i_chipMark invalid: not first symbol index of a x4 chip.");
+
+        // TODO: Calling out FW high
+        // FFDC: MBA target
+        const fapi::Target & MBA = i_target;
+        // FFDC: DRAM width
+        uint8_t DRAM_WIDTH = l_dramWidth;
+        // FFDC: Capure i_rank;
+        uint8_t RANK = i_rank;
+        // FFDC: Capure i_symbolMark;
+        uint8_t SYMBOL_MARK = i_symbolMark;
+        // FFDC: Capure i_chipMark;
+        uint8_t CHIP_MARK = i_chipMark;
+
+        // Create new log.
         FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_CHIP_INDEX);
-           return l_rc;
+        return l_rc;
     }
     else // Convert from symbol index to galois field
     {
@@ -3181,15 +3657,32 @@ fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target,
     l_rc = fapiPutScom(l_targetCentaur, mss_markStoreRegs[i_rank][l_mbaPosition], l_markstore);
     if(l_rc) return l_rc;
 
-    // If MPE FIR for the given rank (scrub or fetch) is on after the read,
-    // we will return TBD fapi::ReturnCode to indicate write may not have worked.
+    // If MPE FIR for the given rank (scrub or fetch) is on after the write,
+    // we will return a fapi::ReturnCode to indicate write may not have worked.
     // Up to caller to read again if they want to see what new chip mark is.
     l_rc = fapiGetScom(l_targetCentaur, mss_mbeccfir[l_mbaPosition], l_mbeccfir);
     if(l_rc) return l_rc;
     if (l_mbeccfir.isBitSet(i_rank) || l_mbeccfir.isBitSet(20 + i_rank))
     {
-        // Create new log.
+        // TODO: Can FW distingish this rc from all the others
+        // so they know they just need to retry after clearing MPR FIR?
+        
         FAPI_ERR("Markstore write may have been blocked due to MPE FIR set.");
+
+        // FFDC: MBA target
+        const fapi::Target & MBA = i_target;
+        // FFDC: DRAM width
+        uint8_t DRAM_WIDTH = l_dramWidth;
+        // FFDC: Capure i_rank;
+        uint8_t RANK = i_rank;
+        // FFDC: Capure i_symbolMark;
+        uint8_t SYMBOL_MARK = i_symbolMark;
+        // FFDC: Capure i_chipMark;
+        uint8_t CHIP_MARK = i_chipMark;
+        // FFDC: Capture MBECCFIR
+        ecmdDataBufferBase & MBECCFIR = l_mbeccfir;
+        
+        // Create new log.
         FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_MARKSTORE_WRITE_BLOCKED);
         return l_rc;
     }
@@ -3286,9 +3779,23 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target,
     }
     else
     {
-        FAPI_ERR("l_dramSparePort0Index out of range.");
-        // Caller needs to recognize a symbol value of 0xfe as invalid.
-        o_dramSparePort0Symbol = 0xfe;
+        FAPI_ERR("Steer mux l_dramSparePort0Index out of range.");
+        
+        // TODO: Calling out FW high
+        // FFDC: MBA target
+        const fapi::Target & MBA = i_target;
+        // FFDC: DRAM width
+        uint8_t DRAM_WIDTH = l_dramWidth;
+        // FFDC: Capure i_rank;
+        uint8_t RANK = i_rank;
+        // FFDC: Capure i_muxType
+        uint8_t MUX_TYPE = i_muxType;       
+        // FFDC: Capture steer mux
+        ecmdDataBufferBase & STEER_MUX = l_steerMux;
+
+        // Create new log. 
+        FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_STEER_MUX);
+        return l_rc;        
     }
 
 
@@ -3312,9 +3819,23 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target,
     }
     else
     {
-        FAPI_ERR("l_dramSparePort1Index out of range.");
-        // Caller needs to recognize a symbol value of 0xfe as invalid.
-        o_dramSparePort1Symbol = 0xfe;
+        FAPI_ERR("Steer mux l_dramSparePort1Index out of range.");
+        
+        // TODO: Calling out FW high
+        // FFDC: MBA target
+        const fapi::Target & MBA = i_target;
+        // FFDC: DRAM width
+        uint8_t DRAM_WIDTH = l_dramWidth;
+        // FFDC: Capure i_rank;
+        uint8_t RANK = i_rank;
+        // FFDC: Capure i_muxType
+        uint8_t MUX_TYPE = i_muxType;       
+        // FFDC: Capture steer mux
+        ecmdDataBufferBase & STEER_MUX = l_steerMux;
+
+        // Create new log. 
+        FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_STEER_MUX);
+        return l_rc;        
     }
 
 
@@ -3335,8 +3856,22 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target,
     else
     {
         FAPI_ERR("o_eccSpareSymbol out of range.");
-        // Caller needs to recognize a symbol value of 0xfe as invalid.
-        o_eccSpareSymbol = 0xfe;
+        
+        // TODO: Calling out FW high
+        // FFDC: MBA target
+        const fapi::Target & MBA = i_target;
+        // FFDC: DRAM width
+        uint8_t DRAM_WIDTH = l_dramWidth;
+        // FFDC: Capure i_rank;
+        uint8_t RANK = i_rank;
+        // FFDC: Capure i_muxType
+        uint8_t MUX_TYPE = i_muxType;       
+        // FFDC: Capture steer mux
+        ecmdDataBufferBase & STEER_MUX = l_steerMux;
+
+        // Create new log. 
+        FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_STEER_MUX);
+        return l_rc;        
     }
 
     FAPI_INF("mss_get_steer_mux(): rank%d, port0 steer = %d, port1 steer = %d, ecc steer = %d",
@@ -3362,15 +3897,6 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target,
 
 
 {
-
-    // TODO: i_symbol = MSS_INVALID_SYMBOL will result 0's entered in steer mux, which
-    // means no steer.
-    // Do I want to allow writing of no steer?
-
-    // TODO: i_symbol has to be first symbol in the chip for us to accept it.
-    // Do I want to allow any symbol as the input? 
-
-
     FAPI_INF("ENTER mss_put_steer_mux()");
 
 
@@ -3443,8 +3969,23 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target,
 
             if ( MSS_X8_STEER_OPTIONS_PER_PORT <= l_dramSparePort0Index )
             {
-                // Create new log. 
                 FAPI_ERR("No match for i_symbol = %d in mss_x8dramSparePort0Index_to_symbol[].", i_symbol);
+                
+                // TODO: Calling out FW high
+                // FFDC: MBA target
+                const fapi::Target & MBA = i_target;
+                // FFDC: DRAM width
+                uint8_t DRAM_WIDTH = l_dramWidth;
+                // FFDC: Capure i_rank;
+                uint8_t RANK = i_rank;
+                // FFDC: Capure i_muxType
+                uint8_t MUX_TYPE = i_muxType;       
+                // FFDC: Capure i_muxType
+                uint8_t STEER_TYPE = i_steerType;       
+                // FFDC: Capure i_muxType
+                uint8_t SYMBOL = i_symbol;       
+
+                // Create new log.                 
                 FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER);
                 return l_rc;
             }
@@ -3464,8 +4005,23 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target,
 
             if ( MSS_X4_STEER_OPTIONS_PER_PORT0 <= l_dramSparePort0Index )
             {
-                // Create new log. 
                 FAPI_ERR("No match for i_symbol in mss_x4dramSparePort0Index_to_symbol[].");
+
+                // TODO: Calling out FW high
+                // FFDC: MBA target
+                const fapi::Target & MBA = i_target;
+                // FFDC: DRAM width
+                uint8_t DRAM_WIDTH = l_dramWidth;
+                // FFDC: Capure i_rank;
+                uint8_t RANK = i_rank;
+                // FFDC: Capure i_muxType
+                uint8_t MUX_TYPE = i_muxType;       
+                // FFDC: Capure i_muxType
+                uint8_t STEER_TYPE = i_steerType;       
+                // FFDC: Capure i_muxType
+                uint8_t SYMBOL = i_symbol;       
+
+                // Create new log. 
                 FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER);
                 return l_rc;
             }
@@ -3492,8 +4048,23 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target,
 
             if ( MSS_X8_STEER_OPTIONS_PER_PORT <= l_dramSparePort1Index )
             {
-                // Create new log. 
                 FAPI_ERR("No match for i_symbol in mss_x8dramSparePort1Index_to_symbol[].");
+
+                // TODO: Calling out FW high
+                // FFDC: MBA target
+                const fapi::Target & MBA = i_target;
+                // FFDC: DRAM width
+                uint8_t DRAM_WIDTH = l_dramWidth;
+                // FFDC: Capure i_rank;
+                uint8_t RANK = i_rank;
+                // FFDC: Capure i_muxType
+                uint8_t MUX_TYPE = i_muxType;       
+                // FFDC: Capure i_muxType
+                uint8_t STEER_TYPE = i_steerType;       
+                // FFDC: Capure i_muxType
+                uint8_t SYMBOL = i_symbol;       
+
+                // Create new log. 
                 FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER);
                 return l_rc;
             }
@@ -3513,8 +4084,23 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target,
 
             if ( MSS_X4_STEER_OPTIONS_PER_PORT1 <= l_dramSparePort1Index )
             {
-                // Create new log. 
                 FAPI_ERR("No match for i_symbol in mss_x4dramSparePort1Index_to_symbol[].");
+
+                // TODO: Calling out FW high
+                // FFDC: MBA target
+                const fapi::Target & MBA = i_target;
+                // FFDC: DRAM width
+                uint8_t DRAM_WIDTH = l_dramWidth;
+                // FFDC: Capure i_rank;
+                uint8_t RANK = i_rank;
+                // FFDC: Capure i_muxType
+                uint8_t MUX_TYPE = i_muxType;       
+                // FFDC: Capure i_muxType
+                uint8_t STEER_TYPE = i_steerType;       
+                // FFDC: Capure i_muxType
+                uint8_t SYMBOL = i_symbol;       
+
+                // Create new log. 
                 FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER);
                 return l_rc;
             }
@@ -3542,17 +4128,46 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target,
 
             if ( MSS_X4_ECC_STEER_OPTIONS <= l_eccSpareIndex )
             {
-                // Create new log. 
                 FAPI_ERR("No match for i_symbol in mss_eccSpareIndex_to_symbol[].");
+
+                // TODO: Calling out FW high
+                // FFDC: MBA target
+                const fapi::Target & MBA = i_target;
+                // FFDC: DRAM width
+                uint8_t DRAM_WIDTH = l_dramWidth;
+                // FFDC: Capure i_rank;
+                uint8_t RANK = i_rank;
+                // FFDC: Capure i_muxType
+                uint8_t MUX_TYPE = i_muxType;       
+                // FFDC: Capure i_muxType
+                uint8_t STEER_TYPE = i_steerType;       
+                // FFDC: Capure i_muxType
+                uint8_t SYMBOL = i_symbol;       
+
+                // Create new log. 
                 FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER);
                 return l_rc;
             }
         }
         else if (l_dramWidth == mss_MemConfig::X8)
         {
+            FAPI_ERR("ECC_SPARE not valid with x8 mode.");
+
+            // TODO: Calling out FW high
+            // FFDC: MBA target
+            const fapi::Target & MBA = i_target;
+            // FFDC: DRAM width
+            uint8_t DRAM_WIDTH = l_dramWidth;
+            // FFDC: Capure i_rank;
+            uint8_t RANK = i_rank;
+            // FFDC: Capure i_muxType
+            uint8_t MUX_TYPE = i_muxType;       
+            // FFDC: Capure i_muxType
+            uint8_t STEER_TYPE = i_steerType;       
+            // FFDC: Capure i_muxType
+            uint8_t SYMBOL = i_symbol;       
 
             // Create new log. 
-            FAPI_ERR("ECC_SPARE not valid with x8 mode.");
             FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_NO_X8_ECC_SPARE);
             return l_rc;
         }
@@ -4240,3 +4855,460 @@ uint8_t mss_centaurDQ_to_symbol( uint8_t i_dq, uint8_t i_port )
 
     return o_symbol;
 }
+
+//------------------------------------------------------------------------------
+// mss_IPL_UE_isolation
+//------------------------------------------------------------------------------
+
+fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target,
+                                       uint8_t i_rank,
+                                       uint8_t (&o_bad_bits)[2][10])
+
+{
+    FAPI_INF("ENTER mss_IPL_UE_isolation()");
+
+    fapi::ReturnCode l_rc;
+    uint32_t l_ecmd_rc = 0;
+
+    static const uint32_t maintBufferReadDataRegs[2][2][8]={
+
+    // UE trap 0:
+      // Port0                                    beat  double word
+    {{MAINT0_MBA_MAINT_BUFF0_DATA0_0x03010655, // 0     DW0
+      MAINT0_MBA_MAINT_BUFF2_DATA0_0x03010675, // 1     DW2
+      MAINT0_MBA_MAINT_BUFF0_DATA1_0x03010656, // 2     DW4
+      MAINT0_MBA_MAINT_BUFF2_DATA1_0x03010676, // 3     DW6
+      MAINT0_MBA_MAINT_BUFF0_DATA2_0x03010657, // 4     DW8
+      MAINT0_MBA_MAINT_BUFF2_DATA2_0x03010677, // 5     DW10
+      MAINT0_MBA_MAINT_BUFF0_DATA3_0x03010658, // 6     DW12
+      MAINT0_MBA_MAINT_BUFF2_DATA3_0x03010678},// 7     DW14
+
+      // Port1
+     {MAINT0_MBA_MAINT_BUFF1_DATA0_0x03010665, // 0     DW1
+      MAINT0_MBA_MAINT_BUFF3_DATA0_0x03010685, // 1     DW3
+      MAINT0_MBA_MAINT_BUFF1_DATA1_0x03010666, // 2     DW5
+      MAINT0_MBA_MAINT_BUFF3_DATA1_0x03010686, // 3     DW7
+      MAINT0_MBA_MAINT_BUFF1_DATA2_0x03010667, // 4     DW9
+      MAINT0_MBA_MAINT_BUFF3_DATA2_0x03010687, // 5     DW11
+      MAINT0_MBA_MAINT_BUFF1_DATA3_0x03010668, // 6     DW13
+      MAINT0_MBA_MAINT_BUFF3_DATA3_0x03010688}},//7     DW15
+      
+    // UE trap 1:
+      // Port0
+    {{MAINT0_MBA_MAINT_BUFF0_DATA4_0x03010659, // 0     DW0
+      MAINT0_MBA_MAINT_BUFF2_DATA4_0x03010679, // 1     DW2
+      MAINT0_MBA_MAINT_BUFF0_DATA5_0x0301065a, // 2     DW4
+      MAINT0_MBA_MAINT_BUFF2_DATA5_0x0301067a, // 3     DW6
+      MAINT0_MBA_MAINT_BUFF0_DATA6_0x0301065b, // 4     DW8
+      MAINT0_MBA_MAINT_BUFF2_DATA6_0x0301067b, // 5     DW10
+      MAINT0_MBA_MAINT_BUFF0_DATA7_0x0301065c, // 6     DW12
+      MAINT0_MBA_MAINT_BUFF2_DATA7_0x0301067c},// 7     DW14
+
+      // Port1
+     {MAINT0_MBA_MAINT_BUFF1_DATA4_0x03010669, // 0     DW1
+      MAINT0_MBA_MAINT_BUFF3_DATA4_0x03010689, // 1     DW3
+      MAINT0_MBA_MAINT_BUFF1_DATA5_0x0301066a, // 2     DW5
+      MAINT0_MBA_MAINT_BUFF3_DATA5_0x0301068a, // 3     DW7
+      MAINT0_MBA_MAINT_BUFF1_DATA6_0x0301066b, // 4     DW9
+      MAINT0_MBA_MAINT_BUFF3_DATA6_0x0301068b, // 5     DW11
+      MAINT0_MBA_MAINT_BUFF1_DATA7_0x0301066c, // 6     DW13
+      MAINT0_MBA_MAINT_BUFF3_DATA7_0x0301068c}}};//7    DW15
+
+
+    static const uint32_t maintBufferRead65thByteRegs[2][4]={
+    // UE trap 0
+     {MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC0_0x03010695,
+      MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC1_0x03010696,
+      MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC2_0x03010697,
+      MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC3_0x03010698},
+    // UE trap 1
+     {MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC4_0x03010699,
+      MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC5_0x0301069a,
+      MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC6_0x0301069b,
+      MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC7_0x0301069c}};
+
+
+    uint8_t l_UE_trap = 0; // 0,1, since UE can be in 1st or 2nd half of buffer
+    uint8_t l_port = 0;    // 0,1
+    uint8_t l_beat = 0;    // 0-7
+    uint8_t l_byte = 0;    // 0-9
+    uint8_t l_loop = 0;        
+    ecmdDataBufferBase l_data(64);
+    ecmdDataBufferBase l_UE_trap0_signature(64);
+    ecmdDataBufferBase l_UE_trap1_signature(64);
+    ecmdDataBufferBase l_mbmmr(64);
+    ecmdDataBufferBase l_mbmct(64);
+    ecmdDataBufferBase l_mbstr(64);    
+    uint8_t l_initPattern = 0;
+    uint8_t l_cmd_type = 0;
+    fapi::Target l_targetCentaur;
+    uint8_t l_mbaPosition = 0;
+    uint32_t l_tmp_data_diff[2];
+    uint8_t l_tag_MDI = 0;
+    uint8_t l_tmp_65th_byte_diff = 0;
+    ecmdDataBufferBase l_diff(64);
+    uint32_t l_ECC = 0;
+    uint32_t l_tmp_ECC_diff = 0;
+    ecmdDataBufferBase l_ECC_diff(32);
+    uint8_t l_ECC_c6_c5_c4_01 = 0;
+    uint8_t l_ECC_c6_c5_c4_23 = 0;
+    uint8_t l_ECC_c3_c2_c1_c0_01 = 0;
+    uint8_t l_ECC_c3_c2_c1_c0_23 = 0;
+    uint8_t l_dramSparePort0Symbol = MSS_INVALID_SYMBOL;
+    uint8_t l_dramSparePort1Symbol = MSS_INVALID_SYMBOL;
+    uint8_t l_eccSpareSymbol = MSS_INVALID_SYMBOL;  
+
+    //----------------------------------------------------
+    // Initialize o_bad_bits
+    //----------------------------------------------------
+
+    for(l_port=0; l_port<2; l_port++ )
+    {
+        for(l_byte=0; l_byte<10; l_byte++ )
+        {
+            o_bad_bits[l_port][l_byte] = 0;
+        }
+    }
+
+
+    //----------------------------------------------------
+    // Get the expected pattern (stored in mbmmr reg)
+    //----------------------------------------------------
+
+    // Get Centaur target for the given MBA
+    l_rc = fapiGetParentChip(i_target, l_targetCentaur);
+    if(l_rc)
+    {
+        FAPI_ERR("Error getting Centaur parent target for the given MBA");
+        return l_rc;
+    }
+
+    // Get MBA position: 0 = mba01, 1 = mba23
+    l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbaPosition);
+    if(l_rc)
+    {
+        FAPI_ERR("Error getting MBA position");
+        return l_rc;
+    }
+
+    // MBMMR[4:7] contains the pattern index
+    l_rc = fapiGetScom(l_targetCentaur, mss_mbmmr[l_mbaPosition], l_mbmmr);
+    if(l_rc) return l_rc;   
+    l_ecmd_rc |= l_mbmmr.extractPreserve(&l_initPattern, 4, 4, 8-4);
+    if(l_ecmd_rc)
+    {
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }
+
+    // MBMCT[0:4] contains the cmd type
+    l_rc = fapiGetScom(i_target, MBA01_MBMCTQ_0x0301060A, l_mbmct);
+    if(l_rc) return l_rc;
+    l_ecmd_rc |= l_mbmct.extractPreserve(&l_cmd_type, 0, 5, 8-5);
+    if(l_ecmd_rc)
+    {
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }
+
+    // No isolation if cmd is timebased steer cleanup, or pattern is random
+    if ((l_cmd_type == 2) || (l_initPattern == 8))
+    {
+        FAPI_ERR("No UE isolation for steer cleanup or random pattern");
+        return l_rc;
+    }
+
+
+    FAPI_INF("Expected pattern%d = 0x%.8X 0x%.8X",l_initPattern,
+    mss_maintBufferData[l_initPattern][0][0],
+    mss_maintBufferData[l_initPattern][0][1]);
+
+    //----------------------------------------------------
+    // Figure out which half of the buffer has the UE...
+    // Remember we had to first load the buffers with
+    // a hex signatue, and whichever gets overwritten
+    // has a UE trapped
+    //----------------------------------------------------
+    l_rc = fapiGetScom(i_target, MAINT0_MBA_MAINT_BUFF0_DATA0_0x03010655, l_UE_trap0_signature);
+    if(l_rc) return l_rc;
+    
+    l_rc = fapiGetScom(i_target, MAINT0_MBA_MAINT_BUFF0_DATA4_0x03010659, l_UE_trap1_signature);
+    if(l_rc) return l_rc;
+
+    // UE may be trapped in both halves of the buffer,
+    // but we will only use one.
+    if ((l_UE_trap0_signature.getWord(0) != 0xFACEB00C) &&
+        (l_UE_trap0_signature.getWord(0) != 0xD15C0DAD))
+    {
+        FAPI_INF("UE trapped in 1st half of maint buffer");
+        l_UE_trap = 0;
+    }
+    else if ((l_UE_trap1_signature.getWord(0) != 0xFACEB00C) &&
+             (l_UE_trap1_signature.getWord(0) != 0xD15C0DAD))
+    {
+        FAPI_INF("UE trapped in 2nd half of maint buffer");
+        l_UE_trap = 1;
+    }
+    else
+    {
+        FAPI_ERR("IPL UE trapping didn't work.");
+        
+        // Read for FFDC: MBSTR[59]: UE trap enable bit
+        l_rc = fapiGetScom(l_targetCentaur, mss_mbstr[l_mbaPosition], l_mbstr);
+        if(l_rc) return l_rc;
+                
+
+        // Calling out MBA target high, deconfig, gard
+        const fapi::Target & MBA = i_target;
+        // FFDC: Capture UE trap contents
+        ecmdDataBufferBase & UE_TRAP0 = l_UE_trap0_signature;
+        ecmdDataBufferBase & UE_TRAP1 = l_UE_trap1_signature;        
+        // FFDC: MBMCT[0:4] contains the cmd type
+        ecmdDataBufferBase & MBMCT = l_mbmct;  
+        // FFDC: MBMMR[4:7] contains the pattern index
+        ecmdDataBufferBase & MBMMR = l_mbmmr;  
+        // FFDC: MBSTR[59]: UE trap enable bit
+        ecmdDataBufferBase & MBSTR = l_mbstr;  
+        
+        // Create new log
+        FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_NO_UE_TRAP);
+   
+        return l_rc;
+    }
+
+
+
+    //----------------------------------------------------
+    // DATA: Do XOR of expected and actual data to find stuck bits
+    //----------------------------------------------------
+
+    for(l_port=0; l_port<2; l_port++ )
+    {
+        l_tmp_data_diff[0] = 0;
+        l_tmp_data_diff[1] = 0;
+        
+        FAPI_INF("port%d", l_port);
+        for(l_beat=0; l_beat<8; l_beat++ )
+        {
+
+            l_rc = fapiGetScom(i_target, maintBufferReadDataRegs[l_UE_trap][l_port][l_beat], l_data);
+            if(l_rc) return l_rc;
+            FAPI_INF("Actual data, beat%d: 0x%.8X 0x%.8X", l_beat, l_data.getWord(0), l_data.getWord(1));
+
+            FAPI_INF("Expected pattern%d = 0x%.8X 0x%.8X",l_initPattern,
+            mss_maintBufferData[l_initPattern][l_port*8 + l_beat][0],
+            mss_maintBufferData[l_initPattern][l_port*8 + l_beat][1]);
+
+            // DO XOR of actual and expected data, and OR the result together for all 8 beats
+            l_tmp_data_diff[0] |= l_data.getWord(0) ^ mss_maintBufferData[l_initPattern][l_port*8 + l_beat][0];
+            l_tmp_data_diff[1] |= l_data.getWord(1) ^ mss_maintBufferData[l_initPattern][l_port*8 + l_beat][1];
+
+            FAPI_INF("***************************************** l_tmp_diff: 0x%.8X 0x%.8X", l_tmp_data_diff[0], l_tmp_data_diff[1]);
+        }
+
+        // Put l_tmp_diff into a ecmdDataBufferBase to make it easier 
+        // to get into o_bad_bits
+        l_ecmd_rc |= l_diff.insert(l_tmp_data_diff[0], 0, 32, 0);
+        l_ecmd_rc |= l_diff.insert(l_tmp_data_diff[1], 32, 32, 0);
+        if(l_ecmd_rc)
+        {
+            l_rc.setEcmdError(l_ecmd_rc);
+            return l_rc;
+        }
+
+        for(l_byte=0; l_byte<8; l_byte++ )
+        {
+            l_ecmd_rc |= l_diff.extractPreserve(&o_bad_bits[l_port][l_byte], 8*l_byte, 8, 0);
+        }
+        if(l_ecmd_rc)
+        {
+            l_rc.setEcmdError(l_ecmd_rc);
+            return l_rc;
+        }
+
+    } // End loop on ports
+
+
+
+    //----------------------------------------------------
+    // 65th byte: Do XOR of expected and actual 65th byte to find stuck bits
+    //----------------------------------------------------
+
+    for(l_loop=0; l_loop<4; l_loop++ )
+    {   
+        l_tag_MDI = 0;
+        l_tmp_65th_byte_diff = 0;
+
+        l_rc = fapiGetScom(i_target, maintBufferRead65thByteRegs[l_UE_trap][l_loop], l_data);
+        if(l_rc) return l_rc;
+
+        // Grab bit 0 = Checkbit0_1
+        // Grab bit 1 = Tag0_2
+        // Grab bit 2 = Tag1_3
+        // Grab bit 3 = MDI
+        l_ecmd_rc |= l_data.extractPreserve(&l_tag_MDI, 0, 4, 0);
+        if(l_ecmd_rc)
+        {
+            l_rc.setEcmdError(l_ecmd_rc);
+            return l_rc;
+        }
+
+        FAPI_INF("Actual:   bit0 (Checkbit0_1), bit1(Tag0_2), bit2(Tag1_3), bit3(MDI) = 0x%.2X", l_tag_MDI);
+
+        FAPI_INF("Expected: bit0 (Checkbit0_1), bit1(Tag0_2), bit2(Tag1_3), bit3(MDI) = 0x%.2X", mss_65thByte[l_initPattern][l_loop]);
+
+        // DO XOR of actual and expected data
+        l_tmp_65th_byte_diff = l_tag_MDI ^ mss_65thByte[l_initPattern][l_loop];
+        FAPI_INF("***************************************** l_tmp_65th_byte_diff: 0x%.2X", l_tmp_65th_byte_diff);
+
+
+        // Check for mismatch in bit 0: Checkbit0_1
+        if (l_tmp_65th_byte_diff & 0x80)
+        {
+            // Checkbit0_1 maps to port0 bit 64, which is on byte8
+            o_bad_bits[0][8] |= 0x80;
+        }        
+
+        // Check for mismatch in bit 1: Tag0_2
+        if (l_tmp_65th_byte_diff & 0x40)
+        {
+            // Tag0_2 maps to port0 bit 65, which is on byte8
+            o_bad_bits[0][8] |= 0x40;
+        }
+
+        // Check for mismatch in bit 2: Tag1_3
+        if (l_tmp_65th_byte_diff & 0x20)
+        {
+            // Tag1_3 maps to port0 bit 64, which is on byte8
+            o_bad_bits[0][8] |= 0x80;
+        }
+
+        // Check for mismatch in bit 3: MDI
+        if (l_tmp_65th_byte_diff & 0x10)
+        {
+            // MDI maps to port0 bit 65, which is on byte8
+            o_bad_bits[0][8] |= 0x40;
+        }
+    } // End loops through trapped 65th byte info
+
+
+    //----------------------------------------------------
+    // ECC: Do XOR of expected and actual ECC bits to find stuck bits
+    //----------------------------------------------------
+
+    for(l_loop=0; l_loop<4; l_loop++ )
+    {   
+        l_ECC = 0;
+
+        l_rc = fapiGetScom(i_target, maintBufferRead65thByteRegs[l_UE_trap][l_loop], l_data);
+        if(l_rc) return l_rc;
+
+        // Grab bits 4:15 = ECC_c6_c5_c4, and bits 16:31 = ECC_c3_c2_c1_c0
+        l_ecmd_rc |= l_data.extractPreserve(&l_ECC, 4, 28, 4);
+        if(l_ecmd_rc)
+        {
+            l_rc.setEcmdError(l_ecmd_rc);
+            return l_rc;
+        }
+
+        FAPI_INF("Actual:   ECC = 0x%.8X", l_ECC);
+
+        FAPI_INF("Expected: ECC = 0x%.8X", mss_ECC[l_initPattern][l_loop]);
+
+        // DO XOR of actual and expected data
+        l_tmp_ECC_diff |= l_ECC ^ mss_ECC[l_initPattern][l_loop];
+        FAPI_INF("***************************************** l_tmp_ECC_diff: 0x%.8X", l_tmp_ECC_diff);
+    }
+
+    // Put l_tmp_ECC_diff into a ecmdDataBufferBase to make it easier
+    // to get into o_bad_bits
+    l_ecmd_rc |= l_ECC_diff.insert(l_tmp_ECC_diff, 0, 32, 0);
+    if(l_ecmd_rc)
+    {
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }
+
+    l_ecmd_rc |= l_ECC_diff.extractPreserve(&l_ECC_c6_c5_c4_01, 4, 6, 8-6);
+    l_ecmd_rc |= l_ECC_diff.extractPreserve(&l_ECC_c6_c5_c4_23, 10, 6, 8-6);
+    l_ecmd_rc |= l_ECC_diff.extractPreserve(&l_ECC_c3_c2_c1_c0_01, 16, 8, 0);
+    l_ecmd_rc |= l_ECC_diff.extractPreserve(&l_ECC_c3_c2_c1_c0_23, 24, 8, 0);
+    if(l_ecmd_rc)
+    {
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }
+
+    // The 6 bits of ECC_c6_c5_c4 maps to byte8 on port0
+    o_bad_bits[0][8] |= l_ECC_c6_c5_c4_01 | l_ECC_c6_c5_c4_23;
+    // The 8 bits of ECC_c3_c2_c1_c0 maps to byte8 byte on port1
+    o_bad_bits[1][8] |= l_ECC_c3_c2_c1_c0_01 | l_ECC_c3_c2_c1_c0_23;
+    
+
+    //----------------------------------------------------
+    // Spare: Mark byte9 bad if bad bits found in position being steered
+    //----------------------------------------------------
+
+    // READ steer mux, which gets me a symbol for port0 and port1
+    l_rc = mss_get_steer_mux(i_target,
+                             i_rank,
+                             mss_SteerMux::READ_MUX,
+                             l_dramSparePort0Symbol,
+                             l_dramSparePort1Symbol,
+                             l_eccSpareSymbol);
+    if(l_rc) return l_rc;
+
+    // If steering on port0
+    if ( l_dramSparePort0Symbol != 0xff)
+    {
+        // Find the byte being steered
+        l_byte = mss_chip_mark_to_centaurDQ[l_dramSparePort0Symbol/4][0]/8;
+
+        // If that byte has any bad bits in it, copy them to byte9,
+        if (o_bad_bits[0][l_byte])
+        {
+            o_bad_bits[0][9] = o_bad_bits[0][l_byte];
+
+            // Clear byte being steered, since it did not contribute to UE
+            o_bad_bits[0][l_byte] = 0;
+        }
+    }
+
+    // If steering on port1
+    if ( l_dramSparePort1Symbol != 0xff)
+    {
+        // Find the byte being steered
+        l_byte = mss_chip_mark_to_centaurDQ[l_dramSparePort1Symbol/4][0]/8;
+
+        // If that byte has any bad bits in it, copy them to byte9,
+        if (o_bad_bits[1][l_byte])
+        {
+            o_bad_bits[1][9] = o_bad_bits[1][l_byte];
+
+            // Clear byte being steered, since it did not contribute to UE
+            o_bad_bits[1][l_byte] = 0;
+        }
+    }
+
+    //----------------------------------------------------
+    // Show results 
+    //----------------------------------------------------
+
+    for(l_port=0; l_port<2; l_port++ )
+    {
+        for(l_byte=0; l_byte<10; l_byte++ )
+        {
+            FAPI_INF("o_bad_bits[%d][%d] = %02x",
+                      l_port, l_byte, o_bad_bits[l_port][l_byte]);
+        }
+    }
+
+
+    FAPI_INF("EXIT mss_IPL_UE_isolation()");
+
+    return l_rc;
+
+
+}
+
+
diff --git a/src/usr/hwpf/hwp/dram_training/memory_errors.xml b/src/usr/hwpf/hwp/dram_training/memory_errors.xml
index 98b56aa52..3eb48ee4a 100644
--- a/src/usr/hwpf/hwp/dram_training/memory_errors.xml
+++ b/src/usr/hwpf/hwp/dram_training/memory_errors.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- IBM CONFIDENTIAL                                                       -->
 <!--                                                                        -->
-<!-- COPYRIGHT International Business Machines Corp. 2012                   -->
+<!-- COPYRIGHT International Business Machines Corp. 2012,2013              -->
 <!--                                                                        -->
 <!-- p1                                                                     -->
 <!--                                                                        -->
@@ -213,92 +213,403 @@
 
   <hwpError>
     <rc>RC_MSS_MAINT_START_NOT_RESET</rc>
-    <description>MCMCCQ[0]: maint_cmd_start not reset by hw.</description>
+    <description>MBMCCQ[0]: maint_cmd_start not reset by hw.</description>
+    <!-- FFDC: Capture register we are checking -->    
+    <ffdc>MBMCC</ffdc>
+    <!-- FFDC: Capture command type we are trying to run -->        
+    <ffdc>CMD_TYPE</ffdc>    
+    <!-- FFDC: MBMCT[0:4] contains the cmd type set in hw -->
+    <ffdc>MBMCT</ffdc>                
+    <!-- Callout MBA HIGH -->
+    <callout><target>MBA</target><priority>HIGH</priority></callout>
+    <!-- Deconfigure MBA -->
+    <deconfigure><target>MBA</target></deconfigure>
+    <!-- Create GARD record for MASTER_CHIP -->    
+    <gard><target>MBA</target></gard>    
 </hwpError>
 
   <hwpError>
     <rc>RC_MSS_MAINT_STOP_NOT_RESET</rc>
-    <description>MCMCCQ[1]: maint_cmd_stop not reset by hw.</description>
+    <description>MBMCCQ[1]: maint_cmd_stop not reset by hw.</description>
+    <!-- FFDC: Capture register we are checking -->    
+    <ffdc>MBMCC</ffdc>
+    <!-- FFDC: Capture command type we are trying to run -->        
+    <ffdc>CMD_TYPE</ffdc>        
+    <!-- FFDC: MBMCT[0:4] contains the cmd type previously run -->
+    <ffdc>MBMCT</ffdc>                
+    <!-- Callout MBA HIGH -->
+    <callout><target>MBA</target><priority>HIGH</priority></callout>
+    <!-- Deconfigure MBA -->
+    <deconfigure><target>MBA</target></deconfigure>
+    <!-- Create GARD record for MASTER_CHIP -->    
+    <gard><target>MBA</target></gard>    
 </hwpError>
 
   <hwpError>
     <rc>RC_MSS_MAINT_CMD_IN_PROGRESS</rc>
     <description>MBMSRQ[0]: Can't start new cmd if previous cmd still in progress.</description>
+    <!-- FFDC: Capture register we are checking -->    
+    <ffdc>MBMSR</ffdc>
+    <!-- FFDC: Capture command type we are trying to run -->        
+    <ffdc>CMD_TYPE</ffdc>        
+    <!-- FFDC: MBMCT[0:4] contains the cmd type previously run -->
+    <ffdc>MBMCT</ffdc>                
+    <!-- TODO: Callout FW HIGH -->
+    <!-- Callout MBA LOW -->
+    <callout><target>MBA</target><priority>LOW</priority></callout>
+    <!-- Deconfigure MBA -->
+    <deconfigure><target>MBA</target></deconfigure>
+    <!-- Create GARD record for MASTER_CHIP -->    
+    <gard><target>MBA</target></gard>        
 </hwpError>
 
   <hwpError>
     <rc>RC_MSS_MAINT_NO_MEM_CNFG</rc>
     <description>MBAXCRn[0:3] = 0, meaning no memory configured behind this MBA.</description>
+    <!-- FFDC: MBA target -->    
+    <ffdc>MBA</ffdc>
+    <!-- FFDC: Capture register we are checking -->    
+    <ffdc>MBAXCR</ffdc>
+    <!-- TODO: Callout FW HIGH -->
 </hwpError>
 
   <hwpError>
     <rc>RC_MSS_MAINT_CCS_MUX_NOT_MAINLINE</rc>
     <description>CCS_MODEQ[29] = 1, meaning mux set for CCS instead of mainline.</description>
+    <!-- FFDC: MBA target -->    
+    <ffdc>MBA</ffdc>
+    <!-- FFDC: Capture register we are checking -->    
+    <ffdc>CCS_MODE</ffdc>
+    <!-- FFDC: Capture command type we are trying to run -->        
+    <ffdc>CMD_TYPE</ffdc>        
+    <!-- TODO: Callout FW HIGH -->
 </hwpError>
 
   <hwpError>
     <rc>RC_MSS_MAINT_ECC_DISABLED</rc>
     <description>MBSECC[0] non zero, meaning ECC check/correct disabled.</description>
+    <!-- FFDC: MBA target -->    
+    <ffdc>MBA</ffdc>
+    <!-- FFDC: Capture register we are checking -->    
+    <ffdc>MBSECC</ffdc>
+    <!-- FFDC: Capture command type we are trying to run -->        
+    <ffdc>CMD_TYPE</ffdc>        
+    <!-- TODO: Callout FW HIGH -->
 </hwpError>
 
   <hwpError>
     <rc>RC_MSS_MAINT_INVALID_CMD</rc>
     <description>MBAFIRQ[0], invalid_maint_cmd.</description>
+    <!-- FFDC: MBA target -->    
+    <ffdc>MBA</ffdc>
+    <!-- FFDC: Capture register we are checking -->    
+    <ffdc>MBAFIR</ffdc>
+    <!-- FFDC: Capture command type we are trying to run -->        
+    <ffdc>CMD_TYPE</ffdc>        
+    <!-- FFDC: MBMCT[0:4] contains the cmd type set in hw -->
+    <ffdc>MBMCT</ffdc>                
+    <!-- TODO: Callout FW HIGH -->
 </hwpError>
 
   <hwpError>
     <rc>RC_MSS_MAINT_INVALID_ADDR</rc>
     <description>MBAFIRQ[1], cmd started with invalid_maint_address.</description>
-</hwpError>
+    <!-- FFDC: MBA target -->    
+    <ffdc>MBA</ffdc>
+    <!-- FFDC: Capture register we are checking -->    
+    <ffdc>MBAFIR</ffdc>
+    <!-- FFDC: Capture command type we are trying to run -->        
+    <ffdc>CMD_TYPE</ffdc>        
+    <!-- FFDC: MBMCT[0:4] contains the cmd type set in hw -->
+    <ffdc>MBMCT</ffdc>                
+    <!-- Collect registers as FFDC -->
+    <collectRegisterFfdc>
+      <id>REG_FFDC_INVALID_ADDR</id>
+      <target>MBA</target>
+    </collectRegisterFfdc>
+    <!-- TODO: Callout FW HIGH -->    
+</hwpError>
+
+<registerFfdc>
+  <id>REG_FFDC_INVALID_ADDR</id>
+  <scomRegister>MBA01_MBMACAQ_0x0301060D</scomRegister>
+  <scomRegister>MBA01_MBMEAQ_0x0301060E</scomRegister>
+  <scomRegister>MBA01_MBA_MCBERRPTQ_0x030106e7</scomRegister>
+</registerFfdc>
+
 
   <hwpError>
     <rc>RC_MSS_MAINT_CMD_TIMEOUT</rc>
     <description>Maint cmd timeout.</description>
+    <!-- FFDC: Capture command type we are trying to run -->        
+    <ffdc>CMD_TYPE</ffdc>        
+    <!-- Collect MBA registers as FFDC -->
+    <collectRegisterFfdc>
+      <id>REG_FFDC_CMD_TIMEOUT_MBA_REGS</id>
+      <target>MBA</target>
+    </collectRegisterFfdc>
+    <!-- Collect MBS registers as FFDC -->
+    <collectRegisterFfdc>
+      <id>REG_FFDC_CMD_TIMEOUT_MBS_REGS</id>
+      <target>CENTAUR</target>
+    </collectRegisterFfdc>
+    <!-- TODO: Callout FW HIGH -->
+    <!-- Callout MBA LOW -->
+    <callout><target>MBA</target><priority>LOW</priority></callout>
+    <!-- Deconfigure MBA -->
+    <deconfigure><target>MBA</target></deconfigure>
+    <!-- Create GARD record for MASTER_CHIP -->    
+    <gard><target>MBA</target></gard>        
+</hwpError>
+
+<registerFfdc>
+  <id>REG_FFDC_CMD_TIMEOUT_MBA_REGS</id>
+  <!-- MBA Maintenance Command Type Register -->    
+  <scomRegister>MBA01_MBMCTQ_0x0301060A</scomRegister>
+  <!-- MBA Maintenance Command Control Register -->
+  <scomRegister>MBA01_MBMCCQ_0x0301060B</scomRegister>
+  <!-- MBA Maintenance Command Status Register -->
+  <scomRegister>MBA01_MBMSRQ_0x0301060C</scomRegister>
+  <!-- MBA Maintenance Command Address Register -->
+  <scomRegister>MBA01_MBMACAQ_0x0301060D</scomRegister>
+  <!-- MBA Maintenance Command End Address Register -->
+  <scomRegister>MBA01_MBMEAQ_0x0301060E</scomRegister>
+  <!-- MBA Memory Scrub/Read Control Register -->
+  <scomRegister>MBA01_MBASCTLQ_0x0301060F</scomRegister>
+  <!-- MBA Error Control Register -->
+  <scomRegister>MBA01_MBECTLQ_0x03010610</scomRegister>
+
+  <!-- MBA Special Attention Registers -->    
+  <scomRegister>MBA01_MBSPAQ_0x03010611</scomRegister>
+  <scomRegister>MBA01_MBSPAMSKQ_0x03010614</scomRegister>
+
+  <!-- MBA Fault Isolation Registers -->  
+  <scomRegister>MBA01_MBAFIRQ_0x03010600</scomRegister>  
+  <scomRegister>MBA01_MBAFIRMASK_0x03010603</scomRegister>  
+  <scomRegister>MBA01_MBAFIRACT0_0x03010606</scomRegister>  
+  <scomRegister>MBA01_MBAFIRACT1_0x03010607</scomRegister>  
+  <!-- MBA Error Report Register -->  
+  <scomRegister>MBA01_MBA_MCBERRPTQ_0x030106e7</scomRegister>  
+
+  <!-- MBA CAL FIR Registers -->  
+  <scomRegister>MBA01_MBACALFIR_0x03010400</scomRegister>  
+  <scomRegister>MBA01_MBACALFIR_MASK_0x03010403</scomRegister>  
+  <scomRegister>MBA01_MBACALFIR_ACTION0_0x03010406</scomRegister>  
+  <scomRegister>MBA01_MBACALFIR_ACTION1_0x03010407</scomRegister>  
+  <!-- MBA Error report register -->  
+  <scomRegister>MBA01_MBA_ERR_REPORTQ_0x0301041A</scomRegister>  
+</registerFfdc>
+
+<registerFfdc>
+  <id>REG_FFDC_CMD_TIMEOUT_MBS_REGS</id>
+  <!-- MBS ECC0 Decoder FIR Registers -->
+  <scomRegister>MBS_ECC0_MBECCFIR_0x02011440</scomRegister>
+  <scomRegister>MBS_ECC0_MBECCFIR_MASK_0x02011443</scomRegister>
+  <scomRegister>MBS_ECC0_MBECCFIR_ACTION0_0x02011446</scomRegister>
+  <scomRegister>MBS_ECC0_MBECCFIR_ACTION1_0x02011447</scomRegister>
+
+  <!-- MBS ECC1 Decoder FIR Registers -->
+  <scomRegister>MBS_ECC1_MBECCFIR_0x02011480</scomRegister>
+  <scomRegister>MBS_ECC1_MBECCFIR_MASK_0x02011483</scomRegister>
+  <scomRegister>MBS_ECC1_MBECCFIR_ACTION0_0x02011486</scomRegister>
+  <scomRegister>MBS_ECC1_MBECCFIR_ACTION1_0x02011487</scomRegister> 
+</registerFfdc>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_ZERO_DDR_FREQ</rc>
+    <description>ATTR_MSS_FREQ set to zero so can't calculate scrub rate.</description>
+    <!-- FFDC: MBA target -->    
+    <ffdc>MBA</ffdc>
+    <!-- FFDC: DDR_FREQ -->    
+    <ffdc>DDR_FREQ</ffdc>
+    <!-- FFDC: Capture command type we are trying to run -->        
+    <ffdc>CMD_TYPE</ffdc>        
+    <!-- TODO: Callout FW HIGH -->
 </hwpError>
 
   <hwpError>
     <rc>RC_MSS_MAINT_INVALID_DRAM_SIZE_WIDTH</rc>
     <description>Invalid dramSize or dramWidth in MBAXCRn.</description>
+    <!-- FFDC: MBA target -->    
+    <ffdc>MBA</ffdc>
+    <!-- FFDC: Capture register we are checking -->    
+    <ffdc>MBAXCR</ffdc>
+    <!-- TODO: Callout FW HIGH -->
 </hwpError>
 
   <hwpError>
     <rc>RC_MSS_MAINT_INVALID_DIMM_CNFG</rc>
     <description>MBAXCRn configured with invalid combination of configType, configSubType, slotConfig.</description>
+    <!-- FFDC: MBA target -->    
+    <ffdc>MBA</ffdc>
+    <!-- FFDC: Capture register we are checking -->    
+    <ffdc>MBAXCR</ffdc>
+    <!-- TODO: Callout FW HIGH -->
 </hwpError>
 
   <hwpError>
-    <rc>RC_MSS_MAINT_NO_X4_SYMBOL</rc>
+    <rc>RC_MSS_MAINT_X4_SYMBOL_ON_READ</rc>
     <description>Symbol mark not allowed in x4 mode.</description>
+    <!-- FFDC: MBA target -->    
+    <ffdc>MBA</ffdc>
+    <!-- FFDC: DRAM width (should be x4) -->    
+    <ffdc>DRAM_WIDTH</ffdc>
+    <!-- FFDC: RANK we are reading markstore for -->    
+    <ffdc>RANK</ffdc>
+    <!-- FFDC: Markstore with non-zero symbol entry -->    
+    <ffdc>MARKSTORE</ffdc>
+    <!-- TODO: Callout FW HIGH -->
 </hwpError>
 
   <hwpError>
     <rc>RC_MSS_MAINT_INVALID_MARKSTORE</rc>
     <description>Invalid galois field in markstore.</description>
+    <!-- FFDC: MBA target -->    
+    <ffdc>MBA</ffdc>
+    <!-- FFDC: DRAM width -->    
+    <ffdc>DRAM_WIDTH</ffdc>
+    <!-- FFDC: RANK we are reading markstore for -->    
+    <ffdc>RANK</ffdc>
+    <!-- FFDC: Markstore with invalid galois field  -->    
+    <ffdc>MARKSTORE</ffdc>
+    <!-- TODO: Callout FW HIGH -->
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_X4_SYMBOL_ON_WRITE</rc>
+    <description>Symbol mark not allowed in x4 mode.</description>
+    <!-- FFDC: MBA target -->    
+    <ffdc>MBA</ffdc>
+    <!-- FFDC: DRAM width (should be x4) -->    
+    <ffdc>DRAM_WIDTH</ffdc>
+    <!-- FFDC: RANK we are reading markstore for -->    
+    <ffdc>RANK</ffdc>
+    <!-- FFDC: Symbol mark we are trying to write to markstore -->    
+    <ffdc>SYMBOL_MARK</ffdc>
+    <!-- FFDC: Chip mark we are trying to write to markstore -->    
+    <ffdc>CHIP_MARK</ffdc>
+    <!-- TODO: Callout FW HIGH -->
 </hwpError>
 
   <hwpError>
     <rc>RC_MSS_MAINT_INVALID_SYMBOL_INDEX</rc>
     <description>Symbol index out of range.</description>
+    <!-- FFDC: MBA target -->    
+    <ffdc>MBA</ffdc>
+    <!-- FFDC: DRAM width -->    
+    <ffdc>DRAM_WIDTH</ffdc>
+    <!-- FFDC: RANK we are reading markstore for -->    
+    <ffdc>RANK</ffdc>
+    <!-- FFDC: Symbol mark we are trying to write to markstore -->    
+    <ffdc>SYMBOL_MARK</ffdc>
+    <!-- FFDC: Chip mark we are trying to write to markstore -->    
+    <ffdc>CHIP_MARK</ffdc>
+    <!-- TODO: Callout FW HIGH -->
 </hwpError>
 
   <hwpError>
     <rc>RC_MSS_MAINT_INVALID_CHIP_INDEX</rc>
     <description>Not first symbol index of a chip.</description>
+    <!-- FFDC: MBA target -->    
+    <ffdc>MBA</ffdc>
+    <!-- FFDC: DRAM width -->    
+    <ffdc>DRAM_WIDTH</ffdc>
+    <!-- FFDC: RANK we are reading markstore for -->    
+    <ffdc>RANK</ffdc>
+    <!-- FFDC: Symbol mark we are trying to write to markstore -->    
+    <ffdc>SYMBOL_MARK</ffdc>
+    <!-- FFDC: Chip mark we are trying to write to markstore -->    
+    <ffdc>CHIP_MARK</ffdc>
+    <!-- TODO: Callout FW HIGH -->
 </hwpError>
 
   <hwpError>
     <rc>RC_MSS_MAINT_MARKSTORE_WRITE_BLOCKED</rc>
     <description>Markstore write may have been blocked due to MPE FIR set.</description>
+    <!-- FFDC: MBA target -->    
+    <ffdc>MBA</ffdc>
+    <!-- FFDC: DRAM width -->    
+    <ffdc>DRAM_WIDTH</ffdc>
+    <!-- FFDC: RANK we are reading markstore for -->    
+    <ffdc>RANK</ffdc>
+    <!-- FFDC: Symbol mark we are trying to write to markstore -->    
+    <ffdc>SYMBOL_MARK</ffdc>
+    <!-- FFDC: Chip mark we are trying to write to markstore -->    
+    <ffdc>CHIP_MARK</ffdc>
+    <!-- FFDC: MBECCFIR showing MPE -->    
+    <ffdc>MBECCFIR</ffdc>
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_INVALID_STEER_MUX</rc>
+    <description>Steer mux index out of range</description>
+    <!-- FFDC: MBA target -->    
+    <ffdc>MBA</ffdc>
+    <!-- FFDC: DRAM width -->    
+    <ffdc>DRAM_WIDTH</ffdc>
+    <!-- FFDC: RANK we are reading steer mux for -->    
+    <ffdc>RANK</ffdc>
+    <!-- FFDC: MUX_TYPE: read or write -->    
+    <ffdc>MUX_TYPE</ffdc>
+    <!-- FFDC: Capture steer mux -->    
+    <ffdc>STEER_MUX</ffdc>
+    <!-- TODO: Callout FW HIGH -->    
 </hwpError>
 
   <hwpError>
     <rc>RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER</rc>
     <description>Trying to steer invalid symbol.</description>
+    <!-- FFDC: MBA target -->    
+    <ffdc>MBA</ffdc>
+    <!-- FFDC: DRAM width -->    
+    <ffdc>DRAM_WIDTH</ffdc>
+    <!-- FFDC: RANK we are reading steer mux for -->    
+    <ffdc>RANK</ffdc>
+    <!-- FFDC: MUX_TYPE: read or write -->    
+    <ffdc>MUX_TYPE</ffdc>
+    <!-- FFDC: STEER_TYPE: port0, port1, or ecc spare -->    
+    <ffdc>STEER_TYPE</ffdc>
+    <!-- FFDC: SYMBOL: Symbol we are trying to steer -->    
+    <ffdc>SYMBOL</ffdc>
+    <!-- TODO: Callout FW HIGH -->    
 </hwpError>
 
   <hwpError>
     <rc>RC_MSS_MAINT_NO_X8_ECC_SPARE</rc>
     <description>Invalid to use ECC spare in x8 mode.</description>
+    <!-- FFDC: MBA target -->    
+    <ffdc>MBA</ffdc>
+    <!-- FFDC: DRAM width -->    
+    <ffdc>DRAM_WIDTH</ffdc>
+    <!-- FFDC: RANK we are reading steer mux for -->    
+    <ffdc>RANK</ffdc>
+    <!-- FFDC: MUX_TYPE: read or write -->    
+    <ffdc>MUX_TYPE</ffdc>
+    <!-- FFDC: STEER_TYPE: port0, port1, or ecc spare -->    
+    <ffdc>STEER_TYPE</ffdc>
+    <!-- FFDC: SYMBOL: Symbol we are trying to steer -->    
+    <ffdc>SYMBOL</ffdc>
+    <!-- TODO: Callout FW HIGH -->    
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_NO_UE_TRAP</rc>
+    <description>IPL UE trapping didn't work.</description>
+    <!-- FFDC: Capture UE trap contents -->
+    <ffdc>UE_TRAP0</ffdc>
+    <ffdc>UE_TRAP1</ffdc>
+    <!-- FFDC: MBMCT[0:4] contains the cmd type -->
+    <ffdc>MBMCT</ffdc>        
+    <!-- FFDC: MBMMR[4:7] contains the pattern index -->
+    <ffdc>MBMMR</ffdc>        
+    <!-- FFDC: MBSTR[59]: UE trap enable bit -->
+    <ffdc>MBSTR</ffdc>        
+    <!-- Callout MBA HIGH -->
+    <callout><target>MBA</target><priority>HIGH</priority></callout>
+    <!-- Deconfigure MBA -->
+    <deconfigure><target>MBA</target></deconfigure>
+    <!-- Create GARD record for MASTER_CHIP -->    
+    <gard><target>MBA</target></gard>    
 </hwpError>
 
   <hwpError>
@@ -411,21 +722,42 @@
   <hwpError>
     <rc>RC_MSS_DIMM_POWER_CURVE_DATA_LAB</rc>
     <description>DIMM power curve data is lab data not MSL</description>
+    <ffdc>FFDC_DATA_1</ffdc>	
+    <ffdc>FFDC_DATA_2</ffdc>	
+    <ffdc>FFDC_DATA_3</ffdc>	
+    <ffdc>FFDC_DATA_4</ffdc>	
+    <callout><target>MEM_CHIP</target><priority>HIGH</priority></callout>
 </hwpError>
 
   <hwpError>
     <rc>RC_MSS_DIMM_POWER_CURVE_DATA_INVALID</rc>
     <description>DIMM power curve data is invalid</description>
+    <ffdc>FFDC_DATA_1</ffdc>	
+    <ffdc>FFDC_DATA_2</ffdc>	
+    <ffdc>FFDC_DATA_3</ffdc>	
+    <ffdc>FFDC_DATA_4</ffdc>	
+    <callout><target>MEM_CHIP</target><priority>HIGH</priority></callout>
 </hwpError>
 
   <hwpError>
     <rc>RC_MSS_DIMM_NOT_FOUND_IN_POWER_TABLE</rc>
     <description>Unable to find matching entry in DIMM power table</description>
+    <ffdc>FFDC_DATA_1</ffdc>	
+    <ffdc>FFDC_DATA_2</ffdc>	
+    <ffdc>FFDC_DATA_3</ffdc>	
+    <callout><target>MEM_DIMM</target><priority>HIGH</priority></callout>
 </hwpError>
 
   <hwpError>
     <rc>RC_MSS_NOT_ENOUGH_AVAILABLE_DIMM_POWER</rc>
-    <description>Unable to find throttle setting that has DIMM power underneath the limit</description>
+    <description>Unable to find throttle setting that has DIMM power underneath the limit.  Callout Firmware.</description>
+    <ffdc>MEM_CHIP</ffdc>	
+    <ffdc>FFDC_DATA_1</ffdc>	
+    <ffdc>FFDC_DATA_2</ffdc>
+    <ffdc>FFDC_DATA_3</ffdc>
+    <ffdc>FFDC_DATA_4</ffdc>
+    <ffdc>FFDC_DATA_5</ffdc>
+    <!-- TODO:  callout firmware -->
 </hwpError>
 
 <hwpError>
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
index e1d9537bc..f333d5939 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit_mc.C,v 1.26 2012/09/11 14:35:22 jdsloat Exp $
+// $Id: mss_draminit_mc.C,v 1.27 2012/12/21 20:39:08 gollub Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -44,6 +44,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.27   | gollub   |21-DEC-12| Calling mss_unmask_maint_errors and mss_unmask_inband_errors after mss_draminit_mc_cloned
 //  1.25   | jdsloat  |11-SEP-12| Changed Periodic Cal to Execute via MBA regs depending upon the ZQ Cal and MEM Cal timer values; 0 = disabled
 //  1.24   | bellows  |16-JUL-12| added in Id tag
 //  1.22   | bellows  |13-JUL-12| Fixed periodic cal bit 61 being set. HW214829
@@ -88,6 +89,7 @@
 //  Centaur function Includes
 //----------------------------------------------------------------------
 #include <mss_funcs.H>
+#include <mss_unmask_errors.H>
 
 //----------------------------------------------------------------------
 //  Address Includes
@@ -103,6 +105,7 @@ using namespace fapi;
 //----------------------------------------------------------------------
 //  Subroutine declarations 
 //----------------------------------------------------------------------
+ReturnCode mss_draminit_mc_cloned(Target& i_target);
 ReturnCode mss_start_refresh (Target& i_mbatarget, Target& i_centarget);
 ReturnCode mss_enable_periodic_cal(Target& i_target);
 ReturnCode mss_set_iml_complete(Target& i_target);
@@ -111,9 +114,32 @@ ReturnCode mss_enable_control_bit_ecc(Target& i_target);
 ReturnCode mss_ccs_mode_reset(Target& i_target);
 
 
+ReturnCode mss_draminit_mc(Target& i_target)
+{
+    // Target is centaur.mba
+    
+    fapi::ReturnCode l_rc;
+    
+    l_rc = mss_draminit_mc_cloned(i_target);
+    
+	// If mss_unmask_maint_errors gets it's own bad rc,
+	// it will commit the passed in rc (if non-zero), and return it's own bad rc.
+	// Else if mss_unmask_maint_errors runs clean, 
+	// it will just return the passed in rc.
+	//l_rc = mss_unmask_maint_errors(i_target, l_rc); // TODO: uncomment after this can be tested on hw
+
+	// If mss_unmask_inband_errors gets it's own bad rc,
+	// it will commit the passed in rc (if non-zero), and return it's own bad rc.
+	// Else if mss_unmask_inband_errors runs clean, 
+	// it will just return the passed in rc.
+	//l_rc = mss_unmask_inband_errors(i_target, l_rc); // TODO: uncomment after this can be tested on hw
+
+	return l_rc;
+}
+
 
 
-ReturnCode mss_draminit_mc (Target& i_target)
+ReturnCode mss_draminit_mc_cloned(Target& i_target)
 {
 // Target is centaur
 //
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.C
index 1fad03077..9bfc137e7 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_access_delay_reg.C,v 1.10 2012/12/14 11:13:03 sasethur Exp $
+// $Id: mss_access_delay_reg.C,v 1.12 2012/12/18 15:31:39 sasethur Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -44,7 +44,10 @@
 //   1.6   | sauchadh |20-Nov-12| Made index to follow ISDIMM net for DQS and added glacier 2 suppport
 //   1.7   | sauchadh |30-Nov-12| Glacier 1 and 2 selected based on init file settings
 //   1.8   | sauchadh |5-Dec-12 | Fixed firmware comments and added DQS align DQS gate
-//   1.9   | sauchadh |14-Dec-12| Fixed Firmware comments 
+//   1.9   | sauchadh |14-Dec-12| Fixed Firmware comments
+//   1.10  | sauchadh |14-Dec-12| Fixed Firmware comments
+//   1.11  | sauchadh |18-Dec-12| Fixed Frimware comments and removed print statements in between
+//   1.12  | sauchadh |18-Dec-12| Added support for unused DQS in x8 mode
 
 
 //----------------------------------------------------------------------
@@ -74,11 +77,11 @@ extern "C" {
 //WR_DQ  - Write delay (DQ) registers
 //RD_DQS - DQS_CLK_ALIGN
 //WR_DQS - Write delay (DQS)registers
-//Input  : Target MBA=i_target_mba, i_access_type_e = READ or WRITE, i_port_u8=0 or 1, i_rank_u8=valid ranks,i_input_type_e=RD_DQ or RD_DQS or WR_DQ or WR_DQS or RAW_modes, i_input_index_u8=follow ISDIMMnet/C4 for non raw modes and supports raw modes   
+//Input  : Target MBA=i_target_mba, i_access_type_e = READ or WRITE, i_port_u8=0 or 1, i_rank_u8=valid ranks,i_input_type_e=RD_DQ or RD_DQS or WR_DQ or WR_DQS or RAW_modes, i_input_index_u8=follow ISDIMMnet/C4 for non raw modes and supports raw modes, i_verbose-extra print statements   
 //Output : delay value=io_value_u32 if i_access_type_e = READ else if i_access_type_e = WRITE no return value
 //******************************************************************************
 
-fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_type_t i_access_type_e, uint8_t i_port_u8, uint8_t i_rank_u8, input_type_t i_input_type_e, uint8_t i_input_index_u8, uint32_t &io_value_u32)
+fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_type_t i_access_type_e, uint8_t i_port_u8, uint8_t i_rank_u8, input_type_t i_input_type_e, uint8_t i_input_index_u8,uint8_t i_verbose,uint32_t &io_value_u32)
 {
    fapi::ReturnCode rc; 
     
@@ -113,11 +116,12 @@ fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_
    
    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width); if(rc) return rc;
    rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbapos);  if(rc) return rc;
-    
-   FAPI_INF("dimm type=%d",l_dimmtype);
-   
-   FAPI_INF("rank pair=%d",l_rank_pair);       
    
+   if(i_verbose==1)
+   {
+      FAPI_INF("dimm type=%d",l_dimmtype);
+      FAPI_INF("rank pair=%d",l_rank_pair);       
+   }
    if((i_port_u8 >1) || (l_mbapos>1))
    {
       FAPI_SET_HWP_ERROR(rc, RC_MSS_INPUT_ERROR);
@@ -127,8 +131,10 @@ fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_
    
    if((l_dram_width ==fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4) || (l_dram_width ==fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8))   // Checking for dram width here so that checking can be skipped in called function
    {
-      FAPI_INF("dram width=%d",l_dram_width);
-      
+      if(i_verbose==1)
+      {
+         FAPI_INF("dram width=%d",l_dram_width);
+      }
    }
    
    else
@@ -171,13 +177,19 @@ fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_
       }
       
          
-      rc=rosetta_map(i_target_mba,i_port_u8,l_type,i_input_index_u8,l_val); if(rc) return rc;
+      rc=rosetta_map(i_target_mba,i_port_u8,l_type,i_input_index_u8,i_verbose,l_val); if(rc) return rc;
       
-      FAPI_INF("C4 value is=%d",l_val);
-      rc=cross_coupled(i_target_mba,i_port_u8,l_rank_pair,i_input_type_e,l_val,l_out); if(rc) return rc;
-      FAPI_INF("scom_address=%llX",l_out.scom_addr);
-      FAPI_INF("start bit=%d",l_out.start_bit);
-      FAPI_INF("length=%d",l_out.bit_length); 
+      if(i_verbose==1)
+      {
+         FAPI_INF("C4 value is=%d",l_val);
+      }   
+      rc=cross_coupled(i_target_mba,i_port_u8,l_rank_pair,i_input_type_e,l_val,i_verbose,l_out); if(rc) return rc;
+      if(i_verbose==1)
+      {
+         FAPI_INF("scom_address=%llX",l_out.scom_addr);
+         FAPI_INF("start bit=%d",l_out.start_bit);
+         FAPI_INF("length=%d",l_out.bit_length);
+      }   
       l_scom_add=l_out.scom_addr;
       l_sbit=l_out.start_bit;
       l_len=l_out.bit_length;
@@ -203,12 +215,18 @@ fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_
       }
       
       
-      rc=rosetta_map(i_target_mba,i_port_u8,l_type,i_input_index_u8,l_val); if(rc) return rc;
-      FAPI_INF("C4 value is=%d",l_val);
-      rc=cross_coupled(i_target_mba,i_port_u8,l_rank_pair,i_input_type_e,l_val,l_out); if(rc) return rc;
-      FAPI_INF("scom_address=%llX",l_out.scom_addr);
-      FAPI_INF("start bit=%d",l_out.start_bit);
-      FAPI_INF("length=%d",l_out.bit_length); 
+      rc=rosetta_map(i_target_mba,i_port_u8,l_type,i_input_index_u8,i_verbose,l_val); if(rc) return rc;
+      if(i_verbose==1)
+      {
+         FAPI_INF("C4 value is=%d",l_val);
+      }
+      rc=cross_coupled(i_target_mba,i_port_u8,l_rank_pair,i_input_type_e,l_val,i_verbose,l_out); if(rc) return rc;
+      if(i_verbose==1)
+      {
+         FAPI_INF("scom_address=%llX",l_out.scom_addr);
+         FAPI_INF("start bit=%d",l_out.start_bit);
+         FAPI_INF("length=%d",l_out.bit_length); 
+      }
       l_scom_add=l_out.scom_addr;
       l_sbit=l_out.start_bit;
       l_len=l_out.bit_length;   
@@ -251,15 +269,20 @@ fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_
       }
      
       ip_type_t l_input=RAW_WR_DQ;
-      FAPI_INF("block=%d",l_block);
-      FAPI_INF("lane=%d",l_lane);
+      if(i_verbose==1)
+      {
+         FAPI_INF("block=%d",l_block);
+         FAPI_INF("lane=%d",l_lane);
+      }
       rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
       l_sbit=l_start_bit;    
       l_len=l_len8;
-      FAPI_INF("scom_address=%llX",l_scom_add);
-      FAPI_INF("start bit=%d",l_start_bit);
-      FAPI_INF("length=%d",l_len8); 
-      
+      if(i_verbose==1)
+      {
+         FAPI_INF("scom_address=%llX",l_scom_add);
+         FAPI_INF("start bit=%d",l_start_bit);
+         FAPI_INF("length=%d",l_len8); 
+      }
    }
    
    else if(i_input_type_e==RAW_RD_DQ_0 || i_input_type_e==RAW_RD_DQ_1 || i_input_type_e==RAW_RD_DQ_2 || i_input_type_e==RAW_RD_DQ_3 || i_input_type_e==RAW_RD_DQ_4)
@@ -295,15 +318,20 @@ fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_
          return rc;      
       }
       ip_type_t l_input=RAW_RD_DQ;
-      FAPI_INF("block=%d",l_block);
-      FAPI_INF("lane=%d",l_lane);
+      if(i_verbose==1)
+      {
+         FAPI_INF("block=%d",l_block);
+         FAPI_INF("lane=%d",l_lane);
+      }
       rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
       l_sbit=l_start_bit;    
       l_len=l_len8;
-      FAPI_INF("scom_address=%llX",l_scom_add);
-      FAPI_INF("start bit=%d",l_start_bit);
-      FAPI_INF("length=%d",l_len8); 
-      
+      if(i_verbose==1)
+      {
+         FAPI_INF("scom_address=%llX",l_scom_add);
+         FAPI_INF("start bit=%d",l_start_bit);
+         FAPI_INF("length=%d",l_len8); 
+      }
    }
    
    else if(i_input_type_e==RAW_RD_DQS_0 || i_input_type_e==RAW_RD_DQS_1 || i_input_type_e==RAW_RD_DQS_2 || i_input_type_e==RAW_RD_DQS_3 || i_input_type_e==RAW_RD_DQS_4)
@@ -340,15 +368,20 @@ fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_
       }
       
       ip_type_t l_input=RAW_RD_DQS;
-      FAPI_INF("block=%d",l_block);
-      FAPI_INF("lane=%d",l_lane);
+      if(i_verbose==1)
+      {
+         FAPI_INF("block=%d",l_block);
+         FAPI_INF("lane=%d",l_lane);
+      }
       rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
       l_sbit=l_start_bit;    
       l_len=l_len8;
-      FAPI_INF("scom_address=%llX",l_scom_add);
-      FAPI_INF("start bit=%d",l_start_bit);
-      FAPI_INF("length=%d",l_len8); 
-      
+      if(i_verbose==1)
+      {
+         FAPI_INF("scom_address=%llX",l_scom_add);
+         FAPI_INF("start bit=%d",l_start_bit);
+         FAPI_INF("length=%d",l_len8); 
+      }
    }
    
    else if(i_input_type_e==RAW_DQS_ALIGN_0 || i_input_type_e==RAW_DQS_ALIGN_1 || i_input_type_e==RAW_DQS_ALIGN_2 || i_input_type_e==RAW_DQS_ALIGN_3 || i_input_type_e==RAW_DQS_ALIGN_4)
@@ -384,15 +417,20 @@ fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_
          return rc;      
       }
       ip_type_t l_input=RAW_DQS_ALIGN;
-      FAPI_INF("block=%d",l_block);
-      FAPI_INF("lane=%d",l_lane);
+      if(i_verbose==1)
+      {
+         FAPI_INF("block=%d",l_block);
+         FAPI_INF("lane=%d",l_lane);
+      }
       rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
       l_sbit=l_start_bit;    
       l_len=l_len8;
-      FAPI_INF("scom_address=%llX",l_scom_add);
-      FAPI_INF("start bit=%d",l_start_bit);
-      FAPI_INF("length=%d",l_len8); 
-      
+      if(i_verbose==1)
+      {
+         FAPI_INF("scom_address=%llX",l_scom_add);
+         FAPI_INF("start bit=%d",l_start_bit);
+         FAPI_INF("length=%d",l_len8); 
+      }
    }
    
    
@@ -429,15 +467,20 @@ fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_
          return rc; 
       }
       ip_type_t l_input=RAW_WR_DQS;
-      FAPI_INF("block=%d",l_block);
-      FAPI_INF("lane=%d",l_lane);
+      if(i_verbose==1)
+      {
+         FAPI_INF("block=%d",l_block);
+         FAPI_INF("lane=%d",l_lane);
+      }
       rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
       l_sbit=l_start_bit;    
       l_len=l_len8;
-      FAPI_INF("scom_address=%llX",l_scom_add);
-      FAPI_INF("start bit=%d",l_start_bit);
-      FAPI_INF("length=%d",l_len8); 
-      
+      if(i_verbose==1)
+      {
+         FAPI_INF("scom_address=%llX",l_scom_add);
+         FAPI_INF("start bit=%d",l_start_bit);
+         FAPI_INF("length=%d",l_len8); 
+      }
    }
    else if(i_input_type_e==RAW_SYS_CLK_0 || i_input_type_e==RAW_SYS_CLK_1 || i_input_type_e==RAW_SYS_CLK_2 || i_input_type_e==RAW_SYS_CLK_3 || i_input_type_e==RAW_SYS_CLK_4)
    {
@@ -472,15 +515,20 @@ fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_
          return rc; 
       }
       ip_type_t l_input=RAW_SYS_CLK;
-      FAPI_INF("block=%d",l_block);
-      FAPI_INF("lane=%d",l_lane);
+      if(i_verbose==1)
+      {
+         FAPI_INF("block=%d",l_block);
+         FAPI_INF("lane=%d",l_lane);
+      }
       rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
       l_sbit=l_start_bit;    
       l_len=l_len8;
-      FAPI_INF("scom_address=%llX",l_scom_add);
-      FAPI_INF("start bit=%d",l_start_bit);
-      FAPI_INF("length=%d",l_len8); 
-      
+      if(i_verbose==1)
+      {
+         FAPI_INF("scom_address=%llX",l_scom_add);
+         FAPI_INF("start bit=%d",l_start_bit);
+         FAPI_INF("length=%d",l_len8); 
+      }
    }
    
    else if(i_input_type_e==RAW_SYS_ADDR_CLK)
@@ -496,14 +544,19 @@ fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_
          return rc; 
       }
       ip_type_t l_input=RAW_SYS_ADDR_CLKS0S1;
-      FAPI_INF("lane=%d",l_lane);
+      if(i_verbose==1)
+      {
+         FAPI_INF("lane=%d",l_lane);
+      }
       rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
       l_sbit=l_start_bit;    
       l_len=l_len8;
-      FAPI_INF("scom_address=%llX",l_scom_add);
-      FAPI_INF("start bit=%d",l_start_bit);
-      FAPI_INF("length=%d",l_len8); 
-      
+      if(i_verbose==1)
+      {
+         FAPI_INF("scom_address=%llX",l_scom_add);
+         FAPI_INF("start bit=%d",l_start_bit);
+         FAPI_INF("length=%d",l_len8); 
+      }
    }
    
    
@@ -540,15 +593,20 @@ fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_
          return rc; 
       }
       ip_type_t l_input=RAW_WR_CLK;
-      FAPI_INF("block=%d",l_block);
-      FAPI_INF("lane=%d",l_lane);
+      if(i_verbose==1)
+      {
+         FAPI_INF("block=%d",l_block);
+         FAPI_INF("lane=%d",l_lane);
+      }
       rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
       l_sbit=l_start_bit;    
       l_len=l_len8;
-      FAPI_INF("scom_address=%llX",l_scom_add);
-      FAPI_INF("start bit=%d",l_start_bit);
-      FAPI_INF("length=%d",l_len8); 
-      
+      if(i_verbose==1)
+      {
+         FAPI_INF("scom_address=%llX",l_scom_add);
+         FAPI_INF("start bit=%d",l_start_bit);
+         FAPI_INF("length=%d",l_len8); 
+      }
    }
    
    else if(i_input_type_e==RAW_ADDR_0 || i_input_type_e==RAW_ADDR_1 || i_input_type_e==RAW_ADDR_2 || i_input_type_e==RAW_ADDR_3)
@@ -580,15 +638,20 @@ fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_
          return rc; 
       }
       ip_type_t l_input=RAW_ADDR;
-      FAPI_INF("block=%d",l_block);
-      FAPI_INF("lane=%d",l_lane);
+      if(i_verbose==1)
+      {
+         FAPI_INF("block=%d",l_block);
+         FAPI_INF("lane=%d",l_lane);
+      }
       rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
       l_sbit=l_start_bit;    
       l_len=l_len8;
-      FAPI_INF("scom_address=%llX",l_scom_add);
-      FAPI_INF("start bit=%d",l_start_bit);
-      FAPI_INF("length=%d",l_len8); 
-      
+      if(i_verbose==1)
+      {
+         FAPI_INF("scom_address=%llX",l_scom_add);
+         FAPI_INF("start bit=%d",l_start_bit);
+         FAPI_INF("length=%d",l_len8); 
+      }
    }
   
    else if(i_input_type_e==RAW_DQS_GATE_0 || i_input_type_e==RAW_DQS_GATE_1 || i_input_type_e==RAW_DQS_GATE_2 || i_input_type_e==RAW_DQS_GATE_3 || i_input_type_e==RAW_DQS_GATE_4)
@@ -625,15 +688,20 @@ fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_
          return rc; 
       }
       ip_type_t l_input=RAW_DQS_GATE;
-      FAPI_INF("block=%d",l_block);
-      FAPI_INF("lane=%d",l_lane);
+      if(i_verbose==1)
+      {
+         FAPI_INF("block=%d",l_block);
+         FAPI_INF("lane=%d",l_lane);
+      }
       rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
       l_sbit=l_start_bit;    
       l_len=l_len8;
-      FAPI_INF("scom_address=%llX",l_scom_add);
-      FAPI_INF("start bit=%d",l_start_bit);
-      FAPI_INF("length=%d",l_len8); 
-      
+      if(i_verbose==1)
+      {
+         FAPI_INF("scom_address=%llX",l_scom_add);
+         FAPI_INF("start bit=%d",l_start_bit);
+         FAPI_INF("length=%d",l_len8); 
+      }
    } 
    
    else
@@ -654,6 +722,7 @@ fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_
         return rc;
       }    
       io_value_u32=l_output;
+      FAPI_INF("Delay value=%d",io_value_u32);
    }
    
    else if(i_access_type_e==WRITE)
@@ -677,8 +746,8 @@ fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_
       }
       else
       {
-         FAPI_ERR("Wrong input value specified rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
          FAPI_SET_HWP_ERROR(rc, RC_MSS_INPUT_ERROR);
+         FAPI_ERR("Wrong input type specified rc = 0x%08X ", uint32_t(rc));
          return rc;      
       }
       rc=fapiGetScom(i_target_mba,l_scom_add,data_buffer_64);if(rc) return rc;	  
@@ -700,11 +769,11 @@ fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_
 //******************************************************************************
 //Function name: cross_coupled()
 //Description:This function returns address,start bit and bit length for RD_DQ, WR_DQ, RD_DQS, WR_DQS
-//Input  : Target MBA=i_target_mba, i_port_u8=0 or 1, i_rank_pair=0 or 1 or 2 or 3, i_input_type_e=RD_DQ or RD_DQS or WR_DQ or WR_DQS,i_input_index_u8=0-79/0-71/0-8/0-19   
+//Input  : Target MBA=i_target_mba, i_port_u8=0 or 1, i_rank_pair=0 or 1 or 2 or 3, i_input_type_e=RD_DQ or RD_DQS or WR_DQ or WR_DQS,i_input_index_u8=0-79/0-71/0-8/0-19 , i_verbose-extra print statements  
 //Output : out (address,start bit and bit length)
 //******************************************************************************    
         
-fapi::ReturnCode cross_coupled(const fapi::Target & i_target_mba,uint8_t i_port, uint8_t i_rank_pair,input_type_t i_input_type_e,uint8_t i_input_index,scom_location& out)
+fapi::ReturnCode cross_coupled(const fapi::Target & i_target_mba,uint8_t i_port, uint8_t i_rank_pair,input_type_t i_input_type_e,uint8_t i_input_index,uint8_t i_verbose,scom_location& out)
 {    
    fapi::ReturnCode rc; 
    const uint8_t l_dqmax=80;
@@ -737,12 +806,18 @@ fapi::ReturnCode cross_coupled(const fapi::Target & i_target_mba,uint8_t i_port,
    uint8_t l_len=0;
    ip_type_t l_input_type;
    ecmdDataBufferBase data_buffer_64(64);
+   uint8_t l_dimmtype=0;
+   uint8_t l_swizzle=0;
+      
+   rc = FAPI_ATTR_GET(ATTR_MSS_DQS_SWIZZLE_TYPE, &i_target_mba, l_swizzle); if(rc) return rc;
       
    rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbapos); if(rc) return rc;
+   
+   rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, l_dimmtype); if(rc) return rc;
          
    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width); if(rc) return rc;
    
-     
+      
    if(i_input_type_e==RD_DQ || i_input_type_e==WR_DQ)
    {
       if(i_port==0 && l_mbapos==0)
@@ -765,10 +840,12 @@ fapi::ReturnCode cross_coupled(const fapi::Target & i_target_mba,uint8_t i_port,
 	 l_lane=lane_dq_p3[i_input_index];
 	 l_block=block_p3[i_input_index];	
       }
-            
-      FAPI_INF("block=%d",l_block);
-      FAPI_INF("lane=%d",l_lane);
-       
+      
+      if(i_verbose==1)
+      {
+         FAPI_INF("block=%d",l_block);
+         FAPI_INF("lane=%d",l_lane);
+      } 
       if(i_input_type_e==RD_DQ)
       {
          l_input_type=RD_DQ_t;
@@ -809,12 +886,18 @@ fapi::ReturnCode cross_coupled(const fapi::Target & i_target_mba,uint8_t i_port,
          l_dq=dqs_dq_lane_p3[i_input_index];   
          l_block=block_dqs_p3[i_input_index]; 
       }
-         
-      FAPI_INF("block=%d",l_block);
-      FAPI_INF("dqs_dq_lane=%d",l_dq);
+       
+      if(i_verbose==1)
+      {
+         FAPI_INF("block=%d",l_block);
+         FAPI_INF("dqs_dq_lane=%d",l_dq);
+      }
       l_input_type=RD_CLK_t; 
       rc=get_address(i_target_mba,i_port,i_rank_pair, l_input_type,l_block,l_lane,l_scom_address_64,l_start_bit,l_len); if(rc) return rc;
-      FAPI_INF("read clock address=%llx",l_scom_address_64);
+      if(i_verbose==1)
+      {
+         FAPI_INF("read clock address=%llx",l_scom_address_64);
+      }
       rc=fapiGetScom(i_target_mba,l_scom_address_64,data_buffer_64);if(rc) return rc; 
             
       if(l_dram_width==fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4)
@@ -863,8 +946,11 @@ fapi::ReturnCode cross_coupled(const fapi::Target & i_target_mba,uint8_t i_port,
          {
             lane_dqs[l_index]=22;
             l_index++;
+         }
+         if(i_verbose==1)
+         {
+            FAPI_INF("array is=%d and %d and %d and %d",lane_dqs[0],lane_dqs[1],lane_dqs[2],lane_dqs[3]);
          }   
-         FAPI_INF("array is=%d and %d and %d and %d",lane_dqs[0],lane_dqs[1],lane_dqs[2],lane_dqs[3]);
          if(l_dq==0)
          {
             l_lane=lane_dqs[0];
@@ -881,9 +967,11 @@ fapi::ReturnCode cross_coupled(const fapi::Target & i_target_mba,uint8_t i_port,
          {
             l_lane=lane_dqs[3];
          }
-          
-         FAPI_INF("lane is=%d",l_lane); 
          
+         if(i_verbose==1)
+         {
+            FAPI_INF("lane is=%d",l_lane); 
+         }
       }			  
    
      
@@ -909,8 +997,10 @@ fapi::ReturnCode cross_coupled(const fapi::Target & i_target_mba,uint8_t i_port,
             lane_dqs[l_index]=22;
             l_index++; 		    
          }
-         FAPI_INF("array is=%d and %d",lane_dqs[0],lane_dqs[1]); 
-          
+         if(i_verbose==1)
+         {
+            FAPI_INF("array is=%d and %d",lane_dqs[0],lane_dqs[1]); 
+         } 
          if((l_dq==0) || (l_dq==4))
          {
             l_lane=lane_dqs[0];
@@ -920,8 +1010,177 @@ fapi::ReturnCode cross_coupled(const fapi::Target & i_target_mba,uint8_t i_port,
             l_lane=lane_dqs[1];
          }
          
-         FAPI_INF("lane is=%d",l_lane);
-      }
+         if(l_dimmtype==fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM)
+         {
+            if((i_input_index==1) || (i_input_index==3) || (i_input_index==5) || (i_input_index==7) || (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) || (i_input_index==17) || (i_input_index==19))
+            {
+               if(l_lane==16)
+               {
+                  l_lane=18;
+               }
+               else if(l_lane==18)
+               {
+                  l_lane=16;
+               }
+               
+               else if(l_lane==20)
+               {
+                  l_lane=22;
+               }
+               
+               else
+               {
+                  l_lane=20;
+               }
+               
+            }
+         }
+         
+         else
+         {
+            if((i_port==0) && (l_mbapos==0))
+            {
+               if(l_swizzle==1)
+               {
+                  if((i_input_index==3) || (i_input_index==1) || (i_input_index==4) || (i_input_index==17)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) ||  (i_input_index==6))
+                  {
+                     if(l_lane==16)
+                     {
+                        l_lane=18;
+                     }
+                     else if(l_lane==18)
+                     {
+                        l_lane=16;
+                     }
+                     
+                     else if(l_lane==20)
+                     {
+                        l_lane=22;
+                     }
+                     
+                     else
+                     {
+                        l_lane=20;
+                     }
+                  
+                  }   
+               }
+                           
+               else
+               {
+                  if((i_input_index==3) || (i_input_index==1) || (i_input_index==5) || (i_input_index==7)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) ||  (i_input_index==17))
+                  {
+                     if(l_lane==16)
+                     {
+                        l_lane=18;
+                     }
+                     else if(l_lane==18)
+                     {
+                        l_lane=16;
+                     }
+                       
+                     else if(l_lane==20)
+                     {
+                        l_lane=22;
+                     }
+                       
+                     else
+                     {
+                        l_lane=20;
+                     }
+                  }   
+                          
+               }
+            }   
+            
+            else if((i_port==1) && (l_mbapos==0))
+            {
+               if(l_swizzle==1)
+               {
+                  if((i_input_index==2) || (i_input_index==0) || (i_input_index==4) || (i_input_index==17)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) ||  (i_input_index==7))
+                  {
+                     if(l_lane==16)
+                     {
+                        l_lane=18;
+                     }
+                     else if(l_lane==18)
+                     {
+                        l_lane=16;
+                     }
+                     
+                     else if(l_lane==20)
+                     {
+                        l_lane=22;
+                     }
+                  
+                     else
+                     {
+                        l_lane=20;
+                     }
+                  }   
+               }
+               
+               else
+               {
+                  if((i_input_index==1) || (i_input_index==3) || (i_input_index==5) || (i_input_index==7)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) ||  (i_input_index==17))
+                  {
+                     if(l_lane==16)
+                     {
+                        l_lane=18;
+                     }
+                     else if(l_lane==18)
+                     {
+                        l_lane=16;
+                     }
+                     
+                     else if(l_lane==20)
+                     {
+                        l_lane=22;
+                     }
+                  
+                     else
+                     {
+                        l_lane=20;
+                     }
+                  }   
+               }
+            }
+                  
+                  
+            else
+            {
+               if((i_input_index==1) || (i_input_index==3) || (i_input_index==5) || (i_input_index==7)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) ||  (i_input_index==17))
+               {
+                  if(l_lane==16)
+                  {
+                     l_lane=18;
+                  }
+                  else if(l_lane==18)
+                  {
+                     l_lane=16;
+                  }
+                  
+                  else if(l_lane==20)
+                  {
+                     l_lane=22;
+                  }
+                  
+                  else
+                  {
+                     l_lane=20;
+                  }
+               
+               }   
+            }
+            
+            
+            
+         }
+         if(i_verbose==1)
+         {
+            FAPI_INF("lane is=%d",l_lane);
+         }   
+      }  
       
       if (i_input_type_e==RD_DQS)
       {
@@ -968,9 +1227,11 @@ fapi::ReturnCode cross_coupled(const fapi::Target & i_target_mba,uint8_t i_port,
          l_block=block_dqs_p3[i_input_index]; 
       }
       
-      FAPI_INF("block=%d",l_block);
-      FAPI_INF("dqs_dq_lane=%d",l_dq);
-         
+      if(i_verbose==1)
+      {
+         FAPI_INF("block=%d",l_block);
+         FAPI_INF("dqs_dq_lane=%d",l_dq);
+      }   
       if(l_dq==0)
       {
          l_lane=16;
@@ -992,9 +1253,11 @@ fapi::ReturnCode cross_coupled(const fapi::Target & i_target_mba,uint8_t i_port,
       }  
      
       l_input_type=DQS_GATE_t;
-         
-      FAPI_INF("lane is=%d",l_lane);
-         
+      
+      if(i_verbose==1)
+      {
+         FAPI_INF("lane is=%d",l_lane);
+      }   
       rc=get_address(i_target_mba,i_port,i_rank_pair,l_input_type,l_block,l_lane,l_scom_address_64,l_start_bit,l_len); if(rc) return rc; 		 
       out.scom_addr=l_scom_address_64;
       out.start_bit=l_start_bit;
@@ -1016,11 +1279,11 @@ fapi::ReturnCode cross_coupled(const fapi::Target & i_target_mba,uint8_t i_port,
 //******************************************************************************
 //Function name: rosetta_map()
 //Description:This function returns C4 bit for the corresponding ISDIMM bit
-//Input  : Target MBA=i_target_mba, i_port_u8=0 or 1,i_input_type_e=RD_DQ or RD_DQS or WR_DQ or WR_DQS, i_input_index_u8=0-79/0-71/0-8/0-19   
+//Input  : Target MBA=i_target_mba, i_port_u8=0 or 1,i_input_type_e=RD_DQ or RD_DQS or WR_DQ or WR_DQS, i_input_index_u8=0-79/0-71/0-8/0-19, i_verbose-extra print statements    
 //Output : C4 bit=o_value
 //****************************************************************************** 
    
-fapi::ReturnCode rosetta_map(const fapi::Target & i_target_mba,uint8_t i_port,input_type i_input_type_e,uint8_t i_input_index,uint8_t &o_value) //This function is used by some other procedures
+fapi::ReturnCode rosetta_map(const fapi::Target & i_target_mba,uint8_t i_port,input_type i_input_type_e,uint8_t i_input_index,uint8_t i_verbose,uint8_t &o_value) //This function is used by some other procedures
 {                                                                                                                                              // Boundary check is done again 
    fapi::ReturnCode rc;
    
@@ -1050,8 +1313,12 @@ fapi::ReturnCode rosetta_map(const fapi::Target & i_target_mba,uint8_t i_port,in
    
    if(l_swizzle ==0 || l_swizzle ==1)
    {
-      FAPI_INF("swizzle type=%d",l_swizzle);
+      if(i_verbose==1)
+      {
+         FAPI_INF("swizzle type=%d",l_swizzle);
+      }   
    }
+   
    else
    {
       FAPI_SET_HWP_ERROR(rc, RC_MSS_INPUT_ERROR);
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.H
index bebaef857..229656866 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.H
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-//$Id: mss_access_delay_reg.H,v 1.5 2012/12/05 16:50:29 sasethur Exp $
+//$Id: mss_access_delay_reg.H,v 1.6 2012/12/18 12:02:33 sasethur Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -158,20 +158,20 @@ struct scom_location {
 };	
 
 
-typedef fapi::ReturnCode (*mss_access_delay_reg_FP_t)(const fapi::Target & i_target_mba, access_type_t i_access_type_e, uint8_t i_port_u8, uint8_t i_rank_u8, input_type_t i_input_type_e, uint8_t i_input_index_u8, uint32_t &io_value_u32);
+typedef fapi::ReturnCode (*mss_access_delay_reg_FP_t)(const fapi::Target & i_target_mba, access_type_t i_access_type_e, uint8_t i_port_u8, uint8_t i_rank_u8, input_type_t i_input_type_e, uint8_t i_input_index_u8,uint8_t i_verbose, uint32_t &io_value_u32);
 
 
 
 extern "C" {
 
 //------------------------------------------------------------------------------
-fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_type_t i_access_type_e, uint8_t i_port_u8, uint8_t i_rank_u8, input_type_t i_input_type_e, uint8_t i_input_index_u8, uint32_t &io_value_u32);
+fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba, access_type_t i_access_type_e, uint8_t i_port_u8, uint8_t i_rank_u8, input_type_t i_input_type_e, uint8_t i_input_index_u8,uint8_t i_verbose, uint32_t &io_value_u32);
 
-fapi::ReturnCode cross_coupled(const fapi::Target & i_target_mba,uint8_t i_port, uint8_t i_rank_pair,input_type_t i_input_type_e,uint8_t i_input_index,scom_location& out);
+fapi::ReturnCode cross_coupled(const fapi::Target & i_target_mba,uint8_t i_port, uint8_t i_rank_pair,input_type_t i_input_type_e,uint8_t i_input_index,uint8_t i_verbose,scom_location& out);
 
 fapi::ReturnCode get_address(const fapi::Target & i_target_mba,uint8_t i_port, uint8_t i_rank_pair,ip_type_t i_input_type_e,uint8_t i_block,uint8_t i_lane,uint64_t &o_scom_address_64,uint8_t &o_start_bit,uint8_t &o_len);
 
-fapi::ReturnCode rosetta_map(const fapi::Target & i_target_mba,uint8_t i_port, input_type i_input_type_e ,uint8_t i_input_index,uint8_t &o_value); 
+fapi::ReturnCode rosetta_map(const fapi::Target & i_target_mba,uint8_t i_port, input_type i_input_type_e ,uint8_t i_input_index,uint8_t i_verbose,uint8_t &o_value); 
 
 fapi::ReturnCode mss_getrankpair(const fapi::Target & i_target_mba,uint8_t i_port,uint8_t i_rank,uint8_t *o_rank_pair,uint8_t o_rankpair_table[8]);
 } // extern "C"
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C
index 16a5b259d..021ba35eb 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_generic_shmoo.C,v 1.16 2012/12/14 16:09:53 sasethur Exp $
+// $Id: mss_generic_shmoo.C,v 1.18 2012/12/18 15:23:47 sasethur Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -39,6 +39,7 @@
 //------------------------------------------------------------------------------
 // Version:|Author: | Date:   | Comment:
 // --------|--------|---------|--------------------------------------------------
+//   1.18  |sasethur|14-DEC-12| Updated for change in access delay function 
 //   1.16  |sasethur|14-DEC-12| Updated for Warning 
 //   1.15  |abhijit |13-DEC-12| Updated for FW review comments 
 //   1.14  |abhijit |06-DEC-12| Fixed more FW review comments
@@ -213,11 +214,11 @@ fapi::ReturnCode generic_shmoo::run(const fapi::Target & i_target,uint32_t *o_ri
     // If memory is OK then we continue to gather nominals and config values
     //  Now Read nominal values for all knobs configured
     // FAPI_DBG("mss_generic_shmoo : run() :read nominal values ");
-    //rc=get_all_noms(i_target);if(rc) return rc;
+    rc=get_all_noms(i_target);if(rc) return rc;
     //Find RIGHT BOUND OR SETUP BOUND
-    //rc=find_bound(i_target,RIGHT);if(rc) return rc;
+    rc=find_bound(i_target,RIGHT);if(rc) return rc;
     //Find LEFT BOUND OR HOLD BOUND
-    //rc=find_bound(i_target,LEFT);if(rc) return rc;
+    rc=find_bound(i_target,LEFT);if(rc) return rc;
     //Find the margins in Ps i.e setup margin ,hold margin,Eye width 
     rc=get_margin(i_target);if(rc) return rc;
     //It is used to find the lowest of setup and hold margin
@@ -402,7 +403,7 @@ fapi::ReturnCode generic_shmoo::do_mcbist_test(const fapi::Target & i_target,uin
     if(iv_dmm_type==1)
     {
 	i_input_index_u8=8*i_byte+4*i_nibble;
-	rc=rosetta_map(i_target,iv_port,l_input_type_e,i_input_index_u8,l_val);if(rc) return rc;
+	rc=rosetta_map(i_target,iv_port,l_input_type_e,i_input_index_u8,0,l_val);if(rc) return rc;
 	i_byte=l_val/8;
 	i_nibble=l_val%4;
 	check_error_map(i_rank,i_byte,i_nibble,pass);
@@ -546,7 +547,7 @@ fapi::ReturnCode generic_shmoo::get_all_noms(const fapi::Target & i_target)
                 {  
 		    l_dq=8*l_byte+4*l_nibble+l_bit;
 		    
-		    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,i_rnk,l_input_type_e,l_dq,val);if(rc) return rc; 
+		    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,i_rnk,l_input_type_e,l_dq,0,val);if(rc) return rc; 
 		    SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rnk].K.nom_val[l_dq][i_rp]=val;
 		    FAPI_INF("Nominal  Value for rank=%d  and rank pair=%d and dq=%d is  %d",i_rnk,i_rp,l_dq,val);
                     
@@ -569,8 +570,8 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_
     ecmdDataBufferBase data_buffer_64(64);
     ecmdDataBufferBase data_buffer_64_1(64);
     uint32_t l_current_val=0;
-    uint32_t l_left_del=20;
-    uint32_t l_right_del=400;
+    uint32_t l_left_del=2;
+    uint32_t l_right_del=10;
     uint32_t l_max_value=0;
     uint32_t l_min_value=0;
     uint16_t l_nibb_err_chk=2*byte+nibble;
@@ -608,7 +609,7 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_
 	    for(l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp];((l_current_val >= l_left_del)&&(pass==1));l_current_val-=l_left_del)
 	    {
 		FAPI_DBG("  The current value inside left bound for dq=%d and rp=%d  is %d  ",l_dq,l_rp,l_current_val);
-		rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,l_current_val);if(rc) return rc;
+		rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc;
 		rc=do_mcbist_test(i_target,rank,byte,nibble,pass);
 		if(rc)
 		{   
@@ -621,7 +622,7 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_
 		pass=1;
 		for(l_current_val=l_current_val+10;((l_current_val>l_min_value)&&(pass==1));l_current_val--)
 		{ 
-		    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,l_current_val);if(rc) return rc;
+		    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc;
 		    rc = fapiGetScom(i_target,MBA01_MBA_PMU0Q_0x03010437,data_buffer_64); if(rc) return rc;
 		    l_rd_cnt_A = data_buffer_64.getDoubleWord(0);
 			do
@@ -698,7 +699,7 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_
 	    }
 	    l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp];
 		FAPI_INF("  the restoring nominal value for rank=%d dq=%d and rp=%d is %d",rank,l_dq,l_rp,l_current_val);
-	    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,l_current_val);if(rc) return rc;
+	    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc;
 	}
     }	
     if(bound==RIGHT)
@@ -709,7 +710,7 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_
 	    for(l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp];((l_current_val<l_max_value)&&(pass==1));l_current_val+=l_right_del)
 	    {
 		FAPI_DBG("  The current value inside right bound dq=%d and rp=%d  is %d  ",l_dq,l_rp,l_current_val);
-		rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,l_current_val);if(rc) return rc;
+		rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc;
 		rc=do_mcbist_test(i_target,rank,byte,nibble,pass);
 		if(rc)
 		{   
@@ -723,7 +724,7 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_
 		pass=1;
 		for(l_current_val=l_current_val-20;((l_current_val<l_max_value)&&(pass==1));l_current_val++)
 		{
-		    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,l_current_val);if(rc) return rc;
+		    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc;
 		    rc = fapiGetScom(i_target,MBA01_MBA_PMU0Q_0x03010437,data_buffer_64); if(rc) return rc;
 		    l_rd_cnt_A = data_buffer_64.getDoubleWord(0);
 		    do
@@ -805,7 +806,7 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_
 	    FAPI_INF("   the right bound %d ",SHMOO[scenario].MBA.P[iv_port].S[rank].K.rb_regval[l_dq][l_rp]);
 	    l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp];
 		FAPI_INF("  the restoring nominal value for rank=%d dq=%d and rp=%d is %d",rank,l_dq,l_rp,l_current_val);
-	    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,l_current_val);if(rc) return rc;
+	    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc;
 	    
 	}
     }
@@ -853,7 +854,7 @@ fapi::ReturnCode generic_shmoo::knob_update_dqs(const fapi::Target & i_target,bo
 	    {
 		    //use saurabh function for writing here 
 		    FAPI_INF("  curr val in left = %d and pass=%d ",l_current_val,pass);
-		    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,0,l_input_type_e,l_dq,l_current_val);if(rc) return rc;
+		    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,0,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc;
 		    
 		    rc=do_mcbist_test(i_target,rank,byte,nibble,pass);
 		    if(rc)
@@ -868,7 +869,7 @@ fapi::ReturnCode generic_shmoo::knob_update_dqs(const fapi::Target & i_target,bo
 	    }
 	    FAPI_INF("  left  bound = %d  ",SHMOO[scenario].MBA.P[iv_port].S[rank].K.rb_regval[l_dq][l_rp]);
 	    l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp];
-	    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,0,l_input_type_e,l_dq,l_current_val);if(rc) return rc;
+	    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,0,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc;
 	    
 	}
     }
@@ -883,7 +884,7 @@ fapi::ReturnCode generic_shmoo::knob_update_dqs(const fapi::Target & i_target,bo
 	    {
 		    //use saurabh function for writing here 
 		    FAPI_INF("  curr val  = %d ",l_current_val);
-		    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,0,l_input_type_e,l_dq,l_current_val);if(rc) return rc;
+		    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,0,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc;
 		    
 		    rc=do_mcbist_test(i_target,rank,byte,nibble,pass);
 		    if(rc)
@@ -898,7 +899,7 @@ fapi::ReturnCode generic_shmoo::knob_update_dqs(const fapi::Target & i_target,bo
 	    }
 	    l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp];
 		
-	    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,0,l_input_type_e,l_dq,l_current_val);if(rc) return rc;
+	    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,0,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc;
 	    FAPI_INF("  right bound = %d  ",SHMOO[scenario].MBA.P[iv_port].S[rank].K.rb_regval[l_dq][l_rp]);
         }
 	    
@@ -1076,7 +1077,7 @@ fapi::ReturnCode generic_shmoo::get_margin(const fapi::Target & i_target)
 			for(l_bit=0;l_bit< MAX_BITS;++l_bit)
 			{
 			    l_dq=8*l_byte+4*l_nibble+l_bit;
-			    FAPI_INF("  the right bound = %d and nominal = %d",SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.rb_regval[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.nom_val[l_dq][l_rp]);
+			    //FAPI_INF("  the right bound = %d and nominal = %d",SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.rb_regval[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.nom_val[l_dq][l_rp]);
 			    SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.right_margin_val[l_dq][l_rp]=(SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.rb_regval[l_dq][l_rp]-SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.nom_val[l_dq][l_rp])*l_factor;
                             SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.left_margin_val[l_dq][l_rp]= (SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.nom_val[l_dq][l_rp]-SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.lb_regval[l_dq][l_rp])*l_factor;//((1/uint32_t_freq*1000000)/128);
 			    SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.total_margin[l_dq][l_rp]=SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.right_margin_val[l_dq][l_rp]+SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.left_margin_val[l_dq][l_rp];
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.C
index 31b462f70..7a0486f02 100755
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_mcbist.C,v 1.23 2012/12/14 06:30:44 sasethur Exp $
+// $Id: mss_mcbist.C,v 1.25 2013/01/03 14:54:43 sasethur Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -38,7 +38,9 @@
 //------------------------------------------------------------------------------
 // Version:|Author: | Date:  | Comment:
 // --------|--------|--------|--------------------------------------------------
-//   1.22  |aditya  |12/14/12|Updated FW review comments   
+//   1.25  |aditya  |01/03/12| Updated FW Comments 
+//   1.23  |aditya  |12/18/12| Updated Review Comments 
+//   1.22  |aditya  |12/14/12| Updated FW review comments   
 //   1.22  |aditya  |12/6/12 | Updated Review Comments
 //   1.21  |aditya  |11/15/12| Updated for FIRMWARE REVIEW COMMENTS
 //   1.20  |aditya  |10/29/12| updated fw review comments 
@@ -216,16 +218,20 @@ fapi::ReturnCode  cfg_mcb_dgen(const fapi::Target & i_target_mba,mcbist_data_gen
         l_var1 =0x0000FFFF0000FFFFull; 
         l_spare = 0xFF00FF00FF00FF00ull;
 		
-        rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}  rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD0Q_0x030106be, l_data_buffer_64); if(rc) return rc;
-        rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD1Q_0x030106bf, l_data_buffer_64); if(rc) return rc;
-        rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD2Q_0x030106c0, l_data_buffer_64); if(rc) return rc;
-	rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD3Q_0x030106c1, l_data_buffer_64); if(rc) return rc;
-	rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD4Q_0x030106c2, l_data_buffer_64); if(rc) return rc;
-	rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD5Q_0x030106c3, l_data_buffer_64); if(rc) return rc;
-	rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD6Q_0x030106c4, l_data_buffer_64); if(rc) return rc;	
-	rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD7Q_0x030106c5, l_data_buffer_64); if(rc) return rc;
-	rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDQ_0x030106c6 , l_data_buffer_64); if(rc) return rc;
-	rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDSPQ_0x030106c7 , l_data_buffer_64); if(rc) return rc;
+        rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}
+		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}
+		rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}
+		
+		rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD0Q_0x030106be, l_var_data_buffer_64); if(rc) return rc;
+        rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD1Q_0x030106bf, l_var1_data_buffer_64); if(rc) return rc;
+        rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD2Q_0x030106c0, l_var_data_buffer_64); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD3Q_0x030106c1, l_var1_data_buffer_64); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD4Q_0x030106c2, l_var_data_buffer_64); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD5Q_0x030106c3, l_var1_data_buffer_64); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD6Q_0x030106c4, l_var_data_buffer_64); if(rc) return rc;	
+	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD7Q_0x030106c5, l_var1_data_buffer_64); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDQ_0x030106c6 , l_spare_data_buffer_64); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDSPQ_0x030106c7 , l_spare_data_buffer_64); if(rc) return rc;
 	
 	
 
@@ -242,17 +248,20 @@ fapi::ReturnCode  cfg_mcb_dgen(const fapi::Target & i_target_mba,mcbist_data_gen
     {
         l_var = 0xFFFFFFFFFFFFFFFFull;                                                                                                                                         
         l_var1 =0x0000000000000000ull;                                                                                                                                                                                                                                            
-        l_spare = 0xFFFF0000FFFF0000ull;                                                                                                                                
-        rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD0Q_0x030106be, l_data_buffer_64); if(rc) return rc; 
-        rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD1Q_0x030106bf, l_data_buffer_64); if(rc) return rc;  
-        rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD2Q_0x030106c0, l_data_buffer_64); if(rc) return rc;   
- 	rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD3Q_0x030106c1, l_data_buffer_64); if(rc) return rc;        
- 	rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD4Q_0x030106c2, l_data_buffer_64); if(rc) return rc;         
- 	rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD5Q_0x030106c3, l_data_buffer_64); if(rc) return rc;        
- 	rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD6Q_0x030106c4, l_data_buffer_64); if(rc) return rc;	    
- 	rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD7Q_0x030106c5, l_data_buffer_64); if(rc) return rc;      
- 	rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDQ_0x030106c6 , l_data_buffer_64); if(rc) return rc;     
- 	rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDSPQ_0x030106c7 , l_data_buffer_64); if(rc) return rc;    
+        l_spare = 0xFFFF0000FFFF0000ull;  
+rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}	
+ rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}	
+ rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}
+        rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD0Q_0x030106be, l_var_data_buffer_64); if(rc) return rc; 
+        rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD1Q_0x030106bf, l_var_data_buffer_64); if(rc) return rc;  
+       rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD2Q_0x030106c0, l_var1_data_buffer_64); if(rc) return rc;   
+ 	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD3Q_0x030106c1, l_var1_data_buffer_64); if(rc) return rc;        
+ 	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD4Q_0x030106c2, l_var_data_buffer_64); if(rc) return rc;         
+ 	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD5Q_0x030106c3, l_var_data_buffer_64); if(rc) return rc;        
+ 	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD6Q_0x030106c4, l_var1_data_buffer_64); if(rc) return rc;	    
+ 	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD7Q_0x030106c5, l_var1_data_buffer_64); if(rc) return rc;      
+ 	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDQ_0x030106c6 , l_spare_data_buffer_64); if(rc) return rc;     
+ 	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDSPQ_0x030106c7 , l_spare_data_buffer_64); if(rc) return rc;    
  
  
     }
@@ -261,19 +270,25 @@ fapi::ReturnCode  cfg_mcb_dgen(const fapi::Target & i_target_mba,mcbist_data_gen
          
         l_var = 0xA5A5A5A5A5A5A5A5ull;                                                                                                                                      
         l_var1 =0x5A5A5A5A5A5A5A5Aull;                                                                                                                                  
-        l_spare = 0xA55AA55AA55AA55Aull;                                                                                                                                
-        rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD0Q_0x030106be, l_data_buffer_64); if(rc) return rc; 
-        rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD1Q_0x030106bf, l_data_buffer_64); if(rc) return rc;
-        rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD2Q_0x030106c0, l_data_buffer_64); if(rc) return rc; 
-  	rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD3Q_0x030106c1, l_data_buffer_64); if(rc) return rc;    
-  	rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD4Q_0x030106c2, l_data_buffer_64); if(rc) return rc;     
-  	rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD5Q_0x030106c3, l_data_buffer_64); if(rc) return rc;    
-  	rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD6Q_0x030106c4, l_data_buffer_64); if(rc) return rc;	    
-  	rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD7Q_0x030106c5, l_data_buffer_64); if(rc) return rc;    
-  	rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDQ_0x030106c6 , l_data_buffer_64); if(rc) return rc;   
-  	rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDSPQ_0x030106c7 , l_data_buffer_64); if(rc) return rc;    
+        l_spare = 0xA55AA55AA55AA55Aull; 
+        
+		rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}
+		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}
+		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}
+		
+        rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD0Q_0x030106be, l_var_data_buffer_64); if(rc) return rc; 
+        rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD1Q_0x030106bf, l_var1_data_buffer_64); if(rc) return rc;
+         rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD2Q_0x030106c0, l_var_data_buffer_64); if(rc) return rc; 
+  	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD3Q_0x030106c1, l_var1_data_buffer_64); if(rc) return rc;    
+  	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD4Q_0x030106c2, l_var_data_buffer_64); if(rc) return rc;     
+  	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD5Q_0x030106c3, l_var1_data_buffer_64); if(rc) return rc;    
+  	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD6Q_0x030106c4, l_var_data_buffer_64); if(rc) return rc;	    
+  	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD7Q_0x030106c5, l_var1_data_buffer_64); if(rc) return rc;    
+  	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDQ_0x030106c6 , l_spare_data_buffer_64); if(rc) return rc;   
+  	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDSPQ_0x030106c7 , l_spare_data_buffer_64); if(rc) return rc;    
   
     }
+	
 	else if((i_datamode == DATA_GEN_DELTA_I) || (i_datamode == MCBIST_2D_CUP_PAT0))
     {
        
@@ -281,17 +296,21 @@ fapi::ReturnCode  cfg_mcb_dgen(const fapi::Target & i_target_mba,mcbist_data_gen
         l_var = 0xFFFFFFFFFFFFFFFFull;                                                                                                                                    
         l_var1 =0x0000000000000000ull;                                                                                                                                    
         l_spare = 0xFF00FF00FF00FF00ull;                                                                                                                                  
-        rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD0Q_0x030106be, l_data_buffer_64); if(rc) return rc;   
-        rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD1Q_0x030106bf, l_data_buffer_64); if(rc) return rc;  
-        rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD2Q_0x030106c0, l_data_buffer_64); if(rc) return rc;   
-	rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD3Q_0x030106c1, l_data_buffer_64); if(rc) return rc;       
-	rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD4Q_0x030106c2, l_data_buffer_64); if(rc) return rc;        
-	rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD5Q_0x030106c3, l_data_buffer_64); if(rc) return rc;       
-	rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD6Q_0x030106c4, l_data_buffer_64); if(rc) return rc;	       
-	rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD7Q_0x030106c5, l_data_buffer_64); if(rc) return rc;       
-	rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDQ_0x030106c6 , l_data_buffer_64); if(rc) return rc;      
-	rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDSPQ_0x030106c7 , l_data_buffer_64); if(rc) return rc;     
-                                                                                                                                                                        
+        rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}
+		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}
+		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}
+		
+        rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD0Q_0x030106be, l_var_data_buffer_64); if(rc) return rc; 
+        rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD1Q_0x030106bf, l_var1_data_buffer_64); if(rc) return rc;
+         rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD2Q_0x030106c0, l_var_data_buffer_64); if(rc) return rc; 
+  	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD3Q_0x030106c1, l_var1_data_buffer_64); if(rc) return rc;    
+  	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD4Q_0x030106c2, l_var_data_buffer_64); if(rc) return rc;     
+  	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD5Q_0x030106c3, l_var1_data_buffer_64); if(rc) return rc;    
+  	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD6Q_0x030106c4, l_var_data_buffer_64); if(rc) return rc;	    
+  	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD7Q_0x030106c5, l_var1_data_buffer_64); if(rc) return rc;    
+  	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDQ_0x030106c6 , l_spare_data_buffer_64); if(rc) return rc;   
+  	rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDSPQ_0x030106c7 , l_spare_data_buffer_64); if(rc) return rc;    
+                                                                                                                                                          
     }
 	
     else if(i_datamode == PSEUDORANDOM)
@@ -302,13 +321,14 @@ fapi::ReturnCode  cfg_mcb_dgen(const fapi::Target & i_target_mba,mcbist_data_gen
         {
             //l_rand_32 = rand();
 			l_rand_32 = 0xFFFFFFFF;//Hard Coded Temporary Fix till random function is fixed
-            rc_num =  l_data_buffer_32.insertFromRight(l_rand_32,0,32); 	 	
-            rc_num =  l_data_buffer_64.insert(l_data_buffer_32,0,32,0);
+            rc_num =  rc_num| l_data_buffer_32.insertFromRight(l_rand_32,0,32);	
+            rc_num =  rc_num|  l_data_buffer_64.insert(l_data_buffer_32,0,32,0);
             //l_rand_32 = rand();
 			l_rand_32 = 0xFFFFFFFF;
-            rc_num =  l_data_buffer_32.insertFromRight(l_rand_32,0,32);             
-            rc_num =  l_data_buffer_64.insert(l_data_buffer_32,32,32,0);
-	    if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, l_mba01_mcb_pseudo_random[l_index] , l_data_buffer_64); if(rc) return rc;
+            rc_num = rc_num| l_data_buffer_32.insertFromRight(l_rand_32,0,32);          
+            rc_num = rc_num| l_data_buffer_64.insert(l_data_buffer_32,32,32,0);
+	    if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}
+		rc = fapiPutScom(i_target_mba, l_mba01_mcb_pseudo_random[l_index] , l_data_buffer_64); if(rc) return rc;
         }
     }
     else
@@ -334,34 +354,40 @@ fapi::ReturnCode  cfg_mcb_dgen(const fapi::Target & i_target_mba,mcbist_data_gen
     	if (l_mbaPosition == 0)
 	{
 	    	//Writing MBS 01 pattern registers for comparison mode   
-	    	
-	                                                                                                                                  
-        rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD0Q_0x02011681, l_data_buffer_64); if(rc) return rc;
-        rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD1Q_0x02011682, l_data_buffer_64); if(rc) return rc;
-        rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD2Q_0x02011683, l_data_buffer_64); if(rc) return rc;
-    	rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD3Q_0x02011684, l_data_buffer_64); if(rc) return rc; 
-	    rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD4Q_0x02011685, l_data_buffer_64); if(rc) return rc; 
-	    rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD5Q_0x02011686, l_data_buffer_64); if(rc) return rc; 
-	    rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD6Q_0x02011687, l_data_buffer_64); if(rc) return rc;	
-	    rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD7Q_0x02011688, l_data_buffer_64); if(rc) return rc; 
-	    rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDQ_0x02011689,  l_data_buffer_64); if(rc) return rc; 
-	    rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDSPQ_0x0201168A,l_data_buffer_64); if(rc) return rc; 
+	    
+    rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}		
+	rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}  
+    rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}	
+	
+        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD0Q_0x02011681, l_var_data_buffer_64); if(rc) return rc;
+        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD1Q_0x02011682, l_var1_data_buffer_64); if(rc) return rc;
+        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD2Q_0x02011683, l_var_data_buffer_64); if(rc) return rc;
+    	rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD3Q_0x02011684, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD4Q_0x02011685, l_var_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD5Q_0x02011686, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD6Q_0x02011687, l_var_data_buffer_64); if(rc) return rc;	
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD7Q_0x02011688, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDQ_0x02011689,  l_spare_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDSPQ_0x0201168A,l_spare_data_buffer_64); if(rc) return rc; 
                                                                                                                                                                             
 	}
 	else if (l_mbaPosition == 1)
 	{
 	    	//Writing MBS 23 pattern registers for comparison mode   
-	                                                                                                                                
-	    rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD0Q_0x02011781, l_data_buffer_64); if(rc) return rc;
-	    rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD1Q_0x02011782, l_data_buffer_64); if(rc) return rc;
-	    rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD2Q_0x02011783, l_data_buffer_64); if(rc) return rc;
-	    rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD3Q_0x02011784, l_data_buffer_64); if(rc) return rc; 
-	    rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD4Q_0x02011785, l_data_buffer_64); if(rc) return rc;  
-	    rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD5Q_0x02011786, l_data_buffer_64); if(rc) return rc; 
-	    rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD6Q_0x02011787, l_data_buffer_64); if(rc) return rc;   
-  	    rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD7Q_0x02011788, l_data_buffer_64); if(rc) return rc; 
-	    rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDQ_0x02011789,  l_data_buffer_64); if(rc) return rc; 
-	    rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);    if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDSPQ_0x0201178A,l_data_buffer_64); if(rc) return rc; 
+	    rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}                                                                                                                            
+	    rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}
+		rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}
+		
+		rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD0Q_0x02011781, l_var_data_buffer_64); if(rc) return rc;
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD1Q_0x02011782, l_var1_data_buffer_64); if(rc) return rc;
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD2Q_0x02011783, l_var_data_buffer_64); if(rc) return rc;
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD3Q_0x02011784, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD4Q_0x02011785, l_var_data_buffer_64); if(rc) return rc;  
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD5Q_0x02011786, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD6Q_0x02011787, l_var_data_buffer_64); if(rc) return rc;   
+  	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD7Q_0x02011788, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDQ_0x02011789,  l_spare_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDSPQ_0x0201178A,l_spare_data_buffer_64); if(rc) return rc; 
                                                                                                                                                                               
 	}
     }
@@ -373,34 +399,42 @@ fapi::ReturnCode  cfg_mcb_dgen(const fapi::Target & i_target_mba,mcbist_data_gen
 	if (l_mbaPosition == 0)
 	{
 	    	//Writing MBS 01 pattern registers for comparison mod
-                                                                                                                                             
-		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD0Q_0x02011681, l_data_buffer_64); if(rc) return rc; 
-		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD1Q_0x02011682, l_data_buffer_64); if(rc) return rc; 
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD2Q_0x02011683, l_data_buffer_64); if(rc) return rc; 
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD3Q_0x02011684, l_data_buffer_64); if(rc) return rc; 
-		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);   if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD4Q_0x02011685, l_data_buffer_64); if(rc) return rc; 
-		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);   if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD5Q_0x02011686, l_data_buffer_64); if(rc) return rc; 
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); 	if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD6Q_0x02011687, l_data_buffer_64); if(rc) return rc; 
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD7Q_0x02011688, l_data_buffer_64); if(rc) return rc; 
-		rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDQ_0x02011689,  l_data_buffer_64); if(rc) return rc; 
-		rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);     if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDSPQ_0x0201168A,l_data_buffer_64); if(rc) return rc;  	
-    	}
+     rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}		
+	rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}  
+    rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}	
+	
+        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD0Q_0x02011681, l_var_data_buffer_64); if(rc) return rc;
+        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD1Q_0x02011682, l_var_data_buffer_64); if(rc) return rc;
+        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD2Q_0x02011683, l_var1_data_buffer_64); if(rc) return rc;
+    	rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD3Q_0x02011684, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD4Q_0x02011685, l_var_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD5Q_0x02011686, l_var_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD6Q_0x02011687, l_var1_data_buffer_64); if(rc) return rc;	
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD7Q_0x02011688, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDQ_0x02011689,  l_spare_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDSPQ_0x0201168A,l_spare_data_buffer_64); if(rc) return rc;                                                                                                                                          
+		
+    }
     	else if (l_mbaPosition == 1)
     	{
 	    	//Writing MBS 23 pattern registers for comparison mod
       
+	  rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}                                                                                                                            
+	    rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}
+		rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}
+		
+		rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD0Q_0x02011781, l_var_data_buffer_64); if(rc) return rc;
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD1Q_0x02011782, l_var_data_buffer_64); if(rc) return rc;
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD2Q_0x02011783, l_var1_data_buffer_64); if(rc) return rc;
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD3Q_0x02011784, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD4Q_0x02011785, l_var_data_buffer_64); if(rc) return rc;  
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD5Q_0x02011786, l_var_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD6Q_0x02011787, l_var1_data_buffer_64); if(rc) return rc;   
+  	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD7Q_0x02011788, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDQ_0x02011789,  l_spare_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDSPQ_0x0201178A,l_spare_data_buffer_64); if(rc) return rc;
 		                                                                                                                                       
-		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);   if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD0Q_0x02011781, l_data_buffer_64); if(rc) return rc;  
-		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);   if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD1Q_0x02011782, l_data_buffer_64); if(rc) return rc;  
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD2Q_0x02011783, l_data_buffer_64); if(rc) return rc;  
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD3Q_0x02011784, l_data_buffer_64); if(rc) return rc;  
-		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);   if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD4Q_0x02011785, l_data_buffer_64); if(rc) return rc;  
-		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);   if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD5Q_0x02011786, l_data_buffer_64); if(rc) return rc;  
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD6Q_0x02011787, l_data_buffer_64); if(rc) return rc;  
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD7Q_0x02011788, l_data_buffer_64); if(rc) return rc;  
-		rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDQ_0x02011789,  l_data_buffer_64); if(rc) return rc;  
-		rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDSPQ_0x0201178A,l_data_buffer_64); if(rc) return rc;       
-
+		
 
         }
     }
@@ -413,33 +447,40 @@ fapi::ReturnCode  cfg_mcb_dgen(const fapi::Target & i_target_mba,mcbist_data_gen
          if (l_mbaPosition == 0)
 	 {
 	    	//Writing MBS 01 pattern registers for comparison mod
-        rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBS_MCBIST01_MBS_MCBFD0Q_0x02011681, l_data_buffer_64); if(rc) return rc;  
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBS_MCBIST01_MBS_MCBFD1Q_0x02011682, l_data_buffer_64); if(rc) return rc;  
-		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBS_MCBIST01_MBS_MCBFD2Q_0x02011683, l_data_buffer_64); if(rc) return rc;  
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBS_MCBIST01_MBS_MCBFD3Q_0x02011684, l_data_buffer_64);  if(rc) return rc;     
-		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBS_MCBIST01_MBS_MCBFD4Q_0x02011685, l_data_buffer_64); if(rc) return rc;      
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBS_MCBIST01_MBS_MCBFD5Q_0x02011686, l_data_buffer_64);  if(rc) return rc;     
-		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBS_MCBIST01_MBS_MCBFD6Q_0x02011687, l_data_buffer_64); if(rc) return rc;      
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBS_MCBIST01_MBS_MCBFD7Q_0x02011688, l_data_buffer_64); if(rc) return rc;      
-		rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBS_MCBIST01_MBS_MCBFDQ_0x02011689,  l_data_buffer_64);  if(rc) return rc;     
-		rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);    if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba,MBS_MCBIST01_MBS_MCBFDSPQ_0x0201168A, l_data_buffer_64); if(rc) return rc;   
-         }
+	rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}		
+	rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}  
+    rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}	
+	
+        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD0Q_0x02011681, l_var_data_buffer_64); if(rc) return rc;
+        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD1Q_0x02011682, l_var1_data_buffer_64); if(rc) return rc;
+        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD2Q_0x02011683, l_var_data_buffer_64); if(rc) return rc;
+    	rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD3Q_0x02011684, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD4Q_0x02011685, l_var_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD5Q_0x02011686, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD6Q_0x02011687, l_var_data_buffer_64); if(rc) return rc;	
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD7Q_0x02011688, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDQ_0x02011689,  l_spare_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDSPQ_0x0201168A,l_spare_data_buffer_64); if(rc) return rc; 
+     }
     	 else if (l_mbaPosition == 1)
     	 {
 	    	//Writing MBS 23 pattern registers for comparison mod
         	                                                                                                                                                                           	 
-		                                                                                                                                        
-		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBS_MCBIST23_MBS_MCBFD0Q_0x02011781, l_data_buffer_64); if(rc) return rc;      
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBS_MCBIST23_MBS_MCBFD1Q_0x02011782, l_data_buffer_64); if(rc) return rc;      
-		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBS_MCBIST23_MBS_MCBFD2Q_0x02011783, l_data_buffer_64); if(rc) return rc;      
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBS_MCBIST23_MBS_MCBFD3Q_0x02011784, l_data_buffer_64); if(rc) return rc;      
-		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBS_MCBIST23_MBS_MCBFD4Q_0x02011785, l_data_buffer_64); if(rc) return rc;      
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBS_MCBIST23_MBS_MCBFD5Q_0x02011786, l_data_buffer_64); if(rc) return rc;      
-		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBS_MCBIST23_MBS_MCBFD6Q_0x02011787, l_data_buffer_64); if(rc) return rc;      
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBS_MCBIST23_MBS_MCBFD7Q_0x02011788, l_data_buffer_64); if(rc) return rc;      
-		rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBS_MCBIST23_MBS_MCBFDQ_0x02011789,  l_data_buffer_64); if(rc) return rc;      
-		rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);    if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_mba, MBS_MCBIST23_MBS_MCBFDSPQ_0x0201178A,l_data_buffer_64); if(rc) return rc;      
-                                                                                                                                                                           	   			
+		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}                                                                                                                            
+	    rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}
+		rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}
+		
+		rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD0Q_0x02011781, l_var_data_buffer_64); if(rc) return rc;
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD1Q_0x02011782, l_var1_data_buffer_64); if(rc) return rc;
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD2Q_0x02011783, l_var_data_buffer_64); if(rc) return rc;
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD3Q_0x02011784, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD4Q_0x02011785, l_var_data_buffer_64); if(rc) return rc;  
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD5Q_0x02011786, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD6Q_0x02011787, l_var_data_buffer_64); if(rc) return rc;   
+  	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD7Q_0x02011788, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDQ_0x02011789,  l_spare_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDSPQ_0x0201178A,l_spare_data_buffer_64); if(rc) return rc;                                                                                                                                        
+		                                                                                                                                                                 	   			
          }
     }
     else if((i_datamode == DATA_GEN_DELTA_I) || (i_datamode == MCBIST_2D_CUP_PAT0))
@@ -451,37 +492,43 @@ fapi::ReturnCode  cfg_mcb_dgen(const fapi::Target & i_target_mba,mcbist_data_gen
 		if (l_mbaPosition == 0)
 		{
 	    	//Writing MBS 01 pattern registers for comparison mod
-        		
+        	rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}		
+	rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}  
+    rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}	
+	
+        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD0Q_0x02011681, l_var_data_buffer_64); if(rc) return rc;
+        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD1Q_0x02011682, l_var1_data_buffer_64); if(rc) return rc;
+        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD2Q_0x02011683, l_var_data_buffer_64); if(rc) return rc;
+    	rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD3Q_0x02011684, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD4Q_0x02011685, l_var_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD5Q_0x02011686, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD6Q_0x02011687, l_var_data_buffer_64); if(rc) return rc;	
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD7Q_0x02011688, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDQ_0x02011689,  l_spare_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDSPQ_0x0201168A,l_spare_data_buffer_64); if(rc) return rc; 	
                                                                                                                                        	
-        rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);   if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD0Q_0x02011681, l_data_buffer_64); if(rc) return rc;
-        rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD1Q_0x02011682, l_data_buffer_64); if(rc) return rc;
-        rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);   if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD2Q_0x02011683, l_data_buffer_64); if(rc) return rc;
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD3Q_0x02011684, l_data_buffer_64); if(rc) return rc;   
-		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);   if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD4Q_0x02011685, l_data_buffer_64); if(rc) return rc;   
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD5Q_0x02011686, l_data_buffer_64); if(rc) return rc;   
-		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);   if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD6Q_0x02011687, l_data_buffer_64); if(rc) return rc;   
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD7Q_0x02011688, l_data_buffer_64); if(rc) return rc;   
-		rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDQ_0x02011689,  l_data_buffer_64); if(rc) return rc;   
-		rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);     if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDSPQ_0x0201168A,l_data_buffer_64); if(rc) return rc;   
-                                                                                                                                                                          	
+                                                                                                                                                                      	
 	
     	}
     	else if (l_mbaPosition == 1)
     	{
 	    	//Writing MBS 23 pattern registers for comparison mod
-        	                                                                                                                                                                    	         
+        	 rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}		
+	rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1); if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}  
+    rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}	
+	
+        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD0Q_0x02011681, l_var_data_buffer_64); if(rc) return rc;
+        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD1Q_0x02011682, l_var1_data_buffer_64); if(rc) return rc;
+        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD2Q_0x02011683, l_var_data_buffer_64); if(rc) return rc;
+    	rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD3Q_0x02011684, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD4Q_0x02011685, l_var_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD5Q_0x02011686, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD6Q_0x02011687, l_var_data_buffer_64); if(rc) return rc;	
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD7Q_0x02011688, l_var1_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDQ_0x02011689,  l_spare_data_buffer_64); if(rc) return rc; 
+	    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDSPQ_0x0201168A,l_spare_data_buffer_64); if(rc) return rc; 	                                                                                                                                                                    	         
 	                                                                                                                               	     
-		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);    if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD0Q_0x02011781, l_data_buffer_64); if(rc) return rc;
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);   if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD1Q_0x02011782, l_data_buffer_64); if(rc) return rc;
-		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);    if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD2Q_0x02011783, l_data_buffer_64); if(rc) return rc;
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);   if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD3Q_0x02011784, l_data_buffer_64); if(rc) return rc; 
-		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);    if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD4Q_0x02011785, l_data_buffer_64); if(rc) return rc; 
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);   if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD5Q_0x02011786, l_data_buffer_64); if(rc) return rc; 
-		rc_num = l_var_data_buffer_64.setDoubleWord(0,l_var);    if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD6Q_0x02011787, l_data_buffer_64); if(rc) return rc; 
-		rc_num = l_var1_data_buffer_64.setDoubleWord(0,l_var1);   if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD7Q_0x02011788, l_data_buffer_64); if(rc) return rc; 
-		rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);  if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDQ_0x02011789,  l_data_buffer_64); if(rc) return rc; 
-		rc_num = l_spare_data_buffer_64.setDoubleWord(0,l_spare);      if (rc_num){ FAPI_ERR( "cfg_mcb_dgen:");rc.setEcmdError(rc_num);return rc;}rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDSPQ_0x0201178A,l_data_buffer_64); if(rc) return rc; 
-
+		
     	}
     }
 	
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H
index 85d8d4824..46761cd11 100755
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_mcbist.H,v 1.17 2012/12/14 06:31:11 sasethur Exp $
+// $Id: mss_mcbist.H,v 1.20 2013/01/03 14:55:10 sasethur Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -38,6 +38,8 @@
 //-------------------------------------------------------------------------------
 // Version:|Author: | Date:   | Comment:
 // --------|--------|---------|--------------------------------------------------
+//   1.20  |aditya  |01/03/12| Updated FW Comments 
+//   1.18  |aditya  |12/18/12| Updated Review Comments 
 //   1.17  |aditya  |12/14/12 |Updated FW review comments   
 //   1.16  |aditya  |12/6/12  | Updated Review Comments
 //   1.15  |aditya  |11/15/12 | Updated for FW REVIEW COMMENTS
@@ -153,7 +155,8 @@ enum mcbist_data_gen
     MCBIST_888_XFER,
     FIRST_XFER_X4MODE,
     MCBIST_LONG,
-    PSEUDORANDOM
+    PSEUDORANDOM,
+	CASTLE
 };
 
 enum mcbist_oper_type
@@ -257,6 +260,6 @@ fapi::ReturnCode cfg_byte_mask(const fapi::Target & i_target_mba,uint8_t i_rank,
 fapi::ReturnCode start_mcb(const fapi::Target & i_target_mba);
 fapi::ReturnCode setup_mcbist(const fapi::Target & i_target_mba, uint8_t i_port,mcbist_data_gen i_mcbpatt,mcbist_test_mem i_mcbtest,mcbist_byte_mask i_mcbbytemask,uint8_t i_mcbrotate,uint8_t i_pattern,uint8_t i_test_type,uint8_t i_rank);
 fapi::ReturnCode cfg_mcb_addr(const fapi::Target & i_target_mba,uint8_t i_rank,uint8_t i_port);
-fapi::ReturnCode  mcb_error_map_print(const fapi::Target & i_target_mba,uint8_t i_port,uint8_t i_rank,ecmdDataBufferBase & l_mcb_fail_320);
+fapi::ReturnCode  mcb_error_map_print(const fapi::Target & i_target_mba,uint8_t i_port,uint8_t i_rank,ecmdDataBufferBase & i_mcb_fail_320);
 }
 #endif
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C
index c472c1111..91d3de08b 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_mcbist_common.C,v 1.10 2012/12/14 16:09:38 sasethur Exp $
+// $Id: mss_mcbist_common.C,v 1.13 2013/01/03 14:54:55 sasethur Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -38,6 +38,7 @@
 //------------------------------------------------------------------------------
 // Version:|Author: | Date:  | Comment:
 // --------|--------|--------|--------------------------------------------------
+//   1.13  |aditya  |01/03/12| Updated FW Comments 
 //   1.10  |sasethur|12/14/12| Updated for warnings
 //   1.9   |aditya  |12/14/12| Updated FW review comments   
 //   1.8   |aditya  |12/6/12 | Updated Review Comments
@@ -120,8 +121,8 @@ fapi::ReturnCode  setup_mcbist(const fapi::Target & i_target_mba, uint8_t i_port
 	
     rc = mcb_reset_trap(i_target_mba); 
     if(rc) return rc;
-/*
-    rc = fapiGetScom(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,l_data_buffer_64); if(rc) return rc; 
+
+   /* rc = fapiGetScom(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,l_data_buffer_64); if(rc) return rc; 
     rc_num = rc_num | l_data_buffer_64.flushTo0();
     rc_num = rc_num | l_data_buffer_64.setBit(18); 
     rc_num = rc_num | l_data_buffer_64.setBit(27); 
@@ -143,15 +144,21 @@ fapi::ReturnCode  setup_mcbist(const fapi::Target & i_target_mba, uint8_t i_port
   */ 
     rc = fapiGetScom(i_target_mba,MBA01_CCS_MODEQ_0x030106a7, l_data_buffer_64);  if(rc) return rc;   
     rc_num =  l_data_buffer_64.clearBit(29); if (rc_num){FAPI_ERR( "Error in function setup_mcb:");rc.setEcmdError(rc_num);return rc;}
-   
+  
+ 
     rc = fapiPutScom(i_target_mba,MBA01_CCS_MODEQ_0x030106a7, l_data_buffer_64);  if(rc) return rc;   
+   //Hard coded to single address - Saravanan for debug 
+   /* rc = fapiGetScom(i_target_mba, MBA01_MCBIST_MCBSEARA0Q_0x030106d2,l_data_buffer_64);if(rc) return rc; 
+    rc_num = rc_num | l_data_buffer_64.flushTo0(); 
+    rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBSEARA0Q_0x030106d2,l_data_buffer_64); if(rc) return rc; 
+    */
     //rc = print_pattern(i_target_mba);if(rc)return rc;
     if((i_test_type == 1) && (i_pattern == 1))
     {
 	FAPI_INF("User pattern and User test_type modes enabled");
 	rc = cfg_mcb_dgen(i_target_mba,USR_MODE,i_mcbrotate); if(rc) return rc;
 	FAPI_INF("Inside setup mcbist Entering cfg_mcb_addr");
-        //rc = cfg_mcb_addr(i_target_mba,i_rank,i_port);if(rc) return rc;
+        rc = cfg_mcb_addr(i_target_mba,i_rank,i_port);if(rc) return rc;
         rc = cfg_mcb_test_mem(i_target_mba,USER_MODE); if(rc) return rc; 
     }
     else if(i_pattern == 1) 
@@ -159,7 +166,7 @@ fapi::ReturnCode  setup_mcbist(const fapi::Target & i_target_mba, uint8_t i_port
         FAPI_INF("User pattern  mode enabled");
         rc = cfg_mcb_dgen(i_target_mba,USR_MODE,i_mcbrotate); if(rc) return rc;
         FAPI_INF("Inside setup mcbist Entering cfg_mcb_addr");
-        //rc = cfg_mcb_addr(i_target_mba,i_rank,i_port);if(rc) return rc;
+        rc = cfg_mcb_addr(i_target_mba,i_rank,i_port);if(rc) return rc;
         rc = cfg_mcb_test_mem(i_target_mba,i_mcbtest); if(rc) return rc;
     }
     else if(i_test_type == 1)
@@ -167,14 +174,14 @@ fapi::ReturnCode  setup_mcbist(const fapi::Target & i_target_mba, uint8_t i_port
 	FAPI_INF(" User test_type mode enabled");
 	rc = cfg_mcb_dgen(i_target_mba,i_mcbpatt,i_mcbrotate); if(rc) return rc;
         FAPI_INF("Inside setup mcbist Entering cfg_mcb_addr");
-        //rc = cfg_mcb_addr(i_target_mba,i_rank,i_port);if(rc) return rc;
+        rc = cfg_mcb_addr(i_target_mba,i_rank,i_port);if(rc) return rc;
         rc = cfg_mcb_test_mem(i_target_mba,USER_MODE); if(rc) return rc;
     }
     else
     {
 	rc = cfg_mcb_dgen(i_target_mba,i_mcbpatt,i_mcbrotate); if(rc) return rc;
 	FAPI_INF("Inside setup mcbist Entering cfg_mcb_addr");
-        //rc = cfg_mcb_addr(i_target_mba,i_rank,i_port);if(rc) return rc;
+        rc = cfg_mcb_addr(i_target_mba,i_rank,i_port);if(rc) return rc;
         rc = cfg_mcb_test_mem(i_target_mba,i_mcbtest); if(rc) return rc;
     }
 	
@@ -206,12 +213,14 @@ fapi::ReturnCode  mcb_reset_trap(const fapi::Target & i_target_mba)
     FAPI_INF("Using MCB Reset Trap Function -- This automatically resets error log RA, error counters, Status Reg and error map");
     
     rc = fapiGetScom(i_target_mba,MBA01_MCBIST_MCBCFGQ_0x030106e0,l_data_buffer_64);if(rc) return rc;
-    rc_num =  l_data_buffer_64.clearBit(60);if (rc_num){FAPI_ERR( "Error in function  mcb_reset_trap:");rc.setEcmdError(rc_num);return rc;}
-    rc = fapiPutScom(i_target_mba,MBA01_MCBIST_MCBCFGQ_0x030106e0,l_data_buffer_64);if(rc) return rc;
     rc_num =  l_data_buffer_64.setBit(60);if (rc_num){FAPI_ERR( "Error in function  mcb_reset_trap:");rc.setEcmdError(rc_num);return rc;}
+    rc = fapiDelay(DELAY_100US, DELAY_2000SIMCYCLES);if(rc) return rc; // wait 2000 simcycles (in sim mode) OR 100 uS (in hw mode)
     rc = fapiPutScom(i_target_mba,MBA01_MCBIST_MCBCFGQ_0x030106e0,l_data_buffer_64);if(rc) return rc;
     rc_num =  l_data_buffer_64.clearBit(60);if (rc_num){FAPI_ERR( "Error in function  mcb_reset_trap:");rc.setEcmdError(rc_num);return rc;}
     rc = fapiPutScom(i_target_mba,MBA01_MCBIST_MCBCFGQ_0x030106e0,l_data_buffer_64);if(rc) return rc;
+    rc = fapiDelay(DELAY_100US, DELAY_2000SIMCYCLES);if(rc) return rc; // wait 2000 simcycles (in sim mode) OR 100 uS (in hw mode)
+    rc_num =  l_data_buffer_64.setBit(60);if (rc_num){FAPI_ERR( "Error in function  mcb_reset_trap:");rc.setEcmdError(rc_num);return rc;}
+    rc = fapiPutScom(i_target_mba,MBA01_MCBIST_MCBCFGQ_0x030106e0,l_data_buffer_64);if(rc) return rc;
     //Reset MCB Maintanence register
     FAPI_INF("Clearing the MCBIST Maintenance ");
     rc_num =  l_data_buffer_64.flushTo0();if (rc_num){FAPI_ERR( "Error in function  mcb_reset_trap:");rc.setEcmdError(rc_num);return rc;}
@@ -475,7 +484,14 @@ fapi::ReturnCode  mcb_error_map_print(const fapi::Target & i_target_mba,uint8_t
 	uint8_t l_rank_pair = 0;
 	char l_str1[200] = "";
 	uint8_t l_index = 0;
+	uint8_t l_dimmtype = 0;
+	rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, l_dimmtype); if(rc) return rc;
+	// if(l_dimmtype==1)
+	// {
+	
+	// return rc;
 	
+	// }
 	if(i_port == 0)
 	{
 	FAPI_INF("################# PortA Error MAP #################");
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
index 6c1e965fa..a31d5b7de 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit_training.C,v 1.43 2012/12/07 13:46:10 bellows Exp $
+// $Id: mss_draminit_training.C,v 1.46 2013/01/03 23:15:35 jdsloat Exp $
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -28,6 +28,9 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|------------------------------------------------
+//  1.46   | jdsloat  |03-JAN-13| RM temp edits to CAL0q and CAL1q; Cleared INIT_CAL_STATUS and INIT_CAL_ERROR Regs before every subtest, edited debug messages
+//  1.45   | gollub   |21-DEC-12| Calling mss_unmask_draminit_training_errors after mss_draminit_training_cloned
+//  1.43   | jdsloat  |20-DEC-12| Temporarily disabled RTT_NOM swap
 //  1.42   | bellows  |06-DEC-12| Fixed up review comments
 //  1.41   | jdsloat  |02-DEC-12| Fixed RTT_NOM swap for Port 1
 //  1.40   | jdsloat  |30-NOV-12| Temporarily comment Bad Bit Mask.
@@ -104,6 +107,7 @@
 #include <cen_scom_addresses.H>
 #include <mss_funcs.H>
 #include <dimmBadDqBitmapFuncs.H>
+#include <mss_unmask_errors.H>
 
 //------------End My Includes-------------------------------------------
 
@@ -138,6 +142,7 @@ extern "C" {
 using namespace fapi;
 
 ReturnCode mss_draminit_training(Target& i_target);
+ReturnCode mss_draminit_training_cloned(Target& i_target);
 ReturnCode mss_check_cal_status(Target& i_target, uint8_t i_port, uint8_t i_group,  mss_draminit_training_result& io_status);
 ReturnCode mss_check_error_status(Target& i_target, uint8_t i_port, uint8_t i_group,  mss_draminit_training_result& io_status);
 ReturnCode mss_rtt_nom_rtt_wr_swap( Target& i_target, uint32_t i_port_number, uint8_t i_rank, uint32_t i_rank_pair_group, uint32_t& io_ccs_inst_cnt);
@@ -146,9 +151,30 @@ ReturnCode setC4dq2reg(const Target &i_mba, const uint8_t i_port, const uint8_t
 ReturnCode mss_set_bbm_regs (const fapi::Target & mba_target);
 ReturnCode mss_get_bbm_regs (const fapi::Target & mba_target);
 
+
 ReturnCode mss_draminit_training(Target& i_target)
 {
     // Target is centaur.mba
+    
+    fapi::ReturnCode l_rc;
+    
+    l_rc = mss_draminit_training_cloned(i_target);
+    
+	// If mss_unmask_draminit_training_errors gets it's own bad rc,
+	// it will commit the passed in rc (if non-zero), and return it's own bad rc.
+	// Else if mss_unmask_draminit_training_errors runs clean, 
+	// it will just return the passed in rc.
+	//l_rc = mss_unmask_draminit_training_errors(i_target, l_rc); // TODO: uncomment after this can be tested on hw
+
+	return l_rc;
+}
+
+
+
+
+ReturnCode mss_draminit_training_cloned(Target& i_target)
+{
+    // Target is centaur.mba
     //Enums and Constants
     enum size 
     {
@@ -209,20 +235,6 @@ ReturnCode mss_draminit_training(Target& i_target)
 
     ecmdDataBufferBase data_buffer_64(64);
 
-    //TEMP MBA CAL REGS bit 12 = 0
-    rc = fapiGetScom(i_target, MBA01_MBA_CAL0Q_0x0301040F, data_buffer_64);
-    if(rc) return rc;
-    rc_num = rc_num | data_buffer_64.clearBit(12);
-    FAPI_INF("+++ TEMP setting bit 12 to 0+++");
-    rc = fapiPutScom(i_target, MBA01_MBA_CAL0Q_0x0301040F, data_buffer_64);
-    if(rc) return rc;
-
-    rc = fapiGetScom(i_target, MBA01_MBA_CAL1Q_0x03010410, data_buffer_64);
-    if(rc) return rc;
-    rc_num = rc_num | data_buffer_64.clearBit(12);
-    FAPI_INF("+++ TEMP setting bit 12 to 0+++");
-    rc = fapiPutScom(i_target, MBA01_MBA_CAL1Q_0x03010410, data_buffer_64);
-    if(rc) return rc;
 
     if(rc_num)
     {
@@ -310,8 +322,9 @@ ReturnCode mss_draminit_training(Target& i_target)
 	    if(primary_ranks_array[group][port] != INVALID)
 	    {
 
+		// Temporarily disable this function for HW debug
 	        // Change the RTT_NOM to RTT_WR, RTT_WR to RTT_NOM
-		rc = mss_rtt_nom_rtt_wr_swap(i_target, port, primary_ranks_array[group][port], group, instruction_number);
+		//rc = mss_rtt_nom_rtt_wr_swap(i_target, port, primary_ranks_array[group][port], group, instruction_number);
                 if(rc) return rc;
 
 
@@ -322,10 +335,56 @@ ReturnCode mss_draminit_training(Target& i_target)
 		rc_num = rc_num | rasn_buffer_1.flushTo1();
 		rc_num = rc_num | ddr_cal_enable_buffer_1.flushTo1(); //Init cal
 
-		FAPI_INF( "+++++++++++++++ Sending init cal on rank group: %d cal_steps: 0x%02X +++++++++++++++", group, cal_steps);
+		FAPI_INF( "+++ Setting up Init Cal on rank group: %d cal_steps: 0x%02X +++", group, cal_steps);
 
 		for(cur_cal_step = 1; cur_cal_step < MAX_CAL_STEPS; cur_cal_step++) //Cycle through all possible cal steps
 		{
+
+		    //Clearing any status or errors bits that may have occured in previous training subtest.
+		    if(port == 0)
+		    {
+			
+			rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, data_buffer_64);
+			if(rc) return rc;
+
+			rc_num = rc_num | data_buffer_64.clearBit(48, 4);
+
+			rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, data_buffer_64);
+			if(rc) return rc;
+			
+			rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, data_buffer_64);
+			if(rc) return rc;
+
+			rc_num = rc_num | data_buffer_64.clearBit(48, 11);
+			rc_num = rc_num | data_buffer_64.clearBit(60, 4);
+
+			rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, data_buffer_64);
+			if(rc) return rc;
+			
+
+		    }
+		    else
+		    {
+			rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, data_buffer_64);
+			if(rc) return rc;
+
+			rc_num = rc_num | data_buffer_64.clearBit(48, 4);
+
+			rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, data_buffer_64);
+			if(rc) return rc;
+
+			rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, data_buffer_64);
+			if(rc) return rc;
+
+			rc_num = rc_num | data_buffer_64.clearBit(48, 11);
+			rc_num = rc_num | data_buffer_64.clearBit(60, 4);
+
+			rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, data_buffer_64);
+			if(rc) return rc;
+
+
+		    }
+
 		    //Setup the Config Reg bit for the only cal step we want
 		    rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64);
 		    if(rc) return rc;
@@ -343,7 +402,7 @@ ReturnCode mss_draminit_training(Target& i_target)
 			 (cal_steps_8.isBitClear(4)) && (cal_steps_8.isBitClear(5)) &&
 			 (cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitClear(7)) )
 		    {
-			FAPI_INF( "+++++ Sending ALL Cal Steps at the same time on rank group: %d +++++", group);
+			FAPI_INF( "+++ Executing ALL Cal Steps at the same time on rank group: %d +++", group);
 			rc_num = rc_num | data_buffer_64.setBit(48);
 			rc_num = rc_num | data_buffer_64.setBit(50);
 			rc_num = rc_num | data_buffer_64.setBit(51);
@@ -354,42 +413,42 @@ ReturnCode mss_draminit_training(Target& i_target)
 		    }
 		    else if ( (cur_cal_step == 1) && (cal_steps_8.isBitSet(1)) )
 		    {
-			FAPI_INF( "+++++ Sending Write Leveling (WR_LVL) on rank group: %d +++++", group);
+			FAPI_INF( "+++ Write Leveling (WR_LVL) on rank group: %d +++", group);
 			rc_num = rc_num | data_buffer_64.setBit(48);
 		    }
 		    else if ( (cur_cal_step == 2) && (cal_steps_8.isBitSet(2)) )
 		    {
-			FAPI_INF( "+++++ Sending DQS Align (DQS_ALIGN) on rank group: %d +++++", group);
+			FAPI_INF( "+++ DQS Align (DQS_ALIGN) on rank group: %d +++", group);
 			rc_num = rc_num | data_buffer_64.setBit(50);
 		    }
 		    else if ( (cur_cal_step == 3) && (cal_steps_8.isBitSet(3)) )
 		    {
-			FAPI_INF( "+++++ Sending RD CLK Align (RDCLK_ALIGN) on rank group: %d +++++", group);
+			FAPI_INF( "+++ RD CLK Align (RDCLK_ALIGN) on rank group: %d +++", group);
 			rc_num = rc_num | data_buffer_64.setBit(51);
 		    }
 		    else if ( (cur_cal_step == 4) && (cal_steps_8.isBitSet(4)) )
 		    {
-			FAPI_INF( "+++++ Sending Read Centering (READ_CTR) on rank group: %d +++++", group);
+			FAPI_INF( "+++ Read Centering (READ_CTR) on rank group: %d +++", group);
 			rc_num = rc_num | data_buffer_64.setBit(52);
 		    }
 		    else if ( (cur_cal_step == 5) && (cal_steps_8.isBitSet(5)) )
 		    {
-			FAPI_INF( "+++++ Sending Write Centering (WRITE_CTR) on rank group: %d +++++", group);
+			FAPI_INF( "+++ Write Centering (WRITE_CTR) on rank group: %d +++", group);
 			rc_num = rc_num | data_buffer_64.setBit(53);
 		    }
 		    else if ( (cur_cal_step == 6) && (cal_steps_8.isBitSet(6)) && (cal_steps_8.isBitClear(7)) )
 		    {
-			FAPI_INF( "+++++ Sending Initial Course Write (COURSE_WR) on rank group: %d +++++", group);
+			FAPI_INF( "+++ Initial Course Write (COURSE_WR) on rank group: %d +++", group);
 			rc_num = rc_num | data_buffer_64.setBit(54);
 		    }
 		    else if ( (cur_cal_step == 6) && (cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitSet(7)) )
 		    {
-			FAPI_INF( "+++++ Sending Course Read (COURSE_RD) on rank group: %d +++++", group);
+			FAPI_INF( "+++ Course Read (COURSE_RD) on rank group: %d +++", group);
 			rc_num = rc_num | data_buffer_64.setBit(55);
 		    }
 		    else if ( (cur_cal_step == 6) && (cal_steps_8.isBitSet(6)) && (cal_steps_8.isBitSet(7)) )
 		    {
-			FAPI_INF( "+++++ Sending Initial Course Write (COURSE_WR) and Course Read (COURSE_RD) on rank group: %d +++++", group);
+			FAPI_INF( "+++ Initial Course Write (COURSE_WR) and Course Read (COURSE_RD) simultaneously on rank group: %d +++", group);
 			rc_num = rc_num | data_buffer_64.setBit(54);
 			rc_num = rc_num | data_buffer_64.setBit(55);
 		    }
@@ -448,8 +507,6 @@ ReturnCode mss_draminit_training(Target& i_target)
 
 			if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
 
-			FAPI_INF( "+++++++++++++++ Execute CCS array +++++++++++++++");
-
 			rc = mss_execute_ccs_inst_array( i_target, NUM_POLL, 60);
 			if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
 
@@ -474,8 +531,9 @@ ReturnCode mss_draminit_training(Target& i_target)
 		    }
 		}//end of step loop
 
+		// Temporarily disable this function for HW debug
 	        // Change the RTT_NOM to RTT_WR, RTT_WR to RTT_NOM
-		rc = mss_rtt_nom_rtt_wr_swap(i_target, port, primary_ranks_array[group][port], group, instruction_number);
+		//rc = mss_rtt_nom_rtt_wr_swap(i_target, port, primary_ranks_array[group][port], group, instruction_number);
 	    }
 	}//end of group loop
     }//end of port loop
@@ -490,14 +548,18 @@ ReturnCode mss_draminit_training(Target& i_target)
 
     if (complete_status == MSS_INIT_CAL_STALL)
     {
-	FAPI_ERR( "+++++++++++++++ Calibration on stalled! +++++++++++++++"); 
+	FAPI_ERR( "+++ Partial/Full calibration stall. Check Debug trace. +++"); 
 	FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_INIT_CAL_STALLED);
     }
     else if (error_status == MSS_INIT_CAL_FAIL)
     {
-	FAPI_ERR( "+++++++++++++++ Calibration on failed! +++++++++++++++");
+	FAPI_ERR( "+++ Partial/Full calibration fail. Check Debug trace. +++");
 	FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_INIT_CAL_FAILED);
     }
+    else
+    {
+	FAPI_INF( "+++ Full calibration successful. +++");
+    }
 
     return rc; 
 }
@@ -510,14 +572,12 @@ ReturnCode mss_check_cal_status( Target& i_target,
 {
     ecmdDataBufferBase cal_status_buffer_64(64);
 
-    uint8_t cal_status_reg_offset = 0;
-    cal_status_reg_offset = 48 + i_group;  
-
     uint8_t poll_count = 1;
+    uint32_t cal_status_reg_offset;
 
-    ReturnCode rc;
+    cal_status_reg_offset = 48 + i_group;
 
-    FAPI_INF( "+++++++++++++++ Check Cal Status on port: %d rank group: %d +++++++++++++++", i_port, i_group);
+    ReturnCode rc;
 
     if(i_port == 0)
     {
@@ -533,7 +593,7 @@ ReturnCode mss_check_cal_status( Target& i_target,
     while((!cal_status_buffer_64.isBitSet(cal_status_reg_offset)) &&
           (poll_count <= 20))
     {
-        FAPI_INF( "+++++++++++++++ Calibration on port: %d rank group: %d in progress. Poll count: %d +++++++++++++++", i_port, i_group, poll_count);
+        FAPI_INF( "+++ Calibration on port: %d rank group: %d in progress. Poll count: %d +++", i_port, i_group, poll_count);
 
         poll_count++;
         if(i_port == 0)
@@ -551,12 +611,12 @@ ReturnCode mss_check_cal_status( Target& i_target,
 
     if(cal_status_buffer_64.isBitSet(cal_status_reg_offset))
     {
-	FAPI_INF( "+++++++++++++++ Calibration on port: %d rank group: %d Completed! +++++++++++++++", i_port, i_group);
+	FAPI_INF( "+++ Calibration on port: %d rank group: %d finished. +++", i_port, i_group);
 	io_status = MSS_INIT_CAL_COMPLETE;
     }
     else
     {
-	FAPI_ERR( "+++++++++++++++ Calibration on port: %d rank group: %d has stalled! +++++++++++++++", i_port, i_group);
+	FAPI_ERR( "+++ Calibration on port: %d rank group: %d has stalled! +++", i_port, i_group);
 	io_status = MSS_INIT_CAL_STALL;
     }
 
@@ -571,14 +631,8 @@ ReturnCode mss_check_error_status( Target& i_target,
 {
 
     ecmdDataBufferBase cal_error_buffer_64(64);
-
-    uint8_t cal_error_reg_offset = 0;
-    cal_error_reg_offset = 60 + i_group;
-
     ReturnCode rc;
 
-    FAPI_INF( "+++++++++++++++ Check Error Status on port: %d rank group: %d +++++++++++++++", i_port, i_group);
-
     if(i_port == 0)
     {
         rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, cal_error_buffer_64);
@@ -590,51 +644,50 @@ ReturnCode mss_check_error_status( Target& i_target,
         if(rc) return rc;
     }
 
-    if(cal_error_buffer_64.isBitSet(cal_error_reg_offset))
+    if((cal_error_buffer_64.isBitSet(60)) || (cal_error_buffer_64.isBitSet(61)) || (cal_error_buffer_64.isBitSet(62)) || (cal_error_buffer_64.isBitSet(63)))
     {
-        FAPI_ERR( "+++++++++++++++ Calibration on port: %d rank group: %d failed! +++++++++++++++", i_port, i_group);
 	io_status = MSS_INIT_CAL_FAIL;
 
         if(cal_error_buffer_64.isBitSet(48))
         {
-            FAPI_ERR( "+++++++++++++++ Write leveling error occured on port: %d rank group: %d! +++++++++++++++", i_port, i_group);
+            FAPI_ERR( "+++ Write leveling error occured on port: %d rank group: %d! +++", i_port, i_group);
         }
         if(cal_error_buffer_64.isBitSet(50))
         {
-            FAPI_ERR( "+++++++++++++++ DQS Alignment error occured on port: %d rank group: %d! +++++++++++++++", i_port, i_group);
+            FAPI_ERR( "+++ DQS Alignment error occured on port: %d rank group: %d! +++", i_port, i_group);
         }
         if(cal_error_buffer_64.isBitSet(51))
         {
-            FAPI_ERR( "+++++++++++++++ RDCLK to SysClk alignment error occured on port: %d rank group: %d! +++++++++++++++", i_port, i_group);
+            FAPI_ERR( "+++ RDCLK to SysClk alignment error occured on port: %d rank group: %d! +++", i_port, i_group);
         }
         if(cal_error_buffer_64.isBitSet(52))
         {
-            FAPI_ERR( "+++++++++++++++ Read centering error occured on port: %d rank group: %d! +++++++++++++++", i_port, i_group);
+            FAPI_ERR( "+++ Read centering error occured on port: %d rank group: %d! +++", i_port, i_group);
         }
         if(cal_error_buffer_64.isBitSet(53))
         {
-            FAPI_ERR( "+++++++++++++++ Write centering error occured on port: %d rank group: %d! +++++++++++++++", i_port, i_group);
+            FAPI_ERR( "+++ Write centering error occured on port: %d rank group: %d! +++", i_port, i_group);
         }
         if(cal_error_buffer_64.isBitSet(55))
         {
-            FAPI_ERR( "+++++++++++++++ Coarse read centering error occured on port: %d rank group: %d! +++++++++++++++", i_port, i_group);
+            FAPI_ERR( "+++ Coarse read centering error occured on port: %d rank group: %d! +++", i_port, i_group);
         }
         if(cal_error_buffer_64.isBitSet(56))
         {
-            FAPI_ERR( "+++++++++++++++ Custom pattern read centering error occured on port: %d rank group: %d! +++++++++++++++", i_port, i_group);
+            FAPI_ERR( "+++ Custom pattern read centering error occured on port: %d rank group: %d! +++", i_port, i_group);
         }
         if(cal_error_buffer_64.isBitSet(57))
         {
-            FAPI_ERR( "+++++++++++++++ Custom pattern write centering error occured on port: %d rank group: %d! +++++++++++++++", i_port, i_group);
+            FAPI_ERR( "+++ Custom pattern write centering error occured on port: %d rank group: %d! +++", i_port, i_group);
         }
         if(cal_error_buffer_64.isBitSet(58))
         {
-            FAPI_ERR( "+++++++++++++++ Digital eye error occured on port: %d rank group: %d! +++++++++++++++", i_port, i_group);
+            FAPI_ERR( "+++ Digital eye error occured on port: %d rank group: %d! +++", i_port, i_group);
         }
     }
     else
     {
-	FAPI_INF( "+++++++++++++++ Calibration on port: %d rank group: %d was successful! +++++++++++++++", i_port, i_group);
+	FAPI_INF( "+++ Calibration on port: %d rank group: %d was successful. +++", i_port, i_group);
 	io_status = MSS_INIT_CAL_PASS;
     }
 
diff --git a/src/usr/hwpf/hwp/dram_training/mss_termination_control.C b/src/usr/hwpf/hwp/dram_training/mss_termination_control.C
index 52edce90c..767c56f98 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_termination_control.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_termination_control.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_termination_control.C,v 1.12 2012/12/14 21:46:04 mwuu Exp $
+// $Id: mss_termination_control.C,v 1.13 2012/12/18 15:00:36 mwuu Exp $
 /* File is created by SARAVANAN SETHURAMAN on Thur 29 Sept 2011. */
 
 //------------------------------------------------------------------------------
@@ -43,6 +43,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.13   | mwuu	  |18-Dec-12| Took out initialization of array_rcs in declaration.
 //  1.12   | mwuu	  |14-Dec-12| Updated additional fw review comments
 //  1.11   | sasethur |07-Dec-12| Updated for fw review comments
 //  1.10   | mwuu     |28-Nov-12| Added changes suggested from FW team.
@@ -853,7 +854,7 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 {
 	fapi::ReturnCode rc;
     uint32_t rc_ecmd = 0;
-	fapi::ReturnCode array_rcs[MAX_NUM_PORTS]={fapi::FAPI_RC_SUCCESS}; // capture rc per port loop
+	fapi::ReturnCode array_rcs[MAX_NUM_PORTS]; // capture rc per port loop
     uint32_t poll_count = 0;
 	uint8_t ports_valid = 0;
 	uint8_t is_sim = 0;
diff --git a/src/usr/hwpf/hwp/include/cen_scom_addresses.H b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
index 45dadf589..331790695 100755
--- a/src/usr/hwpf/hwp/include/cen_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_scom_addresses.H,v 1.45 2012/11/20 18:51:15 lapietra Exp $
+// $Id: cen_scom_addresses.H,v 1.46 2012/12/19 15:31:24 gollub Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/cen_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -44,6 +44,22 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.46   | gollub   |19-Dec-12| Added:
+//         |          |         | MCBERRPTQ
+//         |          |         | MBA_MAINT_BUFF
+//         |          |         | MBA_MAINT_BUFF_65TH_BYTE_64B_ECC
+//         |          |         | MBA_ERR_REPORTQ
+//         |          |         | MBSECCERR
+//         |          |         | MBMMRQ
+//         |          |         | MBS_MAINT_BUFF0_DATA
+//         |          |         | MBS_MAINT_BUFF0_DATA_ECC
+//         |          |         | MBSEC
+//         |          |         | MBSSYMEC
+//         |          |         | MBSEVRQ
+//         |          |         | MBNCERQ
+//         |          |         | MBRCERQ
+//         |          |         | MBMPERQ
+//         |          |         | MBUERQ
 //  1.44   | sglancy  |19-Nov-12| added ECID addresses
 //  1.42   | pardeik  |09-Nov-12| add N/M throttle register in (again)
 //  1.41   | gollub   |26-Oct-12| Added MBECCFIR AND/OR MASK registers
@@ -509,6 +525,11 @@ CONST_UINT64_T( MBA01_MBAFIRACT0_0x03010606        , ULL(0x03010606) );
 CONST_UINT64_T( MBA01_MBAFIRACT1_0x03010607        , ULL(0x03010607) );
 
 //------------------------------------------------------------------------------
+//      MBA Error Report Register
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBA01_MBA_MCBERRPTQ_0x030106e7     , ULL(0x030106e7) );
+
+//------------------------------------------------------------------------------
 //      MBA Maintenance Command Type Register
 //------------------------------------------------------------------------------
 CONST_UINT64_T( MBA01_MBMCTQ_0x0301060A           , ULL(0x0301060A) );
@@ -560,30 +581,50 @@ CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF0_DATA0_0x03010655           , ULL(0x030106
 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF0_DATA1_0x03010656           , ULL(0x03010656) );
 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF0_DATA2_0x03010657           , ULL(0x03010657) );
 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF0_DATA3_0x03010658           , ULL(0x03010658) );
+CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF0_DATA4_0x03010659           , ULL(0x03010659) );
+CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF0_DATA5_0x0301065a           , ULL(0x0301065a) );
+CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF0_DATA6_0x0301065b           , ULL(0x0301065b) );
+CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF0_DATA7_0x0301065c           , ULL(0x0301065c) );
 
 // Maint Read Buffer1
 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF1_DATA0_0x03010665           , ULL(0x03010665) );
 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF1_DATA1_0x03010666           , ULL(0x03010666) );
 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF1_DATA2_0x03010667           , ULL(0x03010667) );
 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF1_DATA3_0x03010668           , ULL(0x03010668) );
+CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF1_DATA4_0x03010669           , ULL(0x03010669) );
+CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF1_DATA5_0x0301066a           , ULL(0x0301066a) );
+CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF1_DATA6_0x0301066b           , ULL(0x0301066b) );
+CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF1_DATA7_0x0301066c           , ULL(0x0301066c) );
 
 // Maint Read Buffer2
 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF2_DATA0_0x03010675           , ULL(0x03010675) );
 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF2_DATA1_0x03010676           , ULL(0x03010676) );
 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF2_DATA2_0x03010677           , ULL(0x03010677) );
 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF2_DATA3_0x03010678           , ULL(0x03010678) );
+CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF2_DATA4_0x03010679           , ULL(0x03010679) );
+CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF2_DATA5_0x0301067a           , ULL(0x0301067a) );
+CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF2_DATA6_0x0301067b           , ULL(0x0301067b) );
+CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF2_DATA7_0x0301067c           , ULL(0x0301067c) );
 
 // Maint Read Buffer3
 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF3_DATA0_0x03010685           , ULL(0x03010685) );
 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF3_DATA1_0x03010686           , ULL(0x03010686) );
 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF3_DATA2_0x03010687           , ULL(0x03010687) );
 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF3_DATA3_0x03010688           , ULL(0x03010688) );
+CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF3_DATA4_0x03010689           , ULL(0x03010689) );
+CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF3_DATA5_0x0301068a           , ULL(0x0301068a) );
+CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF3_DATA6_0x0301068b           , ULL(0x0301068b) );
+CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF3_DATA7_0x0301068c           , ULL(0x0301068c) );
 
 // Maint Read Buffers 65th Byte
 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC0_0x03010695 , ULL(0x03010695) );
 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC1_0x03010696 , ULL(0x03010696) );
 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC2_0x03010697 , ULL(0x03010697) );
 CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC3_0x03010698 , ULL(0x03010698) );
+CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC4_0x03010699 , ULL(0x03010699) );
+CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC5_0x0301069a , ULL(0x0301069a) );
+CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC6_0x0301069b , ULL(0x0301069b) );
+CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC7_0x0301069c , ULL(0x0301069c) );
 
 
 //------------------------------------------------------------------------------
@@ -609,6 +650,11 @@ CONST_UINT64_T( MBA01_MBACALFIR_ACTION0_0x03010406   , ULL(0x03010406) );
 CONST_UINT64_T( MBA01_MBACALFIR_ACTION1_0x03010407   , ULL(0x03010407) );
 
 //------------------------------------------------------------------------------
+//      MBA Error report register
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBA01_MBA_ERR_REPORTQ_0x0301041A     , ULL(0x0301041A) );
+
+//------------------------------------------------------------------------------
 //      MBA WRD Mode Register
 //------------------------------------------------------------------------------
 CONST_UINT64_T( MBA01_MBA_WRD_MODE_0x03010449           , ULL(0x03010449) );
@@ -645,6 +691,14 @@ CONST_UINT64_T( MBS_ECC1_MBECCFIR_ACTION0_0x02011486   , ULL(0x02011486) );
 CONST_UINT64_T( MBS_ECC1_MBECCFIR_ACTION1_0x02011487   , ULL(0x02011487) );
 
 //------------------------------------------------------------------------------
+//      MBS ECC Error Report Hold Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBS_ECC0_MBSECCERR0_0x02011466           , ULL(0x02011466) );
+CONST_UINT64_T( MBS_ECC0_MBSECCERR1_0x02011467           , ULL(0x02011467) );
+CONST_UINT64_T( MBS_ECC1_MBSECCERR0_0x020114A6           , ULL(0x020114A6) );
+CONST_UINT64_T( MBS_ECC1_MBSECCERR1_0x020114A7           , ULL(0x020114A7) );
+
+//------------------------------------------------------------------------------
 //      MBS Memory ECC Mark Store Registers
 //------------------------------------------------------------------------------
 CONST_UINT64_T( MBS_ECC0_MBMS0_0x0201144B           , ULL(0x0201144B) );
@@ -666,6 +720,12 @@ CONST_UINT64_T( MBS_ECC1_MBMS6_0x02011491           , ULL(0x02011491) );
 CONST_UINT64_T( MBS_ECC1_MBMS7_0x02011492           , ULL(0x02011492) );
 
 //------------------------------------------------------------------------------
+//      MBS Maintenance Mark Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBS_ECC0_MBMMRQ_0x0201145B          , ULL(0x0201145B) );
+CONST_UINT64_T( MBS_ECC1_MBMMRQ_0x0201149B          , ULL(0x0201149B) );
+
+//------------------------------------------------------------------------------
 //      MBS Read Bit Steer Control Registers
 //------------------------------------------------------------------------------
 CONST_UINT64_T( MBS_ECC0_MBSBS0_0x0201145E           , ULL(0x0201145E) );
@@ -696,11 +756,13 @@ CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF0_DATA0_0x0201160A				, ULL(0x0201160A) );
 CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF0_DATA1_0x0201160B				, ULL(0x0201160B) );
 CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF0_DATA2_0x0201160C				, ULL(0x0201160C) );
 CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF0_DATA3_0x0201160D				, ULL(0x0201160D) );
+CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF0_DATA4_0x0201160E				, ULL(0x0201160E) );
 
 CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF0_DATA_ECC0_0x02011612			, ULL(0x02011612) );
 CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF0_DATA_ECC1_0x02011613			, ULL(0x02011613) );
 CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF0_DATA_ECC2_0x02011614			, ULL(0x02011614) );
 CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF0_DATA_ECC3_0x02011615			, ULL(0x02011615) );
+CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF0_DATA_ECC4_0x02011616			, ULL(0x02011616) );
 
 // Maint Write Buffer 1
 CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF1_DATA0_0x0201161A				, ULL(0x0201161A) );
@@ -751,11 +813,13 @@ CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF0_DATA0_0x0201170A				, ULL(0x0201170A) );
 CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF0_DATA1_0x0201170B				, ULL(0x0201170B) );
 CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF0_DATA2_0x0201170C				, ULL(0x0201170C) );
 CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF0_DATA3_0x0201170D				, ULL(0x0201170D) );
+CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF0_DATA4_0x0201170E				, ULL(0x0201170E) );
 
 CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF0_DATA_ECC0_0x02011712			, ULL(0x02011712) );
 CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF0_DATA_ECC1_0x02011713			, ULL(0x02011713) );
 CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF0_DATA_ECC2_0x02011714			, ULL(0x02011714) );
 CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF0_DATA_ECC3_0x02011715			, ULL(0x02011715) );
+CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF0_DATA_ECC4_0x02011716			, ULL(0x02011716) );
 
 // Maint Write Buffer 1
 CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF1_DATA0_0x0201171A				, ULL(0x0201171A) );
@@ -809,6 +873,67 @@ CONST_UINT64_T( MBS01_MBSTRQ_0x02011655           , ULL(0x02011655) );
 CONST_UINT64_T( MBS23_MBSTRQ_0x02011755           , ULL(0x02011755) );
 
 //------------------------------------------------------------------------------
+//	    MBS Memory Scrub/Read Error Count Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBS01_MBSEC0Q_0x02011653           , ULL(0x02011653) );
+CONST_UINT64_T( MBS01_MBSEC1Q_0x02011654           , ULL(0x02011654) );
+CONST_UINT64_T( MBS23_MBSEC0Q_0x02011753           , ULL(0x02011753) );
+CONST_UINT64_T( MBS23_MBSEC1Q_0x02011754           , ULL(0x02011754) );
+
+//------------------------------------------------------------------------------
+//      MBS Memory Scrub/Read Symbol Error Count Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBS01_MBSSYMEC0Q_0x02011656           , ULL(0x02011656) );
+CONST_UINT64_T( MBS01_MBSSYMEC1Q_0x02011657           , ULL(0x02011657) );
+CONST_UINT64_T( MBS01_MBSSYMEC2Q_0x02011658           , ULL(0x02011658) );
+CONST_UINT64_T( MBS01_MBSSYMEC3Q_0x02011659           , ULL(0x02011659) );
+CONST_UINT64_T( MBS01_MBSSYMEC4Q_0x0201165A           , ULL(0x0201165A) );
+CONST_UINT64_T( MBS01_MBSSYMEC5Q_0x0201165B           , ULL(0x0201165B) );
+CONST_UINT64_T( MBS01_MBSSYMEC6Q_0x0201165C           , ULL(0x0201165C) );
+CONST_UINT64_T( MBS01_MBSSYMEC7Q_0x0201165D           , ULL(0x0201165D) );
+CONST_UINT64_T( MBS01_MBSSYMEC8Q_0x0201165E           , ULL(0x0201165E) );
+CONST_UINT64_T( MBS23_MBSSYMEC0Q_0x02011756           , ULL(0x02011756) );
+CONST_UINT64_T( MBS23_MBSSYMEC1Q_0x02011757           , ULL(0x02011757) );
+CONST_UINT64_T( MBS23_MBSSYMEC2Q_0x02011758           , ULL(0x02011758) );
+CONST_UINT64_T( MBS23_MBSSYMEC3Q_0x02011759           , ULL(0x02011759) );
+CONST_UINT64_T( MBS23_MBSSYMEC4Q_0x0201175A           , ULL(0x0201175A) );
+CONST_UINT64_T( MBS23_MBSSYMEC5Q_0x0201175B           , ULL(0x0201175B) );
+CONST_UINT64_T( MBS23_MBSSYMEC6Q_0x0201175C           , ULL(0x0201175C) );
+CONST_UINT64_T( MBS23_MBSSYMEC7Q_0x0201175D           , ULL(0x0201175D) );
+CONST_UINT64_T( MBS23_MBSSYMEC8Q_0x0201175E           , ULL(0x0201175E) );
+
+
+//------------------------------------------------------------------------------
+//      MBS Memory Error Vector Register
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBS01_MBSEVRQ_0x0201165F              , ULL(0x0201165F) );
+CONST_UINT64_T( MBS23_MBSEVRQ_0x0201175F              , ULL(0x0201175F) );
+
+//------------------------------------------------------------------------------
+//      MBS Memory NCE Error Address Register
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBS01_MBNCERQ_0x02011660              , ULL(0x02011660) );
+CONST_UINT64_T( MBS23_MBNCERQ_0x02011760              , ULL(0x02011760) );
+
+//------------------------------------------------------------------------------
+//      MBS Memory RCE Error Address Register
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBS01_MBRCERQ_0x02011661              , ULL(0x02011661) );
+CONST_UINT64_T( MBS23_MBRCERQ_0x02011761              , ULL(0x02011761) );
+
+//------------------------------------------------------------------------------
+//      MBS Memory MPE Error Address Register
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBS01_MBMPERQ_0x02011662              , ULL(0x02011662) );
+CONST_UINT64_T( MBS23_MBMPERQ_0x02011762              , ULL(0x02011762) );
+
+//------------------------------------------------------------------------------
+//      MBS Memory UE Error Address Register
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBS01_MBUERQ_0x02011663               , ULL(0x02011663) );
+CONST_UINT64_T( MBS23_MBUERQ_0x02011763               , ULL(0x02011763) );
+
+//------------------------------------------------------------------------------
 //      MBS FIR Registers
 //------------------------------------------------------------------------------
 CONST_UINT64_T( MBS_FIR_REG_0x02011400              , ULL(0x02011400) );
@@ -1363,6 +1488,25 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: cen_scom_addresses.H,v $
+Revision 1.46  2012/12/19 15:31:24  gollub
+
+Added:
+MCBERRPTQ
+MBA_MAINT_BUFF
+MBA_MAINT_BUFF_65TH_BYTE_64B_ECC
+MBA_ERR_REPORTQ
+MBSECCERR
+MBMMRQ
+MBS_MAINT_BUFF0_DATA
+MBS_MAINT_BUFF0_DATA_ECC
+MBSEC
+MBSSYMEC
+MBSEVRQ
+MBNCERQ
+MBRCERQ
+MBMPERQ
+MBUERQ
+
 Revision 1.45  2012/11/20 18:51:15  lapietra
 Fixed errors in get_data
 
diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
index 6df8eb25d..27e0f37b2 100644
--- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile
+++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
@@ -1,5 +1,5 @@
 
-#-- $Id: mba_def.initfile,v 1.22 2012/12/04 16:03:26 mwuu Exp $
+#-- $Id: mba_def.initfile,v 1.24 2013/01/04 20:38:58 yctschan Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
@@ -233,7 +233,7 @@ define def_has_spare    =   (SYS.ATTR_IS_SIMULATION==0) ;
 #define  def_ATTR_EFF_DRAM_2N_MODE = 0;
 #define def_ATTR_EFF_IBM_TYPE           = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
 #define def_ATTR_EFF_NUM_DROPS_PER_PORT = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_ATTR_EFF_DRAM_2N_MODE       = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
+define def_ATTR_EFF_DRAM_2N_MODE       = (CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
 
 define CENTAUR = TGT1;
 
@@ -251,15 +251,15 @@ define def_1b_2socket        = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_T
 ## 1C 1 and 2 sockets not supported
 #define def_1c_1socket   = 0;
 #define def_1c_2socket   = 0;
-define def_1c_1socket        = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_1c_2socket        = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
+define def_1c_1socket        = (CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+define def_1c_2socket        = (CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
 define def_1c_cdimm          = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 3 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 3 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 0));  # same as type1B 2 socket RDIMM cfg for DDR3/4
 
 ## Current they is no 1D IBM type in the attribute
 #define def_1d_1socket       = 0;
 #define def_1d_2socket       = 0;
-#define def_1d_1socket        = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-#define def_1d_2socket        = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
+#define def_1d_1socket        = (CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+#define def_1d_2socket        = (CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
 define def_1d_1socket       = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 4 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1));
 define def_1d_2socket       = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 4 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2));
 
@@ -349,19 +349,19 @@ define def_mtype_3c = ((def_3c_1socket_ddr4)||(def_3c_2socket_ddr4)||(def_4c_ddr
 #define def_mtype_4b = 0; # not supported
 #define def_mtype_4c = 0; # not supported
 #define def_mtype_5a = 0; # not supported
-define def_mtype_4a = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_mtype_4b = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_mtype_4c = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_mtype_5a = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
+define def_mtype_4a = (CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+define def_mtype_4b = (CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+define def_mtype_4c = (CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+define def_mtype_5a = (CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
 define def_mtype_5b = ((def_5b_1socket     )||(def_5b_2socket));
 define def_mtype_5c = ((def_5c_1socket     )||(def_5c_2socket));
 define def_mtype_5d = ((def_5d_1socket     )||(def_5d_2socket));
 #define def_mtype_6a = 0; # not supported
 #define def_mtype_6b = 0; # not supported
 #define def_mtype_6c = 0; # not supported
-define def_mtype_6a = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_mtype_6b = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_mtype_6c = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
+define def_mtype_6a = (CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+define def_mtype_6b = (CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+define def_mtype_6c = (CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
 define def_mtype_7a = ((def_7a_1socket     )||(def_7a_2socket     )||(def_7a_1socket_ddr4)||(def_7a_2socket_ddr4));
 define def_mtype_7b = ((def_7b_1socket     )||(def_7b_2socket     )||(def_7b_1socket_ddr4)||(def_7b_2socket_ddr4));
 define def_mtype_7c = ((def_7c_1socket     )||(def_7c_2socket     )||(def_7c_1socket_ddr4)||(def_7c_2socket_ddr4));
@@ -563,16 +563,16 @@ define  def_ddr4_1866_13_13_13_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR
 #define  def_ddr4_2133_13_13_13_2N = 0;
 #define  def_ddr4_2133_13_13_13_L2 = 0;
 #define  def_ddr4_2133_13_13_13_LR = 0;
-define  def_ddr4_2133_12_12_12    = (SYS.ATTR_IS_SIMULATION==0);
-define  def_ddr4_2133_12_12_12R   = (SYS.ATTR_IS_SIMULATION==0);
-define  def_ddr4_2133_12_12_12_2N = (SYS.ATTR_IS_SIMULATION==0);
-define  def_ddr4_2133_12_12_12_L2 = (SYS.ATTR_IS_SIMULATION==0);
-define  def_ddr4_2133_12_12_12_LR = (SYS.ATTR_IS_SIMULATION==0);
-define  def_ddr4_2133_13_13_13    = (SYS.ATTR_IS_SIMULATION==0);
-define  def_ddr4_2133_13_13_13R   = (SYS.ATTR_IS_SIMULATION==0);
-define  def_ddr4_2133_13_13_13_2N = (SYS.ATTR_IS_SIMULATION==0);
-define  def_ddr4_2133_13_13_13_L2 = (SYS.ATTR_IS_SIMULATION==0);
-define  def_ddr4_2133_13_13_13_LR = (SYS.ATTR_IS_SIMULATION==0);
+define  def_ddr4_2133_12_12_12    = (CENTAUR.ATTR_MSS_FREQ == 1400);
+define  def_ddr4_2133_12_12_12R   = (CENTAUR.ATTR_MSS_FREQ == 1400);
+define  def_ddr4_2133_12_12_12_2N = (CENTAUR.ATTR_MSS_FREQ == 1400);
+define  def_ddr4_2133_12_12_12_L2 = (CENTAUR.ATTR_MSS_FREQ == 1400);
+define  def_ddr4_2133_12_12_12_LR = (CENTAUR.ATTR_MSS_FREQ == 1400);
+define  def_ddr4_2133_13_13_13    = (CENTAUR.ATTR_MSS_FREQ == 1400);
+define  def_ddr4_2133_13_13_13R   = (CENTAUR.ATTR_MSS_FREQ == 1400);
+define  def_ddr4_2133_13_13_13_2N = (CENTAUR.ATTR_MSS_FREQ == 1400);
+define  def_ddr4_2133_13_13_13_L2 = (CENTAUR.ATTR_MSS_FREQ == 1400);
+define  def_ddr4_2133_13_13_13_LR = (CENTAUR.ATTR_MSS_FREQ == 1400);
 
 #define  def_ddr4_2133_12_12_12    = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2));
 #define  def_ddr4_2133_12_12_12R   = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 ));
@@ -596,16 +596,16 @@ define  def_ddr4_2133_13_13_13_LR = (SYS.ATTR_IS_SIMULATION==0);
 #define  def_ddr4_2400_14_14_14_2N = 0;
 #define  def_ddr4_2400_14_14_14_L2 = 0;
 #define  def_ddr4_2400_14_14_14_LR = 0;
-define  def_ddr4_2400_13_13_13    = (SYS.ATTR_IS_SIMULATION==0);
-define  def_ddr4_2400_13_13_13R   = (SYS.ATTR_IS_SIMULATION==0);
-define  def_ddr4_2400_13_13_13_2N = (SYS.ATTR_IS_SIMULATION==0);
-define  def_ddr4_2400_13_13_13_L2 = (SYS.ATTR_IS_SIMULATION==0);
-define  def_ddr4_2400_13_13_13_LR = (SYS.ATTR_IS_SIMULATION==0);
-define  def_ddr4_2400_14_14_14    = (SYS.ATTR_IS_SIMULATION==0);
-define  def_ddr4_2400_14_14_14R   = (SYS.ATTR_IS_SIMULATION==0);
-define  def_ddr4_2400_14_14_14_2N = (SYS.ATTR_IS_SIMULATION==0);
-define  def_ddr4_2400_14_14_14_L2 = (SYS.ATTR_IS_SIMULATION==0);
-define  def_ddr4_2400_14_14_14_LR = (SYS.ATTR_IS_SIMULATION==0);
+define  def_ddr4_2400_13_13_13    = (CENTAUR.ATTR_MSS_FREQ == 1400);
+define  def_ddr4_2400_13_13_13R   = (CENTAUR.ATTR_MSS_FREQ == 1400);
+define  def_ddr4_2400_13_13_13_2N = (CENTAUR.ATTR_MSS_FREQ == 1400);
+define  def_ddr4_2400_13_13_13_L2 = (CENTAUR.ATTR_MSS_FREQ == 1400);
+define  def_ddr4_2400_13_13_13_LR = (CENTAUR.ATTR_MSS_FREQ == 1400);
+define  def_ddr4_2400_14_14_14    = (CENTAUR.ATTR_MSS_FREQ == 1400);
+define  def_ddr4_2400_14_14_14R   = (CENTAUR.ATTR_MSS_FREQ == 1400);
+define  def_ddr4_2400_14_14_14_2N = (CENTAUR.ATTR_MSS_FREQ == 1400);
+define  def_ddr4_2400_14_14_14_L2 = (CENTAUR.ATTR_MSS_FREQ == 1400);
+define  def_ddr4_2400_14_14_14_LR = (CENTAUR.ATTR_MSS_FREQ == 1400);
 
 #define  def_ddr4_2400_13_13_13    = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2));
 #define  def_ddr4_2400_13_13_13R   = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 ));
@@ -2057,24 +2057,25 @@ scom 0x0301040A     {
     30:35   ,   0b010001    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly17 == 1); # wrdata_dly		26
     30:35   ,   0b010010    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly18 == 1); # wrdata_dly		26
     30:35   ,   0b010011    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly19 == 1); # wrdata_dly		26
-    36:41   ,   0b001100    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly12 == 1); # rdtag_dly		27
-    36:41   ,   0b001101    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly13 == 1); # rdtag_dly		27
-    36:41   ,   0b001110    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly14 == 1); # rdtag_dly		27
-    36:41   ,   0b001111    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly15 == 1); # rdtag_dly		27
-    36:41   ,   0b010000    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly16 == 1); # rdtag_dly		27
-    36:41   ,   0b010001    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly17 == 1); # rdtag_dly		27
-    36:41   ,   0b010010    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly18 == 1); # rdtag_dly		27
-    36:41   ,   0b010011    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly19 == 1); # rdtag_dly		27
-    36:41   ,   0b010100    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly20 == 1); # rdtag_dly		27
-    36:41   ,   0b010101    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly21 == 1); # rdtag_dly		27
-    36:41   ,   0b010110    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly22 == 1); # rdtag_dly		27
-    36:41   ,   0b010111    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly23 == 1); # rdtag_dly		27
-    36:41   ,   0b011000    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly24 == 1); # rdtag_dly		27
-    36:41   ,   0b011001    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly25 == 1); # rdtag_dly		27
-    36:41   ,   0b011010    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly26 == 1); # rdtag_dly		27
-    36:41   ,   0b011011    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly27 == 1); # rdtag_dly		27
-    36:41   ,   0b011100    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly28 == 1); # rdtag_dly		27
-    36:41   ,   0b011101    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly29 == 1); # rdtag_dly		27
+#    36:41   ,   0b001100    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly12 == 1); # rdtag_dly		27
+#    36:41   ,   0b001101    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly13 == 1); # rdtag_dly		27
+#    36:41   ,   0b001110    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly14 == 1); # rdtag_dly		27
+#    36:41   ,   0b001111    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly15 == 1); # rdtag_dly		27
+#    36:41   ,   0b010000    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly16 == 1); # rdtag_dly		27
+#    36:41   ,   0b010001    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly17 == 1); # rdtag_dly		27
+#    36:41   ,   0b010010    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly18 == 1); # rdtag_dly		27
+#    36:41   ,   0b010011    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly19 == 1); # rdtag_dly		27
+#    36:41   ,   0b010100    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly20 == 1); # rdtag_dly		27
+#    36:41   ,   0b010101    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly21 == 1); # rdtag_dly		27
+#    36:41   ,   0b010110    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly22 == 1); # rdtag_dly		27
+#    36:41   ,   0b010111    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly23 == 1); # rdtag_dly		27
+#    36:41   ,   0b011000    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly24 == 1); # rdtag_dly		27
+#    36:41   ,   0b011001    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly25 == 1); # rdtag_dly		27
+#    36:41   ,   0b011010    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly26 == 1); # rdtag_dly		27
+#    36:41   ,   0b011011    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly27 == 1); # rdtag_dly		27
+#    36:41   ,   0b011100    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly28 == 1); # rdtag_dly		27
+#    36:41   ,   0b011101    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly29 == 1); # rdtag_dly		27
+    36:41   ,   0b100100    ,           1            ,    any                                 ; # rdtag_dly		36  temporary fix for testfloor
     43:48   ,   0b000101    ,           1            ,    (def_mba_dsm0q_CFG_RODT_BC4_END_DLY5 == 1); # CFG_RODT_BC4_END_DLY 28
     43:48   ,   0b000110    ,           1            ,    (def_mba_dsm0q_CFG_RODT_BC4_END_DLY6 == 1); # CFG_RODT_BC4_END_DLY 28
     43:48   ,   0b000111    ,           1            ,    (def_mba_dsm0q_CFG_RODT_BC4_END_DLY7 == 1); # CFG_RODT_BC4_END_DLY 28
@@ -2406,20 +2407,26 @@ scom 0x03010433      {
 }
 
 #define def_zqcal_timebase_in_ms=(16384*(1/CENTAUR.ATTR_MSS_FREQ)*.001)
-define def_zq_intv  = (ATTR_EFF_ZQCAL_INTERVAL / 16384);
+define def_zq_intv_sel10  = (ATTR_EFF_ZQCAL_INTERVAL / 16384);
+define def_zq_intv_sel11  = (ATTR_EFF_ZQCAL_INTERVAL / 16777216);
 #define def_memcal_timebase_in_ms=(16384*(1/CENTAUR.ATTR_MSS_FREQ)*.001)
-define def_mem_intv =  (ATTR_EFF_MEMCAL_INTERVAL / 16384);
+define def_mem_intv_sel10 =  (ATTR_EFF_MEMCAL_INTERVAL / 16384);
+define def_mem_intv_sel11 =  (ATTR_EFF_MEMCAL_INTERVAL / 16777216);
 #    ATTR_EFF_MEMCAL_INTERVAL are in clock cycles
 #    ATTR_EFF_ZQCAL_INTERVAL are in clock cycles
-
+#ATTR_EFF_MEMCAL_INTERVAL    u32    0x027b9fba
+#ATTR_EFF_ZQCAL_INTERVAL    u32    0x008798a
 # MBA_CAL0Q (this timer to be used for zq cal)
 #
 scom 0x0301040F    {
 
     bits    ,   scom_data        ,       ATTR_FUNCTIONAL,   expr;
     0       ,   0b0              ,          1            ,     any;    #disable timer initially
-    1:2     ,   0b10             ,          1            ,     any;    #timebase; use 16384 cycle timebase; zqcal_timebase_in_ms=16384*(1/DRAM_freq_in_MHz)*1e-3
-    3:11    ,   def_zq_intv      ,          1            ,     any;    #interval timer; computed using zq cal interval attribute; zq_intv=zq_cal_interval_attr/zqcal_timebase_in_ms (assumes attribute defined in milliseconds)
+    1:2     ,   0b10             ,          1            ,     (def_zq_intv_sel10 < 512);    #timebase; use 16384 cycle timebase if less than max of 512
+    1:2     ,   0b11             ,          1            ,     (def_zq_intv_sel10 > 511);    #timebase; use 16777216 cycle timebase if greater than max of 512
+    3:11    ,   def_zq_intv_sel10,          1            ,     (def_zq_intv_sel10 < 512);    #interval timer; computed using zq cal interval attribute; zq_intv=zq_cal_interval_attr/zqcal_timebase_in_ms (assumes attribute defined in milliseconds)
+    3:11    ,   0b000000001      ,          1            ,     (def_zq_intv_sel10 > 511) && (def_zq_intv_sel11 == 0);    #interval timer; computed using zq cal interval attribute; zq_intv=zq_cal_interval_attr/zqcal_timebase_in_ms (assumes attribute defined in milliseconds)
+    3:11    ,   def_zq_intv_sel11,          1            ,     (def_zq_intv_sel10 > 511) && (def_zq_intv_sel11 > 0);    #interval timer; computed using zq cal interval attribute; zq_intv=zq_cal_interval_attr/zqcal_timebase_in_ms (assumes attribute defined in milliseconds)
     12      ,   0b1              ,          1            ,     any;    #enable for type1
     13:16   ,   0b0100           ,          1            ,     any;    #select external zq cal for type1
     17      ,   0b1              ,          1            ,     any;    #wait for done from DDR for type1
@@ -2446,10 +2453,13 @@ scom 0x03010410    {
 
     bits    ,   scom_data                      ,       ATTR_FUNCTIONAL,   expr;
     0       ,   0b0                            ,          1            ,    any;    #disable timer initially
-    1:2     ,   0b10                           ,          1            ,    any;    #timebase; use 16384 cycle timebase; memcal_timebase_in_ms=16384*(1/DRAM_freq_in_MHz)*1e-3
-    3:11    ,   def_mem_intv                   ,          1            ,    any;    #interval timer; computed using zq cal interval attribute; mem_intv=mem_cal_interval_attr/memcal_timebase_in_ms (assumes attribute defined in milliseconds)
+    1:2     ,   0b10                           ,          1            ,    (def_mem_intv_sel10 < 512);    #timebase; use 16384 cycle timebase if less than max of 512
+    1:2     ,   0b11                           ,          1            ,    (def_mem_intv_sel10 > 511);    #timebase; use 16777216 cycle timebase if greater than max of 512
+    3:11    ,   def_mem_intv_sel10             ,          1            ,    (def_mem_intv_sel10 < 512);    #interval timer; computed using zq cal interval attribute; mem_intv=mem_cal_interval_attr/memcal_timebase_in_ms (assumes attribute defined in milliseconds)
+    3:11    ,   0b000000001                    ,          1            ,    (def_mem_intv_sel10 > 511) && (def_mem_intv_sel11 == 0);    #interval timer; computed using zq cal interval attribute; mem_intv=mem_cal_interval_attr/memcal_timebase_in_ms (assumes attribute defined in milliseconds)
+    3:11    ,   def_mem_intv_sel11             ,          1            ,    (def_mem_intv_sel10 > 511) && (def_mem_intv_sel11 > 0);    #interval timer; computed using zq cal interval attribute; mem_intv=mem_cal_interval_attr/memcal_timebase_in_ms (assumes attribute defined in milliseconds)
     12      ,   0b1                            ,          1            ,    any;    #enable for type1
-    13:16   ,   0b0100                         ,          1            ,    any;    #select external zq cal for type1
+    13:16   ,   0b0011                         ,          1            ,    any;    #select Periodic Calbration: Run SysClk, DQS and Read Eye all in parallel for type
     17      ,   0b1                            ,          1            ,    any;    #wait for done from DDR for type1
     18      ,   0b0                            ,          1            ,    any;    #disable type2 timer
     19:22   ,   0b0000                         ,          1            ,    any;    #type2 cal type
diff --git a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile
index 37277bdc2..86d6b08a6 100644
--- a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile
+++ b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile
@@ -1,4 +1,4 @@
-#-- $Id: mbs_def.initfile,v 1.23 2012/10/23 14:29:41 yctschan Exp $
+#-- $Id: mbs_def.initfile,v 1.24 2012/12/18 23:26:51 yctschan Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
@@ -82,9 +82,9 @@ define def_has_spare    =   (SYS.ATTR_IS_SIMULATION==0) ;
 #define def_ATTR_EFF_IBM_TYPE = 1;
 #define def_ATTR_EFF_NUM_DROPS_PER_PORT = 1;
 #define  def_ATTR_EFF_DRAM_2N_MODE = 0;
-#define def_ATTR_EFF_IBM_TYPE           = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-#define def_ATTR_EFF_NUM_DROPS_PER_PORT = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_ATTR_EFF_DRAM_2N_MODE       = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
+#define def_ATTR_EFF_IBM_TYPE           = (SYS.CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+#define def_ATTR_EFF_NUM_DROPS_PER_PORT = (SYS.CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+define def_ATTR_EFF_DRAM_2N_MODE       = (CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
 
 define def_mba01_nomem        =  ((MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] == 0b00000000) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] == 0b00000000));
 define def_mba23_nomem        =  ((MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] == 0b00000000) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] == 0b00000000));
@@ -101,15 +101,15 @@ define def_mba01_1b_2socket        = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2 )))
 ## 1C 1 and 2 sockets not supported
 #define def_mba01_1c_1socket   = 0;
 #define def_mba01_1c_2socket   = 0;
-define def_mba01_1c_1socket        = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_mba01_1c_2socket        = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
+define def_mba01_1c_1socket        = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+define def_mba01_1c_2socket        = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
 define def_mba01_1c_cdimm          = ((((MBA0.ATTR_CHIP_UNIT_POS == 1 ) && (MBA0.ATTR_EFF_IBM_TYPE[1][0] == 3 )) || ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 3 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0));  # same as type1B 2 socket RDIMM cfg for DDR3/4
 
 ## Current they is no 1D IBM type in the attribute
 #define def_mba01_1d_1socket       = 0;
 #define def_mba01_1d_2socket       = 0;
-define def_mba01_1d_1socket        = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_mba01_1d_2socket        = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
+define def_mba01_1d_1socket        = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+define def_mba01_1d_2socket        = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
 #define def_mba01_1d_1socket       = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
 #define def_mba01_1d_2socket       = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2));
 
@@ -197,15 +197,15 @@ define def_mba23_1b_2socket        = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2 )))
 ## 1C 1 and 2 sockets not supported
 #define def_mba23_1c_1socket   = 0;
 #define def_mba23_1c_2socket   = 0;
-define def_mba23_1c_1socket        = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_mba23_1c_2socket        = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
+define def_mba23_1c_1socket        = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+define def_mba23_1c_2socket        = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
 define def_mba23_1c_cdimm          = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 3 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0));  # same as type1B 2 socket RDIMM cfg for DDR3/4
 
 ## Current they is no 1D IBM type in the attribute
 #define def_mba23_1d_1socket       = 0;
 #define def_mba23_1d_2socket       = 0;
-define def_mba23_1d_1socket        = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_mba23_1d_2socket        = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
+define def_mba23_1d_1socket        = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+define def_mba23_1d_2socket        = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
 #define def_mba23_1d_1socket       = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
 #define def_mba23_1d_2socket       = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2));
 
@@ -295,19 +295,19 @@ define def_mba01_mtype_3c = (def_mba01_3c_1socket_ddr4||def_mba01_3c_2socket_ddr
 #define def_mba01_mtype_4b = 0; # not supported
 #define def_mba01_mtype_4c = 0; # not supported
 #define def_mba01_mtype_5a = 0; # not supported
-define def_mba01_mtype_4a = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_mba01_mtype_4b = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_mba01_mtype_4c = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_mba01_mtype_5a = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
+define def_mba01_mtype_4a = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+define def_mba01_mtype_4b = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+define def_mba01_mtype_4c = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+define def_mba01_mtype_5a = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
 define def_mba01_mtype_5b = ((def_mba01_5b_1socket     )||(def_mba01_5b_2socket));
 define def_mba01_mtype_5c = ((def_mba01_5c_1socket     )||(def_mba01_5c_2socket));
 define def_mba01_mtype_5d = ((def_mba01_5d_1socket     )||(def_mba01_5d_2socket));
 #define def_mba01_mtype_6a = 0; # not supported
 #define def_mba01_mtype_6b = 0; # not supported
 #define def_mba01_mtype_6c = 0; # not supported
-define def_mba01_mtype_6a = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_mba01_mtype_6b = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_mba01_mtype_6c = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
+define def_mba01_mtype_6a = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+define def_mba01_mtype_6b = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+define def_mba01_mtype_6c = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
 define def_mba01_mtype_7a = (def_mba01_7a_1socket     ||def_mba01_7a_2socket     ||def_mba01_7a_1socket_ddr4||def_mba01_7a_2socket_ddr4);
 define def_mba01_mtype_7b = (def_mba01_7b_1socket     ||def_mba01_7b_2socket     ||def_mba01_7b_1socket_ddr4||def_mba01_7b_2socket_ddr4);
 define def_mba01_mtype_7c = (def_mba01_7c_1socket     ||def_mba01_7c_2socket     ||def_mba01_7c_1socket_ddr4||def_mba01_7c_2socket_ddr4);
@@ -325,19 +325,19 @@ define def_mba23_mtype_3c = (def_mba23_3c_1socket_ddr4||def_mba23_3c_2socket_ddr
 #define def_mba23_mtype_4b = 0; # not supported
 #define def_mba23_mtype_4c = 0; # not supported
 #define def_mba23_mtype_5a = 0; # not supported
-define def_mba23_mtype_4a = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_mba23_mtype_4b = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_mba23_mtype_4c = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_mba23_mtype_5a = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
+define def_mba23_mtype_4a = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+define def_mba23_mtype_4b = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+define def_mba23_mtype_4c = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+define def_mba23_mtype_5a = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
 define def_mba23_mtype_5b = ((def_mba23_5b_1socket     )||(def_mba23_5b_2socket));
 define def_mba23_mtype_5c = ((def_mba23_5c_1socket     )||(def_mba23_5c_2socket));
 define def_mba23_mtype_5d = ((def_mba23_5d_1socket     )||(def_mba23_5d_2socket));
 #define def_mba23_mtype_6a = 0; # not supported
 #define def_mba23_mtype_6b = 0; # not supported
 #define def_mba23_mtype_6c = 0; # not supported
-define def_mba23_mtype_6a = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_mba23_mtype_6b = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_mba23_mtype_6c = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
+define def_mba23_mtype_6a = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+define def_mba23_mtype_6b = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+define def_mba23_mtype_6c = (ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
 define def_mba23_mtype_7a = (def_mba23_7a_1socket     ||def_mba23_7a_2socket     ||def_mba23_7a_1socket_ddr4||def_mba23_7a_2socket_ddr4);
 define def_mba23_mtype_7b = (def_mba23_7b_1socket     ||def_mba23_7b_2socket     ||def_mba23_7b_1socket_ddr4||def_mba23_7b_2socket_ddr4);
 define def_mba23_mtype_7c = (def_mba23_7c_1socket     ||def_mba23_7c_2socket     ||def_mba23_7c_1socket_ddr4||def_mba23_7c_2socket_ddr4);
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.C
index c7407f789..e754d482c 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,8 +20,9 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_bulk_pwr_throttles.C,v 1.10 2012/11/13 16:45:28 bellows Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_bulk_pwr_throttles.C,v $
+// $Id: mss_bulk_pwr_throttles.C,v 1.11 2012/12/12 20:10:41 pardeik Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
+//          centaur/working/procedures/ipl/fapi/mss_bulk_pwr_throttles.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -36,20 +37,28 @@
 // applicable CQ component memory_screen
 //
 // DESCRIPTION:
-// The purpose of this procedure is to set the throttle attributes based on a power limit for the dimms on the channel pair
-// At the end, output attributes will be updated with throttle values that will have dimms at or below the limit
+// The purpose of this procedure is to set the throttle attributes based on a
+// power limit for the dimms on the channel pair
+// At the end, output attributes will be updated with throttle values that will
+// have dimms at or below the limit
 // NOTE:  ISDIMMs and CDIMMs are handled differently
 //   ISDIMMs use a power per DIMM for the thermal power limit from the MRW
-//   CDIMM will use power per CDIMM (power for all virtual dimms) for the thermal power limit from the MRW
-// Plan is to have ISDIMM use the per-slot throttles (thermal throttles) or per-mba throttles (power throttles), and CDIMM to use the per-chip throttles
-// Note that throttle_n_per_mba takes on different meanings depending on how cfg_nm_per_slot_enabled is set
+//   CDIMM will use power per CDIMM (power for all virtual dimms) for the
+//    thermal power limit from the MRW
+// Plan is to have ISDIMM use the per-slot throttles (thermal throttles) or
+//  per-mba throttles (power throttles), and CDIMM to use the per-chip throttles
+// Note that throttle_n_per_mba takes on different meanings depending on how
+// cfg_nm_per_slot_enabled is set
 //   Can be slot0/slot1 OR slot0/MBA throttling
-// Note that  throttle_n_per_chip takes on different meaning depending on how cfg_count_other_mba_dis is set
+// Note that throttle_n_per_chip takes on different meaning depending on how
+// cfg_count_other_mba_dis is set
 //  Can be per-chip OR per-mba throttling
-// ISDIMM:  These registers need to be setup to these values, will be able to do per slot or per MBA throttling
+// ISDIMM:  These registers need to be setup to these values, will be able to
+//  do per slot or per MBA throttling
 //   cfg_nm_per_slot_enabled = 1
 //   cfg_count_other_mba_dis = 1
-// CDIMM:  These registers need to be setup to these values, will be able to do per slot or per chip throttling
+// CDIMM:  These registers need to be setup to these values, will be able to
+//  do per slot or per chip throttling
 //   cfg_nm_per_slot_enabled = 1
 //   cfg_count_other_mba_dis = 0
 //
@@ -61,17 +70,36 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
-//   1.10   | pardeik  |08-NOV-12| attribute name update for runtime per chip throttles
-//   1.9   | pardeik  |25-OCT-12| updated FAPI_ERR sections, use per_chip variables (in if statements) in the throttle update section when channel pair power is greater than the limit, added CQ component comment line
-//   1.8   | pardeik  |19-OCT-12| Changed throttle_n_per_chip to be based on num_mba_with_dimms
-//         | pardeik  |19-OCT-12| Updated default throttle values to represent cmd bus utilization instead of dram bus utilization
-//         | pardeik  |19-OCT-12| multiple throttle N values by 4 to get dram utilization
-//   1.7   | pardeik  |10-OCT-12| Changed throttle attributes and call new function (mss_throttle_to_power) to calculate the power
+//   1.11  | pardeik  |04-DEC-12| update lines to have a max width of 80 chars
+//         |          |         | added FAPI_ERR before return code lines
+//         |          |         | made trace statements for procedure FAPI_IMP
+//         |          |         | updates for FAPI_SET_HWP_ERROR
+//   1.10  | pardeik  |08-NOV-12| attribute name update for runtime per chip
+//         |          |         | throttles
+//   1.9   | pardeik  |25-OCT-12| updated FAPI_ERR sections, use per_chip
+//         |          |         | variables (in if statements) in the throttle
+//         |          |         | update section when channel pair power is
+//         |          |         | greater than the limit, added CQ component
+//         |          |         | comment line
+//   1.8   | pardeik  |19-OCT-12| Changed throttle_n_per_chip to be based on
+//         |          |         | num_mba_with_dimms
+//         | pardeik  |19-OCT-12| Updated default throttle values to represent
+//         |          |         | cmd bus utilization instead of dram bus
+//         |          |         | utilization
+//         | pardeik  |19-OCT-12| multiple throttle N values by 4 to get dram
+//         |          |         | utilization
+//   1.7   | pardeik  |10-OCT-12| Changed throttle attributes and call new
+//         |          |         | function (mss_throttle_to_power) to calculate
+//         |          |         | the power
 //   1.6   | pardeik  |10-APR-12| power calculation fixes and updates
-//   1.5   | pardeik  |04-APR-12| moved cdimm power calculation to end of section instead of having it in multiple places
-//   1.4   | pardeik  |04-APR-12| do channel throttle denominator check as zero only if there are ranks present
-//         | pardeik  |04-APR-12| use else if instead of if after checking throttle denominator to zero
-//   1.3   | pardeik  |03-APR-12| added cdimm power calculation for half of cdimm, changed i_target from mbs to mba
+//   1.5   | pardeik  |04-APR-12| moved cdimm power calculation to end of
+//         |          |         |section instead of having it in multiple places
+//   1.4   | pardeik  |04-APR-12| do channel throttle denominator check as zero
+//         |          |         |only if there are ranks present
+//         | pardeik  |04-APR-12| use else if instead of if after checking
+//         |          |         | throttle denominator to zero
+//   1.3   | pardeik  |03-APR-12| added cdimm power calculation for half of
+//         |          |         |cdimm, changed i_target from mbs to mba
 //   1.2   | pardeik  |03-APR-12| call mss_eff_config_thermal directly
 //   1.1   | pardeik  |28-MAR-12| Updated to use Attributes
 //         | pardeik  |11-NOV-11| First Draft.
@@ -101,9 +129,10 @@ extern "C" {
 
 
 //------------------------------------------------------------------------------
-// @brief mss_bulk_pwr_throttles(): This function determines the throttle values from a MBA channel pair power limit
+// @brief mss_bulk_pwr_throttles(): This function determines the throttle values
+// from a MBA channel pair power limit
 //
-// @param    const fapi::Target & i_target_mba:  MBA Target passed in
+// @param[in]	const fapi::Target & i_target_mba:  MBA Target passed in
 //
 // @return fapi::ReturnCode
 //------------------------------------------------------------------------------
@@ -114,7 +143,7 @@ extern "C" {
 
 	char procedure_name[32];
 	sprintf(procedure_name, "mss_bulk_pwr_throttles");
-	FAPI_INF("*** Running %s ***", procedure_name);
+	FAPI_IMP("*** Running %s ***", procedure_name);
 
 	enum
 	{
@@ -125,14 +154,22 @@ extern "C" {
 	};
 
 // other variables used in this procedure
-	const uint8_t MAX_NUM_PORTS = 2;			// number of ports per MBA
-	const uint8_t MAX_NUM_DIMMS = 2;			// number of dimms per MBA port
-	const float MIN_UTIL = 1;				// Minimum percent data bus utilization (percent of max) allowed (for floor)
-// If this is changed, also change mss_throttle_to_power MAX_UTIL
-	const float MAX_UTIL = 75;				// Maximum theoretical data bus utilization (percent of max) (for ceiling)
-	const uint32_t MEM_THROTTLE_D_DEFAULT = 512;		// default throttle denominator (unthrottled) for cfg_nm_m
-	const uint32_t MEM_THROTTLE_N_DEFAULT_PER_MBA = (int)(MEM_THROTTLE_D_DEFAULT * (MAX_UTIL / 100) / 4);		// default throttle numerator (unthrottled) for cfg_nm_n_per_mba
-	const uint32_t MEM_THROTTLE_N_DEFAULT_PER_CHIP = (int)(MEM_THROTTLE_D_DEFAULT * (MAX_UTIL / 100) / 4);	// default throttle numerator (unthrottled) for cfg_nm_n_per_chip
+	const uint8_t MAX_NUM_PORTS = 2;
+	const uint8_t MAX_NUM_DIMMS = 2;
+// min utilization (percent of max) allowed for floor
+	const float MIN_UTIL = 1;
+// max utilization (percent of max) allowed for ceiling
+// If MAX_UTIL is changed, also change mss_throttle_to_power MAX_UTIL
+	const float MAX_UTIL = 75;
+// cfg_nm_m default
+	const uint32_t MEM_THROTTLE_D_DEFAULT = 512;
+// cfg_nm_n_per_mba default
+	const uint32_t MEM_THROTTLE_N_DEFAULT_PER_MBA =
+	  (int)(MEM_THROTTLE_D_DEFAULT * (MAX_UTIL / 100) / 4);
+//cfg_nm_n_per_chip default
+	const uint32_t MEM_THROTTLE_N_DEFAULT_PER_CHIP =
+	  (int)(MEM_THROTTLE_D_DEFAULT * (MAX_UTIL / 100) / 4);
+
 	fapi::Target target_chip;
 	std::vector<fapi::Target> target_mba_array;
 	std::vector<fapi::Target> target_dimm_array;
@@ -153,33 +190,70 @@ extern "C" {
 
 // Get input attributes
 	rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, dimm_type);
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_MSS_MEM_WATT_TARGET, &i_target_mba, channel_pair_watt_target);
-	if(rc) return rc;
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_DIMM_TYPE");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_MSS_MEM_WATT_TARGET,
+			   &i_target_mba, channel_pair_watt_target);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_MSS_MEM_WATT_TARGET");
+	    return rc;
+	}
 	rc = FAPI_ATTR_GET(ATTR_MSS_POWER_INT, &i_target_mba, power_int_array);
-	if(rc) return rc;
-// runtime throttles will be the thermal throttle values (or zero if not initialized yet)
-	rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA, &i_target_mba, throttle_n_per_mba);
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP, &i_target_mba, throttle_n_per_chip);
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR, &i_target_mba, throttle_d);
-	if(rc) return rc;
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_MSS_POWER_INT");
+	    return rc;
+	}
+// runtime throttles will be the thermal throttle values (or zero if not
+// initialized yet)
+	rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA,
+			   &i_target_mba, throttle_n_per_mba);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP,
+			   &i_target_mba, throttle_n_per_chip);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR,
+			   &i_target_mba, throttle_d);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR");
+	    return rc;
+	}
 
 // get number of mba's with dimms for a CDIMM
 	if (dimm_type == CDIMM)
 	{
 // Get Centaur target for the given MBA
 	    rc = fapiGetParentChip(i_target_mba, target_chip);
-	    if(rc) return rc;
+	    if (rc) {
+		FAPI_ERR("Error calling fapiGetParentChip");
+		return rc;
+	    }
 // Get MBA targets from the parent chip centaur
-	    rc = fapiGetChildChiplets(target_chip, fapi::TARGET_TYPE_MBA_CHIPLET, target_mba_array, fapi::TARGET_STATE_PRESENT);
-	    if(rc) return rc;
+	    rc = fapiGetChildChiplets(target_chip,
+				      fapi::TARGET_TYPE_MBA_CHIPLET,
+				      target_mba_array,
+				      fapi::TARGET_STATE_PRESENT);
+	    if (rc) {
+		FAPI_ERR("Error calling fapiGetChildChiplets");
+		return rc;
+	    }
 	    num_mba_with_dimms = 0;
 	    for (mba_index=0; mba_index < target_mba_array.size(); mba_index++)
 	    {
-		rc = fapiGetAssociatedDimms(target_mba_array[mba_index], target_dimm_array, fapi::TARGET_STATE_PRESENT);
-		if(rc) return rc;
+		rc = fapiGetAssociatedDimms(target_mba_array[mba_index],
+					    target_dimm_array,
+					    fapi::TARGET_STATE_PRESENT);
+		if (rc) {
+		    FAPI_ERR("Error calling fapiGetAssociatedDimms");
+		    return rc;
+		}
 		if (target_dimm_array.size() > 0)
 		{
 		    num_mba_with_dimms++;
@@ -189,56 +263,77 @@ extern "C" {
 	}
 	else
 	{
-	    // ISDIMMs, set to a value of one since they are handled on a per MBA basis
+// ISDIMMs, set to a value of one since they are handled on a per MBA basis
 	    num_mba_with_dimms = 1;
 	}
 
-///////////////////////////////
+//------------------------------------------------------------------------------
 // THROTTLE SECTION
-///////////////////////////////
+//------------------------------------------------------------------------------
 
-// Determine if the channel pair power for this MBA is over the limit when the runtime memory throttle settings are used
-// If not over the limit, then use the runtime throttle settings (defined in mss_eff_config_thermal)
+// Determine if the channel pair power for this MBA is over the limit when the
+// runtime memory throttle settings are used
+// If not over the limit, then use the runtime throttle settings (defined in
+// mss_eff_config_thermal)
 // If over limit, then increase throttle value until it is at or below limit
 // If unable to get power below limit, then call out an error
 
-// Determine whether to base throttles on thermal or power reasons (power throttles can give you better performance than thermal throttles)
-	if ((throttle_n_per_mba == 0) && (throttle_n_per_chip == 0) && (throttle_d == 0))
+// Determine whether to base throttles on thermal or power reasons (power
+// throttles can give you better performance than thermal throttles)
+	if (
+	    (throttle_n_per_mba == 0) &&
+	    (throttle_n_per_chip == 0) &&
+	    (throttle_d == 0)
+	    )
 	{
-    // runtime throttles are all zero here, they have not been defined yet and need to be
+// runtime throttles are all zero here, they have not been defined yet and need
+// to be
 	    thermal_throttle_active = true;
-    // Set runtime throttles to default values as a starting value
+// Set runtime throttles to default values as a starting value
 	    throttle_n_per_mba = MEM_THROTTLE_N_DEFAULT_PER_MBA;
-	    throttle_n_per_chip = MEM_THROTTLE_N_DEFAULT_PER_CHIP * num_mba_with_dimms;
+	    throttle_n_per_chip = MEM_THROTTLE_N_DEFAULT_PER_CHIP *
+	      num_mba_with_dimms;
 	    throttle_d = MEM_THROTTLE_D_DEFAULT;
 	}
-	else if ((throttle_n_per_mba != MEM_THROTTLE_N_DEFAULT_PER_MBA) || (throttle_n_per_chip != (MEM_THROTTLE_N_DEFAULT_PER_CHIP * num_mba_with_dimms)) || (throttle_d != MEM_THROTTLE_D_DEFAULT))
+	else if (
+		 (throttle_n_per_mba != MEM_THROTTLE_N_DEFAULT_PER_MBA) ||
+		 (throttle_n_per_chip !=
+		  (MEM_THROTTLE_N_DEFAULT_PER_CHIP * num_mba_with_dimms)) ||
+		 (throttle_d != MEM_THROTTLE_D_DEFAULT)
+		 )
 	{
-    // if runtime throttles are not equal to the default values, then thermal throttles are in place
+// if runtime throttles are not equal to the default values, then thermal
+// throttles are in place
 	    thermal_throttle_active = true;
 	}
 	else
 	{
-    // runtime throttles are not all zero and equal to the defaults, so no thermal throttles are in place - so now any throttles will be power based
+// runtime throttles are not all zero and equal to the defaults, so no thermal
+// throttles are in place - so now any throttles will be power based
 	    thermal_throttle_active = false;
 	}
-
 // Adjust power limit value as needed here
-// For CDIMM, we want the throttles to be per-chip, and to allow all commands to go to one MBA to get to the power limit
+// For CDIMM, we want the throttles to be per-chip, and to allow all commands to
+// go to one MBA to get to the power limit
 	if (dimm_type == CDIMM)
 	{
-// Set channel pair power limit to whole CDIMM power limit (multiply by number of MBAs used) and subtract off idle power for dimms on other MBA
-	    channel_pair_watt_target = channel_pair_watt_target * num_mba_with_dimms;
+// Set channel pair power limit to whole CDIMM power limit (multiply by number
+// of MBAs used) and subtract off idle power for dimms on other MBA
+	    channel_pair_watt_target = channel_pair_watt_target *
+	      num_mba_with_dimms;
 	    for (port=0; port < MAX_NUM_PORTS; port++)
 	    {
 		for (dimm=0; dimm < MAX_NUM_DIMMS; dimm++)
 		{
-		    channel_pair_watt_target = channel_pair_watt_target - ((num_mba_with_dimms - 1) * (power_int_array[port][dimm]));
+		    channel_pair_watt_target = channel_pair_watt_target -
+		      ((num_mba_with_dimms - 1) *
+		       (power_int_array[port][dimm]));
 		}
 	    }
 	}
 
-// calculate power and change throttle values in this while loop until limit has been satisfied or throttles have reached the minimum limit
+// calculate power and change throttle values in this while loop until limit has
+// been satisfied or throttles have reached the minimum limit
 	not_enough_available_power = false;
 	channel_pair_throttle_done = false;
 	while (channel_pair_throttle_done == false)
@@ -250,44 +345,92 @@ extern "C" {
 					    throttle_d,
 					    channel_pair_power
 					    );
-	    if(rc)
+	    if (rc)
 	    {
 		FAPI_ERR("Error (0x%x) calling mss_throttle_to_power_calc", static_cast<uint32_t>(rc));
 		return rc;
 	    }
 
-// compare channel pair power to mss_watt_target for channel and decrease throttles if it is above this limit
-// throttle decrease will decrement throttle numerator by one (or increase throttle denominator) and recalculate power until utilization (N/M) reaches a lower limit
+// compare channel pair power to mss_watt_target for channel and decrease
+// throttles if it is above this limit
+// throttle decrease will decrement throttle numerator by one (or increase
+// throttle denominator) and recalculate power until utilization (N/M) reaches a
+// lower limit
 
 	    if (channel_pair_power > channel_pair_watt_target)
 	    {
-// check to see if dimm utilization is greater than the min utilization limit, continue if it is, error if it is not
-		if ((((((float)throttle_n_per_chip * 100 * 4) / throttle_d) > MIN_UTIL) && (dimm_type != CDIMM) && (thermal_throttle_active == false)) || (((((float)throttle_n_per_chip * 100 * 4) / throttle_d) > MIN_UTIL) && (dimm_type != CDIMM) && (thermal_throttle_active == true)) || (((((float)throttle_n_per_chip * 100 * 4) / throttle_d) > MIN_UTIL) && (dimm_type == CDIMM)))
+// check to see if dimm utilization is greater than the min utilization limit,
+// continue if it is, error if it is not
+		if (
+		    (
+		     ((((float)throttle_n_per_chip * 100 * 4) / throttle_d) >
+		      MIN_UTIL) &&
+		     (dimm_type != CDIMM) &&
+		     (thermal_throttle_active == false)
+		     )
+		    ||
+		    (
+		     ((((float)throttle_n_per_chip * 100 * 4) / throttle_d) >
+		      MIN_UTIL) &&
+		     (dimm_type != CDIMM) &&
+		     (thermal_throttle_active == true)
+		     )
+		    ||
+		    (
+		     ((((float)throttle_n_per_chip * 100 * 4) / throttle_d) >
+		      MIN_UTIL) &&
+		     (dimm_type == CDIMM)
+		     )
+		    )
 		{
-		    if (((throttle_n_per_chip > 1) && (dimm_type != CDIMM) && (thermal_throttle_active == false)) || ((throttle_n_per_chip > 1) && (dimm_type != CDIMM) && (thermal_throttle_active == true)) || ((throttle_n_per_chip > 1) && (dimm_type == CDIMM)))
+		    if (
+			(
+			 (throttle_n_per_chip > 1) &&
+			 (dimm_type != CDIMM) &&
+			 (thermal_throttle_active == false)
+			 )
+			||
+			(
+			 (throttle_n_per_chip > 1) &&
+			 (dimm_type != CDIMM) &&
+			 (thermal_throttle_active == true)
+			 )
+			||
+			(
+			 (throttle_n_per_chip > 1) &&
+			 (dimm_type == CDIMM)
+			 )
+			)
 		    {
 			if (dimm_type == CDIMM)
 			{
-			    // CDIMMs, use per chip throttling for any thermal or available power limits
+// CDIMMs, use per chip throttling for any thermal or available power limits
 			    throttle_n_per_chip--;
 			}
 			else
 			{
-			    // ISDIMMs, use per slot throttling for thermal power limits
+// ISDIMMs, use per slot throttling for thermal power limits
 			    if (thermal_throttle_active == true)
 			    {
-// per_mba throttling (ie.  per dimm for ISDIMMs) will limit performance if all traffic is sent to one dimm, so use the per_chip
-// This works as long as the other dimm is providing termination (for 2 dimms per channel)
-//    If the other dimm is not providing termination, then we would want to redefine the power curve in mss_eff_config_thermal and use the per_mba throttle here
-// It there is only one dimm on channel, then it will provide its own termination and the per_mba and per_chip will effectively do the same throttling (ie.  doesn't matter which one we do in this case)
-// Warning:  If this changes, then the two if statements above need to be modified
-//				throttle_n_per_mba--;
+// per_mba throttling (ie.  per dimm for ISDIMMs) will limit performance if all
+// traffic is sent to one dimm, so use the per_chip
+// This works as long as the other dimm is providing termination (for 2 dimms
+// per channel)
+//    If the other dimm is not providing termination, then we would want to
+//    redefine the power curve in mss_eff_config_thermal and use the per_mba
+//    throttle here
+// It there is only one dimm on channel, then it will provide its own
+// termination and the per_mba and per_chip will effectively do the same
+// throttling (ie.  doesn't matter which one we do in this case)
+// Warning:  If this changes, then the two if statements above need to be
+// modified
 				throttle_n_per_chip--;
 			    }
 			    else
 			    {
-				// ISDIMMs, use per mba throttling for available power limit
-// Warning:  If this changes, then the two if statements above need to be modified
+// ISDIMMs, use per mba throttling for available power limit
+// Warning:  If this changes, then the two if statements above need to be
+// modified
 				throttle_n_per_chip--;
 			    }
 			}
@@ -317,27 +460,47 @@ extern "C" {
 
 	FAPI_DBG("Final Throttle Settings [N_per_mba/N_per_chip/M %d/%d/%d]", throttle_n_per_mba, throttle_n_per_chip, throttle_d);
 
-
+//------------------------------------------------------------------------------
 // update output attributes
-	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA, &i_target_mba, throttle_n_per_mba);
-	if(rc) return rc;
-	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP, &i_target_mba, throttle_n_per_chip);
-	if(rc) return rc;
-	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_DENOMINATOR, &i_target_mba, throttle_d);
-	if(rc) return rc;
+	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA,
+			   &i_target_mba, throttle_n_per_mba);
+	if (rc) {
+	    FAPI_ERR("Error writing attribute ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA");
+	    return rc;
+	}
+	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP,
+			   &i_target_mba, throttle_n_per_chip);
+	if (rc) {
+	    FAPI_ERR("Error writing attribute ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP");
+	    return rc;
+	}
+	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_DENOMINATOR,
+			   &i_target_mba, throttle_d);
+	if (rc) {
+	    FAPI_ERR("Error writing attribute ATTR_MSS_MEM_THROTTLE_DENOMINATOR");
+	    return rc;
+	}
 
 	if (not_enough_available_power == true)
 	{
 	    FAPI_ERR("Not enough available memory power [Channel Pair Power %4.2f/%d cW]", channel_pair_power, channel_pair_watt_target);
+// Log an error against firmware (power subsystem does not have enough power
+// for all the hardware, or power allocation values in firmware are off).  Do
+// not deconfigure or gard.
+	    const fapi::Target & MEM_CHIP = i_target_mba;
+	    uint32_t FFDC_DATA_1 = (int)channel_pair_power;
+	    uint32_t FFDC_DATA_2 = channel_pair_watt_target;
+	    uint32_t FFDC_DATA_3 = throttle_n_per_mba;
+	    uint32_t FFDC_DATA_4 = throttle_n_per_chip;
+	    uint32_t FFDC_DATA_5 = throttle_d;
 	    FAPI_SET_HWP_ERROR(rc, RC_MSS_NOT_ENOUGH_AVAILABLE_DIMM_POWER);
 	    if (rc) fapiLogError(rc);
 	}
-	FAPI_INF("*** %s COMPLETE ***", procedure_name);
-	return rc;
 
+	FAPI_IMP("*** %s COMPLETE ***", procedure_name);
+	return rc;
     }
 
-
 } //end extern C
 
 
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.H
index 2b86242c8..a97daff05 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.H
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,8 +20,9 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_bulk_pwr_throttles.H,v 1.3 2012/10/15 13:05:17 pardeik Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_bulk_pwr_throttles.H,v $
+// $Id: mss_bulk_pwr_throttles.H,v 1.4 2012/12/12 20:10:44 pardeik Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
+//          centaur/working/procedures/ipl/fapi/mss_bulk_pwr_throttles.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -42,31 +43,36 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//   1.4   | pardeik  |04-DEC-12| update lines to have a max width of 80 chars
+//         |          |         | removed variable names in typedef
 //   1.3   | pardeik  |11-OCT-12| change i_target to i_target_mba
 //   1.2   | pardeik  |03-APR-12| use mba target intead of mbs
 //   1.1   | pardeik  |11-NOV-11| First Draft.
 
 
-
 #ifndef MSS_BULK_PWR_THROTTLES_H_
 #define MSS_BULK_PWR_THROTTLES_H_
 
-//----------------------------------------------------------------------
+//------------------------------------------------------------------------------
 //  Includes
-//----------------------------------------------------------------------
+//------------------------------------------------------------------------------
 #include <fapi.H>
 
-typedef fapi::ReturnCode (*mss_bulk_pwr_throttles_FP_t)(const fapi::Target & i_target_mba);
+typedef fapi::ReturnCode (*mss_bulk_pwr_throttles_FP_t)
+(
+ const fapi::Target &
+ );
 
 extern "C"
 {
-/**
- * @brief mss_bulk_pwr_throttles procedure. Set dimm and channel throttle attributes based on available centaur mba port power
- *
- * @param[in]  i_target_mba  Reference to centaur mba target
- *
- * @return ReturnCode
- */
+//------------------------------------------------------------------------------
+// @brief mss_bulk_pwr_throttles procedure. Set dimm and channel
+// throttle attributes based on available centaur mba port power
+//
+// @param[in]  i_target_mba  Reference to centaur mba target
+//
+// @return ReturnCode
+//------------------------------------------------------------------------------
 
     fapi::ReturnCode mss_bulk_pwr_throttles(const fapi::Target & i_target_mba);
 
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C
index 946da5294..616c9388b 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_termination.C,v 1.8 2012/12/06 13:45:57 bellows Exp $
+// $Id: mss_eff_config_termination.C,v 1.11 2012/12/23 02:29:44 asaetow Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_termination.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -42,7 +42,13 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
-//   1.9   |          |         |
+//   1.12  |          |         |
+//   1.11  | asaetow  |22-DEC-12| Added CDIMM workaround for EC10 ADR Centerlane race condition, subtract 32ticks.
+//         |          |         | NOTE: Need EC check for Centaur EC10 ADR Centerlane NWELL workaround.
+//   1.10  | asaetow  |22-DEC-12| Added Centaur EC10 ADR Centerlane PR=0x7F workaround for NWELL LVS issue.
+//         |          |         | NOTE: Need EC check for Centaur EC10 ADR Centerlane NWELL workaround.
+//         |          |         | Fixed (l_attr_is_simulation || 1) to (l_attr_is_simulation != 0) from v1.8 and v1.9.
+//   1.9   | bellows  |12-DEC-12| Changed phase rotators for sim to 0x40 for clocks
 //   1.8   | bellows  |06-DEC-12| Added sim leg for rotator values
 //   1.7   | asaetow  |18-NOV-12| Changed ATTR_MSS_CAL_STEP_ENABLE from 0x7F back to 0xFF. 
 //   1.6   | asaetow  |17-NOV-12| Fixed ATTR_EFF_ODT_WR for 4R RDIMMs.
@@ -892,6 +898,35 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) {
    for( int l_port = 0; l_port < PORT_SIZE; l_port += 1 ) {
       for( int l_pr_type_index = 0; l_pr_type_index < PR_TYPE_SIZE; l_pr_type_index += 1 ) {
          l_attr_eff_cen_phase_rot[l_pr_type_index][l_port] = PR_VALUE_U8ARRAY[l_port][l_pr_type_index][l_topo_index];
+         // AST HERE: Need EC check here for Centaur EC10 ADR Centerlane NWELL LVS issue PR=0x7F workaround.
+         if ((((l_target_mba_pos == 0) && (l_port == 0) && (l_pr_type_index == 16)) ||   // MA_CMD_A<12>
+              ((l_target_mba_pos == 0) && (l_port == 0) && (l_pr_type_index ==  4)) ||   // MA_CMS_A<0>
+              ((l_target_mba_pos == 0) && (l_port == 0) && (l_pr_type_index == 17)) ||   // MA_CMD_A<13>
+              ((l_target_mba_pos == 0) && (l_port == 0) && (l_pr_type_index == 20)) ||   // MA_CMD_BA<0>
+              ((l_target_mba_pos == 0) && (l_port == 1) && (l_pr_type_index == 34)) ||   // MB0_CNTL_CSN<2>
+              ((l_target_mba_pos == 0) && (l_port == 1) && (l_pr_type_index == 36)) ||   // MB0_CNTL_ODT<0>
+              ((l_target_mba_pos == 0) && (l_port == 1) && (l_pr_type_index == 15)) ||   // MB_CMD_A<11>
+              ((l_target_mba_pos == 0) && (l_port == 1) && (l_pr_type_index == 28)) ||   // MB0_CNTL_CKE<0>
+              ((l_target_mba_pos == 1) && (l_port == 0) && (l_pr_type_index ==  5)) ||   // MC_CMD_A<1>
+              ((l_target_mba_pos == 1) && (l_port == 0) && (l_pr_type_index == 10)) ||   // MC_CMD_A<6>
+              ((l_target_mba_pos == 1) && (l_port == 0) && (l_pr_type_index == 26)) ||   // MC_CMD_PAR
+              ((l_target_mba_pos == 1) && (l_port == 0) && (l_pr_type_index == 47)) ||   // MC1_CNTL_ODT<1>
+              ((l_target_mba_pos == 1) && (l_port == 1) && (l_pr_type_index == 32)) ||   // MD0_CNTL_CSN<0>
+              ((l_target_mba_pos == 1) && (l_port == 1) && (l_pr_type_index == 14)) ||   // MD_CMD_A<10>
+              ((l_target_mba_pos == 1) && (l_port == 1) && (l_pr_type_index == 44)) ||   // MD1_CNTL_CSN<2>
+              ((l_target_mba_pos == 1) && (l_port == 1) && (l_pr_type_index == 36))) &&  // MD0_CNTL_ODT<0>
+            (l_attr_is_simulation == 0)) {
+            FAPI_INF("WARNING: Centaur EC10 ADR Centerlane PR=0x7F workaround for NWELL LVS issue on CmdLaneIndex %d Port %d %s!", l_pr_type_index, l_port, i_target_mba.toEcmdString());
+            l_attr_eff_cen_phase_rot[l_pr_type_index][l_port] = 0x7F;
+         } else {
+            if (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM) {
+               if ((l_attr_eff_cen_phase_rot[l_pr_type_index][l_port] - 32) >= 0) {
+                  l_attr_eff_cen_phase_rot[l_pr_type_index][l_port] = l_attr_eff_cen_phase_rot[l_pr_type_index][l_port] - 32;
+               } else {
+                  l_attr_eff_cen_phase_rot[l_pr_type_index][l_port] = 0;
+               }
+            }
+         }
       }
    }
 
@@ -920,14 +955,14 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) {
    rc = FAPI_ATTR_SET(ATTR_EFF_ODT_RD, &i_target_mba, l_attr_eff_odt_rd); if(rc) return rc;
    rc = FAPI_ATTR_SET(ATTR_EFF_ODT_WR, &i_target_mba, l_attr_eff_odt_wr); if(rc) return rc;
 
-   if(l_attr_is_simulation || 1) {
+   if(l_attr_is_simulation != 0) {
      FAPI_INF("In Sim Detected %s on %s value is %d", PROCEDURE_NAME, i_target_mba.toEcmdString(), l_attr_is_simulation);
 
      for(int i=0;i<2;i++) {
-       l_attr_eff_cen_phase_rot[0][i]=0;
-       l_attr_eff_cen_phase_rot[1][i]=0;
-       l_attr_eff_cen_phase_rot[2][i]=0;
-       l_attr_eff_cen_phase_rot[3][i]=0;
+       l_attr_eff_cen_phase_rot[0][i]=0x40;
+       l_attr_eff_cen_phase_rot[1][i]=0x40;
+       l_attr_eff_cen_phase_rot[2][i]=0x40;
+       l_attr_eff_cen_phase_rot[3][i]=0x40;
        l_attr_eff_cen_phase_rot[4][i]=0;
        l_attr_eff_cen_phase_rot[5][i]=0;
        l_attr_eff_cen_phase_rot[6][i]=0;
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C
index 30a69e334..fe3123344 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,8 +20,9 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_thermal.C,v 1.13 2012/11/28 21:33:11 pardeik Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_thermal.C,v $
+// $Id: mss_eff_config_thermal.C,v 1.14 2012/12/12 20:10:33 pardeik Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
+//          centaur/working/procedures/ipl/fapi/mss_eff_config_thermal.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -36,11 +37,12 @@
 // applicable CQ component memory_screen
 //
 // DESCRIPTION:
-// The purpose of this procedure is to set the default throttle and power attributes for dimms in a given system
-// -- The power attributes are the slope/intercept values.  Note that these values are in cW.
-// -- The power values are determined by DRAM Generation and Width (with various uplifts/adders applied)
-//	-- Power will be per rank for a given dram generation and width
-//	-- Uplifts will be applied for dimm type, number of ranks
+// The purpose of this procedure is to set the default throttle and power
+// attributes for dimms in a given system
+// -- The power attributes are the slope/intercept values.  Note that these
+//    values are in cW.
+//    -- ISDIMM will calculate values based on various attributes
+//    -- CDIMM will get values from VPD
 // -- The throttle attributes will setup values for safemode and runtime
 //
 //
@@ -51,19 +53,42 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//   1.14  | pardeik  |03-DEC-12| update lines to have a max width of 80 chars
+//         |          |         | added FAPI_ERR before return code lines
+//         |          |         | made trace statements for procedures FAPI_IMP
+//         |          |         | changed some FAPI_INF to FAPI_DBG
+//         |          |         | set per_chip safemode throttles to 32
+//         |          |         | updates for FAPI_SET_HWP_ERROR
 //   1.13  | pardeik  |28-NOV-12| fixed hostboot compile errors
-//   1.12  | pardeik  |07-NOV-12| updated to use new SI attributes and their enums
-//   1.11  | pardeik  |22-OCT-12| Use the schmoo attributes to find wc termination, updated hwp errors, removed unneeded variables, added CQ component comment line, updated safemode throttle default values
-//   1.10  | pardeik  |19-OCT-12| Enable TYPE_1D for ODT mapping.  Set ISDIMM supplier power curve to master power curve
-//   1.9   | pardeik  |11-OCT-12| updated to use new attributes, termination power calculation added in
-//   1.8   | pardeik  |13-JUN-12| Major rewrite to have dimm power determined by dram generation and width, with uplifts applied (not based on dimm size lookup table any longer)
-//   1.7   | pardeik  |04-MAY-12| removed typedef from structures, use fapi to define dimm type enums
-//   1.6   | pardeik  |10-APR-12| update cdimm power/int default, change power_thermal_values_t to use int32_t instead of uint32_t in order to identify a negative value correctly, added dimm config to the messages printed out
-//   1.5   | pardeik  |03-APR-12| fix cdimm size/rank addition to cycle through both mba's
-//   1.4   | pardeik  |26-MAR-12| Rewrite to iterate through the MBA's using fapi functions
+//   1.12  | pardeik  |07-NOV-12| updated to use new SI attributes and their
+//         |          |         | enums
+//   1.11  | pardeik  |22-OCT-12| Use the schmoo attributes to find wc
+//         |          |         | termination, updated hwp errors, removed
+//         |          |         | unneeded variables, added CQ component comment
+//         |          |         | line, updated safemode throttle default values
+//   1.10  | pardeik  |19-OCT-12| Enable TYPE_1D for ODT mapping.  Set ISDIMM
+//         |          |         | supplier power curve to master power curve
+//   1.9   | pardeik  |11-OCT-12| updated to use new attributes, termination
+//         |          |         | power calculation added in
+//   1.8   | pardeik  |13-JUN-12| Major rewrite to have dimm power determined by
+//         |          |         | dram generation and width, with uplifts
+//         |          |         | applied (not based on dimm size lookup table
+//         |          |         | any longer)
+//   1.7   | pardeik  |04-MAY-12| removed typedef from structures, use fapi to
+//         |          |         | define dimm type enums
+//   1.6   | pardeik  |10-APR-12| update cdimm power/int default, change
+//         |          |         | power_thermal_values_t to use int32_t instead
+//         |          |         | of uint32_t in order to identify a negative
+//         |          |         | value correctly, added dimm config to the
+//         |          |         | messages printed out
+//   1.5   | pardeik  |03-APR-12| fix cdimm size/rank addition to cycle through
+//         |          |         | both mba's
+//   1.4   | pardeik  |26-MAR-12| Rewrite to iterate through the MBA's using
+//         |          |         | fapi functions
 //         | pardeik  |01-DEC-11| Updated to align with procedure definition
 //   1.3   | asaetow  |03-NOV-11| Fixed to comply with mss_eff_config_thermal.H
-//   1.2   | asaetow  |03-NOV-11| Changed format of file and made function lower case. 
+//   1.2   | asaetow  |03-NOV-11| Changed format of file and made function lower
+//         |          |         | case. 
 //   1.1   | pardeik  |01-NOV-11| First Draft.
 
 /*
@@ -73,9 +98,10 @@ Waiting for platinit attributes to enable sections in this procedure:
 1.  Power Curves to originate from CDIMM VPD (platinit)
 2.  Thermal memory power limit from MRW (platinit)
 3.  Safemode throttles from MRW (platinit)
-4.  ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO and ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO enable sections of this procedure when they are used
-5.  Need runtime throttles non-volatile and initialized to zero by firmware on the first IPL
-6.  Error callouts
+5.  Need runtime throttles non-volatile and initialized to zero by firmware on
+    the first IPL
+6.  Call out error for CDIMM and lab VPD power curves when it makes sense
+7.  Update power table after hardware measurements are done
 
 */
 
@@ -93,17 +119,19 @@ Waiting for platinit attributes to enable sections in this procedure:
 //------------------------------------------------------------------------------
 //  Constants
 //------------------------------------------------------------------------------
-const uint8_t NUM_PORTS = 2;				// number of ports per MBA
-const uint8_t NUM_DIMMS = 2;				// number of dimms per MBA port
-const uint8_t NUM_RANKS = 4;				// number of ranks per dimm
-const uint32_t ISDIMM_POWER_SLOPE_DEFAULT = 940;		// default power slope (cW/utilization)
-const uint32_t ISDIMM_POWER_INT_DEFAULT = 900;		// default power intercept (cW)
-const uint32_t CDIMM_POWER_SLOPE_DEFAULT = 0x8240;		// default power slope (cW/utilization)
-const uint32_t CDIMM_POWER_INT_DEFAULT = 0x80CE;		// default power intercept (cW)
-const uint8_t IDLE_DIMM_UTILIZATION = 0;		// DRAM data bus utilization percent for the idle power defined in table below - needs to be 0
-const uint8_t ACTIVE_DIMM_UTILIZATION = 70;		// DRAM data bus utilization percent for the active power defined in table below (reads+writes)
-const uint8_t DATA_BUS_READ_PERCENT = 66;		// read percentage of data bus
-const uint8_t DATA_BUS_WRITE_PERCENT = 34;		// write percentage of data bus
+const uint8_t NUM_PORTS = 2;
+const uint8_t NUM_DIMMS = 2;
+const uint8_t NUM_RANKS = 4;
+const uint32_t ISDIMM_POWER_SLOPE_DEFAULT = 940;
+const uint32_t ISDIMM_POWER_INT_DEFAULT = 900;
+const uint32_t CDIMM_POWER_SLOPE_DEFAULT = 0x8240;
+const uint32_t CDIMM_POWER_INT_DEFAULT = 0x80CE;
+// These are based on what was used when ISDIMM power values were taken from the
+// power calculator
+const uint8_t IDLE_DIMM_UTILIZATION = 0;
+const uint8_t ACTIVE_DIMM_UTILIZATION = 70;
+const uint8_t DATA_BUS_READ_PERCENT = 66;
+const uint8_t DATA_BUS_WRITE_PERCENT = 34;
 
 
 extern "C" {
@@ -115,54 +143,57 @@ extern "C" {
 //------------------------------------------------------------------------------
     fapi::ReturnCode mss_eff_config_thermal(const fapi::Target & i_target_mba);
 
-    fapi::ReturnCode mss_eff_config_thermal_term(
-						      const char nom_or_wc_term[4],
-						      uint8_t i_port,
-						      uint8_t i_dimm,
-						      uint8_t i_rank,
-						      uint32_t i_dimm_voltage,
-						      uint8_t i_dram_width,
-						      uint8_t i_dram_tdqs,
-						      uint8_t i_ibm_type[NUM_PORTS][NUM_DIMMS],
-						      uint8_t i_dimm_ranks_configed_array[NUM_PORTS][NUM_DIMMS],
-						      uint8_t i_dimm_dram_ron[NUM_PORTS][NUM_DIMMS],
-						      uint8_t i_dimm_rank_odt_rd[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
-						      uint8_t i_dimm_rank_odt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
-						      uint8_t i_dram_rtt_nom[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
-						      uint8_t i_dram_rtt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
-						      uint8_t i_cen_dq_dqs_rcv_imp[NUM_PORTS],
-						      uint8_t i_cen_dq_dqs_drv_imp[NUM_PORTS],
-						      float &o_dimm_power_adder_termination
-						      );
-
-    fapi::ReturnCode mss_eff_config_thermal_get_wc_term(
-							const fapi::Target &i_target_mba,
-							uint8_t i_port,
-							uint8_t &o_cen_dq_dqs_rcv_imp_wc,
-							uint8_t &o_cen_dq_dqs_drv_imp_wc
-							);
-
-    fapi::ReturnCode mss_eff_config_thermal_get_cen_drv_value(
-							      uint8_t i_cen_dq_dqs_drv_imp,
-							      uint8_t &o_cen_dq_dqs_drv_imp
-							      );
+    fapi::ReturnCode mss_eff_config_thermal_term
+      (
+       const char nom_or_wc_term[4],
+       uint8_t i_port,
+       uint8_t i_dimm,
+       uint8_t i_rank,
+       uint32_t i_dimm_voltage,
+       uint8_t i_dram_width,
+       uint8_t i_dram_tdqs,
+       uint8_t i_ibm_type[NUM_PORTS][NUM_DIMMS],
+       uint8_t i_dimm_ranks_configed_array[NUM_PORTS][NUM_DIMMS],
+       uint8_t i_dimm_dram_ron[NUM_PORTS][NUM_DIMMS],
+       uint8_t i_dimm_rank_odt_rd[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
+       uint8_t i_dimm_rank_odt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
+       uint8_t i_dram_rtt_nom[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
+       uint8_t i_dram_rtt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
+       uint8_t i_cen_dq_dqs_rcv_imp[NUM_PORTS],
+       uint8_t i_cen_dq_dqs_drv_imp[NUM_PORTS],
+       float &o_dimm_power_adder_termination
+       );
+
+    fapi::ReturnCode mss_eff_config_thermal_get_wc_term
+      (
+       const fapi::Target &i_target_mba,
+       uint8_t i_port,
+       uint8_t &o_cen_dq_dqs_rcv_imp_wc,
+       uint8_t &o_cen_dq_dqs_drv_imp_wc
+       );
+
+    fapi::ReturnCode mss_eff_config_thermal_get_cen_drv_value
+      (
+       uint8_t i_cen_dq_dqs_drv_imp,
+       uint8_t &o_cen_dq_dqs_drv_imp
+       );
 
 //------------------------------------------------------------------------------
-// @brief mss_eff_config_thermal(): This function determines the power and throttle attribute values to use
+// @brief mss_eff_config_thermal(): This function determines the power and
+// throttle attribute values to use
 //
-// @param    const fapi::Target & i_target_mba:  MBA Target passed in
+// @param[in]	const fapi::Target & i_target_mba:  MBA Target passed in
 //
 // @return fapi::ReturnCode
 //------------------------------------------------------------------------------
 
     fapi::ReturnCode mss_eff_config_thermal(const fapi::Target & i_target_mba)
     {
-
 	fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
 
 	char procedure_name[32];
 	sprintf(procedure_name, "mss_eff_config_thermal");
-	FAPI_INF("*** Running %s ***", procedure_name);
+	FAPI_IMP("*** Running %s ***", procedure_name);
 
 	enum
 	{
@@ -176,7 +207,8 @@ extern "C" {
 	    X8 = fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8,
 	};
 
-// Structure types for the table that holds dimm power and adjustment values that will be used
+// Structure types for the table that holds dimm power and adjustment values
+// that will be used
 
 	struct dimm_power_t
 	{
@@ -200,29 +232,41 @@ extern "C" {
 	    int32_t		dimm_frequency_base;	    
 	};
 
-// Master Ranks column uses the values in the same table entry for the number of master ranks specified.  Default is to have it use same power for each master rank, so that is why master ranks = 1.  If we need to separate power based on number of master ranks, then have the table setup for descending master rank values.  We always need an entry for master ranks of 1.  Table lookup will stop after first matching entry is found (DRAM Generation, DRAM Width, and Master Ranks = dimm_master_ranks_array OR 1)
+//------------------------------------------------------------------------------
+// Master Ranks column uses the values in the same table entry for the number of
+// master ranks specified.  Default is to have it use same power for each master
+// rank, so that is why master ranks = 1.  If we need to separate power based on
+// number of master ranks, then have the table setup for descending master rank
+// values.  We always need an entry for master ranks of 1.  Table lookup will
+// stop after first matching entry is found (DRAM Generation, DRAM Width, and
+// Master Ranks = dimm_master_ranks_array OR 1)
+//
+// These values need to cover the power of all IBM dimms.  Values will come from
+// the power calculator and be verified by hardware measurements.
 //
-//            DRAM	DRAM	Master	RankPower	DIMMTypeAdder	BaseVoltage	BaseFrequency
-//            GenerationWidth	Ranks	(cW)		(cW)		(mV)		(MHz)
-//            DDR3	X4	1	idle,full	UDIMM,LRDIMM,	1500,1350,1200	1066,1333,1600
-//            or	or				RDIMM		for values in	for values in
-//            DDR4	X8						this table	this table
-//				
+// Base Voltage and Base Frequency values need to match what mss_volt/mss_freq
+// uses.
+//
+//            DRAM  DRAM  Master RankPower  DIMMType    Base    Base
+//            Gen   Width Ranks	 idle,full  Adder       Volt    Freq
+//                               cW         U,LR,RDIMM  mV      MHz
+//------------------------------------------------------------------------------
 	power_data_t power_table[] =
 	{
-	    { DDR3,	X4,	1,	{ 70,373},	{0,93,104},	1350,		1066         },
-	    { DDR3,	X8,	1,	{ 52,300},	{0,93,104},	1350,		1066         },
-	    { DDR4,	X4,	1,	{ 70,373},	{0,93,104},	1350,		1066         },
-	    { DDR4,	X8,	1,	{ 52,300},	{0,93,104},	1350,		1066         },
+	    { DDR3, X4,   1,     { 70,373}, {0,93,104}, 1350,	1066 },
+	    { DDR3, X8,   1,     { 52,300}, {0,93,104}, 1350,	1066 },
+	    { DDR4, X4,   1,     { 70,373}, {0,93,104}, 1350,	1066 },
+	    { DDR4, X8,   1,     { 52,300}, {0,93,104}, 1350,	1066 },
 	};
 
-
 // other variables used in this function
 	fapi::Target target_chip;
 	std::vector<fapi::Target> target_mba_array;
 	std::vector<fapi::Target> target_dimm_array;
 	uint8_t port;
 	uint8_t dimm;
+	uint8_t mba_port;
+	uint8_t mba_dimm;
 	uint8_t rank;
 	uint8_t entry;
 	uint8_t dimm_type;
@@ -283,113 +327,244 @@ extern "C" {
 
 	power_table_size = (sizeof(power_table))/(sizeof(power_data_t));
 
+//------------------------------------------------------------------------------
 // Get input attributes
+//------------------------------------------------------------------------------
 	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target_mba, dram_gen);
-	if(rc) return rc;
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_DRAM_GEN");
+	    return rc;
+	}
 	rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, dimm_type);
-	if(rc) return rc;
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_DIMM_TYPE");
+	    return rc;
+	}
 	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, dram_width);
-	if(rc) return rc;
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_DRAM_WIDTH");
+	    return rc;
+	}
 	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TDQS, &i_target_mba, dram_tdqs);
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, dimm_ranks_array);
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, &i_target_mba, dimm_master_ranks_array);
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RANKS_CONFIGED, &i_target_mba, dimm_ranks_configed_array);
-	if(rc) return rc;
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_DRAM_TDQS");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM,
+			   &i_target_mba, dimm_ranks_array);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_NUM_RANKS_PER_DIMM");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM,
+			   &i_target_mba, dimm_master_ranks_array);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RANKS_CONFIGED,
+			   &i_target_mba, dimm_ranks_configed_array);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_DIMM_RANKS_CONFIGED");
+	    return rc;
+	}
 	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RON, &i_target_mba, dimm_dram_ron);
-	if(rc) return rc;
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_DRAM_RON");
+	    return rc;
+	}
 	rc = FAPI_ATTR_GET(ATTR_EFF_ODT_RD, &i_target_mba, dimm_rank_odt_rd);
-	if(rc) return rc;
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_ODT_RD");
+	    return rc;
+	}
 	rc = FAPI_ATTR_GET(ATTR_EFF_ODT_WR, &i_target_mba, dimm_rank_odt_wr);
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, cen_dq_dqs_rcv_imp);
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, cen_dq_dqs_drv_imp);
-	if(rc) return rc;
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_ODT_WR");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS,
+			   &i_target_mba, cen_dq_dqs_rcv_imp);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_CEN_RCV_IMP_DQ_DQS");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS,
+			   &i_target_mba, cen_dq_dqs_drv_imp);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_CEN_DRV_IMP_DQ_DQS");
+	    return rc;
+	}
 	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RTT_NOM, &i_target_mba, dram_rtt_nom);
-	if(rc) return rc;
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_DRAM_RTT_NOM");
+	    return rc;
+	}
 	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RTT_WR, &i_target_mba, dram_rtt_wr);
-	if(rc) return rc;
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_DRAM_RTT_WR");
+	    return rc;
+	}
 	rc = FAPI_ATTR_GET(ATTR_EFF_IBM_TYPE, &i_target_mba, ibm_type);
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, num_dimms_on_port);
-	if(rc) return rc;
-// TODO:  use vpd values when power curve data is available from CDIMM VPD (platinit), remove hardcoding
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_IBM_TYPE");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT,
+			   &i_target_mba, num_dimms_on_port);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_NUM_DROPS_PER_PORT");
+	    return rc;
+	}
+// TODO:  use vpd values when power curve data is available from CDIMM VPD
+// (platinit), remove hardcoding
 	cdimm_master_power_slope = CDIMM_POWER_SLOPE_DEFAULT;
 	cdimm_master_power_intercept = CDIMM_POWER_INT_DEFAULT;
 	cdimm_supplier_power_slope = CDIMM_POWER_SLOPE_DEFAULT;
 	cdimm_supplier_power_intercept = CDIMM_POWER_INT_DEFAULT;
-//	rc = FAPI_ATTR_GET(ATTR_SPD_CDIMM_MASTER_POWER_SLOPE, &i_target_mba, cdimm_master_power_slope);
-//	if(rc) return rc;
-//	rc = FAPI_ATTR_GET(ATTR_SPD_CDIMM_MASTER_POWER_INTERCEPT, &i_target_mba, cdimm_master_power_intercept);
-//	if(rc) return rc;
-//	rc = FAPI_ATTR_GET(ATTR_SPD_CDIMM_SUPPLIER_POWER_SLOPE, &i_target_mba, cdimm_supplier_power_slope);
-//	if(rc) return rc;
-//	rc = FAPI_ATTR_GET(ATTR_SPD_CDIMM_SUPPLIER_POWER_INTERCEPT, &i_target_mba, cdimm_supplier_power_intercept);
-//	if(rc) return rc;
-// TODO:  Get Safemode throttles from MRW (platinit), hardcode until available - Keep here until cronus is able to set runtime memory throttles at the end of istep
+/*
+	rc = FAPI_ATTR_GET(ATTR_SPD_CDIMM_MASTER_POWER_SLOPE,
+			   &i_target_mba, cdimm_master_power_slope);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_SPD_CDIMM_MASTER_POWER_SLOPE");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_SPD_CDIMM_MASTER_POWER_INTERCEPT,
+			   &i_target_mba, cdimm_master_power_intercept);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_SPD_CDIMM_MASTER_POWER_INTERCEPT");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_SPD_CDIMM_SUPPLIER_POWER_SLOPE,
+			   &i_target_mba, cdimm_supplier_power_slope);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_SPD_CDIMM_SUPPLIER_POWER_SLOPE");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_SPD_CDIMM_SUPPLIER_POWER_INTERCEPT,
+			   &i_target_mba, cdimm_supplier_power_intercept);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_SPD_CDIMM_SUPPLIER_POWER_INTERCEPT");
+	    return rc;
+	}
+*/
+// TODO:  Get Safemode throttles from MRW (platinit), hardcode until available
 	safemode_throttle_n_per_mba = 96;
-//	safemode_throttle_n_per_chip = 32;
-	safemode_throttle_n_per_chip = 96;
+	safemode_throttle_n_per_chip = 32;
 	safemode_throttle_d = 512;
-//	rc = FAPI_ATTR_GET(ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA, &i_target_mba, safemode_throttle_n_per_mba);
-//	if(rc) return rc;
-//	rc = FAPI_ATTR_GET(ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP, &i_target_mba, safemode_throttle_n_per_chip);
-//	if(rc) return rc;
-//	rc = FAPI_ATTR_GET(ATTR_MRW_SAFEMODE_MEM_THROTTLE_DENOMINATOR, &i_target_mba, safemode_throttle_d);
-//	if(rc) return rc;
+/*
+	rc = FAPI_ATTR_GET(ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA,
+			   &i_target_mba, safemode_throttle_n_per_mba);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP,
+			   &i_target_mba, safemode_throttle_n_per_chip);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_MRW_SAFEMODE_MEM_THROTTLE_DENOMINATOR,
+			   &i_target_mba, safemode_throttle_d);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_MRW_SAFEMODE_MEM_THROTTLE_DENOMINATOR");
+	    return rc;
+	}
+*/
 // TODO:  Get Thermal power Limit from MRW (platinit), hardcode until available
 	if (dimm_type == CDIMM)
 	{
 	    dimm_thermal_power_limit = 5000; // in cW, per CDIMM, high limit
-//	    dimm_thermal_power_limit = 2500; // in cW, per CDIMM
 	}
 	else
 	{
 	    dimm_thermal_power_limit = 2000; // in cW, per ISDIMM, high limit
-//	    dimm_thermal_power_limit = 600; // in cW, per ISDIMM
 	}
-//	rc = FAPI_ATTR_GET(ATTR_MRW_THERMAL_MEMORY_POWER_LIMIT, &i_target_mba, dimm_thermal_power_limit);
-//	if(rc) return rc;
-
+/*
+	rc = FAPI_ATTR_GET(ATTR_MRW_THERMAL_MEMORY_POWER_LIMIT,
+			   &i_target_mba, dimm_thermal_power_limit);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_MRW_THERMAL_MEMORY_POWER_LIMIT");
+	    return rc;
+	}
+*/
 
 // Get Centaur target for the given MBA
 	rc = fapiGetParentChip(i_target_mba, target_chip);
-	if(rc) return rc;
+	if (rc) {
+	    FAPI_ERR("Error from fapiGetParentChip");
+	    return rc;
+	}
 // Get voltage and frequency attributes
 	rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &target_chip, dimm_voltage);
-	if(rc) return rc;
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_MSS_VOLT");
+	    return rc;
+	}
 	rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &target_chip, dimm_frequency);
-	if(rc) return rc;
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_MSS_FREQ");
+	    return rc;
+	}
+
 
 // get any attributes from DIMM SPD
 	if (dimm_type != CDIMM)
 	{
-	    rc = fapiGetAssociatedDimms(i_target_mba, target_dimm_array, fapi::TARGET_STATE_PRESENT);
-	    if(rc) return rc;
-	    for (dimm_index=0; dimm_index < target_dimm_array.size(); dimm_index++)
+	    rc = fapiGetAssociatedDimms(i_target_mba, target_dimm_array,
+					fapi::TARGET_STATE_PRESENT);
+	    if (rc) {
+		FAPI_ERR("Error from fapiGetAssociatedDimms");
+		return rc;
+	    }
+	    for (dimm_index=0;
+		 dimm_index < target_dimm_array.size();
+		 dimm_index++)
 	    {
-		rc = FAPI_ATTR_GET(ATTR_MBA_PORT, &target_dimm_array[dimm_index], port);
-		if(rc) return rc;
-		rc = FAPI_ATTR_GET(ATTR_MBA_DIMM, &target_dimm_array[dimm_index], dimm);
-		if(rc) return rc;
-		rc = FAPI_ATTR_GET(ATTR_SPD_NUM_OF_REGISTERS_USED_ON_RDIMM, &target_dimm_array[dimm_index], dimm_number_registers[port][dimm]);
-		if(rc) return rc;
+		rc = FAPI_ATTR_GET(ATTR_MBA_PORT,
+				   &target_dimm_array[dimm_index], port);
+		if (rc) {
+		    FAPI_ERR("Error getting attribute ATTR_MBA_PORT");
+		    return rc;
+		}
+		rc = FAPI_ATTR_GET(ATTR_MBA_DIMM,
+				   &target_dimm_array[dimm_index], dimm);
+		if (rc) {
+		    FAPI_ERR("Error getting attribute ATTR_MBA_DIMM");
+		    return rc;
+		}
+		rc = FAPI_ATTR_GET(ATTR_SPD_NUM_OF_REGISTERS_USED_ON_RDIMM,
+				   &target_dimm_array[dimm_index],
+				   dimm_number_registers[port][dimm]);
+		if (rc) {
+		    FAPI_ERR("Error getting attribute ATTR_SPD_NUM_OF_REGISTERS_USED_ON_RDIMM");
+		    return rc;
+		}
 	    }
 	}
 
 // Get number of Centaur MBAs that have dimms present
 	if (dimm_type == CDIMM)
 	{
-	    rc = fapiGetChildChiplets(target_chip, fapi::TARGET_TYPE_MBA_CHIPLET, target_mba_array, fapi::TARGET_STATE_PRESENT);
-	    if(rc) return rc;
+	    rc = fapiGetChildChiplets(target_chip,
+				      fapi::TARGET_TYPE_MBA_CHIPLET,
+				      target_mba_array,
+				      fapi::TARGET_STATE_PRESENT);
+	    if (rc) {
+		FAPI_ERR("Error from fapiGetChildChiplets");
+		return rc;
+	    }
 	    num_mba_with_dimms = 0;
 	    for (mba_index=0; mba_index < target_mba_array.size(); mba_index++)
 	    {
-		rc = fapiGetAssociatedDimms(target_mba_array[mba_index], target_dimm_array, fapi::TARGET_STATE_PRESENT);
-		if(rc) return rc;
+		rc = fapiGetAssociatedDimms(target_mba_array[mba_index],
+					    target_dimm_array,
+					    fapi::TARGET_STATE_PRESENT);
+		if (rc) {
+		    FAPI_ERR("Error from fapiGetAssociatedDimms");
+		    return rc;
+		}
 		if (target_dimm_array.size() > 0)
 		{
 		    num_mba_with_dimms++;
@@ -402,16 +577,18 @@ extern "C" {
 	{
 // get worst case termination values that will be used
 // Only look at Centaur DQ/DQS Driver and Receiver termination settings
-// Note that the DRAM rtt_nom, rtt_wr, and ron will not be allowed to change, all these will stay at the nominal settings
+// Note that the DRAM rtt_nom, rtt_wr, and ron will not be allowed to change,
+// all these will stay at the nominal settings
 	    for (port=0; port < NUM_PORTS; port++)
 	    {
-		rc = mss_eff_config_thermal_get_wc_term(
-							i_target_mba,
-							port,
-							cen_dq_dqs_rcv_imp_wc[port],
-							cen_dq_dqs_drv_imp_wc[port]
-							);
-		if(rc)
+		rc = mss_eff_config_thermal_get_wc_term
+		  (
+		   i_target_mba,
+		   port,
+		   cen_dq_dqs_rcv_imp_wc[port],
+		   cen_dq_dqs_drv_imp_wc[port]
+		   );
+		if (rc)
 		{
 		    FAPI_ERR("Error (0x%x) calling mss_eff_config_thermal_get_wc_term", static_cast<uint32_t>(rc));
 		    return rc;
@@ -419,9 +596,9 @@ extern "C" {
 	    }
 	}
 
-////////////////////////////////////////////////////////////////////////
+//------------------------------------------------------------------------------
 // Power Curve Determination
-////////////////////////////////////////////////////////////////////////
+//------------------------------------------------------------------------------
 // Iterate through the MBA ports to get power slope/intercept values
 	for (port=0; port < NUM_PORTS; port++)
 	{
@@ -438,69 +615,76 @@ extern "C" {
 		    for (rank=0; rank < NUM_RANKS; rank++)
 		    {
 // nominal termination
-			rc = mss_eff_config_thermal_term(
-							 "NOM",
-							 port,
-							 dimm,
-							 rank,
-							 dimm_voltage,
-							 dram_width,
-							 dram_tdqs,
-							 ibm_type,
-							 dimm_ranks_configed_array,
-							 dimm_dram_ron,
-							 dimm_rank_odt_rd,
-							 dimm_rank_odt_wr,
-							 dram_rtt_nom,
-							 dram_rtt_wr,
-							 cen_dq_dqs_rcv_imp,
-							 cen_dq_dqs_drv_imp,
-							 dimm_power_adder_termination
-							 );
-			if(rc)
+			rc = mss_eff_config_thermal_term
+			  (
+			   "NOM",
+			   port,
+			   dimm,
+			   rank,
+			   dimm_voltage,
+			   dram_width,
+			   dram_tdqs,
+			   ibm_type,
+			   dimm_ranks_configed_array,
+			   dimm_dram_ron,
+			   dimm_rank_odt_rd,
+			   dimm_rank_odt_wr,
+			   dram_rtt_nom,
+			   dram_rtt_wr,
+			   cen_dq_dqs_rcv_imp,
+			   cen_dq_dqs_drv_imp,
+			   dimm_power_adder_termination
+			   );
+			if (rc)
 			{
 			    FAPI_ERR("Error (0x%x) calling mss_eff_config_thermal_term", static_cast<uint32_t>(rc));
 			    return rc;
 			}
-			if (dimm_power_adder_termination > dimm_power_adder_termination_largest)
+			if (dimm_power_adder_termination >
+			    dimm_power_adder_termination_largest)
 			{
-			    dimm_power_adder_termination_largest = dimm_power_adder_termination;
+			    dimm_power_adder_termination_largest =
+			      dimm_power_adder_termination;
 			}
 
 // worst case termination
-			rc = mss_eff_config_thermal_term(
-							 "WC",
-							 port,
-							 dimm,
-							 rank,
-							 dimm_voltage,
-							 dram_width,
-							 dram_tdqs,
-							 ibm_type,
-							 dimm_ranks_configed_array,
-							 dimm_dram_ron,
-							 dimm_rank_odt_rd,
-							 dimm_rank_odt_wr,
-							 dram_rtt_nom,
-							 dram_rtt_wr,
-							 cen_dq_dqs_rcv_imp_wc,
-							 cen_dq_dqs_drv_imp_wc,
-							 dimm_power_adder_termination_wc
-							 );
-			if(rc)
+			rc = mss_eff_config_thermal_term
+			  (
+			   "WC",
+			   port,
+			   dimm,
+			   rank,
+			   dimm_voltage,
+			   dram_width,
+			   dram_tdqs,
+			   ibm_type,
+			   dimm_ranks_configed_array,
+			   dimm_dram_ron,
+			   dimm_rank_odt_rd,
+			   dimm_rank_odt_wr,
+			   dram_rtt_nom,
+			   dram_rtt_wr,
+			   cen_dq_dqs_rcv_imp_wc,
+			   cen_dq_dqs_drv_imp_wc,
+			   dimm_power_adder_termination_wc
+			   );
+			if (rc)
 			{
 			    FAPI_ERR("Error (0x%x) calling mss_eff_config_thermal_term", static_cast<uint32_t>(rc));
 			    return rc;
 			}
-			if (dimm_power_adder_termination_wc > dimm_power_adder_termination_largest_wc)
+			if (dimm_power_adder_termination_wc >
+			    dimm_power_adder_termination_largest_wc)
 			{
-			    dimm_power_adder_termination_largest_wc = dimm_power_adder_termination_wc;
+			    dimm_power_adder_termination_largest_wc =
+			      dimm_power_adder_termination_wc;
 			}
 		    }
 		}
 	    }
 
-// iterate through the dimms on each port again to determine power slope and intercept
+// iterate through the dimms on each port again to determine power slope and
+// intercept
 	    for (dimm=0; dimm < NUM_DIMMS; dimm++)
 	    {
 // initialize dimm entries to zero
@@ -516,88 +700,242 @@ extern "C" {
 // Data in VPD needs to be the power per virtual dimm on the CDIMM
 		    if (dimm_type == CDIMM)
 		    {
-			power_slope_array[port][dimm] = cdimm_master_power_slope;
-			power_int_array[port][dimm] = cdimm_master_power_intercept;
-			power_slope2_array[port][dimm] = cdimm_supplier_power_slope;
-			power_int2_array[port][dimm] = cdimm_supplier_power_intercept;
+			power_slope_array[port][dimm] =
+			  cdimm_master_power_slope;
+			power_int_array[port][dimm] =
+			  cdimm_master_power_intercept;
+			power_slope2_array[port][dimm] =
+			  cdimm_supplier_power_slope;
+			power_int2_array[port][dimm] =
+			  cdimm_supplier_power_intercept;
 
 // check to see if data is valid
-			if ((((cdimm_master_power_slope & 0x8000) != 0) && ((cdimm_master_power_intercept & 0x8000) != 0)) && (((cdimm_supplier_power_slope & 0x8000) != 0) && ((cdimm_supplier_power_intercept & 0x8000) != 0)))
+			if (
+			    (((cdimm_master_power_slope & 0x8000) != 0) &&
+			     ((cdimm_master_power_intercept & 0x8000) != 0))
+			    &&
+			    (((cdimm_supplier_power_slope & 0x8000) != 0) &&
+			     ((cdimm_supplier_power_intercept & 0x8000) != 0))
+			    )
 			{
-			    power_slope_array[port][dimm] = cdimm_master_power_slope & 0x1FFF;
-			    power_int_array[port][dimm] = cdimm_master_power_intercept & 0x1FFF;
-			    power_slope2_array[port][dimm] = cdimm_supplier_power_slope & 0x1FFF;
-			    power_int2_array[port][dimm] = cdimm_supplier_power_intercept & 0x1FFF;
+			    power_slope_array[port][dimm] =
+			      cdimm_master_power_slope & 0x1FFF;
+			    power_int_array[port][dimm] =
+			      cdimm_master_power_intercept & 0x1FFF;
+			    power_slope2_array[port][dimm] =
+			      cdimm_supplier_power_slope & 0x1FFF;
+			    power_int2_array[port][dimm] =
+			      cdimm_supplier_power_intercept & 0x1FFF;
 // check to see if data is lab data
-			    if ((((cdimm_master_power_slope & 0x4000) == 0) || ((cdimm_master_power_intercept & 0x4000) == 0)) || (((cdimm_supplier_power_slope & 0x4000) == 0) || ((cdimm_supplier_power_intercept & 0x4000) == 0)))
+			    if (
+				(((cdimm_master_power_slope & 0x4000) == 0) ||
+				 ((cdimm_master_power_intercept & 0x4000) == 0))
+				||
+				(((cdimm_supplier_power_slope & 0x4000) == 0) ||
+				 ((cdimm_supplier_power_intercept &
+				   0x4000) == 0))
+				)
 			    {
-//TODO:  enable error reporting for this when it makes sense to do (after ship level power curve data is known), remove warning message.  Log error and allow IPL to continue and use the lab data if it is there.
-				FAPI_INF("WARNING:  power curve data is lab data, not ship level data");
-//				FAPI_ERR("power curve data is lab data, not ship level data");
-//				FAPI_SET_HWP_ERROR(rc, RC_MSS_DIMM_POWER_CURVE_DATA_LAB);
-//				if (rc) fapiLogError(rc);
+// TODO:  enable error reporting for this when it makes sense to do (after ship
+// level power curve data is known), remove warning message.  Log error and
+// allow IPL to continue and use the lab data if it is there.
+				FAPI_INF("WARNING:  power curve data is lab data, not ship level data. Using data anyways.");
+/*
+				power_slope_array[port][dimm] =
+				  CDIMM_POWER_SLOPE_DEFAULT;
+				power_int_array[port][dimm] =
+				  CDIMM_POWER_INT_DEFAULT;
+				power_slope2_array[port][dimm] =
+				  CDIMM_POWER_SLOPE_DEFAULT;
+				power_int2_array[port][dimm] =
+				  CDIMM_POWER_INT_DEFAULT;
+				FAPI_ERR("power curve data is lab data, not ship level data.  Use default values");
+				const fapi::Target & MEM_CHIP = target_chip;
+				uint32_t FFDC_DATA_1 = cdimm_master_power_slope;
+				uint32_t FFDC_DATA_2 =
+				  cdimm_master_power_intercept;
+				uint32_t FFDC_DATA_3 =
+				  cdimm_supplier_power_slope;
+				uint32_t FFDC_DATA_4 =
+				  cdimm_supplier_power_intercept;
+				FAPI_SET_HWP_ERROR
+				  (rc, RC_MSS_DIMM_POWER_CURVE_DATA_LAB);
+				if (rc) fapiLogError(rc);
+*/
 			    }
 			}
 			else
 			{
-			    power_slope_array[port][dimm] = CDIMM_POWER_SLOPE_DEFAULT;
-			    power_int_array[port][dimm] = CDIMM_POWER_INT_DEFAULT;
-			    power_slope2_array[port][dimm] = CDIMM_POWER_SLOPE_DEFAULT;
-			    power_int2_array[port][dimm] = CDIMM_POWER_INT_DEFAULT;
+			    power_slope_array[port][dimm] =
+			      CDIMM_POWER_SLOPE_DEFAULT;
+			    power_int_array[port][dimm] =
+			      CDIMM_POWER_INT_DEFAULT;
+			    power_slope2_array[port][dimm] =
+			      CDIMM_POWER_SLOPE_DEFAULT;
+			    power_int2_array[port][dimm] =
+			      CDIMM_POWER_INT_DEFAULT;
 			    FAPI_ERR("power curve data not valid, use default values");
-			    FAPI_SET_HWP_ERROR(rc, RC_MSS_DIMM_POWER_CURVE_DATA_INVALID);
+			    const fapi::Target & MEM_CHIP = target_chip;
+			    uint32_t FFDC_DATA_1 = cdimm_master_power_slope;
+			    uint32_t FFDC_DATA_2 = cdimm_master_power_intercept;
+			    uint32_t FFDC_DATA_3 = cdimm_supplier_power_slope;
+			    uint32_t FFDC_DATA_4 =
+			      cdimm_supplier_power_intercept;
+			    FAPI_SET_HWP_ERROR
+			      (rc, RC_MSS_DIMM_POWER_CURVE_DATA_INVALID);
 			    if (rc) fapiLogError(rc);
 			}
-
-			FAPI_INF("CDIMM Power [P%d:D%d][SLOPE=%d:INT=%d cW][SLOPE2=%d:INT2=%d cW]", port, dimm, power_slope_array[port][dimm], power_int_array[port][dimm], power_slope2_array[port][dimm], power_int2_array[port][dimm]);
+			FAPI_DBG("CDIMM Power [P%d:D%d][SLOPE=%d:INT=%d cW][SLOPE2=%d:INT2=%d cW]", port, dimm, power_slope_array[port][dimm], power_int_array[port][dimm], power_slope2_array[port][dimm], power_int2_array[port][dimm]);
 		    }
 // ISDIMM power slope/intercept will come from equation
 		    else
 		    {
-// Get the dimm power from table and add on any adjustments (if not found in table - should never happen - then default values will be used)
-			power_slope_array[port][dimm] = ISDIMM_POWER_SLOPE_DEFAULT;
+// Get the dimm power from table and add on any adjustments (if not found in
+//  table - should never happen - then default values will be used)
+			power_slope_array[port][dimm] =
+			  ISDIMM_POWER_SLOPE_DEFAULT;
 			power_int_array[port][dimm] = ISDIMM_POWER_INT_DEFAULT;
 
 			found_entry_in_table = 0;
 			for (entry = 0; entry < power_table_size; entry++)
 			{
-			    if ((power_table[entry].dram_generation == dram_gen) && (power_table[entry].dram_width == dram_width) && ((power_table[entry].dimm_ranks == dimm_master_ranks_array[port][dimm]) || (power_table[entry].dimm_ranks == 1)))
+			    if (
+				(power_table[entry].dram_generation == dram_gen)
+				&&
+				(power_table[entry].dram_width == dram_width)
+				&&
+				((power_table[entry].dimm_ranks ==
+				  dimm_master_ranks_array[port][dimm]) ||
+				 (power_table[entry].dimm_ranks == 1))
+				)
 			    {
 // get adder for dimm type
 				if (dimm_type == UDIMM)
 				{
-				    dimm_power_adder_type = power_table[entry].dimm_type_adder.udimm;
+				    dimm_power_adder_type =
+				      power_table[entry].dimm_type_adder.udimm;
 				}
 				else if (dimm_type == LRDIMM)
 				{
-				    dimm_power_adder_type = power_table[entry].dimm_type_adder.lrdimm;
+				    dimm_power_adder_type =
+				      power_table[entry].dimm_type_adder.lrdimm;
 				}
 				else // RDIMM
 				{
-				    dimm_power_adder_type = power_table[entry].dimm_type_adder.rdimm;
+				    dimm_power_adder_type =
+				      power_table[entry].dimm_type_adder.rdimm;
 				}
 
 
 				if (dimm_type == RDIMM) {
-				    dimm_power_adder_type = dimm_power_adder_type * dimm_number_registers[port][dimm];
+				    dimm_power_adder_type =
+				      dimm_power_adder_type *
+				      dimm_number_registers[port][dimm];
 				}
 
 // get adder for dimm voltage
-				dimm_power_multiplier_volt = ((float(dimm_voltage) / power_table[entry].dimm_voltage_base) * (float(dimm_voltage) / power_table[entry].dimm_voltage_base));
+				dimm_power_multiplier_volt =
+				  (
+				   (float(dimm_voltage) /
+				    power_table[entry].dimm_voltage_base)
+				   *
+				   (float(dimm_voltage) /
+				    power_table[entry].dimm_voltage_base)
+				   );
 // get adder for dimm frequency
-				dimm_power_mulitiplier_freq = (float(dimm_frequency) / power_table[entry].dimm_frequency_base);
+				dimm_power_mulitiplier_freq =
+				  (float(dimm_frequency) /
+				   power_table[entry].dimm_frequency_base);
 // get adder for termination using equation (in cW)
-				dimm_power_adder_termination = dimm_power_adder_termination_largest * 100;
-				dimm_power_adder_termination_wc = dimm_power_adder_termination_largest_wc * 100;
-// add up power for each dimm on channel and divide by number of dimms to get an average power for each dimm
-// calculate idle and active dimm power (active power includes worst case termination power)
-				dimm_idle_power = ((float(((power_table[entry].rank_power.idle * (dimm_master_ranks_array[port][dimm] + (dimm_ranks_array[port][dimm] - dimm_master_ranks_array[port][dimm])) + dimm_power_adder_type) * (dimm_power_multiplier_volt) * (dimm_power_mulitiplier_freq)) * num_dimms_on_port) / (num_dimms_on_port)));
-				dimm_active_power = ((float((((power_table[entry].rank_power.idle * (dimm_master_ranks_array[port][dimm] + (dimm_ranks_array[port][dimm] - dimm_master_ranks_array[port][dimm])) + (power_table[entry].rank_power.active - power_table[entry].rank_power.idle)) + dimm_power_adder_type) * (dimm_power_multiplier_volt) * (dimm_power_mulitiplier_freq)) * num_dimms_on_port - (power_table[entry].rank_power.active - power_table[entry].rank_power.idle) * (num_dimms_on_port - 1) + dimm_power_adder_termination + (dimm_power_adder_termination_wc - dimm_power_adder_termination)) / (num_dimms_on_port)));
-// calculate dimm power slope and intercept (add on 0.5 so value is effectively rounded to nearest integer)
-				power_slope_array[port][dimm] = int((dimm_active_power - dimm_idle_power) / (float(ACTIVE_DIMM_UTILIZATION - IDLE_DIMM_UTILIZATION) / 100) + 0.5);
-				power_int_array[port][dimm] = int(dimm_idle_power + 0.5);
-				power_slope2_array[port][dimm] = power_slope_array[port][dimm];
-				power_int2_array[port][dimm] = power_int_array[port][dimm];
+				dimm_power_adder_termination =
+				  dimm_power_adder_termination_largest * 100;
+				dimm_power_adder_termination_wc =
+				  dimm_power_adder_termination_largest_wc * 100;
+// add up power for each dimm on channel and divide by number of dimms to get an
+// average power for each dimm
+// calculate idle and active dimm power (active power includes worst case
+// termination power)
+				dimm_idle_power =
+				  (
+				   (float(
+					  (
+					   (
+					    power_table[entry].rank_power.idle
+					    *
+					    (
+					     dimm_master_ranks_array[port][dimm]
+					     + (dimm_ranks_array[port][dimm] -
+						dimm_master_ranks_array
+						[port][dimm])
+					     ) + dimm_power_adder_type
+					    )
+					   * (dimm_power_multiplier_volt)
+					   * (dimm_power_mulitiplier_freq)
+					   )
+					  *
+					  num_dimms_on_port
+					  )
+				    / (num_dimms_on_port)
+				    )
+				   );
+//------------------------------------------------------------------------------
+				dimm_active_power =
+				  (
+				   (float(
+					  (
+					   (
+					    (power_table[entry].rank_power.idle
+					     *
+					     (
+					      dimm_master_ranks_array[port][dimm]
+					      +
+					      (
+					       dimm_ranks_array[port][dimm] -
+					       dimm_master_ranks_array
+					       [port][dimm]
+					       )
+					      )
+					     +
+					     (
+					      power_table[entry].rank_power.active
+					      -
+					      power_table[entry].rank_power.idle
+					      )
+					     )
+					    +
+					    dimm_power_adder_type
+					    )
+					   * (dimm_power_multiplier_volt)
+					   * (dimm_power_mulitiplier_freq)
+					   )
+					  * num_dimms_on_port -
+					  (power_table[entry].rank_power.active
+					   - power_table[entry].rank_power.idle)
+					  * (num_dimms_on_port - 1)
+					  + dimm_power_adder_termination
+					  + (dimm_power_adder_termination_wc -
+					     dimm_power_adder_termination)
+					  )
+				    /
+				    (num_dimms_on_port)
+				    )
+				   );
+//------------------------------------------------------------------------------
+// calculate dimm power slope and intercept (add on 0.5 so value is effectively
+// rounded to nearest integer)
+				power_slope_array[port][dimm] =
+				  int(
+				      (dimm_active_power - dimm_idle_power) /
+				      (float(ACTIVE_DIMM_UTILIZATION -
+					     IDLE_DIMM_UTILIZATION) / 100)
+				      + 0.5
+				      );
+				power_int_array[port][dimm] =
+				  int(dimm_idle_power + 0.5);
+				power_slope2_array[port][dimm] =
+				  power_slope_array[port][dimm];
+				power_int2_array[port][dimm] =
+				  power_int_array[port][dimm];
 				if (power_table[entry].dram_generation == DDR3)
 				{
 				    sprintf(dram_gen_str, "DDR3");
@@ -610,15 +948,48 @@ extern "C" {
 				found_entry_in_table = 1;
 				FAPI_DBG("FOUND ENTRY:  GEN=%s WIDTH=X%d RANK=%d IDLE(%d%%)=%d ACTIVE(%d%%)=%d ADDER[TYPE=%d WCTERM=%4.2f] Multiplier[VOLT=%4.2f FREQ=%4.2f]", dram_gen_str, power_table[entry].dram_width, power_table[entry].dimm_ranks, IDLE_DIMM_UTILIZATION, power_table[entry].rank_power.idle, ACTIVE_DIMM_UTILIZATION, power_table[entry].rank_power.active, dimm_power_adder_type, dimm_power_adder_termination_wc, dimm_power_multiplier_volt, dimm_power_mulitiplier_freq);
 				FAPI_DBG("ISDIMM Power [P%d:D%d][%s:X%d:R%d/%d:%d:%d][IDLE(%d%%)=%4.2f:ACTIVE(%d%%)=%4.2f cW][SLOPE=%d:INT=%d cW]", port, dimm, dram_gen_str, power_table[entry].dram_width, dimm_master_ranks_array[port][dimm], (dimm_ranks_array[port][dimm] - dimm_master_ranks_array[port][dimm]), dimm_voltage, dimm_frequency, IDLE_DIMM_UTILIZATION, dimm_idle_power, ACTIVE_DIMM_UTILIZATION, dimm_active_power, power_slope_array[port][dimm], power_int_array[port][dimm]);
-				FAPI_INF("ISDIMM Power [P%d:D%d][SLOPE=%d:INT=%d cW][SLOPE2=%d:INT2=%d cW]", port, dimm, power_slope_array[port][dimm], power_int_array[port][dimm], power_slope2_array[port][dimm], power_int2_array[port][dimm]);
+				FAPI_DBG("ISDIMM Power [P%d:D%d][SLOPE=%d:INT=%d cW][SLOPE2=%d:INT2=%d cW]", port, dimm, power_slope_array[port][dimm], power_int_array[port][dimm], power_slope2_array[port][dimm], power_int2_array[port][dimm]);
 				break;
 			    }
 
 			}
+//------------------------------------------------------------------------------
 			if (found_entry_in_table == 0)
 			{
-			    FAPI_ERR( "Failed to Find DIMM Power Values on %s.  Default values will be used [P%d:D%d][Slope=%d:INT=%d cW]", i_target_mba.toEcmdString(), port, dimm, power_slope_array[port][dimm], power_int_array[port][dimm] );
-			    FAPI_SET_HWP_ERROR(rc, RC_MSS_DIMM_NOT_FOUND_IN_POWER_TABLE);
+			    FAPI_ERR("Failed to Find DIMM Power Values on %s.  Default values will be used [P%d:D%d][Slope=%d:INT=%d cW]", i_target_mba.toEcmdString(), port, dimm, power_slope_array[port][dimm], power_int_array[port][dimm]);
+
+// get dimm target, we should always find a valid dimm target from this
+// since we have ranks present on this dimm if we are here in the code
+			    for (dimm_index=0;
+				 dimm_index < target_dimm_array.size();
+				 dimm_index++)
+			    {
+				rc = FAPI_ATTR_GET
+				  (ATTR_MBA_PORT,
+				   &target_dimm_array[dimm_index], mba_port);
+				if (rc) {
+				    FAPI_ERR("Error getting attribute ATTR_MBA_PORT");
+				    return rc;
+				}
+				rc = FAPI_ATTR_GET
+				  (ATTR_MBA_DIMM,
+				   &target_dimm_array[dimm_index], mba_dimm);
+				if (rc) {
+				    FAPI_ERR("Error getting attribute ATTR_MBA_DIMM");
+				    return rc;
+				}
+				if ( (mba_port == port) && (mba_dimm == dimm)) {
+				    break;
+				}
+			    }
+			    const fapi::Target & MEM_DIMM =
+			      target_dimm_array[dimm_index];
+			    uint32_t FFDC_DATA_1 = dram_gen;
+			    uint32_t FFDC_DATA_2 = dram_width;
+			    uint8_t  FFDC_DATA_3 =
+			      dimm_master_ranks_array[port][dimm];
+			    FAPI_SET_HWP_ERROR
+			      (rc, RC_MSS_DIMM_NOT_FOUND_IN_POWER_TABLE);
 			    if (rc) fapiLogError(rc);
 			}
 		    }
@@ -627,66 +998,125 @@ extern "C" {
 	}
 
 // write output attributes
-	rc = FAPI_ATTR_SET(ATTR_MSS_POWER_SLOPE, &i_target_mba, power_slope_array);
-	if(rc) return rc;
+	rc = FAPI_ATTR_SET(ATTR_MSS_POWER_SLOPE,
+			   &i_target_mba, power_slope_array);
+	if (rc) {
+	    FAPI_ERR("Error writing attribute ATTR_MSS_POWER_SLOPE");
+	    return rc;
+	}
 	rc = FAPI_ATTR_SET(ATTR_MSS_POWER_INT, &i_target_mba, power_int_array);
-	if(rc) return rc;
+	if (rc) {
+	    FAPI_ERR("Error writing attribute ATTR_MSS_POWER_INT");
+	    return rc;
+	}
 
-	rc = FAPI_ATTR_SET(ATTR_MSS_POWER_SLOPE2, &i_target_mba, power_slope2_array);
-	if(rc) return rc;
-	rc = FAPI_ATTR_SET(ATTR_MSS_POWER_INT2, &i_target_mba, power_int2_array);
-	if(rc) return rc;
+	rc = FAPI_ATTR_SET(ATTR_MSS_POWER_SLOPE2,
+			   &i_target_mba, power_slope2_array);
+	if (rc) {
+	    FAPI_ERR("Error writing attribute ATTR_MSS_POWER_SLOPE2");
+	    return rc;
+	}
+	rc = FAPI_ATTR_SET(ATTR_MSS_POWER_INT2,
+			   &i_target_mba, power_int2_array);
+	if (rc) {
+	    FAPI_ERR("Error writing attribute ATTR_MSS_POWER_INT2");
+	    return rc;
+	}
 
 
-////////////////////////////////////////////////////////////////////////
+//------------------------------------------------------------------------------
 // Memory Throttle Determination
-////////////////////////////////////////////////////////////////////////
+//------------------------------------------------------------------------------
 
-// Runtime throttles will be non-volatile, so don't recalculate them if they have already been set
+// Runtime throttles will be non-volatile, so don't recalculate them if they
+// have already been set
 
-// TODO:  remove this section when firmware initializes attributes to zero AND runtime throttles are non-volatile
+// TODO:  remove this section when firmware initializes attributes to zero AND
+// runtime throttles are non-volatile
 	runtime_throttle_n_per_mba = 0;
 	runtime_throttle_n_per_chip = 0;
 	runtime_throttle_d = 0;
-	rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA, &i_target_mba, runtime_throttle_n_per_mba);
-	if(rc) return rc;
-	rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP, &i_target_mba, runtime_throttle_n_per_chip);
-	if(rc) return rc;
-	rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR, &i_target_mba, runtime_throttle_d);
-	if(rc) return rc;
+	rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA,
+			   &i_target_mba, runtime_throttle_n_per_mba);
+	if (rc) {
+	    FAPI_ERR("Error writing attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA");
+	    return rc;
+	}
+	rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP,
+			   &i_target_mba, runtime_throttle_n_per_chip);
+	if (rc) {
+	    FAPI_ERR("Error writing attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP");
+	    return rc;
+	}
+	rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR,
+			   &i_target_mba, runtime_throttle_d);
+	if (rc) {
+	    FAPI_ERR("Error writing attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR");
+	    return rc;
+	}
 
 // Get the runtime throttle attributes here
-	rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA, &i_target_mba, runtime_throttle_n_per_mba);
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP, &i_target_mba, runtime_throttle_n_per_chip);
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR, &i_target_mba, runtime_throttle_d);
-	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA,
+			   &i_target_mba, runtime_throttle_n_per_mba);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP,
+			   &i_target_mba, runtime_throttle_n_per_chip);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR,
+			   &i_target_mba, runtime_throttle_d);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR");
+	    return rc;
+	}
 // check to see if runtime throttles are all zero here
-	if ((runtime_throttle_n_per_mba == 0) && (runtime_throttle_n_per_chip == 0) && (runtime_throttle_d == 0))
+	if (
+	    (runtime_throttle_n_per_mba == 0) &&
+	    (runtime_throttle_n_per_chip == 0) &&
+	    (runtime_throttle_d == 0)
+	    )
 	{
 // Values have not been initialized, so get them initialized
-
-// Determine the thermal power limit to use, which represents a single channel pair power limit for the dimms on that channel pair (ie.  power for all dimms attached to one MBA).   The procedure mss_bulk_power_throttles takes the input of channel pair power to determine throttles.
-// CDIMM thermal power limit from MRW is per CDIMM, so divide by number of mbas that have dimms to get channel pair power
-// CDIMM:  Allow all commands to be directed toward one MBA to achieve the power limit
-//   This means that the power limit for a MBA channel pair must be the total CDIMM power limit minus the idle power of the other MBAs logical dimms
+//------------------------------------------------------------------------------
+// Determine the thermal power limit to use, which represents a single channel
+// pair power limit for the dimms on that channel pair (ie.  power for all dimms
+// attached to one MBA).   The procedure mss_bulk_power_throttles takes the
+// input of channel pair power to determine throttles.
+// CDIMM thermal power limit from MRW is per CDIMM, so divide by number of mbas
+// that have dimms to get channel pair power
+// CDIMM:  Allow all commands to be directed toward one MBA to achieve the power
+// limit
+//   This means that the power limit for a MBA channel pair must be the total
+// CDIMM power limit minus the idle power of the other MBAs logical dimms
+//------------------------------------------------------------------------------
 	    if (dimm_type == CDIMM)
 	    {
-		channel_pair_thermal_power_limit = dimm_thermal_power_limit / num_mba_with_dimms;
+		channel_pair_thermal_power_limit =
+		  dimm_thermal_power_limit / num_mba_with_dimms;
 	    }
 // ISDIMMs thermal power limit from MRW is per DIMM, so multiply by number of dimms on channel to get channel power and multiply by 2 to get channel pair power
 	    else
 	    {
 		// ISDIMMs
-		channel_pair_thermal_power_limit = dimm_thermal_power_limit * num_dimms_on_port * 2;
+		channel_pair_thermal_power_limit =
+		  dimm_thermal_power_limit * num_dimms_on_port * 2;
 	    }
 
 // Update the channel pair power limit attribute
-	    rc = FAPI_ATTR_SET(ATTR_MSS_MEM_WATT_TARGET, &i_target_mba, channel_pair_thermal_power_limit);
-	    if(rc) return rc;
+	    rc = FAPI_ATTR_SET(ATTR_MSS_MEM_WATT_TARGET,
+			       &i_target_mba, channel_pair_thermal_power_limit);
+	    if (rc) {
+		FAPI_ERR("Error writing attribute ATTR_MSS_MEM_WATT_TARGET");
+		return rc;
+	    }
 
-// Call the procedure function that takes a channel pair power limit and converts it to throttle values
+// Call the procedure function that takes a channel pair power limit and
+// converts it to throttle values
 
 	    FAPI_EXEC_HWP(rc, mss_bulk_pwr_throttles, i_target_mba);
 	    if (rc)
@@ -696,86 +1126,140 @@ extern "C" {
 	    }
 
 // Read back in the updated throttle attribute values (these are now set to values that will give dimm/channel power underneath the thermal power limit)
-	    rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA, &i_target_mba, runtime_throttle_n_per_mba);
-	    if(rc) return rc;
-	    rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP, &i_target_mba, runtime_throttle_n_per_chip);
-	    if(rc) return rc;
-	    rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_DENOMINATOR, &i_target_mba, runtime_throttle_d);
-	    if(rc) return rc;
+	    rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA,
+			       &i_target_mba, runtime_throttle_n_per_mba);
+	    if (rc) {
+		FAPI_ERR("Error getting attribute ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA");
+		return rc;
+	    }
+	    rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP,
+			       &i_target_mba, runtime_throttle_n_per_chip);
+	    if (rc) {
+		FAPI_ERR("Error getting attribute ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP");
+		return rc;
+	    }
+	    rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_DENOMINATOR,
+			       &i_target_mba, runtime_throttle_d);
+	    if (rc) {
+		FAPI_ERR("Error getting attribute ATTR_MSS_MEM_THROTTLE_DENOMINATOR");
+		return rc;
+	    }
 
 // update output attributes
-	    rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA, &i_target_mba, runtime_throttle_n_per_mba);
-	    if(rc) return rc;
-	    rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP, &i_target_mba, runtime_throttle_n_per_chip);
-	    if(rc) return rc;
-	    rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR, &i_target_mba, runtime_throttle_d);
-	    if(rc) return rc;
+	    rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA,
+			       &i_target_mba, runtime_throttle_n_per_mba);
+	    if (rc) {
+		FAPI_ERR("Error writing attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA");
+		return rc;
+	    }
+	    rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP,
+			       &i_target_mba, runtime_throttle_n_per_chip);
+	    if (rc) {
+		FAPI_ERR("Error writing attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP");
+		return rc;
+	    }
+	    rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR,
+			       &i_target_mba, runtime_throttle_d);
+	    if (rc) {
+		FAPI_ERR("Error writing attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR");
+		return rc;
+	    }
 
 	}
 
-// Initialize the generic throttle attributes to safemode throttles (since the IPL will be done at the safemode throttles)
+// Initialize the generic throttle attributes to safemode throttles (since the
+// IPL will be done at the safemode throttles)
 	throttle_n_per_mba = safemode_throttle_n_per_mba;
 	throttle_n_per_chip = safemode_throttle_n_per_chip;
 	throttle_d = safemode_throttle_d;
 
 // write output attributes
-	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA, &i_target_mba, throttle_n_per_mba);
-	if(rc) return rc;
-	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP, &i_target_mba, throttle_n_per_chip);
-	if(rc) return rc;
-	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_DENOMINATOR, &i_target_mba, throttle_d);
-	if(rc) return rc;
-
-	FAPI_INF("*** %s COMPLETE ***", procedure_name);
+	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA,
+			   &i_target_mba, throttle_n_per_mba);
+	if (rc) {
+	    FAPI_ERR("Error writing attribute ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA");
+	    return rc;
+	}
+	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP,
+			   &i_target_mba, throttle_n_per_chip);
+	if (rc) {
+	    FAPI_ERR("Error writing attribute ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP");
+	    return rc;
+	}
+	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_DENOMINATOR,
+			   &i_target_mba, throttle_d);
+	if (rc) {
+	    FAPI_ERR("Error writing attribute ATTR_MSS_MEM_THROTTLE_DENOMINATOR");
+	    return rc;
+	}
+
+	FAPI_IMP("*** %s COMPLETE ***", procedure_name);
 	return rc;
     }
 
 //------------------------------------------------------------------------------
-// @brief mss_eff_config_thermal_term(): This function calculates the data bus termination power
+// @brief mss_eff_config_thermal_term(): This function calculates the data bus
+// termination power
+//
+// @param[in]   const char i_nom_or_wc_term[4]:  description of what is being
+//              calculated (ie.  NOM or WC)
+// @param[in]   uint8_t i_port:  MBA port being worked on
+// @param[in]   uint8_t i_dimm:  DIMM being worked on
+// @param[in]   uint8_t i_rank:  Rank being worked on
+// @param[in]   uint32_t i_dimm_voltage:  DIMM Voltage
+// @param[in]   uint8_t i_dram_width:  DRAM Width
+// @param[in]   uint8_t i_dram_tdqs:  DRAM TDQS enable/disable
+// @param[in]   uint8_t i_ibm_type[NUM_PORTS][NUM_DIMMS]:  IBM bus topology
+//              type
+// @param[in]   uint8_t i_dimm_ranks_configed_array[NUM_PORTS][NUM_DIMMS]:
+//              Master Ranks configured
+// @param[in]   uint8_t i_dimm_dram_ron[NUM_PORTS][NUM_DIMMS]:  DRAM RON driver
+//              impedance
+// @param[in]   uint8_t i_dimm_rank_odt_rd[NUM_PORTS][NUM_DIMMS][NUM_RANKS]:
+//              Read ODT
+// @param[in]   uint8_t i_dimm_rank_odt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS]:
+//              Write ODT
+// @param[in]   uint8_t i_dram_rtt_nom[NUM_PORTS][NUM_DIMMS][NUM_RANKS]:  DRAM
+//              RTT NOM
+// @param[in]   uint8_t i_dram_rtt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS]:  DRAM
+//              RTT WR
+// @param[in]   uint8_t i_cen_dq_dqs_rcv_imp[NUM_PORTS]:  Centaur DQ/DQS 
+//              receiver impedance
+// @param[in]	uint8_t i_cen_dq_dqs_drv_imp[NUM_PORTS]:  Centaur DQ/DQS driver
+//              impedance
+// @param[out]  float &o_dimm_power_adder_termination:  Termination Power
+//              Calculated in Watts
 //
-// @param    const char i_nom_or_wc_term[4]:  description of what is being calculated (ie.  NOM or WC)
-// @param    uint8_t i_port:  MBA port being worked on
-// @param    uint8_t i_dimm:  DIMM being worked on
-// @param    uint8_t i_rank:  Rank being worked on
-// @param    uint32_t i_dimm_voltage:  DIMM Voltage
-// @param    uint8_t i_dram_width:  DRAM Width
-// @param    uint8_t i_dram_tdqs:  DRAM TDQS enable/disable
-// @param    uint8_t i_ibm_type[NUM_PORTS][NUM_DIMMS]:  IBM bus topology type
-// @param    uint8_t i_dimm_ranks_configed_array[NUM_PORTS][NUM_DIMMS]:  Master Ranks configured
-// @param    uint8_t i_dimm_dram_ron[NUM_PORTS][NUM_DIMMS]:  DRAM RON driver impedance
-// @param    uint8_t i_dimm_rank_odt_rd[NUM_PORTS][NUM_DIMMS][NUM_RANKS]:  Read ODT
-// @param    uint8_t i_dimm_rank_odt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS]:  Write ODT
-// @param    uint8_t i_dram_rtt_nom[NUM_PORTS][NUM_DIMMS][NUM_RANKS]:  DRAM RTT NOM
-// @param    uint8_t i_dram_rtt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS]:  DRAM RTT WR
-// @param    uint8_t i_cen_dq_dqs_rcv_imp[NUM_PORTS]:  Centaur DQ/DQS receiver impedance
-// @param    uint8_t i_cen_dq_dqs_drv_imp[NUM_PORTS]:  Centaur DQ/DQS driver impedance
-// @param    float &o_dimm_power_adder_termination:  Termination Power Calculated in Watts
-
 // @return fapi::ReturnCode
 //------------------------------------------------------------------------------
 
-    fapi::ReturnCode mss_eff_config_thermal_term(
-						 const char i_nom_or_wc_term[4],
-						 uint8_t i_port,
-						 uint8_t i_dimm,
-						 uint8_t i_rank,
-						 uint32_t i_dimm_voltage,
-						 uint8_t i_dram_width,
-						 uint8_t i_dram_tdqs,
-						 uint8_t i_ibm_type[NUM_PORTS][NUM_DIMMS],
-						 uint8_t i_dimm_ranks_configed_array[NUM_PORTS][NUM_DIMMS],
-						 uint8_t i_dimm_dram_ron[NUM_PORTS][NUM_DIMMS],
-						 uint8_t i_dimm_rank_odt_rd[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
-						 uint8_t i_dimm_rank_odt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
-						 uint8_t i_dram_rtt_nom[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
-						 uint8_t i_dram_rtt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
-						 uint8_t i_cen_dq_dqs_rcv_imp[NUM_PORTS],
-						 uint8_t i_cen_dq_dqs_drv_imp[NUM_PORTS],
-						 float &o_dimm_power_adder_termination
-						 )
+    fapi::ReturnCode mss_eff_config_thermal_term
+      (
+       const char i_nom_or_wc_term[4],
+       uint8_t i_port,
+       uint8_t i_dimm,
+       uint8_t i_rank,
+       uint32_t i_dimm_voltage,
+       uint8_t i_dram_width,
+       uint8_t i_dram_tdqs,
+       uint8_t i_ibm_type[NUM_PORTS][NUM_DIMMS],
+       uint8_t i_dimm_ranks_configed_array[NUM_PORTS][NUM_DIMMS],
+       uint8_t i_dimm_dram_ron[NUM_PORTS][NUM_DIMMS],
+       uint8_t i_dimm_rank_odt_rd[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
+       uint8_t i_dimm_rank_odt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
+       uint8_t i_dram_rtt_nom[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
+       uint8_t i_dram_rtt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
+       uint8_t i_cen_dq_dqs_rcv_imp[NUM_PORTS],
+       uint8_t i_cen_dq_dqs_drv_imp[NUM_PORTS],
+       float &o_dimm_power_adder_termination
+       )
     {
-
 	fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
+
+	char procedure_name[32];
+	sprintf(procedure_name, "mss_eff_config_thermal_term");
+	FAPI_IMP("*** Running %s ***", procedure_name);
+
 	uint8_t number_nets_term_rd;
 	uint8_t number_nets_term_wr;
 	uint8_t ma0odt01_dimm;
@@ -793,31 +1277,38 @@ extern "C" {
 	float term_odt_mult_wr;
 	uint8_t cen_dq_dqs_drv_imp_value;
 
-// Get number of nets that will have termination applied from ODT (DQ,DQS,DM,TDQS)
+// Get number of nets that will have termination applied from ODT (DQ,DQS,DM,
+// TDQS)
 // number of nets for DQ (9 DRAMs x 8 bits each, or 18 DRAMs x 4 bits each = 72)
 	number_nets_term_rd = 72;
 	number_nets_term_wr = 72;
-// add in number of nets for DQS + DM + TDQS (TDQS only supported for X8, DM only used for writes)
+// add in number of nets for DQS + DM + TDQS (TDQS only supported for X8, DM
+// only used for writes)
 	if (i_dram_width == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4)
 	{
 	    number_nets_term_rd = number_nets_term_rd + 36 + 0 + 0;
 	    number_nets_term_wr = number_nets_term_wr + 36 + 0 + 0;
 	}
-	else if ((i_dram_width == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8) && (i_dram_tdqs == fapi::ENUM_ATTR_EFF_DRAM_TDQS_DISABLE))
+	else if ((i_dram_width == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8) &&
+		 (i_dram_tdqs == fapi::ENUM_ATTR_EFF_DRAM_TDQS_DISABLE))
 	{
 	    number_nets_term_rd = number_nets_term_rd + 18 + 0 + 0;
 	    number_nets_term_wr = number_nets_term_wr + 18 + 9 + 0;
 	}
-	else if ((i_dram_width == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8) && (i_dram_tdqs == fapi::ENUM_ATTR_EFF_DRAM_TDQS_ENABLE))
+	else if ((i_dram_width == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8) &&
+		 (i_dram_tdqs == fapi::ENUM_ATTR_EFF_DRAM_TDQS_ENABLE))
 	{
 	    number_nets_term_rd = number_nets_term_rd + 18 + 0 + 18;
 	    number_nets_term_wr = number_nets_term_wr + 18 + 0 + 18;
 	}
 
-// which rank is mapped to the [01]ODT[01] nets, from centaur spec, every type uses Ranks 0,1,4,5, with the following exceptions
+// which rank is mapped to the [01]ODT[01] nets, from centaur spec, every type
+// uses Ranks 0,1,4,5, with the following exceptions
 // Type 1D used Ranks 0,2,4,6 in that order (0_ODT0,0_ODT1,1_ODT0,1_ODT1)
-// expect that EFF_ODT_RD and EFF_ODT_WR will be setup correctly so we just need to add up any termination in parallel for the bits set in these attributes
-// Also need to consider if ODT is tied high for writes (if rtt_wr is set for the rank being written to, then it will be assumed that ODT is tied high)
+// expect that EFF_ODT_RD and EFF_ODT_WR will be setup correctly so we just need
+// to add up any termination in parallel for the bits set in these attributes
+// Also need to consider if ODT is tied high for writes (if rtt_wr is set for
+// the rank being written to, then it will be assumed that ODT is tied high)
 
 	if (i_ibm_type[i_port][i_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_1D)
 	{
@@ -838,7 +1329,8 @@ extern "C" {
 	    ma1odt1_rank = 1;
 	}
 
-// check to see if rank is configured, only get termination power for these ranks
+// check to see if rank is configured, only get termination power for these
+// ranks
 	rank_mask = 0x00;
 	if (i_rank == 0)
 	{
@@ -858,90 +1350,179 @@ extern "C" {
 	}
 	if ((i_dimm_ranks_configed_array[i_port][i_dimm] & rank_mask) != 0)
 	{
-// effective net termination = [(active termination in parallel || driver impedance) + active termination in parallel]
+// effective net termination = [(active termination in parallel || driver
+// impedance) + active termination in parallel]
 
 
 
-////////////////////////////////////////////////
+//------------------------------------------------------------------------------
 // calculate out effective termination for reads
-////////////////////////////////////////////////
+//------------------------------------------------------------------------------
 	    eff_term_rd = 0;
 
+//------------------------------------------------------------------------------
 // 0ODT0
-	    if (((i_dimm_rank_odt_rd[i_port][i_dimm][i_rank] & 0x80) != 0) && (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE))
+	    if (
+		((i_dimm_rank_odt_rd[i_port][i_dimm][i_rank] & 0x80) != 0)
+		&&
+		(i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank] !=
+		 fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)
+		)
 	    {
 		if (eff_term_rd == 0)
 		{
-		    eff_term_rd = i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank];
+		    eff_term_rd =
+		      i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank];
 		}
 		else
 		{
-		    eff_term_rd = (eff_term_rd * i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank]) / (eff_term_rd + i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank]);
+		    eff_term_rd =
+		      (eff_term_rd *
+		       i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank])
+		      /
+		      (eff_term_rd +
+		       i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank]);
 		}
 		FAPI_DBG("[P%d:D%d:R%d] 0ODT0 RD TERMINATION = %4.2f (%d)", i_port, i_dimm, i_rank, eff_term_rd, i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank]);
 
 	    }
+//------------------------------------------------------------------------------
 // 0ODT1
-	    if (((i_dimm_rank_odt_rd[i_port][i_dimm][i_rank] & 0x40) != 0) && (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE))
+	    if (
+		((i_dimm_rank_odt_rd[i_port][i_dimm][i_rank] & 0x40) != 0)
+		&&
+		(i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank] !=
+		 fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)
+		)
 	    {
 		if (eff_term_rd == 0)
 		{
-		    eff_term_rd = i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank];
+		    eff_term_rd =
+		      i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank];
 		}
 		else
 		{
-		    eff_term_rd = (eff_term_rd * i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank]) / (eff_term_rd + i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank]);
+		    eff_term_rd =
+		      (eff_term_rd *
+		       i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank])
+		      /
+		      (eff_term_rd +
+		       i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank]);
 		}
 		FAPI_DBG("[P%d:D%d:R%d] 0ODT1 RD TERMINATION = %4.2f (%d)", i_port, i_dimm, i_rank, eff_term_rd, i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank]);
 	    }
+//------------------------------------------------------------------------------
 // 1ODT0
-	    if (((i_dimm_rank_odt_rd[i_port][i_dimm][i_rank] & 0x20) != 0) && (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE))
+	    if (
+		((i_dimm_rank_odt_rd[i_port][i_dimm][i_rank] & 0x20) != 0)
+		&&
+		(i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank] !=
+		 fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)
+		)
 	    {
 		if (eff_term_rd == 0)
 		{
-		    eff_term_rd = i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank];
+		    eff_term_rd =
+		      i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank];
 		}
 		else
 		{
-		    eff_term_rd = (eff_term_rd * i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank]) / (eff_term_rd + i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank]);
+		    eff_term_rd =
+		      (eff_term_rd *
+		       i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank])
+		      /
+		      (eff_term_rd +
+		       i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank]);
 		}
 		FAPI_DBG("[P%d:D%d:R%d] 1ODT0 RD TERMINATION = %4.2f (%d)", i_port, i_dimm, i_rank, eff_term_rd, i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank]);
 	    }
+//------------------------------------------------------------------------------
 // 1ODT1
-	    if (((i_dimm_rank_odt_rd[i_port][i_dimm][i_rank] & 0x10) != 0) && (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE))
+	    if (
+		((i_dimm_rank_odt_rd[i_port][i_dimm][i_rank] & 0x10) != 0)
+		&&
+		(i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank] !=
+		 fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)
+		)
 	    {
 		if (eff_term_rd == 0)
 		{
-		    eff_term_rd = i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank];
+		    eff_term_rd =
+		      i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank];
 		}
 		else
 		{
-		    eff_term_rd = (eff_term_rd * i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank]) / (eff_term_rd + i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank]);
+		    eff_term_rd =
+		      (eff_term_rd *
+		       i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank])
+		      /
+		      (eff_term_rd +
+		       i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank]);
 		}
 		FAPI_DBG("[P%d:D%d:R%d] 1ODT1 RD TERMINATION = %4.2f (%d)", i_port, i_dimm, i_rank, eff_term_rd, i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank]);
 	    }
-		// calculate out effective read termination
+
+// calculate out effective read termination
 	    if (eff_term_rd != 0)
 	    {
-		eff_net_term_rd = (float((float(eff_term_rd * i_cen_dq_dqs_rcv_imp[i_port]) / (eff_term_rd + i_cen_dq_dqs_rcv_imp[i_port])) * i_dimm_dram_ron[i_port][i_dimm]) / ((float(eff_term_rd * i_cen_dq_dqs_rcv_imp[i_port]) / (eff_term_rd + i_cen_dq_dqs_rcv_imp[i_port])) + i_dimm_dram_ron[i_port][i_dimm])) + (float(eff_term_rd * i_cen_dq_dqs_rcv_imp[i_port]) / (eff_term_rd + i_cen_dq_dqs_rcv_imp[i_port]));
+		eff_net_term_rd =
+		  (float(
+			 (float(eff_term_rd * i_cen_dq_dqs_rcv_imp[i_port]) /
+			  (eff_term_rd + i_cen_dq_dqs_rcv_imp[i_port]))
+			 * i_dimm_dram_ron[i_port][i_dimm]
+			 )
+		   /
+		   (
+		    (float(eff_term_rd * i_cen_dq_dqs_rcv_imp[i_port]) /
+		     (eff_term_rd + i_cen_dq_dqs_rcv_imp[i_port])
+		     )
+		    + i_dimm_dram_ron[i_port][i_dimm]
+		    )
+		   )
+		  +
+		  (float(eff_term_rd * i_cen_dq_dqs_rcv_imp[i_port]) /
+		   (eff_term_rd + i_cen_dq_dqs_rcv_imp[i_port]));
 		term_odt_mult_rd = 1.25;
 	    }
 	    else
 	    {
-		eff_net_term_rd = (float((i_cen_dq_dqs_rcv_imp[i_port]) * i_dimm_dram_ron[i_port][i_dimm]) / ((i_cen_dq_dqs_rcv_imp[i_port]) + i_dimm_dram_ron[i_port][i_dimm])) + (i_cen_dq_dqs_rcv_imp[i_port]);
+		eff_net_term_rd =
+		  (float((i_cen_dq_dqs_rcv_imp[i_port]) *
+			 i_dimm_dram_ron[i_port][i_dimm])
+		   / ((i_cen_dq_dqs_rcv_imp[i_port]) +
+		      i_dimm_dram_ron[i_port][i_dimm])
+		   )
+		  +
+		  (i_cen_dq_dqs_rcv_imp[i_port]);
 		term_odt_mult_rd = 1;
 	    }
 // writes
-/////////////////////////////////////////////////
+//------------------------------------------------------------------------------
 // calculate out effective termination for writes
-/////////////////////////////////////////////////
+//------------------------------------------------------------------------------
 	    eff_term_wr = 0;
 
-// check to see if ODT is tied high (rank is not one of the ranks that get ODT driven to it, and rtt_wr or rtt_nom are enabled)
-	    if (((((i_rank != ma0odt0_rank) && (i_rank != ma0odt1_rank)) && (i_dimm == 0)) || (((i_rank != ma1odt0_rank) && (i_rank != ma1odt1_rank)) && (i_dimm == 1))) && ((i_dram_rtt_wr[i_port][i_dimm][i_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) || (i_dram_rtt_nom[i_port][i_dimm][i_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)))
+// check to see if ODT is tied high (rank is not one of the ranks that get ODT
+// driven to it, and rtt_wr or rtt_nom are enabled)
+	    if (
+		(
+		 (((i_rank != ma0odt0_rank) && (i_rank != ma0odt1_rank)) &&
+		  (i_dimm == 0))
+		 ||
+		 (((i_rank != ma1odt0_rank) && (i_rank != ma1odt1_rank)) &&
+		  (i_dimm == 1))
+		 )
+		&&
+		((i_dram_rtt_wr[i_port][i_dimm][i_rank] !=
+		  fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) ||
+		 (i_dram_rtt_nom[i_port][i_dimm][i_rank] !=
+		  fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE))
+		)
 	    {
-		// dynamic ODT enabled, so use rtt_wr (only if the rank being written to has it enabled)
-		if (i_dram_rtt_wr[i_port][i_dimm][i_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE)
+// dynamic ODT enabled, so use rtt_wr (only if the rank being written to has
+// it enabled)
+		if (i_dram_rtt_wr[i_port][i_dimm][i_rank] !=
+		    fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE)
 		{
 		    if (eff_term_wr == 0)
 		    {
@@ -949,11 +1530,16 @@ extern "C" {
 		    }
 		    else
 		    {
-			eff_term_wr = (eff_term_wr * i_dram_rtt_wr[i_port][i_dimm][i_rank]) / (eff_term_wr + i_dram_rtt_wr[i_port][i_dimm][i_rank]);
+			eff_term_wr =
+			  (eff_term_wr * i_dram_rtt_wr[i_port][i_dimm][i_rank])
+			  /
+			  (eff_term_wr + i_dram_rtt_wr[i_port][i_dimm][i_rank]);
 		    }
 		}
+
 		// dynamic ODT disabled, so use rtt_nom
-		else if (i_dram_rtt_nom[i_port][i_dimm][i_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)
+		else if (i_dram_rtt_nom[i_port][i_dimm][i_rank] !=
+			 fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)
 		{
 		    if (eff_term_wr == 0)
 		    {
@@ -961,139 +1547,253 @@ extern "C" {
 		    }
 		    else
 		    {
-			eff_term_wr = (eff_term_wr * i_dram_rtt_nom[i_port][i_dimm][i_rank]) / (eff_term_wr + i_dram_rtt_nom[i_port][i_dimm][i_rank]);
+			eff_term_wr =
+			  (eff_term_wr * i_dram_rtt_nom[i_port][i_dimm][i_rank])
+			  /
+			  (eff_term_wr +
+			   i_dram_rtt_nom[i_port][i_dimm][i_rank]);
 		    }
 
 		}
 		FAPI_DBG("[P%d:D%d:R%d] WR TERMINATION = %4.2f (%d/%d)", i_port, i_dimm, i_rank, eff_term_wr, i_dram_rtt_wr[i_port][i_dimm][i_rank], i_dram_rtt_nom[i_port][i_dimm][i_rank]);
 	    }
-/// 0ODT0
-	    if (((i_dimm_rank_odt_wr[i_port][i_dimm][i_rank] & 0x80) != 0) && ((i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt0_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) || (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)))
+//------------------------------------------------------------------------------
+// 0ODT0
+	    if (
+		((i_dimm_rank_odt_wr[i_port][i_dimm][i_rank] & 0x80) != 0)
+		&&
+		((i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt0_rank] !=
+		  fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) ||
+		 (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank] !=
+		  fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE))
+		)
 	    {
-		// dynamic ODT enabled, so use rtt_wr (only if the rank being written to has it enabled)
-		if ((i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt0_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) && (i_dimm == 0) && (i_rank == ma0odt0_rank))
+// dynamic ODT enabled, so use rtt_wr (only if the rank being written to has
+// it enabled)
+		if (
+		    (i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt0_rank] !=
+		     fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE)
+		    && (i_dimm == 0)
+		    && (i_rank == ma0odt0_rank)
+		    )
 		{
 		    if (eff_term_wr == 0)
 		    {
-			eff_term_wr = i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt0_rank];
+			eff_term_wr =
+			  i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt0_rank];
 		    }
 		    else
 		    {
-			eff_term_wr = (eff_term_wr * i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt0_rank]) / (eff_term_wr + i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt0_rank]);
+			eff_term_wr =
+			  (eff_term_wr *
+			   i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt0_rank])
+			  /
+			  (eff_term_wr +
+			   i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt0_rank]);
 		    }
 		}
 		// dynamic ODT disabled, so use rtt_nom
-		else if (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)
+		else if (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank] !=
+			 fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)
 		{
 		    if (eff_term_wr == 0)
 		    {
-			eff_term_wr = i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank];
+			eff_term_wr =
+			  i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank];
 		    }
 		    else
 		    {
-			eff_term_wr = (eff_term_wr * i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank]) / (eff_term_wr + i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank]);
+			eff_term_wr =
+			  (eff_term_wr *
+			   i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank])
+			  /
+			  (eff_term_wr +
+			   i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank]);
 		    }
 
 		}
 		FAPI_DBG("[P%d:D%d:R%d] 0ODT0 WR TERMINATION = %4.2f (%d/%d)", i_port, i_dimm, i_rank, eff_term_wr, i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank], i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt0_rank]);
 	    }
+//------------------------------------------------------------------------------
 // 0ODT1
-	    if (((i_dimm_rank_odt_wr[i_port][i_dimm][i_rank] & 0x40) != 0) && ((i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt1_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) || (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)))
+	    if (
+		((i_dimm_rank_odt_wr[i_port][i_dimm][i_rank] & 0x40) != 0)
+		&&
+		((i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt1_rank] !=
+		  fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) ||
+		 (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank] !=
+		  fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE))
+		)
 	    {
-		// dynamic ODT enabled, so use rtt_wr (only if the rank being written to has it enabled)
-		if ((i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt1_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) && (i_dimm == 0) && (i_rank == ma0odt1_rank))
+// dynamic ODT enabled, so use rtt_wr (only if the rank being written to has
+// it enabled)
+		if (
+		    (i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt1_rank] !=
+		     fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE)
+		    && (i_dimm == 0)
+		    && (i_rank == ma0odt1_rank)
+		    )
 		{
 		    if (eff_term_wr == 0)
 		    {
-			eff_term_wr = i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt1_rank];
+			eff_term_wr =
+			  i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt1_rank];
 		    }
 		    else
 		    {
-			eff_term_wr = (eff_term_wr * i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt1_rank]) / (eff_term_wr + i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt1_rank]);
+			eff_term_wr =
+			  (eff_term_wr *
+			   i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt1_rank])
+			  /
+			  (eff_term_wr +
+			   i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt1_rank]);
 		    }
 		}
-		// dynamic ODT disabled, so use rtt_nom
-		else if (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)
+// dynamic ODT disabled, so use rtt_nom
+		else if (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank] !=
+			 fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)
 		{
 		    if (eff_term_wr == 0)
 		    {
-			eff_term_wr = i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank];
+			eff_term_wr =
+			  i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank];
 		    }
 		    else
 		    {
-			eff_term_wr = (eff_term_wr * i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank]) / (eff_term_wr + i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank]);
+			eff_term_wr =
+			  (eff_term_wr *
+			   i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank])
+			  /
+			  (eff_term_wr +
+			   i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank]);
 		    }
 
 		}
 		FAPI_DBG("[P%d:D%d:R%d] 0ODT1 WR TERMINATION = %4.2f (%d/%d)", i_port, i_dimm, i_rank, eff_term_wr, i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank], i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt1_rank]);
 	    }
+//------------------------------------------------------------------------------
 // 1ODT0
-	    if (((i_dimm_rank_odt_wr[i_port][i_dimm][i_rank] & 0x20) != 0) && ((i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt0_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) || (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)))
+	    if (
+		((i_dimm_rank_odt_wr[i_port][i_dimm][i_rank] & 0x20) != 0)
+		&&
+		((i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt0_rank] !=
+		  fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) ||
+		 (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank] !=
+		  fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE))
+		)
 	    {
-		// dynamic ODT enabled, so use rtt_wr (only if the rank being written to has it enabled)
-		if ((i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt0_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) && (i_dimm == 1) && (i_rank == ma1odt0_rank))
+// dynamic ODT enabled, so use rtt_wr (only if the rank being written to has
+// it enabled)
+		if (
+		    (i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt0_rank] !=
+		     fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE)
+		    && (i_dimm == 1)
+		    && (i_rank == ma1odt0_rank)
+		    )
 		{
 		    if (eff_term_wr == 0)
 		    {
-			eff_term_wr = i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt0_rank];
+			eff_term_wr =
+			  i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt0_rank];
 		    }
 		    else
 		    {
-			eff_term_wr = (eff_term_wr * i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt0_rank]) / (eff_term_wr + i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt0_rank]);
+			eff_term_wr =
+			  (eff_term_wr *
+			   i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt0_rank])
+			  /
+			  (eff_term_wr +
+			   i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt0_rank]);
 		    }
 		}
 		// dynamic ODT disabled, so use rtt_nom
-		else if (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)
+		else if (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank] !=
+			 fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)
 		{
 		    if (eff_term_wr == 0)
 		    {
-			eff_term_wr = i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank];
+			eff_term_wr =
+			  i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank];
 		    }
 		    else
 		    {
-			eff_term_wr = (eff_term_wr * i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank]) / (eff_term_wr + i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank]);
+			eff_term_wr =
+			  (eff_term_wr *
+			   i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank])
+			  /
+			  (eff_term_wr +
+			   i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank]);
 		    }
 
 		}
 		FAPI_DBG("[P%d:D%d:R%d] 1ODT0 WR TERMINATION = %4.2f (%d/%d)", i_port, i_dimm, i_rank, eff_term_wr, i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank], i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt0_rank]);
 	    }
+//------------------------------------------------------------------------------
 // 1ODT1
-	    if (((i_dimm_rank_odt_wr[i_port][i_dimm][i_rank] & 0x10) != 0) && ((i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt1_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) || (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)))
+	    if (
+		((i_dimm_rank_odt_wr[i_port][i_dimm][i_rank] & 0x10) != 0)
+		&&
+		((i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt1_rank] !=
+		  fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) ||
+		 (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank] !=
+		  fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE))
+		)
 	    {
-		// dynamic ODT enabled, so use rtt_wr (only if the rank being written to has it enabled)
-		if ((i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt1_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) && (i_dimm == 1) && (i_rank == ma1odt1_rank))
+// dynamic ODT enabled, so use rtt_wr (only if the rank being written to has
+// it enabled)
+		if (
+		    (i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt1_rank] !=
+		     fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE)
+		    && (i_dimm == 1)
+		    && (i_rank == ma1odt1_rank)
+		    )
 		{
 		    if (eff_term_wr == 0)
 		    {
-			eff_term_wr = i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt1_rank];
+			eff_term_wr =
+			  i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt1_rank];
 		    }
 		    else
 		    {
-			eff_term_wr = (eff_term_wr * i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt1_rank]) / (eff_term_wr + i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt1_rank]);
+			eff_term_wr =
+			  (eff_term_wr *
+			   i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt1_rank])
+			  /
+			  (eff_term_wr +
+			   i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt1_rank]);
 		    }
 		}
 		// dynamic ODT disabled, so use rtt_nom
-		else if (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)
+		else if (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank] !=
+			 fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)
 		{
 		    if (eff_term_wr == 0)
 		    {
-			eff_term_wr = i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank];
+			eff_term_wr =
+			  i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank];
 		    }
 		    else
 		    {
-			eff_term_wr = (eff_term_wr * i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank]) / (eff_term_wr + i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank]);
+			eff_term_wr =
+			  (eff_term_wr *
+			   i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank])
+			  /
+			  (eff_term_wr +
+			   i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank]);
 		    }
 
 		}
 		FAPI_DBG("[P%d:D%d:R%d] 1ODT1 WR TERMINATION = %4.2f (%d/%d)", i_port, i_dimm, i_rank, eff_term_wr, i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank], i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt1_rank]);
 	    }
 
+
 // Translate enum value to a resistance value for i_cen_dq_dqs_drv_imp[i_port]
-	    rc = mss_eff_config_thermal_get_cen_drv_value(
-							  i_cen_dq_dqs_drv_imp[i_port],
-							  cen_dq_dqs_drv_imp_value
-							  );
-	    if(rc)
+	    rc = mss_eff_config_thermal_get_cen_drv_value
+	      (
+	       i_cen_dq_dqs_drv_imp[i_port],
+	       cen_dq_dqs_drv_imp_value
+	       );
+	    if (rc)
 	    {
 		FAPI_ERR("Error (0x%x) calling mss_eff_config_thermal_get_cen_drv_value", static_cast<uint32_t>(rc));
 		return rc;
@@ -1101,7 +1801,9 @@ extern "C" {
 
 	    if (eff_term_wr != 0)
 	    {
-		eff_net_term_wr = (float(eff_term_wr * cen_dq_dqs_drv_imp_value) / (eff_term_wr + cen_dq_dqs_drv_imp_value)) + eff_term_wr;
+		eff_net_term_wr =
+		  (float(eff_term_wr * cen_dq_dqs_drv_imp_value) /
+		   (eff_term_wr + cen_dq_dqs_drv_imp_value)) + eff_term_wr;
 		term_odt_mult_wr = 1.25;
 	    }
 	    else
@@ -1110,41 +1812,69 @@ extern "C" {
 		term_odt_mult_wr = 1;
 	    }
 
+//------------------------------------------------------------------------------
 // From Warren:
-// Termination power = (voltage/net termination) * number of nets * (% of traffic on bus*1.25)
-// The net termination is the effective termination that exists between the power rail and ground. So in my calculations this is all the active termination in parallel with the driver impedance + all the active termination in parallel. The value is different for reads and writes. 
+// Termination power = (voltage/net termination) * number of nets *
+// (% of traffic on bus*1.25)
+// The net termination is the effective termination that exists between the
+// power rail and ground. So in my calculations this is all the active
+// termination in parallel with the driver impedance + all the active
+//  termination in parallel. The value is different for reads and writes. 
 // Number of nets includes the strobe nets (2 nets per strobe)
-// % of traffic on bus is the % of the bus used for data traffic split out from reads and writes. The 1.25 factor is due to the odt_en signals being active longer then the data windows.
+// % of traffic on bus is the % of the bus used for data traffic split out from
+// reads and writes. The 1.25 factor is due to the odt_en signals being active
+// longer then the data windows.
 // Value here is in Watts (W)
-	    o_dimm_power_adder_termination = float(i_dimm_voltage) / 1000 * (((float(i_dimm_voltage) / 1000 / eff_net_term_rd) * (number_nets_term_rd) * (float(ACTIVE_DIMM_UTILIZATION) / 100) * (float(DATA_BUS_READ_PERCENT) / 100) * (term_odt_mult_rd)) + ((float(i_dimm_voltage) / 1000 / eff_net_term_wr) * (number_nets_term_wr) * (float(ACTIVE_DIMM_UTILIZATION) / 100) * (float(DATA_BUS_WRITE_PERCENT) / 100) * (term_odt_mult_wr)));
+	    o_dimm_power_adder_termination =
+	      float(i_dimm_voltage) / 1000
+	      *
+	      (
+	       ((float(i_dimm_voltage) / 1000 / eff_net_term_rd) *
+		(number_nets_term_rd) *
+		(float(ACTIVE_DIMM_UTILIZATION) / 100) *
+		(float(DATA_BUS_READ_PERCENT) / 100) * (term_odt_mult_rd))
+	       +
+	       ((float(i_dimm_voltage) / 1000 / eff_net_term_wr) *
+		(number_nets_term_wr) *
+		(float(ACTIVE_DIMM_UTILIZATION) / 100) *
+		(float(DATA_BUS_WRITE_PERCENT) / 100) * (term_odt_mult_wr))
+	       );
 	    FAPI_DBG("%s TERM:[P%d:D%d:R%d] CEN[DRV=%d RCV=%d] DRAM[DRV=%d ODT_RD=%4.2f ODT_WR=%4.2f]", i_nom_or_wc_term, i_port, i_dimm, i_rank, cen_dq_dqs_drv_imp_value, i_cen_dq_dqs_rcv_imp[i_port], i_dimm_dram_ron[i_port][i_dimm], eff_term_rd, eff_term_wr);
 	    FAPI_DBG("%s TERM POWER:[P%d:D%d:R%d] RD[Nets=%d EffTerm=%3.2f ODTMult=%1.2f] WR[Nets=%d EffTerm=%3.2f ODTMult=%1.2f] TermPower(%d%%)=%2.2f W", i_nom_or_wc_term, i_port, i_dimm, i_rank, number_nets_term_rd, eff_net_term_rd, term_odt_mult_rd, number_nets_term_wr, eff_net_term_wr, term_odt_mult_wr, ACTIVE_DIMM_UTILIZATION, o_dimm_power_adder_termination);
 	}	
 
+	FAPI_IMP("*** %s COMPLETE ***", procedure_name);
 	return rc;
     }
 
 //------------------------------------------------------------------------------
-// @brief mss_eff_config_thermal_get_wc_term(): This function finds the worst case termination settings possible for a given set
-//           of termination settings
+// @brief mss_eff_config_thermal_get_wc_term(): This function finds the worst
+// case termination settings possible for a given set of termination settings
 //
-// @param    const fapi::Target &i_target_mba:  MBA Target
-// @param    uint8_t i_port:  MBA port being worked on
-// @param    uint8_t &o_cen_dq_dqs_rcv_imp_wc:  Worst Case Centaur DQ/DQS receiver impedance (output)
-// @param    uint8_t &o_cen_dq_dqs_drv_imp_wc:  Worst Case Centaur DQ/DQS driver impedance (output)
+// @param[in]	const fapi::Target &i_target_mba:  MBA Target
+// @param[in]   uint8_t i_port:  MBA port being worked on
+// @param[out]  uint8_t &o_cen_dq_dqs_rcv_imp_wc:  Worst Case Centaur DQ/DQS
+//              receiver impedance (output)
+// @param[out]  uint8_t &o_cen_dq_dqs_drv_imp_wc:  Worst Case Centaur DQ/DQS 
+//              driver impedance (output)
 //
 // @return fapi::ReturnCode
 //------------------------------------------------------------------------------
 
-    fapi::ReturnCode mss_eff_config_thermal_get_wc_term(
-							const fapi::Target &i_target_mba,
-							uint8_t i_port,
-							uint8_t &o_cen_dq_dqs_rcv_imp_wc,
-							uint8_t &o_cen_dq_dqs_drv_imp_wc
-							)
+    fapi::ReturnCode mss_eff_config_thermal_get_wc_term
+      (
+       const fapi::Target &i_target_mba,
+       uint8_t i_port,
+       uint8_t &o_cen_dq_dqs_rcv_imp_wc,
+       uint8_t &o_cen_dq_dqs_drv_imp_wc
+       )
     {
 	fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
 
+	char procedure_name[32];
+	sprintf(procedure_name, "mss_eff_config_thermal_get_wc_term");
+	FAPI_IMP("*** Running %s ***", procedure_name);
+
 	uint8_t l_cen_dq_dqs_rcv_imp[NUM_PORTS];
 	uint8_t l_cen_dq_dqs_drv_imp[NUM_PORTS];
 	uint32_t l_cen_dq_dqs_rcv_imp_schmoo[NUM_PORTS];
@@ -1152,8 +1882,10 @@ extern "C" {
 	uint32_t l_loop;
 	uint32_t l_schmoo_mask;
 
-// This lists out the number and enum values for the centaur dq/dqs receiver and driver impedance.  Have the list go from strongest to weakest termination.
-// If the size changes at all, then updates are needed below to get the correct mask
+// This lists out the number and enum values for the centaur dq/dqs receiver and
+// driver impedance.  Have the list go from strongest to weakest termination.
+// If the size changes at all, then updates are needed below to get the correct
+// mask
 
 	const uint8_t MAX_CEN_RCV_IMP = 10;
 	uint8_t cen_rcv_imp_array[] = {
@@ -1189,21 +1921,39 @@ extern "C" {
 	    fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE120
 	};
 
+
 // Get attributes for nominal settings and possible settings to choose from
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, l_cen_dq_dqs_rcv_imp);
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_cen_dq_dqs_drv_imp);
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO, &i_target_mba, l_cen_dq_dqs_rcv_imp_schmoo);
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO, &i_target_mba, l_cen_dq_dqs_drv_imp_schmoo);
-	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS,
+			   &i_target_mba, l_cen_dq_dqs_rcv_imp);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_CEN_RCV_IMP_DQ_DQS");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS,
+			   &i_target_mba, l_cen_dq_dqs_drv_imp);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_CEN_DRV_IMP_DQ_DQS");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO,
+			   &i_target_mba, l_cen_dq_dqs_rcv_imp_schmoo);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO,
+			   &i_target_mba, l_cen_dq_dqs_drv_imp_schmoo);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO");
+	    return rc;
+	}
 
 // initialize to default values in case below does not find a match
 	o_cen_dq_dqs_rcv_imp_wc = l_cen_dq_dqs_rcv_imp[i_port];
 	o_cen_dq_dqs_drv_imp_wc = l_cen_dq_dqs_drv_imp[i_port];
 
-// find strongest termination setting that could be used, if none found, then use nominal
+// find strongest termination setting that could be used, if none found, then
+// use nominal
 	l_schmoo_mask = 0x00000000;
 	for (l_loop=0; l_loop < MAX_CEN_RCV_IMP; l_loop++)
 	{
@@ -1312,27 +2062,35 @@ extern "C" {
 	    }
 	}
 
+	FAPI_IMP("*** %s COMPLETE ***", procedure_name);
 	return rc;
     }
 
 
 //------------------------------------------------------------------------------
-// @brief mss_eff_config_thermal_get_cen_drv_value(): This function will translate
-//           the centaur driver impedance enum value to a termination resistance
+// @brief mss_eff_config_thermal_get_cen_drv_value(): This function will
+// translate the centaur driver impedance enum value to a termination resistance
 //
-// @param    uint8_t &i_cen_dq_dqs_drv_imp:  Centaur DQ/DQS driver impedance enum setting (input)
-// @param    uint8_t &o_cen_dq_dqs_drv_imp:  Centaur DQ/DQS driver impedance value (output)
+// @param[in]	uint8_t &i_cen_dq_dqs_drv_imp:  Centaur DQ/DQS driver impedance
+//           enum setting (input)
+// @param[out]  uint8_t &o_cen_dq_dqs_drv_imp:  Centaur DQ/DQS driver impedance
+//           value (output)
 //
 // @return fapi::ReturnCode
 //------------------------------------------------------------------------------
 
-    fapi::ReturnCode mss_eff_config_thermal_get_cen_drv_value(
-							      uint8_t i_cen_dq_dqs_drv_imp,
-							      uint8_t &o_cen_dq_dqs_drv_imp
-							      )
+    fapi::ReturnCode mss_eff_config_thermal_get_cen_drv_value
+      (
+       uint8_t i_cen_dq_dqs_drv_imp,
+       uint8_t &o_cen_dq_dqs_drv_imp
+       )
     {
 	fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
 
+	char procedure_name[32];
+	sprintf(procedure_name, "mss_eff_config_thermal_get_cen_drv_value");
+	FAPI_IMP("*** Running %s ***", procedure_name);
+
 	switch (i_cen_dq_dqs_drv_imp)
 	{
 	    case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM24_FFE0:
@@ -1387,6 +2145,7 @@ extern "C" {
 		o_cen_dq_dqs_drv_imp = 24;
 	}
 
+	FAPI_IMP("*** %s COMPLETE ***", procedure_name);
 	return rc;
     }
 
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.H
index f4d7c7861..5c80a9451 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.H
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,8 +20,9 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_thermal.H,v 1.4 2012/10/15 13:05:10 pardeik Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_thermal.H,v $
+// $Id: mss_eff_config_thermal.H,v 1.5 2012/12/12 20:10:37 pardeik Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
+//          centaur/working/procedures/ipl/fapi/mss_eff_config_thermal.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -42,6 +43,8 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//   1.5   | pardeik  |03-DEC-12| update lines to have a max width of 80 chars
+//         |          |         | removed variable names in typedef
 //   1.4   | pardeik  |11-OCT-12| change i_target to i_target_mba
 //   1.3   | pardeik  |03-APR-12| use mba target instead of mbs
 //   1.2   | pardeik  |26-MAR-12| Removed structure (going into .C file)
@@ -49,27 +52,29 @@
 //   1.1   | asaetow  |03-NOV-11| First Draft.
 
 
-
 #ifndef MSS_EFF_CONFIG_THERMAL_H_
 #define MSS_EFF_CONFIG_THERMAL_H_
 
-//----------------------------------------------------------------------
+//------------------------------------------------------------------------------
 //  Includes
-//----------------------------------------------------------------------
+//------------------------------------------------------------------------------
 #include <fapi.H>
 
-
-typedef fapi::ReturnCode (*mss_eff_config_thermal_FP_t)(const fapi::Target & i_target_mba);
+typedef fapi::ReturnCode (*mss_eff_config_thermal_FP_t)
+(
+ const fapi::Target &
+ );
 
 
 extern "C" {
-/**
- * @brief mss_eff_config_thermal procedure. Sets up dimm power curve attributes and dimm and channel throttle attributes
- *
- * @param[in]  i_target_mba  Reference to centaur mba target
- *
- * @return ReturnCode
- */
+//------------------------------------------------------------------------------
+// @brief mss_eff_config_thermal procedure. Sets up dimm power curve attributes
+//  and dimm and channel throttle attributes
+//
+// @param[in]  i_target_mba  Reference to centaur mba target
+//
+// @return ReturnCode
+//------------------------------------------------------------------------------
 
     fapi::ReturnCode mss_eff_config_thermal(const fapi::Target & i_target_mba);
 
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.C
index b8c1211dd..5fc5e4d70 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,8 +20,9 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_throttle_to_power.C,v 1.8 2012/10/31 13:40:27 pardeik Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_throttle_to_power.C,v $
+// $Id: mss_throttle_to_power.C,v 1.9 2012/12/12 20:10:47 pardeik Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
+//          centaur/working/procedures/ipl/fapi/mss_throttle_to_power.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -36,7 +37,8 @@
 // applicable CQ component memory_screen
 //
 // DESCRIPTION:
-// The purpose of this procedure is to set the power attributes for each dimm and channel pair
+// The purpose of this procedure is to set the power attributes for each dimm
+// and channel pair
 //
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
@@ -45,16 +47,28 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
-//   1.8   | pardeik  |25-OCT-12| updated FAPI_ERR sections, added CQ component comment line
-//   1.7   | pardeik  |19-OCT-12| use ATTR_MSS_CHANNEL_PAIR_MAXPOWER instead of ATTR_MSS_CHANNEL_MAXPOWER
-//         | pardeik  |19-OCT-12| multiple throttle N values by 4 to get dram utilization
-//   1.6   | pardeik  |11-OCT-12| updated to use new throttle attributes, made function mss_throttle_to_power_calc
+//   1.9   | pardeik  |04-DEC-12| update lines to have a max width of 80 chars
+//         |          |         | added FAPI_ERR before return code lines
+//         |          |         | made trace statements for procedures FAPI_IMP
+//   1.8   | pardeik  |25-OCT-12| updated FAPI_ERR sections, added CQ component
+//         |          |         | comment line
+//   1.7   | pardeik  |19-OCT-12| use ATTR_MSS_CHANNEL_PAIR_MAXPOWER instead of
+//         |          |         | ATTR_MSS_CHANNEL_MAXPOWER
+//         | pardeik  |19-OCT-12| multiple throttle N values by 4 to get dram
+//         |          |         | utilization
+//   1.6   | pardeik  |11-OCT-12| updated to use new throttle attributes, made
+//         |          |         | function mss_throttle_to_power_calc
 //   1.5   | pardeik  |10-APR-12| power calculation updates and fixes
 //   1.5   | pardeik  |10-APR-12| power calculation updates and fixes
-//   1.4   | pardeik  |04-APR-12| moved cdimm power calculation to end of section instead of having it in multiple places
-//   1.3   | pardeik  |04-APR-12| use else if instead of if after checking throttle denominator to zero
-//   1.2   | pardeik  |03-APR-12| use mba target intead of mbs, added cdimm power calculation for half of cdimm
-//   1.1   | pardeik  |01-APR-11| Updated to use attributes and fapi functions to loop through ports/dimms
+//   1.4   | pardeik  |04-APR-12| moved cdimm power calculation to end of
+//         |          |         | section instead of having it in multiple
+//         |          |         | places
+//   1.3   | pardeik  |04-APR-12| use else if instead of if after checking
+//         |          |         | throttle denominator to zero
+//   1.2   | pardeik  |03-APR-12| use mba target intead of mbs, added cdimm
+//         |          |         | power calculation for half of cdimm
+//   1.1   | pardeik  |01-APR-11| Updated to use attributes and fapi functions
+//         |          |         | to loop through ports/dimms
 //         | pardeik  |01-DEC-11| First Draft.
 
 
@@ -63,9 +77,9 @@
 //------------------------------------------------------------------------------
 #include <mss_throttle_to_power.H>
 
-//----------------------------------------------------------------------
+//------------------------------------------------------------------------------
 //  Includes
-//----------------------------------------------------------------------
+//------------------------------------------------------------------------------
 #include <fapi.H>
 
 
@@ -79,19 +93,22 @@ extern "C" {
 //------------------------------------------------------------------------------
     fapi::ReturnCode mss_throttle_to_power(const fapi::Target & i_target_mba);
 
-    fapi::ReturnCode mss_throttle_to_power_calc(
-						const fapi::Target &i_target_mba,
-						uint32_t i_throttle_n_per_mba,
-						uint32_t i_throttle_n_per_chip,
-						uint32_t i_throttle_d,
-						float &channel_pair_power
-						);
+    fapi::ReturnCode mss_throttle_to_power_calc
+      (
+       const fapi::Target &i_target_mba,
+       uint32_t i_throttle_n_per_mba,
+       uint32_t i_throttle_n_per_chip,
+       uint32_t i_throttle_d,
+       float &channel_pair_power
+       );
 
 
 //------------------------------------------------------------------------------
-// @brief mss_throttle_to_power(): This function will get the throttle attributes and call another function to determine the dimm and channel pair power based on those throttles
+// @brief mss_throttle_to_power(): This function will get the throttle
+// attributes and call another function to determine the dimm and channel pair
+// power based on those throttles
 //
-// @param    const fapi::Target &i_target_mba:  MBA Target
+// @param[in]	const fapi::Target &i_target_mba:  MBA Target
 //
 // @return fapi::ReturnCode
 //------------------------------------------------------------------------------
@@ -102,7 +119,7 @@ extern "C" {
 
 	char procedure_name[32];
 	sprintf(procedure_name, "mss_throttle_to_power");
-	FAPI_INF("*** Running %s ***", procedure_name);
+	FAPI_IMP("*** Running %s ***", procedure_name);
 
 	uint32_t throttle_n_per_mba;
 	uint32_t throttle_n_per_chip;
@@ -110,12 +127,24 @@ extern "C" {
 	float channel_pair_power;
 
 // Get input attributes
-	rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA, &i_target_mba, throttle_n_per_mba);
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP, &i_target_mba, throttle_n_per_chip);
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_DENOMINATOR, &i_target_mba, throttle_d);
-	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA,
+			   &i_target_mba, throttle_n_per_mba);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP,
+			   &i_target_mba, throttle_n_per_chip);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_DENOMINATOR,
+			   &i_target_mba, throttle_d);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_MSS_MEM_THROTTLE_DENOMINATOR");
+	    return rc;
+	}
 
 // Call function mss_throttle_to_power_calc
 	rc = mss_throttle_to_power_calc(
@@ -125,13 +154,13 @@ extern "C" {
 					throttle_d,
 					channel_pair_power
 					);
-	if(rc)
+	if (rc)
 	{
 	    FAPI_ERR("Error (0x%x) calling mss_throttle_to_power_calc", static_cast<uint32_t>(rc));
 	    return rc;
 	}
 
-	FAPI_INF("*** %s COMPLETE ***", procedure_name);
+	FAPI_IMP("*** %s COMPLETE ***", procedure_name);
 	return rc;
 
     }
@@ -139,31 +168,41 @@ extern "C" {
 
 
 //------------------------------------------------------------------------------
-// @brief mss_throttle_to_power_calc(): This function will calculate the dimm and channel pair power and update attributes with the power values
+// @brief mss_throttle_to_power_calc(): This function will calculate the dimm
+// and channel pair power and update attributes with the power values
 //
-// @param    const fapi::Target &i_target_mba:  MBA Target
-// @param    uint32_t i_throttle_n_per_mba:  Throttle value for cfg_nm_n_per_mba
-// @param    uint32_t i_throttle_n_per_chip:  Throttle value for cfg_nm_n_per_chip
-// @param    uint32_t i_throttle_d:  Throttle value for cfg_nm_m
-// @param    float &o_channel_pair_power:  channel pair power at these throttle settings
+// @param[in]   const fapi::Target &i_target_mba:  MBA Target
+// @param[in]   uint32_t i_throttle_n_per_mba:  Throttle value for
+//              cfg_nm_n_per_mba
+// @param[in]   uint32_t i_throttle_n_per_chip:  Throttle value for
+//              cfg_nm_n_per_chip
+// @param[in]	uint32_t i_throttle_d:  Throttle value for cfg_nm_m
+// @param[out]  float &o_channel_pair_power:  channel pair power at these
+//              throttle settings
 //
 // @return fapi::ReturnCode
 //------------------------------------------------------------------------------
 
-    fapi::ReturnCode mss_throttle_to_power_calc(
-						const fapi::Target &i_target_mba,
-						uint32_t i_throttle_n_per_mba,
-						uint32_t i_throttle_n_per_chip,
-						uint32_t i_throttle_d,
-						float &o_channel_pair_power
-						)
+    fapi::ReturnCode mss_throttle_to_power_calc
+      (
+       const fapi::Target &i_target_mba,
+       uint32_t i_throttle_n_per_mba,
+       uint32_t i_throttle_n_per_chip,
+       uint32_t i_throttle_d,
+       float &o_channel_pair_power
+       )
     {
 	fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
 
-	const uint8_t MAX_NUM_PORTS = 2;			// number of ports per MBA
-	const uint8_t MAX_NUM_DIMMS = 2;			// number of dimms per MBA port
+	char procedure_name[32];
+	sprintf(procedure_name, "mss_throttle_to_power_calc");
+	FAPI_IMP("*** Running %s ***", procedure_name);
+
+	const uint8_t MAX_NUM_PORTS = 2;
+	const uint8_t MAX_NUM_DIMMS = 2;
+// Maximum theoretical data bus utilization (percent of max) (for ceiling)
 // If this is changed, also change mss_bulk_pwr_throttles MAX_UTIL
-	const float MAX_UTIL = 75;				// Maximum theoretical data bus utilization (percent of max) (for ceiling)
+	const float MAX_UTIL = 75;				
 
 	uint32_t l_power_slope_array[MAX_NUM_PORTS][MAX_NUM_DIMMS];
 	uint32_t l_power_int_array[MAX_NUM_PORTS][MAX_NUM_DIMMS];
@@ -179,16 +218,33 @@ extern "C" {
 	uint8_t l_num_dimms_on_port;
 
 // get input attributes
-	rc = FAPI_ATTR_GET(ATTR_MSS_POWER_SLOPE, &i_target_mba, l_power_slope_array);
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_MSS_POWER_INT, &i_target_mba, l_power_int_array);
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_dimm_ranks_array);
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, l_num_dimms_on_port);
-	if(rc) return rc;
-
-// add up the power from all dimms for this MBA (across both channels) using the throttle values
+	rc = FAPI_ATTR_GET(ATTR_MSS_POWER_SLOPE,
+			   &i_target_mba, l_power_slope_array);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_MSS_POWER_SLOPE");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_MSS_POWER_INT,
+			   &i_target_mba, l_power_int_array);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_MSS_POWER_INT");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM,
+			   &i_target_mba, l_dimm_ranks_array);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_NUM_RANKS_PER_DIMM");
+	    return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT,
+			   &i_target_mba, l_num_dimms_on_port);
+	if (rc) {
+	    FAPI_ERR("Error getting attribute ATTR_EFF_NUM_DROPS_PER_PORT");
+	    return rc;
+	}
+
+// add up the power from all dimms for this MBA (across both channels) using the
+// throttle values
 	o_channel_pair_power = 0;
 	l_channel_pair_power_integer = 0;
 	for (l_port = 0; l_port < MAX_NUM_PORTS; l_port++)
@@ -204,73 +260,114 @@ extern "C" {
 // See if there are any ranks present on the dimm (configured or deconfigured)
 		if (l_dimm_ranks_array[l_port][l_dimm] > 0)
 		{
-// N/M throttling has the dimm0 and dimm1 throttles the same for DIMM level throttling, which we plan to use
-// MBA or chip level throttling could limit the commands to a dimm (used along with the dimm level throttling)
+// N/M throttling has the dimm0 and dimm1 throttles the same for DIMM level
+// throttling, which we plan to use
+// MBA or chip level throttling could limit the commands to a dimm (used along
+// with the dimm level throttling)
 // If MBA/chip throttle is less than dimm throttle, then use MBA/chip throttle
-// If MBA/chip throttle is greater than dimm throttle, then use the dimm throttle
+// If MBA/chip throttle is greater than dimm throttle, then use the dimm
+// throttle
 // If either of these are above the MAX_UTIL, then use MAX_UTIL
 // Get power from each dimm here
-// Note that the MAX_UTIL effectively is the percent of maximum bandwidth for that dimm
+// Note that the MAX_UTIL effectively is the percent of maximum bandwidth for
+// that dimm
 
 		    if (i_throttle_d == 0)
 		    {
-			    // throttle denominator is zero (N/M throttling disabled), set dimm power to the maximum
+// throttle denominator is zero (N/M throttling disabled), set dimm power to the
+// maximum
 			FAPI_DBG("N/M Throttling is disabled (M=0).  Use Max DIMM Power");
-			l_dimm_power_array[l_port][l_dimm] = (l_power_slope_array[l_port][l_dimm] * ((float)MAX_UTIL / 100) + l_power_int_array[l_port][l_dimm]);
+			l_dimm_power_array[l_port][l_dimm] =
+			  (l_power_slope_array[l_port][l_dimm] *
+			   ((float)MAX_UTIL / 100) +
+			   l_power_int_array[l_port][l_dimm]);
 			l_utilization = (float)MAX_UTIL;
 		    }
-		    else if ((((float)i_throttle_n_per_mba * 100 * 4) / i_throttle_d * l_num_dimms_on_port) > (((float)i_throttle_n_per_chip * 100 * 4) / i_throttle_d))
+		    else if (
+			     (
+			      ((float)i_throttle_n_per_mba * 100 * 4) /
+			      i_throttle_d *
+			      l_num_dimms_on_port
+			      )
+			     >
+			     (((float)i_throttle_n_per_chip * 100 * 4) /
+			      i_throttle_d)
+			     )
 		    {
-			// limited by the mba/chip throttles (ie.  cfg_nm_n_per_chip)
-			if ((((float)i_throttle_n_per_chip * 100 * 4) / i_throttle_d) > MAX_UTIL)
+// limited by the mba/chip throttles (ie.  cfg_nm_n_per_chip)
+			if ((((float)i_throttle_n_per_chip * 100 * 4) /
+			     i_throttle_d) > MAX_UTIL)
 			{
-			    // limited by the maximum utilization
-			    l_dimm_power_array[l_port][l_dimm] = (l_power_slope_array[l_port][l_dimm] * ((float)MAX_UTIL / 100) + l_power_int_array[l_port][l_dimm]);
+// limited by the maximum utilization
+			    l_dimm_power_array[l_port][l_dimm] =
+			      (l_power_slope_array[l_port][l_dimm] *
+			       ((float)MAX_UTIL / 100) +
+			       l_power_int_array[l_port][l_dimm]);
 			    l_utilization = (float)MAX_UTIL;
 			}
 			else
 			{
-			    // limited by the per chip throttles
-			    l_dimm_power_array[l_port][l_dimm] = (l_power_slope_array[l_port][l_dimm] * (((float)i_throttle_n_per_chip * 4) / i_throttle_d) + l_power_int_array[l_port][l_dimm]);
-			    l_utilization = (((float)i_throttle_n_per_chip * 100 * 4) / i_throttle_d);
+// limited by the per chip throttles
+			    l_dimm_power_array[l_port][l_dimm] =
+			      (l_power_slope_array[l_port][l_dimm] *
+			       (((float)i_throttle_n_per_chip * 4)
+				/ i_throttle_d) +
+			       l_power_int_array[l_port][l_dimm]);
+			    l_utilization = (((float)i_throttle_n_per_chip *
+					      100 * 4) / i_throttle_d);
 			}
 		    }
 		    else
 		    {
-			// limited by the per mba throttles (ie.  cfg_nm_n_per_mba)
-			if ((((float)i_throttle_n_per_mba * 100 * 4) / i_throttle_d * l_num_dimms_on_port) > MAX_UTIL)
+// limited by the per mba throttles (ie.  cfg_nm_n_per_mba)
+			if ((((float)i_throttle_n_per_mba * 100 * 4) /
+			     i_throttle_d * l_num_dimms_on_port) > MAX_UTIL)
 			{
-			    // limited by the maximum utilization
-			    l_dimm_power_array[l_port][l_dimm] = (l_power_slope_array[l_port][l_dimm] * ((float)MAX_UTIL / 100) + l_power_int_array[l_port][l_dimm]);
+// limited by the maximum utilization
+			    l_dimm_power_array[l_port][l_dimm] =
+			      (l_power_slope_array[l_port][l_dimm] *
+			       ((float)MAX_UTIL / 100) +
+			       l_power_int_array[l_port][l_dimm]);
 			    l_utilization = (float)MAX_UTIL;
 			}
 			else
 			{
-			    // limited by the per mba throttles
-			    // multiply by number of dimms on port since other dimm has same throttle value
-			    l_dimm_power_array[l_port][l_dimm] = (l_power_slope_array[l_port][l_dimm] * (((float)i_throttle_n_per_mba * 4) / i_throttle_d * l_num_dimms_on_port) + l_power_int_array[l_port][l_dimm]);
-			    l_utilization = (((float)i_throttle_n_per_mba * 100 * 4) / i_throttle_d * l_num_dimms_on_port);
+// limited by the per mba throttles
+// multiply by number of dimms on port since other dimm has same throttle value
+			    l_dimm_power_array[l_port][l_dimm] =
+			      (l_power_slope_array[l_port][l_dimm] *
+			       (((float)i_throttle_n_per_mba * 4) /
+				i_throttle_d * l_num_dimms_on_port) +
+			       l_power_int_array[l_port][l_dimm]);
+			    l_utilization =
+			      (((float)i_throttle_n_per_mba * 100 * 4) /
+			       i_throttle_d * l_num_dimms_on_port);
 			}
 		    }
 		}
 // Get dimm power in integer format (add on 1 since value will get truncated)
 		if (l_dimm_power_array[l_port][l_dimm] > 0)
 		{
-		    l_dimm_power_array_integer[l_port][l_dimm] = (int)l_dimm_power_array[l_port][l_dimm] + 1;
+		    l_dimm_power_array_integer[l_port][l_dimm] =
+		      (int)l_dimm_power_array[l_port][l_dimm] + 1;
 		}
 // calculate channel power by adding up the power of each dimm
-		l_channel_power_array[l_port] = l_channel_power_array[l_port] + l_dimm_power_array[l_port][l_dimm];
+		l_channel_power_array[l_port] = l_channel_power_array[l_port] +
+		  l_dimm_power_array[l_port][l_dimm];
 		FAPI_DBG("[P%d:D%d][CH Util %4.2f/%4.2f][Slope:Int %d:%d][Power %4.2f cW]", l_port, l_dimm, l_utilization, MAX_UTIL, l_power_slope_array[l_port][l_dimm], l_power_int_array[l_port][l_dimm], l_dimm_power_array[l_port][l_dimm]);
 	    }
 	    FAPI_DBG("[P%d][Power %4.2f cW]", l_port, l_channel_power_array[l_port]);
 	}
-// get the channel pair power for this MBA (add on 1 since value will get truncated)
+// get the channel pair power for this MBA (add on 1 since value will get
+// truncated)
 	for (l_port = 0; l_port < MAX_NUM_PORTS; l_port++)
 	{
-	    o_channel_pair_power = o_channel_pair_power + l_channel_power_array[l_port];
+	    o_channel_pair_power = o_channel_pair_power +
+	      l_channel_power_array[l_port];
 	    if (l_channel_power_array_integer[l_port] > 0)
 	    {
-		l_channel_power_array_integer[l_port] = (int)l_channel_power_array[l_port] + 1;
+		l_channel_power_array_integer[l_port] =
+		  (int)l_channel_power_array[l_port] + 1;
 	    }
 	}
 	FAPI_DBG("Channel Pair Power %4.2f cW]", o_channel_pair_power);
@@ -279,13 +376,22 @@ extern "C" {
 	{
 	    l_channel_pair_power_integer = (int)o_channel_pair_power + 1;
 	}
-
+//------------------------------------------------------------------------------
 // Update output attributes
-	rc = FAPI_ATTR_SET(ATTR_MSS_DIMM_MAXPOWER, &i_target_mba, l_dimm_power_array_integer);
-	if(rc) return rc;
-	rc = FAPI_ATTR_SET(ATTR_MSS_CHANNEL_PAIR_MAXPOWER, &i_target_mba, l_channel_pair_power_integer);
-	if(rc) return rc;
+	rc = FAPI_ATTR_SET(ATTR_MSS_DIMM_MAXPOWER,
+			   &i_target_mba, l_dimm_power_array_integer);
+	if (rc) {
+	    FAPI_ERR("Error writing attribute ATTR_MSS_DIMM_MAXPOWER");
+	    return rc;
+	}
+	rc = FAPI_ATTR_SET(ATTR_MSS_CHANNEL_PAIR_MAXPOWER,
+			   &i_target_mba, l_channel_pair_power_integer);
+	if (rc) {
+	    FAPI_ERR("Error writing attribute ATTR_MSS_CHANNEL_PAIR_MAXPOWER");
+	    return rc;
+	}
 
+	FAPI_IMP("*** %s COMPLETE ***", procedure_name);
 	return rc;
     }
 
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.H
index ee9398e70..a46512dc7 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.H
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,8 +20,9 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_throttle_to_power.H,v 1.3 2012/10/15 13:05:23 pardeik Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_throttle_to_power.H,v $
+// $Id: mss_throttle_to_power.H,v 1.4 2012/12/12 20:10:50 pardeik Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
+//          centaur/working/procedures/ipl/fapi/mss_throttle_to_power.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -42,6 +43,8 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//   1.4   | pardeik  |04-DEC-12| update lines to have a max width of 80 chars
+//         |          |         | removed variable names in typedef's
 //   1.3   | pardeik  |11-OCT-12| change i_target to i_target_mba
 //   1.2   | pardeik  |03-APR-12| use mba target instead of mbs
 //   1.1   | pardeik  |01-DEC-11| First Draft.
@@ -51,28 +54,31 @@
 #ifndef MSS_THROTTLE_TO_POWER_H_
 #define MSS_THROTTLE_TO_POWER_H_
 
-//----------------------------------------------------------------------
+//------------------------------------------------------------------------------
 //  Includes
-//----------------------------------------------------------------------
+//------------------------------------------------------------------------------
 #include <fapi.H>
 
-typedef fapi::ReturnCode (*mss_throttle_to_power_FP_t)(const fapi::Target & i_target_mba);
+typedef fapi::ReturnCode (*mss_throttle_to_power_FP_t)(const fapi::Target &);
 
-typedef fapi::ReturnCode (*mss_throttle_to_power_calc_FP_t)(
-						const fapi::Target &i_target_mba,
-						uint32_t i_throttle_n_per_mba,
-						uint32_t i_throttle_n_per_chip,
-						uint32_t i_throttle_d,
-						float &channel_pair_power
-						);
+typedef fapi::ReturnCode (*mss_throttle_to_power_calc_FP_t)
+(
+ const fapi::Target &,
+ uint32_t,
+ uint32_t,
+ uint32_t,
+ float &
+ );
 
 extern "C"
 {
 
 //------------------------------------------------------------------------------
-// @brief mss_throttle_to_power(): This function will get the throttle attributes and call another function to determine the dimm and channel pair power based on those throttles
+// @brief mss_throttle_to_power(): This function will get the throttle
+// attributes and call another function to determine the dimm and channel pair
+// power based on those throttles
 //
-// @param    const fapi::Target &i_target_mba:  MBA Target
+// @param[in]	const fapi::Target &i_target_mba:  MBA Target
 //
 // @return fapi::ReturnCode
 //------------------------------------------------------------------------------
@@ -80,24 +86,29 @@ extern "C"
     fapi::ReturnCode mss_throttle_to_power(const fapi::Target & i_target_mba);
 
 //------------------------------------------------------------------------------
-// @brief mss_throttle_to_power_calc(): This function will calculate the dimm and channel pair power and update attributes with the power values
+// @brief mss_throttle_to_power_calc(): This function will calculate the dimm
+// and channel pair power and update attributes with the power values
 //
-// @param    const fapi::Target &i_target_mba:  MBA Target
-// @param    uint32_t i_throttle_n_per_mba:  Throttle value for cfg_nm_n_per_mba
-// @param    uint32_t i_throttle_n_per_chip:  Throttle value for cfg_nm_n_per_chip
-// @param    uint32_t i_throttle_d:  Throttle value for cfg_nm_m
-// @param    float &o_channel_pair_power:  channel pair power at these throttle settings
+// @param[in]   const fapi::Target &i_target_mba:  MBA Target
+// @param[in]   uint32_t i_throttle_n_per_mba:  Throttle value for
+//              cfg_nm_n_per_mba
+// @param[in]   uint32_t i_throttle_n_per_chip:  Throttle value for
+//              cfg_nm_n_per_chip
+// @param[in]   uint32_t i_throttle_d:  Throttle value for cfg_nm_m
+// @param[out]	float &o_channel_pair_power:  channel pair power at these
+//              throttle settings
 //
 // @return fapi::ReturnCode
 //------------------------------------------------------------------------------
 
-    fapi::ReturnCode mss_throttle_to_power_calc(
-						const fapi::Target &i_target_mba,
-						uint32_t i_throttle_n_per_mba,
-						uint32_t i_throttle_n_per_chip,
-						uint32_t i_throttle_d,
-						float &channel_pair_power
-						);
+    fapi::ReturnCode mss_throttle_to_power_calc
+      (
+       const fapi::Target &i_target_mba,
+       uint32_t i_throttle_n_per_mba,
+       uint32_t i_throttle_n_per_chip,
+       uint32_t i_throttle_d,
+       float &channel_pair_power
+       );
 
 } // extern "C"