diff options
| author | Josh Rispoli <jprispol@us.ibm.com> | 2014-07-09 14:53:58 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-07-23 14:41:08 -0500 |
| commit | 3b7ee0582ef65751e7674e7fe5ba64ed7bebd334 (patch) | |
| tree | 73ab7006e85055b86d5559239976e4c92709d8e6 /src/usr/hwpf/hwp | |
| parent | 1a4fc108fb5ba46aa8ba4f8da37c842c352d0598 (diff) | |
| download | talos-hostboot-3b7ee0582ef65751e7674e7fe5ba64ed7bebd334.tar.gz talos-hostboot-3b7ee0582ef65751e7674e7fe5ba64ed7bebd334.zip | |
SW265488: enable channel checkstop for MCIFIR[40]: channel timeout error
Change-Id: I718807da7a4a38b135126015cdfd1843afd661c5
CQ:SW265488
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/12061
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: MATTHEW A. PLOETZ <maploetz@us.ibm.com>
Tested-by: MATTHEW A. PLOETZ <maploetz@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/12062
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp')
| -rw-r--r-- | src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile index 35565b0c1..40ad488e2 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile @@ -1,9 +1,11 @@ -#-- $Id: p8.mcs.scom.initfile,v 1.13 2014/05/21 19:17:17 baysah Exp $ +#-- $Id: p8.mcs.scom.initfile,v 1.14 2014/06/12 22:59:56 baysah Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- #-- | | | +#-- 1.14|baysah |06/12/14|- SW265488 : enable channel checkstop for MCIFIR[40]: channel timeout error +#-- | | | #-- 1.13|baysah |05/20/14|- Added Best MCS Spec filter setting to MODE2 reg (2011809 16 20 9007F) for power and perf improvement #-- | | | #-- 1.12|baysah |01/08/14|- Moved ECC bypass qualifier from MCMODE1(63) TO MCMODE1(62), bit 63 is perfmon. @@ -61,7 +63,7 @@ define ecc_bypass_disable = ((TGT1.ATTR_CHIP_EC_FEATURE_MCS_ECC_BYPASS_DISABLE ! 28:31, 0x0 , any ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_HTM_OPS 32:35, 0x0 , any ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_HA_ASSIST 36 , 0b1 , any ; # MCMODE0Q_MCFGRP_19_IS_HO_BIT - 37 , 0b0 , any ; # MCMODE0Q_CL_CHANNEL_TIMEOUT_FORCES_CHANNEL_FAIL + 37 , 0b1 , any ; # MCMODE0Q_CL_CHANNEL_TIMEOUT_FORCES_CHANNEL_FAIL 38 , 0b0 , any ; # MCMODE0Q_ENABLE_FAULT_LINE_FOR_GLOBAL_CHECKSTOP 39:43, 0b00000 , any ; # MCMODE0Q_RESERVED_39_43 Reserved 44:52, 0b001100010 , any ; # MCMODE0Q_ADDRESS_COLLISION_MODES |
