INITPROC: Hostboot - High Priority HW Init Procedures for week of 5/14

SW203933

Change-Id: Idd78a0c3a4790a84d66725d71149a1dc0b2a13fe
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4734
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Tested-by: Jenkins Server

16 files changed, 2607 insertions, 605 deletions

diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C
index 1c4047085..80dc5a4aa 100644
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp_fbc_cd.C,v 1.7 2013/03/04 14:53:51 jmcgill Exp $
+// $Id: proc_build_smp_fbc_cd.C,v 1.8 2013/05/07 22:10:20 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_cd.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -1252,6 +1252,142 @@ fapi::ReturnCode proc_build_smp_set_sconfig_we1(
 }
 
 
+//------------------------------------------------------------------------------
+// function: program PB serial SCOM chain (west/east #5)
+// parameters: i_smp_chip => structure encapsulating SMP chip
+//             i_smp      => structure encapsulating SMP
+// returns: FAPI_RC_SUCCESS if register programming is successful,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_sconfig_we5(
+    const proc_build_smp_chip& i_smp_chip,
+    const proc_build_smp_system& i_smp)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    ecmdDataBufferBase data(64);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_sconfig_we5: Start");
+
+    do
+    {
+        // build register content
+        // pb_cfg_lock_on_links
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE5_LOCK_ON_LINKS_BIT,
+            PB_SCONFIG_WE5_LOCK_ON_LINKS?1:0);
+
+        // pb_cfg_x_on_link_tok_agg_threshold
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD,
+            PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT,
+            (PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_END_BIT-
+             PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT+1));
+
+        // pb_cfg_x_off_link_tok_agg_threshold
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD,
+            PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT,
+            (PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_END_BIT-
+             PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT+1));
+
+        // pb_cfg_x_a_link_tok_agg_threshold
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD,
+            PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT,
+            (PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_END_BIT-
+             PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT+1));
+
+        // pb_cfg_x_f_link_tok_agg_threshold
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD,
+            PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT,
+            (PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_END_BIT-
+             PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT+1));
+
+        // pb_cfg_x_a_link_tok_ind_threshold
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD,
+            PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT,
+            (PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_END_BIT-
+             PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT+1));
+
+        // pb_cfg_passthru_enable
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE5_PASSTHRU_ENABLE_BIT,
+            PB_SCONFIG_WE5_PASSTHRU_ENABLE?1:0);
+
+        // pb_cfg_passthru_x_priority
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY,
+            PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT,
+            (PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_END_BIT-
+             PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT+1));
+
+        // pb_cfg_passthru_a_priority
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY,
+            PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT,
+            (PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_END_BIT-
+             PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT+1));
+
+        // pb_cfg_a_tok_init
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_WE5_A_TOK_INIT,
+            PB_SCONFIG_WE5_A_TOK_INIT_START_BIT,
+            (PB_SCONFIG_WE5_A_TOK_INIT_END_BIT-
+             PB_SCONFIG_WE5_A_TOK_INIT_START_BIT+1));
+
+        // pb_cfg_f_tok_init
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_WE5_F_TOK_INIT,
+            PB_SCONFIG_WE5_F_TOK_INIT_START_BIT,
+            (PB_SCONFIG_WE5_F_TOK_INIT_END_BIT-
+             PB_SCONFIG_WE5_F_TOK_INIT_START_BIT+1));
+
+        // pb_cfg_em_fp_enable
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE5_EM_FP_ENABLE_BIT,
+            PB_SCONFIG_WE5_EM_FP_ENABLE?1:0);
+
+        // spare
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_WE5_SPARE,
+            PB_SCONFIG_WE5_SPARE_START_BIT,
+            (PB_SCONFIG_WE5_SPARE_END_BIT-
+             PB_SCONFIG_WE5_SPARE_START_BIT+1));
+
+        // pb_cfg_mem_stv_priority
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_WE5_MEM_STV_PRIORITY,
+            PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT,
+            (PB_SCONFIG_WE5_MEM_STV_PRIORITY_END_BIT-
+             PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT+1));
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_sconfig_we5: Error 0x%x setting up PB Serial Configuration load register data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // call common routine to program chain
+        rc = proc_build_smp_set_sconfig(i_smp_chip, PB_SCONFIG_WE5_DEF, data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_sconfig_we5: Error from proc_build_smp_set_sconfig");
+            break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_sconfig_we5: End");
+    return rc;
+}
+
+
 // NOTE: see comments above function prototype in header
 fapi::ReturnCode proc_build_smp_set_fbc_cd(
     proc_build_smp_system& i_smp)
@@ -1343,6 +1479,13 @@ fapi::ReturnCode proc_build_smp_set_fbc_cd(
                 break;
             }
 
+            rc = proc_build_smp_set_sconfig_we5(p_iter->second, i_smp);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_set_sconfig_we5");
+                break;
+            }
+
             // issue single switch CD to force all updates to occur
             rc = proc_build_smp_switch_cd(p_iter->second);
             if (!rc.ok())
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H
index a8d831450..03299b2ba 100644
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp_fbc_cd.H,v 1.5 2013/03/04 14:53:56 jmcgill Exp $
+// $Id: proc_build_smp_fbc_cd.H,v 1.6 2013/05/07 22:10:24 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_cd.H,v $
 //------------------------------------------------------------------------------
 // *|
@@ -406,6 +406,54 @@ const bool    PB_SCONFIG_WE1_FP_C2I_HSHAKE = false;                    // off
 const bool    PB_SCONFIG_WE1_FP_C2I_SPARE_MODE = false;                // spare
 
 
+//
+// PBH_DAT_ARB_EM (east/west, chain #5) field/bit definitions
+//
+
+const proc_build_smp_sconfig_def PB_SCONFIG_WE5_DEF = { 0x5, 51, false, { true, false, true } };
+
+const uint32_t PB_SCONFIG_WE5_LOCK_ON_LINKS_BIT = 13;
+const uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT = 14;
+const uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_END_BIT = 17;
+const uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT = 18;
+const uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_END_BIT = 21;
+const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT = 22;
+const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_END_BIT = 25;
+const uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT = 26;
+const uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_END_BIT = 29;
+const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT = 30;
+const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_END_BIT = 33;
+const uint32_t PB_SCONFIG_WE5_PASSTHRU_ENABLE_BIT = 34;
+const uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT = 35;
+const uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_END_BIT = 42;
+const uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT = 43;
+const uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_END_BIT = 50;
+const uint32_t PB_SCONFIG_WE5_A_TOK_INIT_START_BIT = 51;
+const uint32_t PB_SCONFIG_WE5_A_TOK_INIT_END_BIT = 54;
+const uint32_t PB_SCONFIG_WE5_F_TOK_INIT_START_BIT = 55;
+const uint32_t PB_SCONFIG_WE5_F_TOK_INIT_END_BIT = 58;
+const uint32_t PB_SCONFIG_WE5_EM_FP_ENABLE_BIT = 59;
+const uint32_t PB_SCONFIG_WE5_SPARE_START_BIT = 60;
+const uint32_t PB_SCONFIG_WE5_SPARE_END_BIT = 61;
+const uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT = 62;
+const uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_END_BIT = 63;
+
+const bool    PB_SCONFIG_WE5_LOCK_ON_LINKS = true;                   // lock
+const uint8_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD = 0x4;      // cnt_4
+const uint8_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD = 0x4;     // cnt_4
+const uint8_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD = 0x4;         // cnt_4
+const uint8_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD = 0x0;         // cnt_0
+const uint8_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD = 0x0;         // cnt_0
+const bool    PB_SCONFIG_WE5_PASSTHRU_ENABLE = true;                 // enable
+const uint8_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY = 0xFE;             // cnt_7to1
+const uint8_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY = 0xFE;             // cnt_7to1
+const uint8_t PB_SCONFIG_WE5_A_TOK_INIT = 0x8;                       // cnt_8
+const uint8_t PB_SCONFIG_WE5_F_TOK_INIT = 0x4;                       // cnt_4
+const bool    PB_SCONFIG_WE5_EM_FP_ENABLE = true;                    // enable
+const uint8_t PB_SCONFIG_WE5_SPARE = 0x0;                            // spare
+const uint8_t PB_SCONFIG_WE5_MEM_STV_PRIORITY = 0x2;                 // stv
+
+
 extern "C"
 {
 
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C
index e3cd8e8d4..07cb97413 100644
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C
+++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pore_table_gen_api_fixed.C,v 1.6 2013/03/08 18:18:21 cmolsen Exp $
+// $Id: p8_pore_table_gen_api_fixed.C,v 1.7 2013/05/08 20:16:18 cmolsen Exp $
 //
 /*------------------------------------------------------------------------------*/
 /* *! (C) Copyright International Business Machines Corp. 2012                  */
@@ -35,7 +35,7 @@
 //                  Other usages:
 //
 /* *! COMMENTS :    - Start file: p7p_pore_api.c                                */
-//                  - The DYNAMIC_RAM_TABLE_PPD was dropped in v1.12 of this
+//                  - The DYNAMIC_RAM_TABLE_PPD was dropped in v1.12 of this 
 //                    code. See v1.12 for explanation and code implementation.
 //
 /*------------------------------------------------------------------------------*/
@@ -51,16 +51,14 @@
 // i_modeBuild -   0: HB/IPL mode, 1: PHYP/Rebuild mode, 2: SRAM mode.
 // i_regName -     unswizzled enum SPR value (NOT a name)
 // i_regData -     data to write
-// i_coreIndex -   core ID
-// i_threadIndex - thread to operate on, API changes thread num to 0 for shared
-//                 SPRs, except for HRMOR which is always done on thread 3 to be
-//                 the last SPR
+// i_coreIndex -   core ID = [0:15]
+// i_threadIndex - thread to operate on = [0:7]. 
 */
 uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
                               uint8_t   i_modeBuild,
-                              uint32_t  i_regName,
-                              uint64_t  i_regData,
-                              uint32_t  i_coreId,   // [0:15]
+                              uint32_t  i_regName, 
+                              uint64_t  i_regData, 
+                              uint32_t  i_coreId,
                               uint32_t  i_threadId)
 {
   uint32_t  rc=0, rcLoc=0, iCount=0;
@@ -78,7 +76,7 @@ uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
   SbeXipItem    xipTocItem;
   RamTableEntry ramEntryThis, *ramEntryNext;
   uint32_t  sprSwiz=0;
-
+  
   // -------------------------------------------------------------------------
   // Validate Ramming parameters.
   //
@@ -117,7 +115,7 @@ uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
   if (rcLoc)
     return IMGBUILD_ERR_RAM_INVALID_PARM;
   rcLoc = 0;
-
+  
   // -------------------------------------------------------------------------
   // Get pointer to SLW section where Ram table resides
   // NB! Only needed for modeBuild==2 !
@@ -126,11 +124,11 @@ uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
       i_modeBuild==P8_SLW_MODEBUILD_REBUILD)  {  // Fixed image.
     // CMO-20130114: Remove this asap. Only for fixed img transition. - Begin
     //               hostSlwSectionFixed isn't needed for modeBuild=0,1 !
-    hostSlwSectionFixed = (void*)( (uintptr_t)io_image +
+    hostSlwSectionFixed = (void*)( (uintptr_t)io_image + 
                                    FIXED_SLW_IMAGE_SIZE -
                                    FIXED_FFDC_SECTION_SIZE -
                                    FIXED_SLW_SECTION_SIZE );
-    // We may want to continue calling this because it would be practical to
+    // We may want to continue calling this because it would be practical to 
     // crosscheck the section size.  Though, the offset is NOT reliable !
     rc = sbe_xip_get_section( io_image, SBE_XIP_SECTION_SLW, &xipSection);
     if (rc)  {
@@ -165,7 +163,7 @@ uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
     return IMGBUILD_ERR_RAM_HDRS_NOT_SYNCED;
   }
   if (xipSection.iv_size!=FIXED_SLW_SECTION_SIZE)  {
-    MY_ERR("Fixed SLW table size in *.H header file differs from SLW section size in image.\n");
+    MY_ERR("Fixed SLW table size in *.H header file differs from SLW section size in image.\n"); 
     MY_ERR("Check code or image version.\n");
     return IMGBUILD_ERR_RAM_HDRS_NOT_SYNCED;
   }
@@ -180,7 +178,7 @@ uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
   MY_INF("\tThread ID = %i\n",i_threadId);
   MY_INF("Image validation and size checks - OK\n");
   MY_INF("\tSLW section size=  %i\n",xipSection.iv_size);
-
+  
   // -------------------------------------------------------------------------
   // Locate RAM vector and locate RAM table associated with "This" core ID.
   //
@@ -211,7 +209,7 @@ uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
       bNewTable = 0;
     }
     else  {
-      hostRamTableThis = (void*)( (uintptr_t)hostSlwRamSection +
+      hostRamTableThis = (void*)( (uintptr_t)hostSlwRamSection + 
                                   SLW_RAM_TABLE_SPACE_PER_CORE*i_coreId );
       bNewTable = 1;
     }
@@ -225,8 +223,8 @@ uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
     hostRamEntryThis = hostRamTableThis;
     if (i_modeBuild==P8_SLW_MODEBUILD_SRAM)  {
       // Update RAM vector (since it is currently NULL)
-      *((uint64_t*)hostRamVector + i_coreId) =
-                           myRev64( xipSlwRamSection +
+      *((uint64_t*)hostRamVector + i_coreId) = 
+                           myRev64( xipSlwRamSection + 
                                     SLW_RAM_TABLE_SPACE_PER_CORE*i_coreId );
     }
     bEntryEnd = 1;
@@ -271,21 +269,22 @@ uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
   // Create, or modify, the RAM entry.
   //
   if (i_regName==P8_MSR_MSR)  {
-    // ...do the MSR header
+    // ...make the MSR header
     headerType = 0x1; // MTMSRD header.
     ramEntryThis.header = ( ((uint32_t)bEntryEnd)  << RAM_HEADER_END_START_C    & RAM_HEADER_END_MASK_C )    |
-                          ( ((uint32_t)headerType) << RAM_HEADER_TYPE_START_C   & RAM_HEADER_TYPE_MASK_C );
-    // ...do the MSR instr
+                          ( ((uint32_t)headerType) << RAM_HEADER_TYPE_START_C   & RAM_HEADER_TYPE_MASK_C )   |
+                          (            i_threadId  << RAM_HEADER_THREAD_START_C & RAM_HEADER_THREAD_MASK_C );
+    // ...make the MSR instr
     ramEntryThis.instr =  RAM_MTMSRD_INSTR_TEMPL_C;
   }
   else  {
-    // ...do the SPR header
+    // ...make the SPR header
     headerType = 0x0; // MTSPR header.
     ramEntryThis.header = ( ((uint32_t)bEntryEnd)  << RAM_HEADER_END_START_C    & RAM_HEADER_END_MASK_C )    |
                           ( ((uint32_t)headerType) << RAM_HEADER_TYPE_START_C   & RAM_HEADER_TYPE_MASK_C )   |
                           (            i_regName   << RAM_HEADER_SPRN_START_C   & RAM_HEADER_SPRN_MASK_C )   |
                           (            i_threadId  << RAM_HEADER_THREAD_START_C & RAM_HEADER_THREAD_MASK_C );
-    // ...do the SPR instr
+    // ...make the SPR instr 
     sprSwiz = i_regName>>5 | (i_regName & 0x0000001f)<<5;
     if (sprSwiz!=SLW_SPR_REGS[iReg].swizzled)  {
       MY_ERR("Inconsistent swizzle rules implemented. Check code. Dumping data.\n");
@@ -295,7 +294,7 @@ uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
     }
     ramEntryThis.instr =  RAM_MTSPR_INSTR_TEMPL_C | ( ( sprSwiz<<RAM_MTSPR_SPR_START_C ) & RAM_MTSPR_SPR_MASK_C );
   }
-  // ...do the data
+  // ...make the data
   ramEntryThis.data  = i_regData;
   // ...summarize new table entry data
   MY_INF("New table entry data (host format):\n");
@@ -328,7 +327,7 @@ uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
 
 /*
 // io_image -    Pointer to SLW image.
-// i_modeBuild - 0: HB/IPL mode, 1: PHYP/Rebuild mode, 2: SRAM mode.
+// i_modeBuild - 0: HB/IPL mode, 1: PHYP/Rebuild mode, 2: SRAM mode. 
 // i_scomAddr -  Scom address.
 // i_coreId -    The core ID [0:15].
 // i_scomData -  Data to write to scom register.
@@ -338,7 +337,7 @@ uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
 uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
                             uint8_t    i_modeBuild,
                             uint32_t   i_scomAddr,
-                            uint32_t   i_coreId,     // [0:15]
+                            uint32_t   i_coreId,     // [0:15] 
                             uint64_t   i_scomData,
                             uint32_t   i_operation,  // [0:5]
                             uint32_t   i_section)    // [0,1,2]
@@ -359,7 +358,7 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
   SbeXipSection xipSection;
   SbeXipItem    xipTocItem;
   PoreInlineContext ctx;
-
+  
   // -------------------------------------------------------------------------
   // Validate Scom parameters.
   //
@@ -388,7 +387,7 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
   if (rcLoc)
     return IMGBUILD_ERR_SCOM_INVALID_PARM;
   rcLoc = 0;
-
+ 
   // -------------------------------------------------------------------------
   // Get pointer to SLW section where Scom table resides
   // NB! Only needed for modeBuild==2 !
@@ -397,11 +396,11 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
       i_modeBuild==P8_SLW_MODEBUILD_REBUILD)  {  // Fixed image.
     // CMO-20130114: Remove this asap. Only for fixed img transition. - Begin
     //               hostSlwSectionFixed isn't needed for modeBuild=0,1 !
-    hostSlwSectionFixed = (void*)( (uintptr_t)io_image +
+    hostSlwSectionFixed = (void*)( (uintptr_t)io_image + 
                                    FIXED_SLW_IMAGE_SIZE -
                                    FIXED_FFDC_SECTION_SIZE -
                                    FIXED_SLW_SECTION_SIZE );
-    // We may want to continue calling this because it would be practical to
+    // We may want to continue calling this because it would be practical to 
     // crosscheck the section size.  Though, the offset is NOT reliable !
     rc = sbe_xip_get_section( io_image, SBE_XIP_SECTION_SLW, &xipSection);
     if (rc)  {
@@ -446,9 +445,9 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
   MY_INF("\tCore ID   = %i\n",i_coreId);
   MY_INF("Image validation and size checks - OK\n");
   MY_INF("\tSLW section size=  %i\n",xipSection.iv_size);
-
+  
   // -------------------------------------------------------------------------
-  // Locate Scom vector according to i_section and then locate Scom table
+  // Locate Scom vector according to i_section and then locate Scom table 
   //   associated with "This" core ID.
   //
   if (i_modeBuild==P8_SLW_MODEBUILD_IPL ||
@@ -531,7 +530,7 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
   //   doesn't include NOP entries.)
   // - If no NOP found, insert at first RET.
   //
-
+  
   // First, create search strings for addr, nop and ret.
   // Note, the following IIS will also be used in case of
   // - i_operation==append
@@ -555,7 +554,7 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
     MY_ERR("pore_NOP generated rc = %d", ctx.error);
     return IMGBUILD_ERR_PORE_INLINE_ASM;
   }
-
+  
   // Second, search for addr and nop in relevant coreId table until first RET.
   // Note:
   // - We go through ALL entries until first RET instr. We MUST find a RET instr,
@@ -563,7 +562,7 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
   // - Count number of entries and check for overrun, though we'll continue
   //   searching until we find an RET. (Should be improved.)
   // - The STI(+SCOM_addr) opcode is in the 2nd word of the Scom entry.
-  // - For an append operation, if a NOP is found (before a RET obviously), the
+  // - For an append operation, if a NOP is found (before a RET obviously), the 
   //   SCOM is replacing that NNNN sequence.
   hostScomEntryNext = hostScomTableThis;
   MY_DBG("hostScomEntryNext (addr): 0x%016llx\n ",(uint64_t)hostScomEntryNext);
@@ -581,7 +580,7 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
     hostScomEntryNext = (void*)((uintptr_t)hostScomEntryNext + XIPSIZE_SCOM_ENTRY);
   }
   hostScomEntryRET = hostScomEntryNext; // The last EntryNext is always the first RET.
-
+  
   switch (i_section)  {
   case P8_SCOM_SECTION_NC:
     if (entriesCount>=SLW_MAX_SCOMS_NC)  {
@@ -657,7 +656,7 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
       i_operation, P8_PORE_SCOM_FIRST_OP, P8_PORE_SCOM_LAST_OP);
     return IMGBUILD_ERR_SCOM_INVALID_PARM;
   }
-
+  
   // -------------------------------------------------------------------------
   // Assuming pre-allocated Scom table (after pre-allocated Ram table):
   // - Table is pre-filled with RNNN ISS.
@@ -666,7 +665,7 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
   // - Remember to check for more than SLW_MAX_SCOMS_NC entries!
   switch (operation)  {
 
-  case P8_PORE_SCOM_APPEND:  // Append a Scom at first occurring NNNN or RNNN,
+  case P8_PORE_SCOM_APPEND:  // Append a Scom at first occurring NNNN or RNNN,  
     if (hostScomEntryNOP)  {
       // ... replace the NNNN
       MY_INF("Append at NOP\n");
@@ -701,7 +700,7 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
       MY_INF("Replace existing Scom w/NOPs\n");
       memcpy(hostScomEntryMatch,(void*)bufIIS,XIPSIZE_SCOM_ENTRY);
     }
-    else  {
+    else  { 
       // do nothing, and assume everything is fine, since we did no damage.
     }
     break;
@@ -709,10 +708,10 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
     if (hostScomEntryMatch)  {
       // ... do an OR on the data (which is the 2nd DWord in the entry)
       MY_INF("Overlay existing Scom - OR case\n");
-      *((uint64_t*)hostScomEntryMatch+1) =
+      *((uint64_t*)hostScomEntryMatch+1) = 
         *((uint64_t*)hostScomEntryMatch+1) | myRev64(i_scomData);
     }
-    else  {
+    else  { 
       MY_ERR("No Scom entry found to do OR operation with.\n");
       return IMGBUILD_ERR_SCOM_ENTRY_NOT_FOUND;
     }
@@ -721,10 +720,10 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
     if (hostScomEntryMatch)  {
       // ... do an AND on the data (which is the 2nd DWord in the entry)
       MY_INF("Overlay existing Scom - AND case\n");
-      *((uint64_t*)hostScomEntryMatch+1) =
+      *((uint64_t*)hostScomEntryMatch+1) = 
         *((uint64_t*)hostScomEntryMatch+1) & myRev64(i_scomData);
     }
-    else  {
+    else  { 
       MY_ERR("No Scom entry found to do AND operation with.\n");
       return IMGBUILD_ERR_SCOM_ENTRY_NOT_FOUND;
     }
@@ -740,7 +739,7 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
   default:
     MY_ERR("Impossible value of operation (=%i). Check code.\n",operation);
     return IMGBUILD_ERR_CHECK_CODE;
-
+  
   }  // End of switch(operation)
 
   return rc;
diff --git a/src/usr/hwpf/hwp/dram_initialization/makefile b/src/usr/hwpf/hwp/dram_initialization/makefile
index 5b8b2a91f..6f0e9461d 100644
--- a/src/usr/hwpf/hwp/dram_initialization/makefile
+++ b/src/usr/hwpf/hwp/dram_initialization/makefile
@@ -49,6 +49,7 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init
 EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp/dram_initialization/mss_memdiag
+EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_eff_config/
 
 ##  NOTE: add new object files when you add a new HWP
 OBJS =  dram_initialization.o \
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C
index abb0cebfb..be79c7fb7 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,24 +20,25 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_setup_bars.C,v 1.25 2012/12/04 14:47:59 bellows Exp $
+// $Id: mss_setup_bars.C,v 1.27 2013/05/06 15:02:09 jmcgill Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //------------------------------------------------------------------------------
+// *!
 // *! TITLE       : mss_setup_bars.C
-// *! DESCRIPTION : see additional comments below
+// *! DESCRIPTION : Program MCS base address registers (BARs) (FAPI)
+// *!
+// *! OWNER NAME  : Girisankar Paulraj      Email: gpaulraj@in.ibm.com
+// *! OWNER NAME  : Mark Bellows            Email: bellows@us.ibm.com
+// *!
 //------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-//Owner :- Girisankar paulraj
-//Back-up owner :- Mark bellows
-//
 // CHANGE HISTORY:
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.26   | jmcgill  | 04/22/13| rewrite to line up with attribute changes
 //  1.23   | bellows  | 12/04/12| more updates
 //  1.22   | gpaulraj | 10/03/12| review updates
 //  1.21   | gpaulraj | 10/02/12| review updates
@@ -47,282 +48,442 @@
 //  1.16   | bellows  | 08/29/12| remove compile error, use 32bit group info
 //         |          |         | as a temporary fix
 //  1.10   | bellows  | 07/16/12| added in Id tag
-//  1.4    | bellows  | 06-05-12| Updates to Match First Configuration, work for P8 and Murano
+//  1.4    | bellows  | 06-05-12| Updates to Match First Configuration, work for
+//         |          |         | P8 and Murano
 //  1.3    | gpaulraj | 05-22-12| 2MCS/group supported for 128GB CDIMM
 //  1.2    | gpaulraj | 05-07-12| 256 group configuration in
 //  1.1    | gpaulraj | 03-19-12| First drop for centaur
-//----------------------------------------------------------------------
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
 //  Includes
-//----------------------------------------------------------------------
+//------------------------------------------------------------------------------
 
 #include <mss_setup_bars.H>
 
+
+//------------------------------------------------------------------------------
+//  Function definitions
+//------------------------------------------------------------------------------
+
 extern "C" {
 
-  fapi::ReturnCode mss_setup_bars(
-                                  const fapi::Target& i_chip_target)
-  {
+
+//------------------------------------------------------------------------------
+// function: write non-mirrored BAR registers (MCFGP/MCFGPA) for a single MCS
+// parameters: i_mcs_target      => MCS chiplet target
+//             i_pri_valid       => true if MCS primary non-mirrored BAR
+//                                  should be marked valid
+//             i_group_member_id => group member ID (only valid if
+//                                  i_pri_valid=true)
+//             i_group_data      => MSS_MCS_GROUP_32 attribute data
+//                                  for member group (only valid if
+//                                  i_pri_valid=true)
+// returns: FAPI_RC_SUCCESS if all register writes are successful,
+//          else failing return code
+//------------------------------------------------------------------------------
+fapi::ReturnCode mss_setup_bars_init_nm_bars(
+    const fapi::Target& i_mcs_target,
+    bool i_pri_valid,
+    uint32_t i_group_member_id,
+    uint32_t i_group_data[])
+{
     fapi::ReturnCode rc;
-    std::vector<fapi::Target> l_mcs_chiplets;
-    ecmdDataBufferBase MCFGP_data(64);
-    ecmdDataBufferBase MCFGPM_data(64);
-    ecmdDataBufferBase MCFGPA_data(64);
-    ecmdDataBufferBase MCFGPMA_data(64);
-//    uint64_t mem_base;
-//    uint64_t mirror_base;
-    uint64_t mem_bases[8];
-    uint64_t l_memory_sizes[8];
-    uint64_t mirror_bases[4];
-    uint64_t l_mirror_sizes[4];
-//    uint64_t alter_mem_base;
-//    uint64_t alter_mirror_base;
-    uint32_t groupID[16][16];
-    uint8_t groups[8];
+    uint32_t rc_ecmd = 0;
+
+    ecmdDataBufferBase MCFGP(64);
+    ecmdDataBufferBase MCFGPA(64);
+
     do
     {
-      rc = FAPI_ATTR_GET(ATTR_MSS_MCS_GROUP_32, &i_chip_target, groupID);
-      if (!rc.ok())
-      {
-        FAPI_ERR("Error reading ATTR_MSS_MCS_GROUP_32");
-        break;
-      }
-      rc = FAPI_ATTR_GET(ATTR_PROC_MEM_SIZES, &i_chip_target, l_memory_sizes);
-      if (!rc.ok())
-      {
-        FAPI_ERR("Error reading ATTR_PROC_MEM_SIZES");
-        break;
-      }
-      rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASES, &i_chip_target, mem_bases);
-      if (!rc.ok())
-      {
-        FAPI_ERR("Error reading ATTR_PROC_MEM_BASES");
-        break;
-      }
-        //base addresses for distinct non-mirrored ranges
-
-        //
-        // process non-mirrored ranges
-        //
-
-        // read chip base address attribute
-        //
-        // process mirrored ranges
-        //
-
-      rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASES, &i_chip_target, mirror_bases);
-      if (!rc.ok())
-      {
-        FAPI_ERR("Error reading ATTR_PROC_MIRROR_BASES");
-        break;
-      }
-      rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_SIZES, &i_chip_target, l_mirror_sizes);
-      if (!rc.ok())
-      {
-        FAPI_ERR("Error  reading ATTR_PROC_MIRROR_SIZES");
-        break;
-      }
-      rc = FAPI_ATTR_GET(ATTR_MSS_MEM_MC_IN_GROUP, &i_chip_target, groups);
-      if (!rc.ok())
-      {
-        FAPI_ERR("Error  reading ATTR_MSS_MEM_MC_IN_GROUP");
-        break;
-      }
-
-        //
-        // write HW registers
-        //
+        // establish base content for MCFGP register
+        rc_ecmd |= MCFGP.setBit(MCFGP_ENABLE_RCMD0_BIT);
+        rc_ecmd |= MCFGP.setBit(MCFGP_ENABLE_RCMD1_BIT);
+        rc_ecmd |= MCFGP.setBit(MCFGP_RSVD_1_BIT);
+        rc_ecmd |= MCFGP.setBit(MCFGP_ENABLE_FASTPATH_BIT);
 
-        // get child MCS chiplets
-      rc = fapiGetChildChiplets(i_chip_target,
-                                fapi::TARGET_TYPE_MCS_CHIPLET,
-                                l_mcs_chiplets,
-                                fapi::TARGET_STATE_FUNCTIONAL);
-      if (!rc.ok())
-      {
-        FAPI_ERR("Error from fapiGetChildChiplets");
-        break;
-      }
-
-        // loop through & set configuration of each child
-      for (std::vector<fapi::Target>::iterator iter = l_mcs_chiplets.begin();
-           iter != l_mcs_chiplets.end() && rc.ok();
-           iter++)
-      {
-        uint8_t mcs_pos = 0x0;
-        rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*iter), mcs_pos);
+        if (i_pri_valid)
+        {
+            // MCFGPQ_VALID
+            rc_ecmd |= MCFGP.setBit(MCFGP_VALID_BIT);
+            // MCFGPQ_MCS_UNITS_PER_GROUP
+            rc_ecmd |= MCFGP.insertFromRight(
+                i_group_data[MSS_MCS_GROUP_32_MCS_IN_GROUP_INDEX] / 2,
+                MCFGP_MCS_UNITS_PER_GROUP_START_BIT,
+                (MCFGP_MCS_UNITS_PER_GROUP_END_BIT-
+                 MCFGP_MCS_UNITS_PER_GROUP_START_BIT)+1);
+            // MCFGPQ_GROUP_MEMBER_IDENTIFICATION
+            rc_ecmd |= MCFGP.insertFromRight(
+                i_group_member_id,
+                MCFGP_GROUP_MEMBER_ID_START_BIT,
+                (MCFGP_GROUP_MEMBER_ID_END_BIT-
+                 MCFGP_GROUP_MEMBER_ID_START_BIT)+1);
+            // MCFGPQ_GROUP_SIZE
+            rc_ecmd |= MCFGP.insertFromRight(
+                (i_group_data[MSS_MCS_GROUP_32_SIZE_INDEX]/4)-1,
+                MCFGP_GROUP_SIZE_START_BIT,
+                (MCFGP_GROUP_SIZE_END_BIT-
+                 MCFGP_GROUP_SIZE_START_BIT)+1);
+
+            // MCFGPQ_BASE_ADDRESS_OF_GROUP
+            rc_ecmd |= MCFGP.insertFromRight(
+                i_group_data[MSS_MCS_GROUP_32_BASE_INDEX] >> 2,
+                MCFGP_BASE_ADDRESS_START_BIT,
+                (MCFGP_BASE_ADDRESS_END_BIT-
+                 MCFGP_BASE_ADDRESS_START_BIT)+1);
+
+            // check buffer manipulation return codes
+            if (rc_ecmd)
+            {
+                FAPI_ERR("mss_setup_bars_init_nm_bars: Error 0x%X setting up MCFGP data buffer",
+                         rc_ecmd);
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+
+            bool alt_valid = i_group_data[MSS_MCS_GROUP_32_ALT_VALID_INDEX];
+            if (alt_valid)
+            {
+                // MCFGPAQ_VALID
+                rc_ecmd |= MCFGPA.setBit(MCFGPA_VALID_BIT);
+
+                // MCFGPAQ_GROUP_SIZE
+                rc_ecmd |= MCFGPA.insertFromRight(
+                    (i_group_data[MSS_MCS_GROUP_32_ALT_SIZE_INDEX]/4)-1,
+                    MCFGPA_GROUP_SIZE_START_BIT,
+                    (MCFGPA_GROUP_SIZE_END_BIT-
+                     MCFGPA_GROUP_SIZE_START_BIT)+1);
+
+                // MCFGPAQ_BASE_ADDRESS_OF_GROUP
+                rc_ecmd |= MCFGPA.insertFromRight(
+                    i_group_data[MSS_MCS_GROUP_32_ALT_BASE_INDEX] >> 2,
+                    MCFGPA_BASE_ADDRESS_START_BIT,
+                    (MCFGPA_BASE_ADDRESS_END_BIT-
+                     MCFGPA_BASE_ADDRESS_START_BIT)+1);
+
+                if (i_group_data[MSS_MCS_GROUP_32_ALT_BASE_INDEX] !=
+                    (i_group_data[MSS_MCS_GROUP_32_BASE_INDEX] +
+                     (i_group_data[MSS_MCS_GROUP_32_SIZE_INDEX]/2)))
+                {
+                    FAPI_ERR("Invalid non-mirrored alternate BAR configuration");
+                    FAPI_SET_HWP_ERROR(rc,
+                                       RC_MSS_SETUP_BARS_NM_ALT_BAR_ERR);
+                    break;
+                }
+            }
+
+            // check buffer manipulation return codes
+            if (rc_ecmd)
+            {
+                FAPI_ERR("mss_setup_bars_init_nm_bars: Error 0x%X setting up MCFGPA data buffer",
+                         rc_ecmd);
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+        }
+
+        // write registers
+        rc = fapiPutScom(i_mcs_target, MCS_MCFGP_0x02011800, MCFGP);
         if (!rc.ok())
         {
-          FAPI_ERR("Error reading ATTR_CHIP_UNIT_POS");
-          break;
+            FAPI_ERR("Error from fapiPutScom (MCS_MCFGP_0x02011800)");
+            break;
+        }
+
+        rc = fapiPutScom(i_mcs_target, MCS_MCFGPA_0x02011814, MCFGPA);
+        if (!rc.ok())
+        {
+            FAPI_ERR("Error from fapiPutScom (MCS_MCFGPA_0x02011814)");
+            break;
+        }
+    } while(0);
+
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: write mirrored BAR registers (MCFGPM/MCFGPMA) for a single MCS
+// parameters: i_mcs_target => MCS chiplet target
+//             i_pri_valid  => true if MCS primary mirrored BAR
+//                             should be marked valid
+//             i_group_data => MSS_MCS_GROUP_32 attribute data
+//                             for member group (only valid if
+//                             i_pri_valid=true)
+// returns: FAPI_RC_SUCCESS if all register writes are successful,
+//          else failing return code
+//------------------------------------------------------------------------------
+fapi::ReturnCode mss_setup_bars_init_m_bars(
+    const fapi::Target& i_mcs_target,
+    bool i_pri_valid,
+    uint32_t i_group_data[])
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0;
+
+    ecmdDataBufferBase MCFGPM(64);
+    ecmdDataBufferBase MCFGPMA(64);
+
+    do
+    {
+        if (i_pri_valid)
+        {
+            // MCFGPMQ_VALID
+            rc_ecmd |= MCFGPM.setBit(MCFGPM_VALID_BIT);
+            // MCFGPMQ_GROUP_SIZE
+            rc_ecmd |= MCFGPM.insertFromRight(
+                (i_group_data[MSS_MCS_GROUP_32_SIZE_INDEX]/4)-1,
+                MCFGPM_GROUP_SIZE_START_BIT,
+                (MCFGPM_GROUP_SIZE_END_BIT-
+                 MCFGPM_GROUP_SIZE_START_BIT)+1);
+
+            // MCFGPMQ_BASE_ADDRESS_OF_GROUP
+            rc_ecmd |= MCFGPM.insertFromRight(
+                i_group_data[MSS_MCS_GROUP_32_BASE_INDEX] >> 2,
+                MCFGPM_BASE_ADDRESS_START_BIT,
+                (MCFGPM_BASE_ADDRESS_END_BIT-
+                 MCFGPM_BASE_ADDRESS_START_BIT)+1);
+
+            // check buffer manipulation return codes
+            if (rc_ecmd)
+            {
+                FAPI_ERR("mss_setup_bars_init_m_bars: Error 0x%X setting up MCFGPM data buffer",
+                         rc_ecmd);
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+
+            bool alt_valid = i_group_data[MSS_MCS_GROUP_32_ALT_VALID_INDEX];
+            if (alt_valid)
+            {
+                // MCFGPMAQ_VALID
+                rc_ecmd |= MCFGPMA.setBit(MCFGPMA_VALID_BIT);
+
+                // MCFGPMAQ_GROUP_SIZE
+                rc_ecmd |= MCFGPMA.insertFromRight(
+                    (i_group_data[MSS_MCS_GROUP_32_ALT_SIZE_INDEX]/4)-1,
+                    MCFGPMA_GROUP_SIZE_START_BIT,
+                    (MCFGPMA_GROUP_SIZE_END_BIT-
+                     MCFGPMA_GROUP_SIZE_START_BIT)+1);
+
+                // MCFGPMAQ_BASE_ADDRESS_OF_GROUP
+                rc_ecmd |= MCFGPMA.insertFromRight(
+                    i_group_data[MSS_MCS_GROUP_32_ALT_BASE_INDEX] >> 2,
+                    MCFGPMA_BASE_ADDRESS_START_BIT,
+                    (MCFGPMA_BASE_ADDRESS_END_BIT-
+                     MCFGPMA_BASE_ADDRESS_START_BIT)+1);
+
+                if (i_group_data[MSS_MCS_GROUP_32_ALT_BASE_INDEX] !=
+                    (i_group_data[MSS_MCS_GROUP_32_BASE_INDEX] +
+                     (i_group_data[MSS_MCS_GROUP_32_SIZE_INDEX]/2)))
+                {
+                    FAPI_ERR("Invalid mirrored alternate BAR configuration");
+                    FAPI_SET_HWP_ERROR(rc,
+                                       RC_MSS_SETUP_BARS_M_ALT_BAR_ERR);
+                    break;
+                }
+            }
+
+            // check buffer manipulation return codes
+            if (rc_ecmd)
+            {
+                FAPI_ERR("mss_setup_bars_init_m_bars: Error 0x%X setting up MCFGPMA data buffer",
+                         rc_ecmd);
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
         }
 
-        MCFGP_data.flushTo0();
-        MCFGPM_data.flushTo0();
-        MCFGPA_data.flushTo0();
-        MCFGPMA_data.flushTo0();
-        rc = fapiGetScom(*iter, MCS_MCFGP_0x02011800, MCFGP_data);
+        // write registers
+        rc = fapiPutScom(i_mcs_target, MCS_MCFGPM_0x02011801, MCFGPM);
         if (!rc.ok())
         {
-          FAPI_ERR("Error Reading  MCS_MCFGP_0x02011800");
-          break;
+            FAPI_ERR("Error from fapiPutScom (MCS_MCFGPM_0x02011801)");
+            break;
         }
-        MCFGP_data.setBit(9);
-        MCFGP_data.setBit(10);
-        MCFGP_data.setBit(24);
-        rc = fapiPutScom(*iter, MCS_MCFGP_0x02011800, MCFGP_data);
+        rc = fapiPutScom(i_mcs_target, MCS_MCFGPMA_0x02011815, MCFGPMA);
+        if (!rc.ok())
+        {
+            FAPI_ERR("Error from fapiPutScom (MCS_MCFGPMA_0x02011815");
+            break;
+        }
+    } while(0);
+
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: mss_setup_bars HWP entry point
+//           NOTE: see comments above function prototype in header
+//------------------------------------------------------------------------------
+fapi::ReturnCode mss_setup_bars(const fapi::Target& i_pu_target)
+{
+    fapi::ReturnCode rc;
+    std::vector<fapi::Target> l_mcs_chiplets;
+    uint32_t group_data[16][16];
+
+    do
+    {
+        // obtain group configuration attribute for this chip
+        rc = FAPI_ATTR_GET(ATTR_MSS_MCS_GROUP_32, &i_pu_target, group_data);
         if (!rc.ok())
         {
-          FAPI_ERR("Error writing  MCS_MCFGP_0x02011800");
-          break;
+            FAPI_ERR("Error reading ATTR_MSS_MCS_GROUP_32");
+            break;
         }
-        rc = fapiGetScom(*iter, MCS_MCFGPM_0x02011801, MCFGPM_data);
+
+        // get child MCS chiplets
+        rc = fapiGetChildChiplets(i_pu_target,
+                                  fapi::TARGET_TYPE_MCS_CHIPLET,
+                                  l_mcs_chiplets,
+                                  fapi::TARGET_STATE_FUNCTIONAL);
         if (!rc.ok())
         {
-          FAPI_ERR("Error Reading  MCS_MCFGPM_0x02011801");
-          break;
-        }	       	
-        for(uint8_t i=0; (i<16)&&(rc.ok()); i++)
+            FAPI_ERR("Error from fapiGetChildChiplets");
+            break;
+        }
+
+        // loop through & set configuration of each MCS chiplet
+        for (std::vector<fapi::Target>::iterator iter = l_mcs_chiplets.begin();
+             iter != l_mcs_chiplets.end() && rc.ok();
+             iter++)
         {
-          uint32_t temp=0;
-          temp = groupID[i][1];
-          uint32_t b=0;
-          for(uint32_t j=4;(j<temp+4)&&(rc.ok());j++)
-          {
-            if(groupID[i][j]==mcs_pos)
+            // obtain MCS chip unit number
+            uint8_t mcs_pos = 0x0;
+            rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*iter), mcs_pos);
+            if (!rc.ok())
             {
-              FAPI_INF(" Group ID of no MCS %d is %d MCS_POS  ID  found for %d as %d ",temp, i,mcs_pos,(j-4));
-                        //temp =(temp/2;
-              MCFGP_data.insertFromRight(temp/2,1,3);
-              MCFGP_data.insertFromRight((j-4),4,5);
-
-              b = ((l_memory_sizes[i]>>30) / 4) - 1;
-              MCFGP_data.insertFromRight(b,11,13);
-              b = mem_bases[i]>>32;
-              MCFGP_data.insertFromRight(b,26,18);
-              MCFGP_data.setBit(25);
-              rc = fapiPutScom(*iter, MCS_MCFGP_0x02011800, MCFGP_data);
-              if (!rc.ok())
-              {
-                FAPI_ERR("Error writing  MCS_MCFGP_0x02011800");
-                break;
-              }		
-              rc = fapiGetScom(*iter, MCS_MCFGP_0x02011800, MCFGP_data);
-              if (!rc.ok())
-              {
-                FAPI_ERR("Error Reading  MCS_MCFGP_0x02011800");
+                FAPI_ERR("Error reading ATTR_CHIP_UNIT_POS");
                 break;
-              }			
-              MCFGP_data.setBit(0);  //  Read registers value and set Zero bit as per register specification
-              FAPI_DBG("Writing MCS %d MCFGP = 0x%llx",mcs_pos, MCFGP_data.getDoubleWord(0));
-              rc = fapiPutScom(*iter, MCS_MCFGP_0x02011800, MCFGP_data);
-              if (!rc.ok())
-              {
-                FAPI_ERR("Error from fapiPutScom MCS_MCFGP_0x02011800");
-                break;
-              }
-
-             if(temp>1)
-             {
-
-                //setting the MCFGPM register
-                  b = ((l_mirror_sizes[i]>>30) / 4) - 1;
-                  MCFGPM_data.insertFromRight(b,11,13);
-                  b = mirror_bases[i]>>32;
-                  MCFGPM_data.insertFromRight(b,26,18);
-                  rc = fapiPutScom(*iter, MCS_MCFGPM_0x02011801, MCFGPM_data);
-                  if (!rc.ok())
-                  {
-                     FAPI_ERR("Error writing  MCS_MCFGPM_0x02011801");
-                     break;
-                  }		       		
-                  rc = fapiGetScom(*iter, MCS_MCFGPM_0x02011801, MCFGPM_data);
-                  if (!rc.ok())
-                  {
-                    FAPI_ERR("Error reading  MCS_MCFGPM_0x02011801");
-                    break;
-                  }
-
-                  MCFGPM_data.setBit(0);
-                  FAPI_DBG("Writing MCS %d MCFGPM = 0x%llx",mcs_pos, MCFGPM_data.getDoubleWord(0));
-                  rc = fapiPutScom(*iter, MCS_MCFGPM_0x02011801, MCFGPM_data);
-                  if (!rc.ok())
-                  {
-                     FAPI_ERR("Error from fapiPutScom MCS_MCFGPM_0x02011801");
-                     break;
-                  }
-              }
-
-              if(groupID[i][12])
-
-              {
-
-                b = (groupID[i][13] / 4) - 1;
-                MCFGPA_data.insertFromRight(b,11,13);
-                b = groupID[i][14]>>2;
-                MCFGPA_data.insertFromRight(b,26,18);
-                rc = fapiPutScom(*iter, MCS_MCFGPA_0x02011814, MCFGPA_data);
-                if (!rc.ok())
+            }
+
+            // determine non-mirrored member group
+            bool nm_bar_valid = false;
+            uint8_t nm_bar_group_index = 0x0;
+            uint8_t nm_bar_group_member_id = 0x0;
+            for (size_t i = MSS_MCS_GROUP_32_NM_START_INDEX;
+                 (i <= MSS_MCS_GROUP_32_NM_END_INDEX) && rc.ok();
+                 i++)
+            {
+                // only process valid groups
+                if (group_data[i][MSS_MCS_GROUP_32_SIZE_INDEX] == 0)
                 {
-                  FAPI_ERR("Error writing  MCS_MCFGPA_0x02011814");
-                  break;
-                }		       		
-                rc = fapiGetScom(*iter, MCS_MCFGPA_0x02011814, MCFGPA_data);
-                if (!rc.ok())
+                    continue;
+                }
+
+                uint32_t mcs_in_group = group_data[i][MSS_MCS_GROUP_32_MCS_IN_GROUP_INDEX];
+                for (size_t j = MSS_MCS_GROUP_32_MEMBERS_START_INDEX;
+                     (j < MSS_MCS_GROUP_32_MEMBERS_START_INDEX+mcs_in_group) &&
+                     (rc.ok());
+                     j++)
                 {
-                  FAPI_ERR("Error reading  MCS_MCFGPA_0x02011814");
-                  break;
-                }					
-                MCFGPA_data.setBit(0);  //  Read registers value and set Zero bit as per register specification
-                FAPI_DBG("Writing MCS %d MCFGPA = 0x%llx",mcs_pos, MCFGPA_data.getDoubleWord(0));
-                rc = fapiPutScom(*iter, MCS_MCFGPA_0x02011814, MCFGPA_data);
-                if (!rc.ok())
+                    if (mcs_pos == group_data[i][j])
+                    {
+                        if (nm_bar_valid)
+                        {
+                            const uint8_t& MCS_POS = mcs_pos;
+                            const uint8_t& GROUP_INDEX_A = nm_bar_group_index;
+                            const uint8_t& GROUP_INDEX_B = i;
+                            FAPI_ERR("MCS %d is listed as a member in multiple non-mirrored groups",
+                                     mcs_pos);
+                            FAPI_SET_HWP_ERROR(
+                                rc,
+                                RC_MSS_SETUP_BARS_MULTIPLE_GROUP_ERR);
+                            break;
+                        }
+                        nm_bar_valid = true;
+                        nm_bar_group_index = i;
+                        nm_bar_group_member_id =
+                            j-MSS_MCS_GROUP_32_MEMBERS_START_INDEX;
+                    }
+                }
+            }
+            if (!rc.ok())
+            {
+                break;
+            }
+
+            // write non-mirrored BARs based on group configuration
+            rc = mss_setup_bars_init_nm_bars(
+                *iter,
+                nm_bar_valid,
+                nm_bar_group_member_id,
+                group_data[nm_bar_group_index]);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from mss_setup_bars_init_nm_bars");
+                break;
+            }
+
+            // determine mirrored member group
+            bool m_bar_valid = false;
+            uint8_t m_bar_group_index = 0x0;
+            for (size_t i = MSS_MCS_GROUP_32_M_START_INDEX;
+                 (i <= MSS_MCS_GROUP_32_M_END_INDEX) && rc.ok();
+                 i++)
+            {
+                // only process valid groups
+                if (group_data[i][MSS_MCS_GROUP_32_SIZE_INDEX] == 0)
                 {
-                  FAPI_ERR("Error writing  MCS_MCFGPA_0x02011814");
-                  break;
-                }		       		
+                    continue;
+                }
 
-                if(temp>1)
+                uint32_t mcs_in_group = group_data[i][MSS_MCS_GROUP_32_MCS_IN_GROUP_INDEX];
+                for (size_t j = MSS_MCS_GROUP_32_MEMBERS_START_INDEX;
+                     (j < MSS_MCS_GROUP_32_MEMBERS_START_INDEX+mcs_in_group) &&
+                     (rc.ok());
+                     j++)
                 {
-                   //setting MCFGPMA
-                   b = (groupID[i+8][13]/ 4) - 1;
-                   MCFGPMA_data.insertFromRight(b,11,13);
-                   b = groupID[i+8][14]>>2;
-                   MCFGPMA_data.insertFromRight(b,26,18);
-                   rc = fapiPutScom(*iter, MCS_MCFGPMA_0x02011815, MCFGPMA_data);
-                   if (!rc.ok())
-                   {
-                     FAPI_ERR("Error writing  MCS_MCFpGPMA_0x02011815");
-                     break;
-                   }		       		
-                   rc = fapiGetScom(*iter, MCS_MCFGPMA_0x02011815, MCFGPMA_data);
-                   if (!rc.ok())
-                   {
-                     FAPI_ERR("Error reading  MCS_MCFGPMA_0x02011815");
-                     break;
-                   }					
-                   MCFGPMA_data.setBit(0);  //  Read registers value and set Zero bit as per register specification
-                   FAPI_DBG("Writing MCS %d MCFGPMA = 0x%llx",mcs_pos, MCFGPMA_data.getDoubleWord(0));
-                   rc = fapiPutScom(*iter, MCS_MCFGPMA_0x02011815, MCFGPMA_data);
-                   if (!rc.ok())
-                   {
-                     FAPI_ERR("Error writing  MCS_MCFGPMA_0x02011815");
-                     break;
-                   }
-                 }
-              }
+                    if (mcs_pos == group_data[i][j])
+                    {
+                        if (m_bar_valid)
+                        {
+                            const uint8_t& MCS_POS = mcs_pos;
+                            const uint8_t& GROUP_INDEX_A = m_bar_group_index;
+                            const uint8_t& GROUP_INDEX_B = i;
+                            FAPI_ERR("MCS %d is listed as a member in multiple mirrored groups",
+                                     mcs_pos);
+                            FAPI_SET_HWP_ERROR(
+                                rc,
+                                RC_MSS_SETUP_BARS_MULTIPLE_GROUP_ERR);
+                            break;
+                        }
+                        m_bar_valid = true;
+                        m_bar_group_index = i;
+                    }
+                }
+            }
+            if (!rc.ok())
+            {
+                break;
+            }
+
+            // write non-mirrored BARs based on group configuration
+            rc = mss_setup_bars_init_m_bars(
+                *iter,
+                m_bar_valid,
+                group_data[m_bar_group_index]);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from mss_setup_bars_init_m_bars");
+                break;
+            }
+
+            // write attribute signifying BARs are valid & MSS inits are finished
+            uint8_t final = 1;
+            rc = FAPI_ATTR_SET(ATTR_MSS_MEM_IPL_COMPLETE, &i_pu_target, final);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_MSS_MEM_IPL_COMPLETE)");
+                break;
             }
-          }
-        }
-      }
-       uint8_t final=1;
-       rc=FAPI_ATTR_SET( ATTR_MSS_MEM_IPL_COMPLETE, &i_chip_target ,final);
-       if (!rc.ok())
-       {
-           FAPI_ERR("Error writing  TARGET_TYPE_PROC_CHIP");
-           break;
         }
-    }while(0);
+    } while(0);
+
     return rc;
-  }
+}
+
 
 } // extern "C"
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H
index f86879271..3862438d7 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,42 +20,126 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_setup_bars.H,v 1.3 2012/07/17 13:23:32 bellows Exp $
+// $Id: mss_setup_bars.H,v 1.4 2013/04/26 13:57:03 jmcgill Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //------------------------------------------------------------------------------
-// *! TITLE       : mss_setup_bars.H
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Girisankar Paulraj     Email: gpaulraj@in.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// Header file for mss_setup_bars.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
+// *!
+// *! TITLE       : mss_setup_bars.C
+// *! DESCRIPTION : Program MCS base address registers (BARs) (FAPI)
+// *!
+// *! OWNER NAME  : Girisankar Paulraj      Email: gpaulraj@in.ibm.com
+// *! OWNER NAME  : Mark Bellows            Email: bellows@us.ibm.com
+// *!
 //------------------------------------------------------------------------------
 // CHANGE HISTORY:
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.3    | bellows  | 07/16/12| added in ID tag
 //  1.1    | gpaulraj | 03/19/12| Updated
-//  1.3    | bellows  | 07/16/12| added in Id tag
+//------------------------------------------------------------------------------
 
 #ifndef MSS_SETUP_BARS_H_
 #define MSS_SETUP_BARS_H_
 
+//------------------------------------------------------------------------------
+//  Includes
+//------------------------------------------------------------------------------
+
 #include <fapi.H>
 #include "p8_scom_addresses.H"
 
-typedef fapi::ReturnCode (*mss_setup_bars_FP_t)(const fapi::Target&);
+
+//------------------------------------------------------------------------------
+//  Constant definitions
+//------------------------------------------------------------------------------
+
+// MCFGP bit/field definitions
+const uint32_t MCFGP_VALID_BIT = 0;
+const uint32_t MCFGP_MCS_UNITS_PER_GROUP_START_BIT = 1;
+const uint32_t MCFGP_MCS_UNITS_PER_GROUP_END_BIT = 3;
+const uint32_t MCFGP_GROUP_MEMBER_ID_START_BIT = 4;
+const uint32_t MCFGP_GROUP_MEMBER_ID_END_BIT = 8;
+const uint32_t MCFGP_ENABLE_RCMD0_BIT = 9;
+const uint32_t MCFGP_ENABLE_RCMD1_BIT = 10;
+const uint32_t MCFGP_GROUP_SIZE_START_BIT = 11;
+const uint32_t MCFGP_GROUP_SIZE_END_BIT = 23;
+const uint32_t MCFGP_RSVD_1_BIT = 24;
+const uint32_t MCFGP_ENABLE_FASTPATH_BIT = 25;
+const uint32_t MCFGP_BASE_ADDRESS_START_BIT = 26;
+const uint32_t MCFGP_BASE_ADDRESS_END_BIT = 43;
+
+// MCFGPA bit/field defintions
+const uint32_t MCFGPA_VALID_BIT = 0;
+const uint32_t MCFGPA_GROUP_SIZE_START_BIT = 11;
+const uint32_t MCFGPA_GROUP_SIZE_END_BIT = 23;
+const uint32_t MCFGPA_BASE_ADDRESS_START_BIT = 26;
+const uint32_t MCFGPA_BASE_ADDRESS_END_BIT = 43;
+
+// MCFGPM bit/field definitions
+const uint32_t MCFGPM_VALID_BIT = 0;
+const uint32_t MCFGPM_GROUP_SIZE_START_BIT = 11;
+const uint32_t MCFGPM_GROUP_SIZE_END_BIT = 23;
+const uint32_t MCFGPM_BASE_ADDRESS_START_BIT = 26;
+const uint32_t MCFGPM_BASE_ADDRESS_END_BIT = 43;
+
+// MCFGPMA bit/field definitions
+const uint32_t MCFGPMA_VALID_BIT = 0;
+const uint32_t MCFGPMA_GROUP_SIZE_START_BIT = 11;
+const uint32_t MCFGPMA_GROUP_SIZE_END_BIT = 23;
+const uint32_t MCFGPMA_BASE_ADDRESS_START_BIT = 26;
+const uint32_t MCFGPMA_BASE_ADDRESS_END_BIT = 43;
+
+// attribute index constants
+// first array dimension (group ID)
+const uint8_t MSS_MCS_GROUP_32_NM_START_INDEX = 0;
+const uint8_t MSS_MCS_GROUP_32_NM_END_INDEX   = 7;
+const uint8_t MSS_MCS_GROUP_32_M_START_INDEX  = 8;
+const uint8_t MSS_MCS_GROUP_32_M_END_INDEX    = 15;
+
+// second array dimension (group definition)
+const uint8_t MSS_MCS_GROUP_32_MCS_SIZE_INDEX      = 0;
+const uint8_t MSS_MCS_GROUP_32_MCS_IN_GROUP_INDEX  = 1;
+const uint8_t MSS_MCS_GROUP_32_SIZE_INDEX          = 2;
+const uint8_t MSS_MCS_GROUP_32_BASE_INDEX          = 3;
+const uint8_t MSS_MCS_GROUP_32_MEMBERS_START_INDEX = 4;
+const uint8_t MSS_MCS_GROUP_32_MEMBERS_END_INDEX   = 11;
+const uint8_t MSS_MCS_GROUP_32_ALT_VALID_INDEX     = 12;
+const uint8_t MSS_MCS_GROUP_32_ALT_SIZE_INDEX      = 13;
+const uint8_t MSS_MCS_GROUP_32_ALT_BASE_INDEX      = 14;
+const uint8_t MSS_MCS_GROUP_32_LARGEST_MBA_INDEX   = 15;
+
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+// function pointer typedef definition for HWP call support
+typedef fapi::ReturnCode (*mss_setup_bars_FP_t)(const fapi::Target& i_pu_target);
+
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
 
 extern "C"
 {
 
-fapi::ReturnCode mss_setup_bars(const fapi::Target& i_chip_target);
+//------------------------------------------------------------------------------
+// function: program MCS base address registers (BARs)
+//           writes non-mirrored (MCFGP/MCFGPA) &
+//           mirrored BAR registers (MCFGPM/MCFGPMA)
+// parameters: i_pu_target  => chip level target
+// returns: FAPI_RC_SUCCESS if all register writes are successful,
+//          RC_MSS_SETUP_BARS_MULTIPLE_GROUP_ERR if a child MCS is listed
+//            as a member in multiple groups
+//          else failing return code
+//------------------------------------------------------------------------------
+fapi::ReturnCode mss_setup_bars(const fapi::Target& i_pu_target);
+
 
 } // extern "C"
 
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C
index 9396db2c5..2b24bf858 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_setup_bars.C,v 1.10 2013/04/27 21:48:59 jmcgill Exp $
+// $Id: proc_setup_bars.C,v 1.13 2013/05/09 04:03:25 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -61,6 +61,9 @@ const std::map<uint64_t, uint64_t> proc_setup_bars_fsp_mmio_mask_size::xlate_map
 const std::map<uint64_t, uint64_t> proc_setup_bars_nx_mmio_bar_size::xlate_map =
     proc_setup_bars_nx_mmio_bar_size::create_map();
 
+const std::map<uint64_t, uint64_t> proc_setup_bars_as_mmio_bar_size::xlate_map =
+    proc_setup_bars_as_mmio_bar_size::create_map();
+
 const std::map<uint64_t, uint64_t> proc_setup_bars_mcd_bar_size::xlate_map =
     proc_setup_bars_mcd_bar_size::create_map();
 
@@ -195,8 +198,7 @@ fapi::ReturnCode proc_setup_bars_memory_get_non_mirrored_attrs(
     // return code
     fapi::ReturnCode rc;
     // temporary attribute storage used to build procedure data structures
-    uint64_t non_mirrored_base_attrs[PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES];
-    uint64_t non_mirrored_size_attrs[PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES];
+    uint32_t mss_mcs_group_32[OPT_MEMMAP_GROUP_32_DIM1][OPT_MEMMAP_GROUP_32_DIM2];
     proc_setup_bars_addr_range non_mirrored_ranges[PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES];
 
     // mark function entry
@@ -205,20 +207,12 @@ fapi::ReturnCode proc_setup_bars_memory_get_non_mirrored_attrs(
     do
     {
         // retrieve non-mirrored memory base address/size attributes
-        rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASES,
-                           i_target,
-                           non_mirrored_base_attrs);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_memory_get_non_mirrored_attrs: Error querying ATTR_PROC_MEM_BASES");
-            break;
-        }
-        rc = FAPI_ATTR_GET(ATTR_PROC_MEM_SIZES,
+        rc = FAPI_ATTR_GET(ATTR_MSS_MCS_GROUP_32,
                            i_target,
-                           non_mirrored_size_attrs);
+                           mss_mcs_group_32);
         if (!rc.ok())
         {
-            FAPI_ERR("proc_setup_bars_memory_get_non_mirrored_attrs: Error querying ATTR_PROC_MEM_SIZES");
+            FAPI_ERR("proc_setup_bars_memory_get_non_mirrored_attrs: Error querying ATTR_MSS_MCS_GROUP_32");
             break;
         }
 
@@ -226,10 +220,12 @@ fapi::ReturnCode proc_setup_bars_memory_get_non_mirrored_attrs(
         for (uint8_t r = 0; r < PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES; r++)
         {
             // build range content
-            non_mirrored_ranges[r].base_addr = non_mirrored_base_attrs[r];
-            non_mirrored_ranges[r].size = non_mirrored_size_attrs[r];
+            non_mirrored_ranges[r].base_addr =
+                (mss_mcs_group_32[OPT_MEMMAP_GROUP_32_NM_START_INDEX+r][OPT_MEMMAP_GROUP_32_BASE_INDEX])*OPT_MEMMAP_GB;
+            non_mirrored_ranges[r].size =
+                (mss_mcs_group_32[OPT_MEMMAP_GROUP_32_NM_START_INDEX+r][OPT_MEMMAP_GROUP_32_SIZE_INDEX])*OPT_MEMMAP_GB;
             // consider range enabled if size is non-zero
-            non_mirrored_ranges[r].enabled = (non_mirrored_size_attrs[r] != 0x0);
+            non_mirrored_ranges[r].enabled = (non_mirrored_ranges[r].size != 0x0);
             // check attribute content
             FAPI_DBG("proc_setup_bars_memory_get_non_mirrored_attrs: Range %d", r);
             if (proc_setup_bars_common_check_bar(
@@ -319,8 +315,7 @@ fapi::ReturnCode proc_setup_bars_memory_get_mirrored_attrs(
     // return code
     fapi::ReturnCode rc;
     // temporary attribute storage used to build procedure data structures
-    uint64_t mirrored_base_attrs[PROC_SETUP_BARS_NUM_MIRRORED_RANGES];
-    uint64_t mirrored_size_attrs[PROC_SETUP_BARS_NUM_MIRRORED_RANGES];
+    uint32_t mss_mcs_group_32[OPT_MEMMAP_GROUP_32_DIM1][OPT_MEMMAP_GROUP_32_DIM2];
     proc_setup_bars_addr_range mirrored_ranges[PROC_SETUP_BARS_NUM_MIRRORED_RANGES];
 
     // mark function entry
@@ -329,20 +324,12 @@ fapi::ReturnCode proc_setup_bars_memory_get_mirrored_attrs(
     do
     {
         // retrieve mirrored memory base address/size attributes
-        rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASES,
-                           i_target,
-                           mirrored_base_attrs);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_memory_get_mirrored_attrs: Error querying ATTR_PROC_MIRROR_BASE");
-            break;
-        }
-        rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_SIZES,
+        rc = FAPI_ATTR_GET(ATTR_MSS_MCS_GROUP_32,
                            i_target,
-                           mirrored_size_attrs);
+                           mss_mcs_group_32);
         if (!rc.ok())
         {
-            FAPI_ERR("proc_setup_bars_memory_get_mirrored_attrs: Error querying ATTR_PROC_MIRROR_SIZE");
+            FAPI_ERR("proc_setup_bars_memory_get_mirrored_attrs: Error querying ATTR_MSS_MCS_GROUP_32");
             break;
         }
 
@@ -350,10 +337,12 @@ fapi::ReturnCode proc_setup_bars_memory_get_mirrored_attrs(
         for (uint8_t r = 0; r < PROC_SETUP_BARS_NUM_MIRRORED_RANGES; r++)
         {
             // build range content
-            mirrored_ranges[r].base_addr = mirrored_base_attrs[r];
-            mirrored_ranges[r].size = mirrored_size_attrs[r];
+            mirrored_ranges[r].base_addr =
+                (mss_mcs_group_32[OPT_MEMMAP_GROUP_32_M_START_INDEX+r][OPT_MEMMAP_GROUP_32_BASE_INDEX])*OPT_MEMMAP_GB;
+            mirrored_ranges[r].size =
+                (mss_mcs_group_32[OPT_MEMMAP_GROUP_32_M_START_INDEX+r][OPT_MEMMAP_GROUP_32_SIZE_INDEX])*OPT_MEMMAP_GB;
             // consider range enabled if size is non-zero
-            mirrored_ranges[r].enabled = (mirrored_size_attrs[r] != 0x0);
+            mirrored_ranges[r].enabled = (mirrored_ranges[r].size != 0x0);
             // check attribute content
             FAPI_DBG("proc_setup_bars_memory_get_mirrored_attrs: Range %d", r);
             if (proc_setup_bars_common_check_bar(
@@ -899,6 +888,78 @@ fapi::ReturnCode proc_setup_bars_nx_get_mmio_bar_attrs(
 
 
 //------------------------------------------------------------------------------
+// function: retrieve attributes defining AS MMIO BAR programming
+// parameters: i_target      => pointer to chip target
+//             io_addr_range => address range structure encapsulating
+//                              attribute values
+// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values
+//              are valid,
+//          RC_PROC_SETUP_BARS_AS_MMIO_BAR_ATTR_ERR if chip AS MMIO range
+//              attribute content violates expected behavior,
+//          else FAPI_ATTR_GET return code
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_setup_bars_as_get_mmio_bar_attrs(
+    const fapi::Target* i_target,
+    proc_setup_bars_addr_range& io_addr_range)
+{
+    // return code
+    fapi::ReturnCode rc;
+    uint8_t bar_enabled;
+
+    FAPI_DBG("proc_setup_bars_as_get_mmio_bar_attrs: Start");
+    do
+    {
+        // BAR base address
+        rc = FAPI_ATTR_GET(ATTR_PROC_AS_MMIO_BAR_BASE_ADDR,
+                           i_target,
+                           io_addr_range.base_addr);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_setup_bars_as_get_mmio_bar_attrs: Error querying ATTR_PROC_AS_MMIO_BAR_BASE_ADDR");
+            break;
+        }
+
+        // BAR enable
+        rc = FAPI_ATTR_GET(ATTR_PROC_AS_MMIO_BAR_ENABLE,
+                           i_target,
+                           bar_enabled);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_setup_bars_as_get_mmio_bar_attrs: Error querying ATTR_PROC_AS_MMIO_BAR_ENABLE");
+            break;
+        }
+        io_addr_range.enabled = (bar_enabled == 0x1);
+
+        // BAR size
+        rc = FAPI_ATTR_GET(ATTR_PROC_AS_MMIO_BAR_SIZE,
+                           i_target,
+                           io_addr_range.size);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_setup_bars_as_get_mmio_bar_attrs: Error querying ATTR_PROC_AS_MMIO_BAR_SIZE");
+            break;
+        }
+
+        // check BAR attribute content
+        if (proc_setup_bars_common_check_bar(
+                as_mmio_bar_def,
+                io_addr_range) != false)
+        {
+            FAPI_ERR("proc_setup_bars_as_get_mmio_bar_attrs: Error from proc_setup_bars_common_check_bar");
+            const uint64_t& BASE_ADDR = io_addr_range.base_addr;
+            const uint64_t& SIZE = io_addr_range.size;
+            FAPI_SET_HWP_ERROR(rc,
+               RC_PROC_SETUP_BARS_AS_MMIO_BAR_ATTR_ERR);
+            break;
+        }
+    } while(0);
+
+    FAPI_DBG("proc_setup_bars_as_get_mmio_bar_attrs: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
 // function: retrieve attributes defining PCIe IO BAR programming
 // parameters: i_target       => pointer to chip target
 //             io_addr_ranges => 2D array of address range structures
@@ -1105,6 +1166,16 @@ fapi::ReturnCode proc_setup_bars_get_bar_attrs(
             break;
         }
 
+        FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for AS MMIO address range");
+        rc = proc_setup_bars_as_get_mmio_bar_attrs(
+            &(io_smp_chip.chip->this_chip),
+            io_smp_chip.as_mmio_range);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_intp_get_bar_attrs");
+            break;
+        }
+
         FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for PCIe address ranges");
         rc = proc_setup_bars_pcie_get_bar_attrs(
             &(io_smp_chip.chip->this_chip),
@@ -2362,6 +2433,18 @@ proc_setup_bars_write_local_chip_region_bars(
                 FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
                 break;
             }
+
+            FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing AS MMIO BAR register");
+            rc = proc_setup_bars_common_write_bar_reg(
+                i_smp_chip.chip->this_chip,
+                NX_AS_MMIO_BAR_0x0201309E,
+                as_mmio_bar_reg_def,
+                i_smp_chip.as_mmio_range);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
+                break;
+            }
         }
 
         // NX (non-mirrored)
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H
index 871a79d09..4bd959bb2 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_setup_bars.H,v 1.6 2013/04/27 21:49:01 jmcgill Exp $
+// $Id: proc_setup_bars.H,v 1.8 2013/05/09 04:03:27 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars.H,v $
 //------------------------------------------------------------------------------
 // *|
@@ -98,6 +98,7 @@
 #include <map>
 #include <fapi.H>
 #include "proc_fab_smp.H"
+#include "opt_memmap.H"
 #include "p8_scom_addresses.H"
 
 
@@ -332,6 +333,7 @@ struct proc_setup_bars_smp_chip
     proc_setup_bars_addr_range fsp_mmio_mask_range;
     proc_setup_bars_addr_range intp_range;
     proc_setup_bars_addr_range nx_mmio_range;
+    proc_setup_bars_addr_range as_mmio_range;
     proc_setup_bars_addr_range pcie_ranges[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT];
 };
 
@@ -470,6 +472,21 @@ struct proc_setup_bars_nx_mmio_bar_size
     static const std::map<uint64_t, uint64_t> xlate_map;
 };
 
+// define set of AS MMIO mask sizes
+struct proc_setup_bars_as_mmio_bar_size
+{
+    static std::map<uint64_t, uint64_t> create_map()
+    {
+        std::map<uint64_t, uint64_t> m;
+        m[PROC_SETUP_BARS_SIZE_2_MB]   = 0x3;
+        m[PROC_SETUP_BARS_SIZE_1_MB]   = 0x2;
+        m[PROC_SETUP_BARS_SIZE_512_KB] = 0x1;
+        m[PROC_SETUP_BARS_SIZE_256_KB] = 0x0;
+        return m;
+    }
+    static const std::map<uint64_t, uint64_t> xlate_map;
+};
+
 // define set of MCD BAR sizes
 struct proc_setup_bars_mcd_bar_size
 {
@@ -844,6 +861,32 @@ const proc_setup_bars_bar_reg_def nx_mmio_bar_reg_def =
     0x0ULL
 };
 
+// AS MMIO BAR constants
+const proc_setup_bars_bar_def as_mmio_bar_def =
+{
+    0xFFFC000000000FFFULL,         // base: RA 14:51
+    PROC_SETUP_BARS_SIZE_4_KB,     // size (min): 4 KB
+    PROC_SETUP_BARS_SIZE_16_GB,    // size (max): 16 GB
+    true
+};
+
+const proc_setup_bars_bar_reg_def as_mmio_bar_reg_def =
+{
+    true,                          // base: bits 14:51
+    PROC_SETUP_BARS_SHIFT_NONE,
+    0,
+    14,
+    51,
+    true,                          // enable: bit 52
+    52,
+    true,                          // size: bits 53:55
+    53,
+    55,
+    &proc_setup_bars_as_mmio_bar_size::xlate_map,
+    0x0ULL,
+    0x0ULL
+};
+
 // MCD Configuration Register constants
 const proc_setup_bars_bar_def mcd_bar_def =
 {
@@ -1160,6 +1203,8 @@ extern "C"
 //              attribute content violates expected behavior,
 //          RC_PROC_SETUP_BARS_NX_MMIO_BAR_ATTR_ERR if chip NX MMIO range
 //              attribute content violates expected behavior,
+//          RC_PROC_SETUP_BARS_NX_MMIO_BAR_ATTR_ERR if chip AS MMIO range
+//              attribute content violates expected behavior,
 //          RC_PROC_SETUP_BARS_PCIE_BAR_ATTR_ERR if individual chip PCIe IO
 //              range attribute content violates expected behavior,
 //          RC_PROC_SETUP_BARS_NODE_ADD_INTERNAL_ERR if node map insert fails,
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_errors.xml b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_errors.xml
index 512fa602d..f61538e2a 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_errors.xml
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_errors.xml
@@ -1,25 +1,25 @@
-<!--  IBM_PROLOG_BEGIN_TAG
-     This is an automatically generated prolog.
-   
-     $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_errors.xml $
-   
-     IBM CONFIDENTIAL
-   
-     COPYRIGHT International Business Machines Corp. 2012
-   
-     p1
-   
-     Object Code Only (OCO) source materials
-     Licensed Internal Code Source Materials
-     IBM HostBoot Licensed Internal Code
-   
-     The source code for this program is not published or other-
-     wise divested of its trade secrets, irrespective of what has
-     been deposited with the U.S. Copyright Office.
-   
-     Origin: 30
-   
-     IBM_PROLOG_END_TAG -->
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_errors.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2012,2013              -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
 <!-- Error definitions for proc_setup_bars -->
 <hwpErrors>
   <!-- *********************************************************************** -->
@@ -97,6 +97,12 @@
     <ffdc>SIZE</ffdc>
   </hwpError>
   <hwpError>
+    <rc>RC_PROC_SETUP_BARS_AS_MMIO_BAR_ATTR_ERR</rc>
+    <description>Invalid definition for AS MMIO BAR address range (from platform attributes).</description>
+    <ffdc>BASE_ADDR</ffdc>
+    <ffdc>SIZE</ffdc>
+  </hwpError>
+  <hwpError>
     <rc>RC_PROC_SETUP_BARS_PCIE_BAR_ATTR_ERR</rc>
     <description>Invalid definition for PCIe BAR address range (from platform attributes).</description>
     <ffdc>UNIT</ffdc>
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml
index cbfe25851..4046388f3 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- IBM CONFIDENTIAL                                                       -->
 <!--                                                                        -->
-<!-- COPYRIGHT International Business Machines Corp. 2012                   -->
+<!-- COPYRIGHT International Business Machines Corp. 2012,2013              -->
 <!--                                                                        -->
 <!-- p1                                                                     -->
 <!--                                                                        -->
@@ -24,6 +24,28 @@
 <attributes>
   <!-- ********************************************************************* -->
   <attribute>
+    <id>ATTR_MEM_MIRROR_PLACEMENT_POLICY</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Define placement policy/scheme for non-mirrored/mirrored memory
+                 layout
+      creator: platform
+      consumer: opt_memmap
+      firmware notes:
+        NORMAL  = non-mirrored start: 0, mirrored start: 512TB
+        FLIPPED = mirrored start: 0, non-mirrored start: 512TB
+        SELECTIVE = non-mirrored/mirrored start (interleaved): 0
+    </description>
+    <valueType>uint8</valueType>
+    <enum>
+      NORMAL    = 0x0,
+      FLIPPED   = 0x1,
+      SELECTIVE = 0x2
+    </enum>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
     <id>ATTR_PROC_MEM_BASE</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>Base address for non-mirrored memory regions
@@ -222,4 +244,87 @@
     <persistRuntime/>
   </attribute>
   <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_HTM_BAR_SIZE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>Desired HTM trace memory size value
+      creator: platform
+      firmware notes:
+        set by platform to request size of per-chip area reserved
+        for HTM trace memory
+    </description>
+    <valueType>uint64</valueType>
+    <enum>
+      256_GB = 0x0000004000000000,
+      128_GB = 0x0000002000000000,
+       64_GB = 0x0000001000000000,
+       32_GB = 0x0000000800000000,
+       16_GB = 0x0000000400000000,
+        8_GB = 0x0000000200000000,
+        4_GB = 0x0000000100000000,
+        2_GB = 0x0000000080000000,
+        1_GB = 0x0000000040000000,
+      512_MB = 0x0000000020000000,
+      256_MB = 0x0000000010000000,
+      128_MB = 0x0000000008000000,
+       64_MB = 0x0000000004000000,
+       32_MB = 0x0000000002000000,
+       16_MB = 0x0000000001000000,
+        ZERO = 0x0000000000000000
+    </enum>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_HTM_BAR_BASE_ADDR</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>HTM trace memory base address allocated
+    </description>
+    <valueType>uint64</valueType>
+    <writeable/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_OCC_SANDBOX_SIZE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>Desired size of OCC sandbox memory region
+      creator: platform
+      firmware notes:
+        set by platform to request size of per-chip area reserved
+        for OCC sandbox function
+    </description>
+    <valueType>uint64</valueType>
+    <enum>
+      256_GB = 0x0000004000000000,
+      128_GB = 0x0000002000000000,
+       64_GB = 0x0000001000000000,
+       32_GB = 0x0000000800000000,
+       16_GB = 0x0000000400000000,
+        8_GB = 0x0000000200000000,
+        4_GB = 0x0000000100000000,
+        2_GB = 0x0000000080000000,
+        1_GB = 0x0000000040000000,
+      512_MB = 0x0000000020000000,
+      256_MB = 0x0000000010000000,
+      128_MB = 0x0000000008000000,
+       64_MB = 0x0000000004000000,
+       32_MB = 0x0000000002000000,
+       16_MB = 0x0000000001000000,
+        ZERO = 0x0000000000000000
+    </enum>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_OCC_SANDBOX_BASE_ADDR</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>OCC sandbox base address allocated
+    </description>
+    <valueType>uint64</valueType>
+    <writeable/>
+    <persistRuntime/>
+  </attribute>
 </attributes>
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml
index efede3a78..aa3423f5f 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml
@@ -1,25 +1,25 @@
-<!--  IBM_PROLOG_BEGIN_TAG
-     This is an automatically generated prolog.
-
-     $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml $
-
-     IBM CONFIDENTIAL
-
-     COPYRIGHT International Business Machines Corp. 2012
-
-     p1
-
-     Object Code Only (OCO) source materials
-     Licensed Internal Code Source Materials
-     IBM HostBoot Licensed Internal Code
-
-     The source code for this program is not published or other-
-     wise divested of its trade secrets, irrespective of what has
-     been deposited with the U.S. Copyright Office.
-
-     Origin: 30
-
-     IBM_PROLOG_END_TAG -->
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2012,2013              -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
 <!-- proc_setup_bars_mmio_attributes.xml -->
 <attributes>
   <!-- ********************************************************************* -->
@@ -163,6 +163,54 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
+    <id>ATTR_PROC_AS_MMIO_BAR_ENABLE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>AS MMIO BAR enable
+      creator: platform
+      consumer: proc_setup_bars
+      firmware notes: none
+    </description>
+    <valueType>uint8</valueType>
+    <enum>DISABLE = 0x0, ENABLE = 0x1</enum>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_AS_MMIO_BAR_BASE_ADDR</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>AS MMIO BAR base address value
+      creator: platform
+      consumer: proc_setup_bars
+      firmware notes:
+        64-bit address representing BAR RA
+        NOTE: BAR register covers RA 14:51
+    </description>
+    <valueType>uint64</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_AS_MMIO_BAR_SIZE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>AS MMIO BAR size value
+      creator: platform
+      consumer: proc_setup_bars
+      firmware notes: none
+    </description>
+    <valueType>uint64</valueType>
+    <enum>
+        2_MB = 0x0000000000200000,
+        1_MB = 0x0000000000100000,
+      512_KB = 0x0000000000080000,
+      256_KB = 0x0000000000040000
+    </enum>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
     <id>ATTR_PROC_NX_MMIO_BAR_ENABLE</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>NX MMIO BAR enable
@@ -303,4 +351,4 @@
     <persistRuntime/>
   </attribute>
   <!-- ********************************************************************* -->
-</attributes>
\ No newline at end of file
+</attributes>
diff --git a/src/usr/hwpf/hwp/include/p8_scom_addresses.H b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
index 95ecceed3..ede10ca8c 100755
--- a/src/usr/hwpf/hwp/include/p8_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_scom_addresses.H,v 1.149 2013/05/09 04:05:36 jmcgill Exp $
+// $Id: p8_scom_addresses.H,v 1.150 2013/05/15 04:22:35 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/p8_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -1113,9 +1113,16 @@ CONST_UINT64_T( X_TRACE_DATA_LO_T1_0x04010801         , ULL(0x04010801) );
 //------------------------------------------------------------------------------
 //      X-BUS PBEN
 //------------------------------------------------------------------------------
-CONST_UINT64_T( PB_X_MODE_0x04010C0A                  , ULL(0x04010C0A) );
+CONST_UINT64_T( PB_X_FIR_0x04010C00                   , ULL(0x04010C00) );
+CONST_UINT64_T( PB_X_FIR_AND_0x04010C01               , ULL(0x04010C01) );
+CONST_UINT64_T( PB_X_FIR_OR_0x04010C02                , ULL(0x04010C02) );
+CONST_UINT64_T( PB_X_FIR_MASK_0x04010803              , ULL(0x04010C03) );
+CONST_UINT64_T( PB_X_FIR_MASK_AND_0x04010804          , ULL(0x04010C04) );
+CONST_UINT64_T( PB_X_FIR_MASK_OR_0x04010805           , ULL(0x04010C05) );
+CONST_UINT64_T( PB_X_FIR_ACTION0_0x04010806           , ULL(0x04010C06) );
+CONST_UINT64_T( PB_X_FIR_ACTION1_0x04010807           , ULL(0x04010C07) );
 
-CONST_UINT64_T( X_PBEN_MISC_FIR_AND_0x04010C01       , ULL(0x04010C01) );
+CONST_UINT64_T( PB_X_MODE_0x04010C0A                  , ULL(0x04010C0A) );
 
 //------------------------------------------------------------------------------
 //      X-BUS IOPSI
@@ -1283,6 +1290,15 @@ CONST_UINT64_T( A_HANG_PRE_0x080F0028                 , ULL(0x080F0028) ); // AB
 //------------------------------------------------------------------------------
 //      A-BUS PBES
 //------------------------------------------------------------------------------
+CONST_UINT64_T( PB_A_FIR_0x08010800                   , ULL(0x08010800) );
+CONST_UINT64_T( PB_A_FIR_AND_0x08010801               , ULL(0x08010801) );
+CONST_UINT64_T( PB_A_FIR_OR_0x08010802                , ULL(0x08010802) );
+CONST_UINT64_T( PB_A_FIR_MASK_0x08010803              , ULL(0x08010803) );
+CONST_UINT64_T( PB_A_FIR_MASK_AND_0x08010804          , ULL(0x08010804) );
+CONST_UINT64_T( PB_A_FIR_MASK_OR_0x08010805           , ULL(0x08010805) );
+CONST_UINT64_T( PB_A_FIR_ACTION0_0x08010806           , ULL(0x08010806) );
+CONST_UINT64_T( PB_A_FIR_ACTION1_0x08010807           , ULL(0x08010807) );
+
 CONST_UINT64_T( PB_A_MODE_0x0801080A                  , ULL(0x0801080A) );
 CONST_UINT64_T( PB_A_TRACE_0x08010812                 , ULL(0x08010812) );
 CONST_UINT64_T( PB_A_FMR_CFG_0x08010813               , ULL(0x08010813) );
@@ -1380,8 +1396,25 @@ CONST_UINT64_T( PCIE_PERV_LFIR_ACT1_0x09040011        , ULL(0x09040011) );
 
 CONST_UINT64_T( ES_PBES_WRAP_TOP_FIR_AND_0x09010801   , ULL(0x09010801) );
 
-CONST_UINT64_T( PCIE_PLL_CNTL_FIR_AND_0x09011401      , ULL(0x09011401) );
-CONST_UINT64_T( PCIE_PLL1_CNTL_FIR_AND_0x09011841     , ULL(0x09011841) );
+CONST_UINT64_T( PCIE_IOP0_PLL_FIR_0x09011400          , ULL(0x09011400) );
+CONST_UINT64_T( PCIE_IOP0_PLL_FIR_AND_0x09011401      , ULL(0x09011401) );
+CONST_UINT64_T( PCIE_IOP0_PLL_FIR_OR_0x09011402       , ULL(0x09011402) );
+CONST_UINT64_T( PCIE_IOP0_PLL_FIR_MASK_0x09011403     , ULL(0x09011403) );
+CONST_UINT64_T( PCIE_IOP0_PLL_FIR_MASK_AND_0x09011404 , ULL(0x09011404) );
+CONST_UINT64_T( PCIE_IOP0_PLL_FIR_MASK_OR_0x09011405  , ULL(0x09011405) );
+CONST_UINT64_T( PCIE_IOP0_PLL_FIR_ACTION0_0x09011406  , ULL(0x09011406) );
+CONST_UINT64_T( PCIE_IOP0_PLL_FIR_ACTION1_0x09011407  , ULL(0x09011407) );
+CONST_UINT64_T( PCIE_IOP0_PLL_FIR_WOF_0x09011408      , ULL(0x09011408) );
+
+CONST_UINT64_T( PCIE_IOP1_PLL_FIR_0x09011840          , ULL(0x09011840) );
+CONST_UINT64_T( PCIE_IOP1_PLL_FIR_AND_0x09011841      , ULL(0x09011841) );
+CONST_UINT64_T( PCIE_IOP1_PLL_FIR_OR_0x09011842       , ULL(0x09011842) );
+CONST_UINT64_T( PCIE_IOP1_PLL_FIR_MASK_0x09011843     , ULL(0x09011843) );
+CONST_UINT64_T( PCIE_IOP1_PLL_FIR_MASK_AND_0x09011844 , ULL(0x09011844) );
+CONST_UINT64_T( PCIE_IOP1_PLL_FIR_MASK_OR_0x09011845  , ULL(0x09011845) );
+CONST_UINT64_T( PCIE_IOP1_PLL_FIR_ACTION0_0x09011846  , ULL(0x09011846) );
+CONST_UINT64_T( PCIE_IOP1_PLL_FIR_ACTION1_0x09011847  , ULL(0x09011847) );
+CONST_UINT64_T( PCIE_IOP1_PLL_FIR_WOF_0x09011848      , ULL(0x09011848) );
 
 //------------------------------------------------------------------------------
 //      PLL LOCK
@@ -1892,6 +1925,9 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: p8_scom_addresses.H,v $
+Revision 1.150  2013/05/15 04:22:35  jmcgill
+add PB X/A, PCI IOP PLL FIR register addresses
+
 Revision 1.149  2013/05/09 04:05:36  jmcgill
 add AS MMIO BAR
 
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C
index 0c564c3b4..6a6650ad7 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_termination.C,v 1.18 2013/04/10 16:31:47 lapietra Exp $
+// $Id: mss_eff_config_termination.C,v 1.21 2013/05/07 23:04:38 lapietra Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_termination.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -30,7 +30,7 @@
 // *! TITLE       : mss_eff_config_termination
 // *! DESCRIPTION : see additional comments below
 // *! OWNER NAME  : Dave Cadigan      Email: dcadiga@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
+// *! BACKUP NAME : Anuwat Saetow     Email: asaetow@us.ibm.com
 // *! ADDITIONAL COMMENTS :
 //
 // This procedure is a place holder for attributes set by the machine parsable workbook.
@@ -42,6 +42,9 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//   1.21  | dcadiga  |07-MAY-13| Fixed RC/A Clk Drive and Impedance Settings, Added RC B4 and some patches to make it work, Added in fix for AL in 2N mode
+//   1.20  | dcadiga  |30-APR-13| Fixed Hostboot Compile Error LN 972
+//   1.19  | dcadiga  |19-APR-13| Added Cdimm RCB/RCC, changed RDIMM settings for MBA0 so that a 1R card will work and a 4R card will work
 //   1.18  | dcadiga  |10-APR-13| Added UDIMM for ICICLE DDR4, fixed DD0 Clk shift
 //   1.17  | asaetow  |26-MAR-13| Removed width check for RDIMM MBA0 4Rank 1333. 
 //   1.16  | dcadiga  |25-MAR-13| Added in 2N Addressing Mode.
@@ -101,7 +104,7 @@ uint8_t attr_eff_odt_rd[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
 uint8_t attr_eff_odt_wr[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
 uint32_t attr_eff_cen_rd_vref[PORT_SIZE];
 uint32_t attr_eff_dram_wr_vref[PORT_SIZE];
-//uint8_t attr_eff_dram_wrddr4_vref[PORT_SIZE];
+uint8_t attr_eff_dram_wrddr4_vref[PORT_SIZE];
 uint8_t attr_eff_cen_rcv_imp_dq_dqs[PORT_SIZE];
 uint8_t attr_eff_cen_drv_imp_dq_dqs[PORT_SIZE];
 uint8_t attr_eff_cen_drv_imp_cntl[PORT_SIZE];
@@ -162,6 +165,7 @@ uint8_t attr_eff_cen_phase_rot_m1_cntl_csn3[PORT_SIZE];
 uint8_t attr_eff_cen_phase_rot_m1_cntl_odt0[PORT_SIZE];
 uint8_t attr_eff_cen_phase_rot_m1_cntl_odt1[PORT_SIZE];
 uint8_t attr_eff_dram_2n_mode_enabled;
+uint8_t attr_eff_dram_al;
 
 /*
 const uint8_t valid_attrs[200] = {
@@ -370,35 +374,35 @@ attr_eff_cen_phase_rot_m1_cntl_odt1[1]
 //Declare the different dimms here:
 //Cdimm rc_A
 uint32_t cdimm_rca_1r_1333_mba0[200] = 
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,89,0,91,0,13,13,13,8,5,6,8,7,9,13,17,14,14,14,13,17,12,11,17,18,17,18,0,0,19,0,21,0,0,0,0,0,2,0,19,0,0,0,7,0,0,0,3,0,86,0,92,0,17,15,18,8,6,5,7,6,12,12,18,12,16,15,13,16,10,9,17,18,21,19,0,0,19,0,24,0,2,0,0,0,2,0,20,0,0,0,3,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
+{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,89,0,91,0,13,13,13,8,5,6,8,7,9,13,17,14,14,14,13,17,12,11,17,18,17,18,0,0,19,0,21,0,0,0,0,0,2,0,19,0,0,0,7,0,0,0,3,0,86,0,92,0,17,15,18,8,6,5,7,6,12,12,18,12,16,15,13,16,10,9,17,18,21,19,0,0,19,0,24,0,2,0,0,0,2,0,20,0,0,0,3,0,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
 };
 
 uint32_t cdimm_rca_1r_1333_mba1[200] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,87,0,92,0,18,18,18,11,11,11,13,13,15,18,16,18,17,20,18,15,9,11,14,15,18,14,0,0,26,0,32,0,11,0,0,0,3,0,29,0,0,0,2,0,0,0,10,0,86,0,91,0,12,13,15,6,7,9,9,8,9,15,11,15,12,14,15,12,6,7,12,12,11,11,0,0,17,0,31,0,1,0,0,0,0,0,17,0,0,0,6,0,0,0,1,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
+{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,87,0,92,0,18,18,18,11,11,11,13,13,15,18,16,18,17,20,18,15,9,11,14,15,18,14,0,0,26,0,32,0,11,0,0,0,3,0,29,0,0,0,2,0,0,0,10,0,86,0,91,0,12,13,15,6,7,9,9,8,9,15,11,15,12,14,15,12,6,7,12,12,11,11,0,0,17,0,31,0,1,0,0,0,0,0,17,0,0,0,6,0,0,0,1,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
 };
 
 uint32_t cdimm_rca_1r_1600_mba0[200] = 
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,93,0,96,0,15,16,15,10,7,7,10,9,11,15,20,16,17,16,16,20,14,13,21,22,21,21,0,0,24,0,27,0,0,0,0,0,2,0,24,0,0,0,9,0,0,0,4,0,90,0,98,0,20,18,21,10,7,7,9,7,15,14,22,15,20,18,16,20,12,11,21,22,25,23,0,0,24,0,30,0,3,0,0,0,2,0,25,0,0,0,4,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
+{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,93,0,96,0,15,16,15,10,7,7,10,9,11,15,20,16,17,16,16,20,14,13,21,22,21,21,0,0,24,0,27,0,0,0,0,0,2,0,24,0,0,0,9,0,0,0,4,0,90,0,98,0,20,18,21,10,7,7,9,7,15,14,22,15,20,18,16,20,12,11,21,22,25,23,0,0,24,0,30,0,3,0,0,0,2,0,25,0,0,0,4,0,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
 };
 
 uint32_t cdimm_rca_1r_1600_mba1[200] = 
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,91,0,97,0,22,22,21,14,13,14,16,15,19,21,19,22,21,24,22,18,11,13,17,18,22,17,0,0,32,0,39,0,13,0,0,0,3,0,35,0,0,0,3,0,0,0,12,0,90,0,96,0,15,16,18,8,9,10,11,10,11,18,13,18,15,17,18,15,8,8,14,15,13,13,0,0,22,0,38,0,1,0,0,0,0,0,22,0,0,0,7,0,0,0,1,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
+{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,91,0,97,0,22,22,21,14,13,14,16,15,19,21,19,22,21,24,22,18,11,13,17,18,22,17,0,0,32,0,39,0,13,0,0,0,3,0,35,0,0,0,3,0,0,0,12,0,90,0,96,0,15,16,18,8,9,10,11,10,11,18,13,18,15,17,18,15,8,8,14,15,13,13,0,0,22,0,38,0,1,0,0,0,0,0,22,0,0,0,7,0,0,0,1,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
 };
 
 uint32_t cdimm_rca_2r_1333_mba0[200] = 
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,95,0,103,0,6,7,7,3,0,0,3,2,4,6,11,8,8,7,7,11,6,6,11,12,11,12,0,0,31,0,24,0,12,0,0,0,14,0,31,0,34,0,19,0,0,0,15,0,90,0,99,0,11,9,12,2,0,0,1,0,7,5,12,6,10,9,7,10,4,4,11,12,15,13,0,0,32,0,27,0,14,0,0,0,14,0,33,0,33,0,15,0,0,0,12,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
+{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,95,0,103,0,6,7,7,3,0,0,3,2,4,6,11,8,8,7,7,11,6,6,11,12,11,12,0,0,31,0,24,0,12,0,0,0,14,0,31,0,34,0,19,0,0,0,15,0,90,0,99,0,11,9,12,2,0,0,1,0,7,5,12,6,10,9,7,10,4,4,11,12,15,13,0,0,32,0,27,0,14,0,0,0,14,0,33,0,33,0,15,0,0,0,12,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
 };
 
 uint32_t cdimm_rca_2r_1333_mba1[200] = 
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,90,0,98,0,11,11,10,5,4,5,6,6,9,10,8,11,10,13,11,8,3,4,7,7,11,7,0,0,38,0,34,0,21,0,0,0,14,0,41,0,34,0,13,0,0,0,21,0,91,0,99,0,7,8,10,2,2,4,4,3,5,10,5,10,7,9,10,7,1,2,6,7,5,5,0,0,31,0,36,0,14,0,0,0,13,0,31,0,32,0,19,0,0,0,13,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
+{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,90,0,98,0,11,11,10,5,4,5,6,6,9,10,8,11,10,13,11,8,3,4,7,7,11,7,0,0,38,0,34,0,21,0,0,0,14,0,41,0,34,0,13,0,0,0,21,0,91,0,99,0,7,8,10,2,2,4,4,3,5,10,5,10,7,9,10,7,1,2,6,7,5,5,0,0,31,0,36,0,14,0,0,0,13,0,31,0,32,0,19,0,0,0,13,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
 };
 
 uint32_t cdimm_rca_2r_1600_mba0[200] = 
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,100,0,109,0,9,9,9,3,0,0,3,2,4,8,14,10,10,10,9,14,7,6,14,15,14,15,0,0,37,0,29,0,14,0,0,0,16,0,37,0,40,0,23,0,0,0,17,0,95,0,105,0,13,11,14,3,0,0,2,0,8,7,15,8,13,11,9,13,5,4,14,15,18,16,0,0,38,0,32,0,16,0,0,0,16,0,39,0,40,0,18,0,0,0,14,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
+{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,100,0,109,0,9,9,9,3,0,0,3,2,4,8,14,10,10,10,9,14,7,6,14,15,14,15,0,0,37,0,29,0,14,0,0,0,16,0,37,0,40,0,23,0,0,0,17,0,95,0,105,0,13,11,14,3,0,0,2,0,8,7,15,8,13,11,9,13,5,4,14,15,18,16,0,0,38,0,32,0,16,0,0,0,16,0,39,0,40,0,18,0,0,0,14,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
 };
 
 uint32_t cdimm_rca_2r_1600_mba1[200] = 
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,95,0,104,0,14,14,13,6,5,6,8,8,11,13,11,14,12,16,14,10,3,5,9,9,13,9,0,0,44,0,40,0,25,0,0,0,16,0,47,0,41,0,15,0,0,0,24,0,96,0,104,0,9,10,12,2,3,4,5,4,5,12,7,12,8,11,12,9,1,2,8,9,7,7,0,0,37,0,42,0,15,0,0,0,15,0,36,0,38,0,21,0,0,0,15,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
+{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,95,0,104,0,14,14,13,6,5,6,8,8,11,13,11,14,12,16,14,10,3,5,9,9,13,9,0,0,44,0,40,0,25,0,0,0,16,0,47,0,41,0,15,0,0,0,24,0,96,0,104,0,9,10,12,2,3,4,5,4,5,12,7,12,8,11,12,9,1,2,8,9,7,7,0,0,37,0,42,0,15,0,0,0,15,0,36,0,38,0,21,0,0,0,15,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
 };
 
 //Cdimm rc_A DD1.0
@@ -433,6 +437,67 @@ uint32_t cdimm_rca_2r_1600_mba1_DD10[200] =
 {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,72,0,0,64,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,12,0,8,0,0,0,0,0,0,0,15,0,9,0,0,0,0,0,0,64,64,0,72,0,0,0,0,0,0,0,0,0,0,0,64,0,0,0,0,0,0,0,0,0,0,0,0,0,5,0,10,0,64,0,0,0,64,0,4,0,6,0,0,0,64,0,0,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
 };
 
+//RCB
+
+uint32_t cdimm_rcb_2r_1333_mba0[200] =
+{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,102,100,100,101,1,2,2,3,0,0,4,2,4,1,7,3,3,2,2,7,8,7,7,8,7,8,0,0,22,0,29,0,19,0,0,0,21,0,22,0,31,0,29,0,0,0,23,0,96,110,98,109,6,4,7,4,1,1,3,1,9,0,7,1,5,4,2,6,6,5,6,8,11,9,0,0,22,0,26,0,23,0,0,0,22,0,24,0,26,0,25,0,0,0,20,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
+
+};
+
+uint32_t cdimm_rcb_2r_1333_mba1[200] =
+{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,98,99,98,100,9,9,9,4,3,4,6,6,10,9,5,9,8,12,10,5,0,3,3,4,9,3,0,0,16,0,44,0,20,0,0,0,1,0,18,0,45,0,1,0,0,0,18,0,100,99,100,99,5,6,9,1,2,3,4,3,4,9,3,9,5,8,9,5,0,1,4,5,3,3,0,0,6,0,40,0,4,0,0,0,4,0,6,0,39,0,14,0,0,0,4,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
+
+};
+
+uint32_t cdimm_rcb_2r_1600_mba0[200] =
+{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,108,106,106,108,2,2,2,3,0,0,4,2,5,1,7,3,4,3,2,7,8,7,8,9,8,8,0,0,29,0,37,0,24,0,0,0,27,0,29,0,39,0,36,0,0,0,29,0,99,119,101,119,7,5,8,4,1,1,3,1,10,0,8,1,6,5,2,6,7,6,7,9,13,10,0,0,28,0,29,0,27,0,0,0,27,0,29,0,30,0,29,0,0,0,23,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
+
+};
+
+uint32_t cdimm_rcb_2r_1600_mba1[200] =
+{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,105,112,105,112,10,10,9,4,3,4,6,6,10,9,6,10,8,13,10,5,0,3,3,4,9,3,0,0,22,0,53,0,26,0,0,0,10,0,25,0,54,0,10,0,0,0,25,0,108,106,109,106,6,7,10,1,2,4,5,4,5,11,4,10,5,9,10,6,0,1,4,6,3,3,0,0,8,0,49,0,7,0,0,0,6,0,8,0,48,0,18,0,0,0,7,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
+
+};
+
+//RCB4
+
+
+uint32_t cdimm_rcb4_2r_1600_mba0[200] =
+{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,108,106,106,108,2,2,2,3,0,0,4,2,5,1,7,3,4,3,2,7,8,7,8,9,8,8,0,9,29,0,37,0,24,0,0,0,27,0,29,0,39,0,36,0,0,0,29,0,99,119,101,119,7,5,8,4,1,1,3,1,10,0,8,1,6,5,2,6,7,6,7,9,13,10,0,3,28,0,29,0,27,0,0,0,27,0,29,0,30,0,29,0,0,0,23,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
+
+};
+
+uint32_t cdimm_rcb4_2r_1600_mba1[200] =
+{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS,105,112,105,112,10,10,9,4,3,4,6,6,10,9,6,10,8,13,10,5,0,3,3,4,9,3,0,4,22,0,53,0,26,0,0,0,10,0,25,0,54,0,10,0,0,0,25,0,108,106,109,106,6,7,10,1,2,4,5,4,5,11,4,10,5,9,10,6,0,1,4,6,3,3,0,3,8,0,49,0,7,0,0,0,6,0,8,0,48,0,18,0,0,0,7,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
+
+};
+
+
+//RCC
+
+uint32_t cdimm_rcc_2r_1333_mba0[200] =
+{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,94,0,95,0,19,19,19,19,17,16,18,14,19,19,22,20,20,19,19,23,20,18,22,25,24,24,0,0,0,0,64,0,5,0,0,0,8,0,0,0,66,0,16,0,0,0,10,0,91,0,95,0,22,20,23,18,16,15,17,13,22,17,22,17,21,21,18,22,18,16,21,24,27,25,0,0,0,0,63,0,7,0,0,0,6,0,1,0,64,0,9,0,0,0,3,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
+
+};
+
+uint32_t cdimm_rcc_2r_1333_mba1[200] =
+{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,84,0,86,0,12,12,11,13,13,12,13,10,18,11,9,12,11,14,12,9,8,8,7,9,12,8,0,0,1,0,62,0,12,0,0,0,0,0,4,0,62,0,0,0,0,0,11,0,94,0,96,0,20,21,23,20,21,22,22,18,19,24,17,23,18,20,23,20,16,15,18,20,18,18,0,0,0,0,67,0,2,0,0,0,2,0,0,0,66,0,11,0,0,0,2,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
+
+};
+
+uint32_t cdimm_rcc_2r_1600_mba0[200] =
+{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,101,0,100,0,21,22,22,22,20,18,21,13,22,21,25,23,23,22,22,26,22,20,25,28,27,27,0,0,0,0,79,0,4,0,0,0,8,0,0,0,82,0,19,0,0,0,10,0,98,0,102,0,27,25,28,23,21,18,20,13,28,21,26,22,26,25,23,26,21,19,26,29,31,29,0,0,0,0,81,0,11,0,0,0,11,0,1,0,82,0,14,0,0,0,7,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
+
+};
+
+uint32_t cdimm_rcc_2r_1600_mba1[200] =
+{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,90,0,91,0,15,15,15,16,16,15,17,11,21,15,12,15,14,18,15,12,8,10,10,12,15,11,0,0,3,0,79,0,17,0,0,0,1,0,6,0,80,0,0,0,0,0,16,0,101,0,102,0,23,24,27,23,25,25,25,18,22,28,21,28,22,24,27,23,18,18,21,23,21,21,0,0,0,0,84,0,4,0,0,0,3,0,0,0,83,0,14,0,0,0,4,0,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_EFF_DRAM_2N_MODE_ENABLED_FALSE
+
+};
+
+
+
+
 
 //RDIMM A/B Ports MBA0 Glacier
 uint32_t rdimm_glacier_1600_r10_mba0[200] = 
@@ -549,6 +614,7 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) {
    uint32_t l_mss_volt = 0;
    uint8_t l_nwell_misplacement = 0;
    uint8_t l_num_ranks_per_dimm_u8array[PORT_SIZE][DIMM_SIZE];
+   uint8_t l_stack_type_u8array[PORT_SIZE][DIMM_SIZE];
    // ATTR_EFF_DRAM_GEN: EMPTY = 0, DDR3 = 1, DDR4 = 2, 
    uint8_t l_dram_gen_u8;
    // ATTR_EFF_DIMM_TYPE: CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3,
@@ -566,13 +632,17 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) {
       FAPI_ERR("Invalid ATTR_MSS_FREQ = %d on %s!", l_mss_freq, i_target_mba.toEcmdString());
       FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
    }
+   rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_AL, &i_target_mba, attr_eff_dram_al); if(rc) return rc;
    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm_u8array); if(rc) return rc;
+   rc = FAPI_ATTR_GET(ATTR_EFF_STACK_TYPE, &i_target_mba, l_stack_type_u8array); if(rc) return rc;
    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target_mba, l_dram_gen_u8); if(rc) return rc;
    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, l_dimm_type_u8); if(rc) return rc;
    rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_dimm_custom_u8); if(rc) return rc;
    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, l_num_drops_per_port); if(rc) return rc;
    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width_u8); if(rc) return rc;
-
+   
+   
+   
 
    // Fetch impacted attributes
    uint64_t l_attr_eff_dimm_rcd_cntl_word_0_15[PORT_SIZE][DIMM_SIZE];
@@ -585,7 +655,8 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) {
 
    // Define local attribute variables
    uint8_t l_attr_mss_cal_step_enable = 0xFF;
-   
+   //DEBUG MESSAGE!
+   FAPI_INF("DRAM GEN %d WIDTH %d 00R %d 10R %d 01R %d 11R %d DPP %d stack %d\n",l_dram_gen_u8,l_dram_width_u8,l_num_ranks_per_dimm_u8array[0][0],l_num_ranks_per_dimm_u8array[1][0],l_num_ranks_per_dimm_u8array[0][1],l_num_ranks_per_dimm_u8array[1][1],l_num_drops_per_port,l_stack_type_u8array[0][0]);
 
    //Now, Determine The Type Of Dimm We Are Using
    //l_target_mba_pos == 0,1 - MBA POS
@@ -613,8 +684,8 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) {
    else if( (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM) ){ 
       if((l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM) ){
          //This is a CDIMM!
-         if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){
-            //1R Cdimm
+         if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 8) && (l_stack_type_u8array[0][0] == 0) && (l_dram_gen_u8 == 1)){
+            //1R Cdimm RCA
             if ( l_mss_freq <= 1466 ) { // 1333Mbps
                if((l_target_mba_pos == 0) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_FALSE)){
 	          memcpy(base_var_array,cdimm_rca_1r_1333_mba0,200*sizeof(uint32_t));
@@ -671,8 +742,8 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) {
             }//1600 1R
 
 	 }//1R CDIMM
-         else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){
-            //2R Cdimm
+         else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 8) && (l_stack_type_u8array[0][0] == 0) && (l_dram_gen_u8 == 1)){
+            //2R Cdimm RCA
             if ( l_mss_freq <= 1466 ) { // 1333Mbps
                if((l_target_mba_pos == 0) && (l_nwell_misplacement == fapi::ENUM_ATTR_MSS_NWELL_MISPLACEMENT_FALSE)){
 	          memcpy(base_var_array,cdimm_rca_2r_1333_mba0,200*sizeof(uint32_t));
@@ -696,7 +767,7 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) {
 
                }
                else{
-                  FAPI_ERR("Invalid Dimm Type CDIMM FREQ %d\n",l_mss_freq);
+                  FAPI_ERR("Invalid Dimm Type CDIMM RCA FREQ %d\n",l_mss_freq);
                   FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
                }
             } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
@@ -722,16 +793,111 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) {
 
                }
                else{
-                  FAPI_ERR("Invalid Dimm Type CDIMM FREQ %d\n",l_mss_freq);
+                  FAPI_ERR("Invalid Dimm Type CDIMM RCA FREQ %d\n",l_mss_freq);
                   FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
                }
                
             }//1600 2R
-	 }//2R CDIMM
-         else{
-            FAPI_ERR("Invalid Dimm Type CDIMM FREQ %d\n",l_mss_freq);
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
-         }
+	 }//2R CDIMM RCA
+         else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4) && (l_stack_type_u8array[0][0] == 0) && (l_dram_gen_u8 == 1)){
+            //2R Cdimm RCB
+            if ( l_mss_freq <= 1466 ) { // 1333Mbps
+	       if(l_target_mba_pos == 0){
+                  memcpy(base_var_array,cdimm_rcb_2r_1333_mba0,200*sizeof(uint32_t));
+                  FAPI_INF("CDIMM rcb_2r_1333 MBA0 \n");
+  
+	       
+	       }
+	       else if(l_target_mba_pos == 1){
+                  memcpy(base_var_array,cdimm_rcb_2r_1333_mba1,200*sizeof(uint32_t));
+                  FAPI_INF("CDIMM rcb_2r_1333 MBA1 \n");
+	       
+	       }
+               else{
+                  FAPI_ERR("Invalid Dimm Type CDIMM RCB FREQ %d\n",l_mss_freq);
+                  FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+               }
+	       
+            } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
+	       if(l_target_mba_pos == 0){
+                  memcpy(base_var_array,cdimm_rcb_2r_1600_mba0,200*sizeof(uint32_t));
+                  FAPI_INF("CDIMM rcb_2r_1600 MBA0 \n");
+  
+	       
+	       }
+	       else if(l_target_mba_pos == 1){
+                  memcpy(base_var_array,cdimm_rcb_2r_1600_mba1,200*sizeof(uint32_t));
+                  FAPI_INF("CDIMM rcb_2r_1600 MBA1 \n");
+	       
+	       }
+              else{
+                 FAPI_ERR("Invalid Dimm Type CDIMM RCB FREQ %d\n",l_mss_freq);
+                 FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+              }
+            }
+         }//CDIMM RCB
+         else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[1][0] == 1)  && ((l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) || (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE))  && (l_dram_width_u8 == 4) && (l_stack_type_u8array[0][0] == 0) && (l_dram_gen_u8 == 2)){
+            //2R Cdimm RCB4
+            if ( l_mss_freq <= 1733 ) { // 1600Mbps
+	       if(l_target_mba_pos == 0){
+                  memcpy(base_var_array,cdimm_rcb4_2r_1600_mba0,200*sizeof(uint32_t));
+                  FAPI_INF("CDIMM rcb4_2r_1600 MBA0 \n");
+  
+	       
+	       }
+	       else if(l_target_mba_pos == 1){
+                  memcpy(base_var_array,cdimm_rcb4_2r_1600_mba1,200*sizeof(uint32_t));
+                  FAPI_INF("CDIMM rcb4_2r_1600 MBA1 \n");
+	       
+	       }
+              else{
+                 FAPI_ERR("Invalid Dimm Type CDIMM RCB4 FREQ %d\n",l_mss_freq);
+                 FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+              }
+            }
+         }//CDIMM RCB4
+         else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4) && (l_stack_type_u8array[0][0] == 1)  && (l_dram_gen_u8 == 1)){
+            //2R Cdimm RCC
+            if ( l_mss_freq <= 1466 ) { // 1333Mbps
+	       if(l_target_mba_pos == 0){
+                  memcpy(base_var_array,cdimm_rcc_2r_1333_mba0,200*sizeof(uint32_t));
+                  FAPI_INF("CDIMM rcc_2r_1333 MBA0 \n");
+  
+	       
+	       }
+	       else if(l_target_mba_pos == 1){
+                  memcpy(base_var_array,cdimm_rcc_2r_1333_mba1,200*sizeof(uint32_t));
+                  FAPI_INF("CDIMM rcc_2r_1333 MBA1 \n");
+	       
+	       }
+               else{
+                  FAPI_ERR("Invalid Dimm Type CDIMM RCC FREQ %d\n",l_mss_freq);
+                  FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+               }
+	       
+            } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
+	       if(l_target_mba_pos == 0){
+                  memcpy(base_var_array,cdimm_rcc_2r_1600_mba0,200*sizeof(uint32_t));
+                  FAPI_INF("CDIMM rcc_2r_1600 MBA0 \n");
+  
+	       
+	       }
+	       else if(l_target_mba_pos == 1){
+                  memcpy(base_var_array,cdimm_rcc_2r_1600_mba1,200*sizeof(uint32_t));
+                  FAPI_INF("CDIMM rcc_2r_1600 MBA1 \n");
+	       
+	       }
+              else{
+                 FAPI_ERR("Invalid Dimm Type CDIMM RCC FREQ %d\n",l_mss_freq);
+                 FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+              }
+            }
+         }//CDIMM RCC
+	 else{
+	       FAPI_ERR("Invalid Dimm Type");
+               FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+
+	 }
       }//End CDIMM
       else{
          //This is a UDIMM!
@@ -778,10 +944,16 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) {
    else if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ){
       if( l_target_mba_pos == 0){
          if ( l_mss_freq <= 1466 ) { // 1333Mbps
+	 
             if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 4)){
                memcpy(base_var_array,rdimm_glacier_1333_r20e_mba0,200*sizeof(uint32_t));
                FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
             }
+	    else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){
+	       //Removed Width Check, use settings for either x8 or x4, use 1600 settings for 1333!
+               memcpy(base_var_array,rdimm_glacier_1600_r10_mba0,200*sizeof(uint32_t));
+               FAPI_INF("RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
+            }
             else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 8)){
                memcpy(base_var_array,rdimm_glacier_1333_r20b_mba0,200*sizeof(uint32_t));
                FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
@@ -796,18 +968,27 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) {
             }
 
          } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
-            if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 8)){
+            if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){
+	       //Removed Width Check, use settings for either x8 or x4
                memcpy(base_var_array,rdimm_glacier_1600_r10_mba0,200*sizeof(uint32_t));
                FAPI_INF("RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
             }
             else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 4)){
+		
                memcpy(base_var_array,rdimm_glacier_1600_r20e_mba0,200*sizeof(uint32_t));
                FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
+	       
             }
             else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 8)){
                memcpy(base_var_array,rdimm_glacier_1600_r20b_mba0,200*sizeof(uint32_t));
                FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
             }
+	    else if((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){
+	       //USE 1333 settings at 1600
+               memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,200*sizeof(uint32_t));
+               FAPI_INF("RDIMM r40 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
+            }
+
             else{
                FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d MBA0\n",l_mss_freq);
                FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
@@ -854,6 +1035,13 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) {
                memcpy(base_var_array,rdimm_glacier_1333_r22b_mba1,200*sizeof(uint32_t)); 
                FAPI_INF("RDIMM r22b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); 
             }        
+            else if((((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 0))) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){
+	       //Use 4R MBA0 settings for CD only!
+               memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,200*sizeof(uint32_t));
+               FAPI_INF("RDIMM r40 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
+            }
+
+
             else{
                FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d HERE MBA1\n",l_mss_freq);
                FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
@@ -869,8 +1057,9 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) {
                FAPI_INF("RDIMM r11 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
             }        
             else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 4)){  
-               memcpy(base_var_array,rdimm_glacier_1600_r20e_mba1,200*sizeof(uint32_t));  
-               FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
+	       memcpy(base_var_array,rdimm_glacier_1600_r20e_mba1,200*sizeof(uint32_t)); 
+	       FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
+	       
             }        
             else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 8)){  
                memcpy(base_var_array,rdimm_glacier_1600_r20b_mba1,200*sizeof(uint32_t));
@@ -1048,10 +1237,17 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) {
    attr_eff_odt_wr[1][1][3] = base_var_array[i++];
    attr_eff_cen_rd_vref[0] = base_var_array[i++];
    attr_eff_cen_rd_vref[1] = base_var_array[i++];
-   attr_eff_dram_wr_vref[0] = base_var_array[i++];
-   attr_eff_dram_wr_vref[1] = base_var_array[i++];
-   //attr_eff_dram_wrddr4_vref[0] = base_var_array[i++];
-   //attr_eff_dram_wrddr4_vref[1] = base_var_array[i++];
+   if(l_dram_gen_u8 == 1){
+      attr_eff_dram_wr_vref[0] = base_var_array[i++];
+      attr_eff_dram_wr_vref[1] = base_var_array[i++];
+   }
+   else if(l_dram_gen_u8 == 2){
+      attr_eff_dram_wrddr4_vref[0] = base_var_array[i++];
+      attr_eff_dram_wrddr4_vref[1] = base_var_array[i++];
+      //THIS IS A HACK FOR RC B4!!
+      attr_eff_dram_wrddr4_vref[0] = 16;
+      attr_eff_dram_wrddr4_vref[1] = 16;
+   }
    attr_eff_cen_rcv_imp_dq_dqs[0] = base_var_array[i++];
    attr_eff_cen_rcv_imp_dq_dqs[1] = base_var_array[i++];
    attr_eff_cen_drv_imp_dq_dqs[0] = base_var_array[i++];
@@ -1269,6 +1465,9 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) {
    rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RON, &i_target_mba, attr_eff_dram_ron); if(rc) return rc;
    rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RTT_NOM, &i_target_mba, attr_eff_dram_rtt_nom); if(rc) return rc;
    rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RTT_WR, &i_target_mba, attr_eff_dram_rtt_wr); if(rc) return rc;
+   if(l_dram_gen_u8 == 2){
+      rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WRDDR4_VREF, &i_target_mba, attr_eff_dram_wrddr4_vref); if(rc) return rc;
+   }
    rc = FAPI_ATTR_SET(ATTR_EFF_ODT_RD, &i_target_mba, attr_eff_odt_rd); if(rc) return rc;
    rc = FAPI_ATTR_SET(ATTR_EFF_ODT_WR, &i_target_mba, attr_eff_odt_wr); if(rc) return rc;
    rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0, &i_target_mba, attr_eff_cen_phase_rot_m0_clk_p0); if(rc) return rc;
@@ -1320,8 +1519,16 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) {
    rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_odt0); if(rc) return rc;
    rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1, &i_target_mba, attr_eff_cen_phase_rot_m1_cntl_odt1); if(rc) return rc;
    rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_2N_MODE_ENABLED, &i_target_mba, attr_eff_dram_2n_mode_enabled); if(rc) return rc;
-
-
+   
+   //Set AL to be 1 less IF 2N Mode Is Enabled
+   if(attr_eff_dram_2n_mode_enabled){
+      FAPI_INF("Changing Additive Latency For 2N Mode\nCurrent AL IS %d\n",attr_eff_dram_al);
+      if(attr_eff_dram_al == 1){
+         attr_eff_dram_al = 2;
+      }
+      rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_AL, &i_target_mba, attr_eff_dram_al); if(rc) return rc;
+   
+   }
 
    FAPI_INF("%s on %s COMPLETE", PROCEDURE_NAME, i_target_mba.toEcmdString());
    return rc;
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.C
index 9725ece00..4dc08f9fd 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.C
@@ -20,253 +20,1179 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: opt_memmap.C,v 1.6 2013/02/22 22:27:34 vanlee Exp $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012, 2013
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//------------------------------------------------------------------------------
-// *! TITLE       : opt_memmap.C
-// *! DESCRIPTION : see additional comments below
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
+// $Id: opt_memmap.C,v 1.8 2013/05/06 15:15:36 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/opt_memmap.C,v $
+
+
 //------------------------------------------------------------------------------
-//Owner :- Girisankar paulraj
-//Back-up owner :- Mark bellows
-//
 // CHANGE HISTORY:
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
-//  1.1    | vanlee   | 12/01/12| First drop
-//  1.4    | vanlee   | 01/04/13| Added version string
-//  1.5    | vanlee   | 02/20/13| Add init paramter
+//  1.8    | jmcgill  | 04/28/13| Add HTM/OCC memory allocation, fix namespace
+//  1.7    | jmcgill  | 04/20/13| Rewrite to add additional sorting capabilities
+//         |          |         | desired for exercisor mirroring testing
 //  1.6    | vanlee   | 02/22/13| Update sort logic of ProcBase class
+//  1.5    | vanlee   | 02/20/13| Add init paramter
+//  1.4    | vanlee   | 01/04/13| Added version string
+//  1.1    | vanlee   | 12/01/12| First drop
+//------------------------------------------------------------------------------
+
 //------------------------------------------------------------------------------
-// Design flow
+// Design flow:
 //
-// opt_memmap() is run alternatively between two mss_eff_grouping() calls.
+// opt_memmap() interacts with mss_eff_grouping() to define the assignment
+// of non-mirrored/mirrored real address space on each chip in the system
+//
+// opt_memmap() will be called twice in the IPL flow, once before and once
+// after mss_eff_grouping()
 //
 // 1) Call opt_memmap() with i_init = true
 //    - Each proc's ATTR_PROC_MEM_BASE attribute is set to 0
 //    - Each proc's ATTR_PROC_MIRROR_BASE attribute is set to 512TB
-// 2) First mss_eff_grouping() call
+//
+//    This provides a basis for mss_eff_grouping() to stack all on-chip
+//    groups.
+//
+// 2) mss_eff_grouping() call
 //    - The HWP updates each proc's ATTR_PROC_MEM_BASES and ATTR_PROC_MEM_SIZES
-//      attributes based on installed memory behind each proc
+//      attributes based on the address regions allocated for installed memory
+//      behind each proc
+//    - ATTR_MSS_MCS_GROUP_32 encapsulates the properties of each group formed.
+//
 // 3) Call opt_memmap() with i_init = false
-//    - Get "effective stackable" size (EffSize) of each proc. Due to (1), 
-//        (a) EffSize = highest ATTR_PROC_MEM_BASES +
-//                      its corresponding ATTR_PROC_MEM_SIZES
-//        (b) Round up EffSize to a power of 2
-//        (c) Save (proc,EffSize) pair to a vector
-//        Repeat (a) - (c) for all procs
-//    - Sort all (proc,EffSize) pairs of the above vector based on EffSize from
-//      smallest to largest
-//    - Set the ATTR_PROC_MEM_BASE and ATTR_PROC_MIRROR_BASE attributes for
-//      each proc:
-//        cur_mem_base = 0
-//        cur_mirror_base = 512TB
-//        Starting from the last (proc,EffSize) pair of the vector
-//        while this (proc,EffSize) pair is not yet processed
-//        Begin
-//          set this proc ATTR_PROC_MEM_BASE = cur_mem_base
-//          set this proc ATTR_PROC_MIRROR_BASE = cur_mirrow_base
-//          cur_mem_base += "This proc EffSize"
-//          cur_mirrow_base += "This proc EffSize" / 2
-//          move backward to preceeding (proc,EffSize) pair
-//        End
-// 4) Second mss_eff_grouping() call
-//    - The HWP adjusts each proc's ATTR_PROC_MEM_BASES using the updated
-//      ATTR_PROC_MEM_BASE value from (3).
+//    - Consume mss_eff_grouping() attributes for each proc
+//    - Align the per-chip non-mirrored and mirrored stacks on each proc to
+//      a common origin (0)
+//    - Associate non-mirrored and mirrored partner groups
+//    - Resize groups & re-stack if producing selective mirrored config
+//    - Get "effective stackable" size of non-mirrored/mirrored regions
+//      on each proc
+//    - Stack procs based on their effective size and desired placement
+//      policy
+//                                         non-mirrored    mirrored
+//         mirror       eff. stacking       stacking       stacking
+//         policy       sort criteria        origin         origin
+//        --------      -------------      ------------    --------
+//         NORMAL            nm                0TB           512TB
+//         FLIPPED           m                512TB           0TB
+//        SELECTIVE         nm+m               0TB            0TB
+//
+//    - Rewrite all attributes produced by mss_eff_grouping to reflect
+//      chip placement
+//    - Satisfy requests for HTM/OCC memory reservations on each chip
+//      (HTM requests will alter ATTR_PROC_MEM_SIZES/ATTR_PROC_MIRROR_SIZES,
+//       as these must reflect the true usable memory allocated for PHYP)
+//------------------------------------------------------------------------------
+
 //------------------------------------------------------------------------------
 //  Includes
 //------------------------------------------------------------------------------
 
 #include <opt_memmap.H>
 
+
+//------------------------------------------------------------------------------
+//  Constant definitions
+//------------------------------------------------------------------------------
+
 extern "C" {
 
-    using namespace fapi;
+using namespace fapi;
+
+
+//------------------------------------------------------------------------------
+//  Function definitions
+//------------------------------------------------------------------------------
+
+
+// round to next largest power of 2
+inline uint64_t PowerOf2Roundedup(uint64_t i_number)
+{
+    if (i_number)
+    {
+        --i_number;
+        i_number |= i_number >> 1;
+        i_number |= i_number >> 2;
+        i_number |= i_number >> 4;
+        i_number |= i_number >> 8;
+        i_number |= i_number >> 16;
+        i_number |= i_number >> 32;
+        ++i_number;
+    }
+    return i_number;
+}
+
+
+// class to represent group of memory controllers
+// shadows attribute data from mss_eff_grouping procedure
+class MemGroup
+{
+
+public:
+
+    // group type (mirrored/non-mirrored)
+    enum group_type { nm = 0, m = 8 };
+
+    // group type
+    group_type iv_group_type;
+    // group ID, 1st dimension index to MSS_MCS_GROUP_32[]
+    uint8_t iv_group_id;
+    // group ID of partner group
+    uint8_t iv_partner_group_id;
+
+    // group parameters
+    uint64_t iv_size_per_mcs;
+    uint8_t  iv_group_size;
+    uint64_t iv_size;
+    uint64_t iv_base;
+    uint8_t  iv_mcs_member_ids[OPT_MEMMAP_MAX_NM_REGIONS];
+    bool     iv_use_alt;
+    uint64_t iv_size_alt;
+    uint64_t iv_base_alt;
+    uint64_t iv_biggest_mba;
+
+    // memory allocation state
+    // portion of size which will be exposed to exerciser/PHYP
+    uint64_t iv_size_exposed;
+
+    // comparison operator for sort
+    bool operator < (MemGroup rhs) const
+    {
+        bool l_lt = true;
+        if (iv_base > rhs.iv_base ||
+            ((iv_base == rhs.iv_base) && (iv_size > rhs.iv_size)))
+        {
+            l_lt = false;
+        }
+        return l_lt;
+    }
+
+    // adjust base address of group (by negative offset)
+    void decBase(const uint64_t& offset)
+    {
+        iv_base -= offset;
+        if (iv_use_alt)
+        {
+            iv_base_alt -= offset;
+        }
+    }
+
+    // adjust base address of group (positive offset)
+    void incBase(const uint64_t& offset)
+    {
+        iv_base += offset;
+        if (iv_use_alt)
+        {
+            iv_base_alt += offset;
+        }
+    }
 
-    class MemRegion
+    // halve size of group
+    // assumes no allocations have been made
+    void halveSize()
     {
-    public:
-        uint64_t iv_base;
-        uint64_t iv_size;
-        bool operator<(MemRegion rhs) const
-        { 
-            bool l_lt = true;
-            if (iv_base > rhs.iv_base || 
-                (iv_base == rhs.iv_base && iv_size != 0))
-            {
-                l_lt = false;
-            }
-            return l_lt;
+        iv_size /= 2;
+        iv_size_per_mcs /= 2;
+        iv_size_exposed /= 2;
+
+        if (iv_use_alt)
+        {
+            iv_size_alt /= 2;
         }
-        MemRegion(uint64_t b, uint64_t s) : iv_base(b), iv_size(s) {}
-    };
 
-    class ProcBase
+        iv_biggest_mba /= 2;
+    }
+
+    // construct from attribute data array
+    MemGroup(group_type group_type, uint8_t group_id, uint32_t (*group_data)[OPT_MEMMAP_GROUP_32_DIM2])
     {
-    public:
-        fapi::Target *iv_tgt;
-        uint64_t iv_size;
-        uint32_t iv_pos;
-        // sorting in increasing size, and decreasing proc position
-        // e.g. proc0 and proc2 have same size, then the order will be
-        // proc2 then proc0
-        bool operator<(ProcBase rhs) const
+        iv_group_type = group_type;
+        iv_group_id = group_id;
+        iv_partner_group_id = 0xFF;
+
+        // consume data from attributes
+        iv_size_per_mcs = (uint64_t) (group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_MCS_SIZE_INDEX]) * OPT_MEMMAP_GB;
+        iv_group_size = (uint8_t)  (group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_MCS_IN_GROUP_INDEX]);
+        iv_size = (uint64_t) (group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_SIZE_INDEX]) * OPT_MEMMAP_GB;
+        iv_base = (uint64_t) (group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_BASE_INDEX]) * OPT_MEMMAP_GB;
+        for (uint8_t i = OPT_MEMMAP_GROUP_32_MEMBERS_START_INDEX;
+             i <= OPT_MEMMAP_GROUP_32_MEMBERS_END_INDEX;
+             i++)
         {
-            bool l_lt = true;
-            if (iv_size > rhs.iv_size ||
-                (iv_size == rhs.iv_size && iv_pos < rhs.iv_pos))
+            if (i < (OPT_MEMMAP_GROUP_32_MEMBERS_START_INDEX + iv_group_size))
             {
-                l_lt = false;
+                iv_mcs_member_ids[i-OPT_MEMMAP_GROUP_32_MEMBERS_START_INDEX] = (uint8_t) (group_data[iv_group_type+iv_group_id][i]);
             }
-            return l_lt;
+            else
+            {
+                iv_mcs_member_ids[i-OPT_MEMMAP_GROUP_32_MEMBERS_START_INDEX] = 0xFF;
+            }
+        }
+
+        iv_use_alt  = group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_ALT_VALID_INDEX]?(true):(false);
+        iv_size_alt = (uint64_t) (group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_ALT_SIZE_INDEX]) * OPT_MEMMAP_GB;
+        iv_base_alt = (uint64_t) (group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_ALT_BASE_INDEX]) * OPT_MEMMAP_GB;
+        iv_biggest_mba = (uint64_t) (group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_LARGEST_MBA_INDEX]) * OPT_MEMMAP_GB;
+
+        // mark all size as exposed
+        iv_size_exposed = iv_size;
+    }
+
+    // debug function
+    void dumpGroup()
+    {
+        FAPI_DBG("Group %d [ %s ]", iv_group_id, (iv_group_type == nm)?("nm"):("m"));
+        FAPI_DBG("  Base: %016llX", iv_base);
+        FAPI_DBG("  Size: %016llX", iv_size);
+        FAPI_DBG("   MCs: %d [ %016llX ]", iv_group_size, iv_size_per_mcs);
+        for (uint8_t i = 0; i < iv_group_size; i++)
+        {
+            FAPI_DBG("      : %d", iv_mcs_member_ids[i]);
+        }
+        FAPI_DBG("     Alt: %s", (iv_use_alt)?("true"):("false"));
+        FAPI_DBG("   ABase: %016llX", iv_base_alt);
+        FAPI_DBG("   ASize: %016llX", iv_size_alt);
+        FAPI_DBG(" Big MBA: %016llX", iv_biggest_mba);
+    }
+
+    // flush back to attribute data array
+    void flushAttributes(uint64_t chip_bases[], uint64_t chip_sizes[], uint32_t (*group_data)[OPT_MEMMAP_GROUP_32_DIM2])
+    {
+        // chip size/range attribute arrays expect addresses in B
+        chip_bases[iv_group_id] = iv_base;
+        chip_sizes[iv_group_id] = iv_size_exposed;
+
+        // group attribute arrays expect addresses in GB
+        group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_MCS_SIZE_INDEX] = (uint32_t) ((iv_size_per_mcs) / OPT_MEMMAP_GB);
+        group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_MCS_IN_GROUP_INDEX] = iv_group_size;
+        group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_SIZE_INDEX] = (uint32_t) ((iv_size) / OPT_MEMMAP_GB);
+        group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_BASE_INDEX] = (uint32_t) ((iv_base) / OPT_MEMMAP_GB);
+
+        for (uint8_t i = OPT_MEMMAP_GROUP_32_MEMBERS_START_INDEX;
+             i <= OPT_MEMMAP_GROUP_32_MEMBERS_END_INDEX;
+             i++)
+        {
+            group_data[iv_group_type+iv_group_id][i] = iv_mcs_member_ids[i-OPT_MEMMAP_GROUP_32_MEMBERS_START_INDEX];
+
+        }
+
+        group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_ALT_VALID_INDEX] = (iv_use_alt)?(1):(0);
+        group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_ALT_SIZE_INDEX] = (uint32_t) ((iv_size_alt) / OPT_MEMMAP_GB);
+        group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_ALT_BASE_INDEX] = (uint32_t) ((iv_base_alt) / OPT_MEMMAP_GB);
+        group_data[iv_group_type+iv_group_id][OPT_MEMMAP_GROUP_32_LARGEST_MBA_INDEX] = (uint32_t) ((iv_biggest_mba) / OPT_MEMMAP_GB);
+    }
+
+    // memory allocation function
+    // returns true if request can be wholly satisfied by this group,
+    // false otherwise
+    bool allocate(uint64_t size_req)
+    {
+        if (size_req <= iv_size_exposed)
+        {
+            iv_size_exposed -= size_req;
+            return true;
+        }
+        else
+        {
+            iv_size_exposed = 0;
+            return false;
         }
-        ProcBase(fapi::Target* t, uint64_t s, uint32_t p) :
-                                   iv_tgt(t), iv_size(s), iv_pos(p) {}
-    };
+    }
+};
+
+
+// class to represent memory map (non-mirrored/mirrored) on one processor chip
+class ProcChipMemmap
+{
+
+public:
+    static const uint8_t PROC_CHIP_MEMMAP_NUM_ALLOCATIONS = 2;
+    static const uint8_t PROC_CHIP_MEMMAP_HTM_ALLOC_INDEX = 0;
+    static const uint8_t PROC_CHIP_MEMMAP_OCC_ALLOC_INDEX = 1;
+
+    // pointer to processor chip target
+    Target *iv_target;
+    // mirroring policy
+    uint8_t iv_mirror_policy;
+
+    // chip location information
+    uint8_t iv_pos;
+    uint8_t iv_node_id;
+    uint8_t iv_chip_id;
 
-    inline uint64_t PowerOf2Roundedup( uint64_t i_number )
+    // chip non-mirrored base, effective size, and member groups
+    uint64_t iv_nm_base;
+    uint64_t iv_nm_eff_size;
+    std::vector<MemGroup> iv_nm_groups;
+
+    // chip mirrored base, effective size, and member groups
+    uint64_t iv_m_base;
+    uint64_t iv_m_eff_size;
+    std::vector<MemGroup> iv_m_groups;
+
+    // base/size for allocated memory areas
+    uint64_t iv_alloc_size[PROC_CHIP_MEMMAP_NUM_ALLOCATIONS];
+    uint64_t iv_alloc_base[PROC_CHIP_MEMMAP_NUM_ALLOCATIONS];
+
+    // comparison operator for sort
+    // sort in increasing size, and decreasing proc position
+    // e.g. proc0 and proc2 have same size, then the order will be
+    // proc2 then proc0
+    bool operator < (ProcChipMemmap rhs) const
     {
-        if (i_number)
+        bool l_lt = true;
+        uint64_t l_this_eff_size = 0;
+        uint64_t l_rhs_eff_size = 0;
+
+        // compute effective size based on mirror policy
+        // sort by non-mirrored size
+        if ((iv_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL) &&
+            (rhs.iv_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL))
+        {
+            l_this_eff_size = iv_nm_eff_size;
+            l_rhs_eff_size  = rhs.iv_nm_eff_size;
+        }
+        // sort by mirrored size
+        else if ((iv_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_FLIPPED) &&
+                 (rhs.iv_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_FLIPPED))
+        {
+            l_this_eff_size = iv_m_eff_size;
+            l_rhs_eff_size  = rhs.iv_m_eff_size;
+        }
+        // sort by sum of non-mirrored/mirrored sizes
+        else if ((iv_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_SELECTIVE) &&
+                 (rhs.iv_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_SELECTIVE))
+        {
+            l_this_eff_size = PowerOf2Roundedup(iv_nm_eff_size  + iv_m_eff_size);
+            l_rhs_eff_size  = PowerOf2Roundedup(rhs.iv_nm_eff_size + rhs.iv_m_eff_size);
+        }
+
+        // perform sort comparison
+        if (l_this_eff_size > l_rhs_eff_size ||
+            (l_this_eff_size == l_rhs_eff_size && iv_pos < rhs.iv_pos))
         {
-            --i_number;
-            i_number |= i_number >> 1;
-            i_number |= i_number >> 2;
-            i_number |= i_number >> 4;
-            i_number |= i_number >> 8;
-            i_number |= i_number >> 16;
-            i_number |= i_number >> 32;
-            ++i_number;
+            l_lt = false;
         }
-        return i_number;
+        return l_lt;
     }
 
-    ReturnCode opt_memmap(std::vector<fapi::Target> & i_procs, bool i_init)
+    // constructor
+    ProcChipMemmap(Target* t, uint8_t mirror_policy) :
+        iv_target(t), iv_mirror_policy(mirror_policy) {}
+
+    // process chip data from attributes
+    ReturnCode processAttributes()
     {
         ReturnCode rc;
-        std::vector<ProcBase> l_procBases;
-        const size_t l_MCS_per_proc = 8;
-        uint64_t l_bases[l_MCS_per_proc];
-        uint64_t l_sizes[l_MCS_per_proc];
-        uint32_t l_pos = 0;
-
-        for (std::vector<fapi::Target>::iterator l_iter = i_procs.begin();
-             l_iter != i_procs.end(); ++l_iter)
+        uint64_t l_nm_bases[OPT_MEMMAP_MAX_NM_REGIONS];
+        uint64_t l_nm_sizes[OPT_MEMMAP_MAX_NM_REGIONS];
+        uint64_t l_m_bases[OPT_MEMMAP_MAX_M_REGIONS];
+        uint64_t l_m_sizes[OPT_MEMMAP_MAX_M_REGIONS];
+        uint32_t l_mss_mcs_group_32[OPT_MEMMAP_GROUP_32_DIM1][OPT_MEMMAP_GROUP_32_DIM2];
+
+        do
         {
-            // If request to initialize MEM_BASE, just do it for each proc
-            if (i_init)
+            // obtain node/chip ID
+            rc = FAPI_ATTR_GET(ATTR_FABRIC_NODE_ID,
+                               iv_target,
+                               iv_node_id);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_FABRIC_NODE)");
+                break;
+            }
+
+            rc = FAPI_ATTR_GET(ATTR_FABRIC_CHIP_ID,
+                               iv_target,
+                               iv_chip_id);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_FABRIC_CHIP)");
+                break;
+            }
+            iv_pos = ((4*iv_node_id)+iv_chip_id);
+
+            // retrieve base address for each chip, align to common origin
+            rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASE,
+                               iv_target,
+                               iv_nm_base);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MEM_BASE)");
+                break;
+            }
+            if (iv_nm_base != OPT_MEMMAP_BASE_ORIGIN)
+            {
+                const uint64_t& ADDR = iv_nm_base;
+                FAPI_ERR("Unexpected value returned for ATTR_PROC_MEM_BASE (=%016llX)",
+                         iv_nm_base);
+                FAPI_SET_HWP_ERROR(rc, RC_OPT_MEMMAP_MEM_BASE_ERR);
+                break;
+            }
+
+            rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASE,
+                               iv_target,
+                               iv_m_base);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MIRROR_BASE)");
+                break;
+            }
+            if (iv_m_base != OPT_MEMMAP_OFFSET_ORIGIN)
+            {
+                const uint64_t& ADDR = iv_m_base;
+                FAPI_ERR("Unexpected value returned for ATTR_PROC_MIRROR_BASE (=%016llX)",
+                         iv_m_base);
+                FAPI_SET_HWP_ERROR(rc, RC_OPT_MEMMAP_MIRROR_BASE_ERR);
+                break;
+            }
+            iv_m_base -= OPT_MEMMAP_OFFSET_ORIGIN;
+
+            // retrieve regions (bases and sizes) computed by mss_eff_grouping
+            rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASES,
+                               iv_target,
+                               l_nm_bases);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MEM_BASES)");
+                break;
+            }
+
+            rc = FAPI_ATTR_GET(ATTR_PROC_MEM_SIZES,
+                               iv_target,
+                               l_nm_sizes);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MEM_SIZES)");
+                break;
+            }
+            rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASES,
+                               iv_target,
+                               l_m_bases);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MIRROR_BASES)");
+                break;
+            }
+
+            rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_SIZES,
+                               iv_target,
+                               l_m_sizes);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MIRROR_SIZES)");
+                break;
+            }
+
+            // retrieve data structure describing groups formed by mss_eff_grouping
+            rc = FAPI_ATTR_GET(ATTR_MSS_MCS_GROUP_32,
+                               iv_target,
+                               l_mss_mcs_group_32);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_MSS_MCS_GROUP_32)");
+                break;
+            }
+
+            // populate non-mirrored groups
+            FAPI_INF("Chip n%d:p%d", iv_node_id, iv_chip_id);
+            for (uint8_t i = 0; i < OPT_MEMMAP_MAX_NM_REGIONS; i++)
             {
-                uint64_t l_base = 0;
-                rc = FAPI_ATTR_SET(ATTR_PROC_MEM_BASE, &(*l_iter), l_base);
-                if (rc)
+                if (l_nm_sizes[i] != 0)
                 {
-                    break;
+                    FAPI_INF("  l_nm_bases[%d] = %016llX", i, l_nm_bases[i]);
+                    FAPI_INF("  l_nm_sizes[%d] = %016llX", i, l_nm_sizes[i]);
+                    MemGroup g(MemGroup::nm, i, l_mss_mcs_group_32);
+                    if ((l_nm_bases[i] != g.iv_base) ||
+                        (l_nm_sizes[i] != g.iv_size))
+                    {
+                        const uint8_t& GROUP = i;
+                        const uint64_t& MEM_BASES = l_nm_bases[i];
+                        const uint64_t& MEM_SIZES = l_nm_sizes[i];
+                        const uint64_t& GROUP_BASE = g.iv_base;
+                        const uint64_t& GROUP_SIZE = g.iv_size;
+                        FAPI_ERR("Inconsistent non-mirrored group content");
+                        FAPI_SET_HWP_ERROR(rc,
+                                           RC_OPT_MEMMAP_NON_MIRROR_GROUP_ERR);
+                        break;
+                    }
+                    iv_nm_groups.push_back(g);
                 }
-                continue;
+            }
+            if (!rc.ok())
+            {
+                break;
             }
 
-            rc = FAPI_ATTR_GET(ATTR_POS, &(*l_iter), l_pos);
-            if (rc)
+            // populate mirrored groups
+            for (uint8_t i = 0; i < OPT_MEMMAP_MAX_M_REGIONS; i++)
+            {
+                if (l_m_sizes[i] != 0)
+                {
+                    // align to common origin
+                    l_m_bases[i] -= OPT_MEMMAP_OFFSET_ORIGIN;
+                    FAPI_INF("  l_m_bases[%d] = %016llX", i, l_m_bases[i]);
+                    FAPI_INF("  l_m_sizes[%d] = %016llX", i, l_m_sizes[i]);
+                    MemGroup g(MemGroup::m, i, l_mss_mcs_group_32);
+                    // align to common origin
+                    g.decBase(OPT_MEMMAP_OFFSET_ORIGIN);
+                    if ((l_m_bases[i] != g.iv_base) ||
+                        (l_m_sizes[i] != g.iv_size))
+                    {
+                        const uint8_t& GROUP = i;
+                        const uint64_t& MIRROR_BASES = l_m_bases[i];
+                        const uint64_t& MIRROR_SIZES = l_m_sizes[i];
+                        const uint64_t& GROUP_BASE = g.iv_base;
+                        const uint64_t& GROUP_SIZE = g.iv_size;
+                        FAPI_ERR("Inconsistent mirrored group content");
+                        FAPI_SET_HWP_ERROR(rc,
+                                           RC_OPT_MEMMAP_MIRROR_GROUP_ERR);
+                        break;
+                    }
+                    iv_m_groups.push_back(g);
+                }
+            }
+            if (!rc.ok())
             {
-                FAPI_ERR("Error reading ATTR_POS");
                 break;
             }
-            else
+
+            // dump configuration for non-mirrored groups
+            for (uint8_t i = 0; i < iv_nm_groups.size(); i++)
             {
-                FAPI_INF("Proc %d :", l_pos);
+                iv_nm_groups[i].dumpGroup();
             }
+            // link mirrored group with their non-mirrored partner
+            for (uint8_t i = 0; i < iv_m_groups.size(); i++)
+            {
+                // loop through all non-mirrored groups
+                // until a match is found
+                bool match = false;
+                for (uint8_t j = 0; (j < iv_nm_groups.size()) && (!match); j++)
+                {
+                    // sizes match?
+                    match = ((iv_m_groups[i].iv_group_id ==
+                              iv_nm_groups[j].iv_group_id) &&
+                             (iv_m_groups[i].iv_size ==
+                              (iv_nm_groups[j].iv_size / 2)));
+                    if (match)
+                    {
+                        // set MCS unit parameters for mirrored group
+                        for (uint8_t k = 0; k < OPT_MEMMAP_MAX_NM_REGIONS; k++)
+                        {
+                            iv_m_groups[i].iv_mcs_member_ids[k] =
+                                iv_nm_groups[j].iv_mcs_member_ids[k];
+                        }
+                        iv_m_groups[i].iv_group_size =
+                            iv_nm_groups[j].iv_group_size;
+                        iv_m_groups[i].iv_size_per_mcs =
+                            iv_m_groups[i].iv_size /
+                            iv_m_groups[i].iv_group_size;
 
-            // retrieve bases and sizes
-            rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASES, &(*l_iter), l_bases);
-            if (rc)
+                        // link groups
+                        iv_m_groups[i].iv_partner_group_id = iv_nm_groups[j].iv_group_id;
+                        iv_nm_groups[j].iv_partner_group_id = iv_m_groups[i].iv_group_id;
+                    }
+                }
+                // valid mirrored group, but couldn't find non-mirrored partner
+                if (!match)
+                {
+                    const uint8_t& GROUP = i;
+                    FAPI_ERR("Unable to find non-mirrored group partner for mirrored group!");
+                    FAPI_SET_HWP_ERROR(rc, RC_OPT_MEMMAP_GROUP_PARTNER_ERR);
+                    break;
+                }
+                // dump configuration for mirrored group
+                iv_m_groups[i].dumpGroup();
+            }
+            if (!rc.ok())
             {
-                FAPI_ERR("Error reading ATTR_PROC_MEM_BASES");
                 break;
             }
-            else
+
+            // compress/re-stack groups for the selective mirror configuration
+            if (iv_mirror_policy ==
+                ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_SELECTIVE)
             {
-                for(size_t i = 0; i < l_MCS_per_proc; i++)
+                for (uint8_t i = 0; i < iv_nm_groups.size(); i++)
+                {
+                    // only multi-member groups (with a mirrrored partner) will
+                    // change in size
+                    if ((iv_nm_groups[i].iv_group_size != 1) &&
+                        (iv_nm_groups[i].iv_partner_group_id != 0xFF))
+                    {
+                        iv_nm_groups[i].halveSize();
+                        for (uint8_t j = 0; j < iv_m_groups.size(); j++)
+                        {
+                            if (iv_nm_groups[i].iv_partner_group_id ==
+                                iv_m_groups[j].iv_group_id)
+                            {
+                                iv_m_groups[j].halveSize();
+                            }
+                        }
+                    }
+                }
+
+                // realign each group to origin
+                for (uint8_t i = 0; i < iv_nm_groups.size(); i++)
+                {
+                    iv_nm_groups[i].decBase(iv_nm_groups[i].iv_base);
+                }
+                for (uint8_t i = 0; i < iv_m_groups.size(); i++)
                 {
-                    FAPI_INF("  l_bases[%d] = %016llX", i, l_bases[i]);
+                    iv_m_groups[i].decBase(iv_m_groups[i].iv_base);
                 }
+
+                // re-stack set of groups, largest->smallest
+                uint64_t l_nm_group_base = OPT_MEMMAP_BASE_ORIGIN;
+                std::sort(iv_nm_groups.begin(), iv_nm_groups.end());
+                for (uint8_t i = iv_nm_groups.size(); i != 0; --i)
+                {
+                    iv_nm_groups[i-1].incBase(l_nm_group_base);
+                    l_nm_group_base += iv_nm_groups[i-1].iv_size;
+                }
+
+                uint64_t l_m_group_base = OPT_MEMMAP_BASE_ORIGIN;
+                std::sort(iv_m_groups.begin(), iv_m_groups.end());
+                for (uint8_t i = iv_m_groups.size(); i != 0; --i)
+                {
+                    iv_m_groups[i-1].incBase(l_m_group_base);
+                    l_m_group_base += iv_m_groups[i-1].iv_size;
+                }
+            }
+
+            // sort regions for effective size calculations
+            std::sort(iv_nm_groups.begin(), iv_nm_groups.end());
+            std::sort(iv_m_groups.begin(), iv_m_groups.end());
+
+            // compute effective size of chip address space
+            // this is simply the end address of the last region in
+            // each stack (rounded up to a power of 2)
+            if (iv_nm_groups.size() != 0)
+            {
+                iv_nm_eff_size = iv_nm_groups[iv_nm_groups.size()-1].iv_base;
+                iv_nm_eff_size += iv_nm_groups[iv_nm_groups.size()-1].iv_size;
+                iv_nm_eff_size = PowerOf2Roundedup(iv_nm_eff_size);
+            }
+            else
+            {
+                iv_nm_eff_size = 0;
             }
+            FAPI_INF("  nm_eff_size = %016llX", iv_nm_eff_size);
 
-            rc = FAPI_ATTR_GET(ATTR_PROC_MEM_SIZES, &(*l_iter), l_sizes);
-            if (rc)
+            if (iv_m_groups.size() != 0)
             {
-                FAPI_ERR("Error reading ATTR_PROC_MEM_SIZES");
+                iv_m_eff_size = iv_m_groups[iv_m_groups.size()-1].iv_base;
+                iv_m_eff_size += iv_m_groups[iv_m_groups.size()-1].iv_size;
+                iv_m_eff_size = PowerOf2Roundedup(iv_m_eff_size);
+            }
+            else
+            {
+                iv_m_eff_size = 0;
+            }
+            FAPI_INF("  m_eff_size = %016llX", iv_m_eff_size);
+
+            // retrieve request for HTM/OCC address space
+            rc = FAPI_ATTR_GET(ATTR_PROC_HTM_BAR_SIZE,
+                               iv_target,
+                               iv_alloc_size[PROC_CHIP_MEMMAP_HTM_ALLOC_INDEX]);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_HTM_BAR_SIZE)");
                 break;
             }
+
+            rc = FAPI_ATTR_GET(ATTR_PROC_OCC_SANDBOX_SIZE,
+                               iv_target,
+                               iv_alloc_size[PROC_CHIP_MEMMAP_OCC_ALLOC_INDEX]);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_OCC_SANDBOX_SIZE)");
+                break;
+            }
+        } while(0);
+
+        return rc;
+    }
+
+    // establish new non-mirrored base address for this chip
+    // and adjust all groups to track
+    void setNMBase(const uint64_t& base)
+    {
+        iv_nm_base = base;
+        for (uint8_t i = 0; i < iv_nm_groups.size(); ++i)
+        {
+            iv_nm_groups[i].incBase(base);
+        }
+    }
+
+    // establish new mirrored base address for this chip
+    // and adjust all groups to track
+    void setMBase(const uint64_t& base)
+    {
+        iv_m_base = base;
+        for (uint8_t i = 0; i < iv_m_groups.size(); ++i)
+        {
+            iv_m_groups[i].incBase(base);
+        }
+    }
+
+    // allocate HTM/OCC memory requests for this chip
+    ReturnCode allocate()
+    {
+        ReturnCode rc;
+
+        // groups have already been sorted for stacking
+        // build ordered list of groups to consider in service of
+        // allocation requests, based on mirroring mode
+        std::vector<MemGroup*> alloc_groups;
+
+        do
+        {
+            if (iv_mirror_policy ==
+                ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_SELECTIVE)
+            {
+                // mirrored groups occupy highest address space,
+                // then non-mirrored, all are independent
+                alloc_groups.resize(iv_m_groups.size()+
+                                    iv_nm_groups.size());
+                for (uint8_t i = 0; i < iv_m_groups.size(); i++)
+                {
+                    alloc_groups[iv_m_groups.size()-1-i] = &(iv_m_groups[i]);
+                }
+                for (uint8_t i = 0; i < iv_nm_groups.size(); i++)
+                {
+                    alloc_groups[iv_m_groups.size()+iv_nm_groups.size()-1-i] = &(iv_nm_groups[i]);
+                }
+            }
+            else if (iv_mirror_policy ==
+                     ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_FLIPPED)
+            {
+                // perform allocation in mirrored space,
+                // adjust non-mirrored partner group
+                alloc_groups.resize(iv_m_groups.size());
+                for (uint8_t i = 0; i < iv_m_groups.size(); i++)
+                {
+                    alloc_groups[iv_m_groups.size()-1-i] = &(iv_m_groups[i]);
+                }
+            }
             else
             {
-                for(size_t i = 0; i < l_MCS_per_proc; i++)
+                // perform allocation in non-mirrored space,
+                // adjust mirrored partner group
+                alloc_groups.resize(iv_nm_groups.size());
+                for (uint8_t i = 0; i < iv_nm_groups.size(); i++)
                 {
-                    FAPI_INF("  l_sizes[%d] = %016llX", i, l_sizes[i]);
+                    alloc_groups[iv_nm_groups.size()-1-i] = &(iv_nm_groups[i]);
                 }
             }
 
-            // create the l_regions vector and sort it
-            std::vector<MemRegion> l_regions;
-            for (size_t i = 0; i < l_MCS_per_proc; i++)
+            // perform allocations
+            for (uint8_t r = 0;
+                 (r < PROC_CHIP_MEMMAP_NUM_ALLOCATIONS) && rc.ok();
+                 r++)
             {
-                MemRegion l_region(l_bases[i], l_sizes[i]);
-                l_regions.push_back(l_region);
-            }
+                uint64_t alloc_size_req = iv_alloc_size[r];
+                iv_alloc_base[r] = 0;
 
-            // compute effective size and round up to power of 2
-            std::sort( l_regions.begin(), l_regions.end() );
-            uint64_t round_size = l_regions[l_regions.size()-1].iv_base;
-            round_size += l_regions[l_regions.size()-1].iv_size;
-            round_size = PowerOf2Roundedup( round_size );
+                if (alloc_size_req != 0)
+                {
+                    bool alloc_done = false;
+                    for (uint8_t i = 0;
+                         (i < alloc_groups.size()) && !alloc_done;
+                         i++)
+                    {
+                        FAPI_DBG("Searching group %d for allocation %d (remaining size: %016llX)",
+                                 i, r, alloc_size_req);
+                        // allocate from primary group
+                        alloc_done = alloc_groups[i]->allocate(alloc_size_req);
+                        // take allocation from partner group as well
+                        if (iv_mirror_policy ==
+                            ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_FLIPPED)
+                        {
+                            FAPI_DBG("Registering allocation with partner non-mirrored group");
+                            for (uint8_t j = 0; j < iv_nm_groups.size(); j++)
+                            {
+                                if (alloc_groups[i]->iv_partner_group_id ==
+                                    iv_nm_groups[j].iv_group_id)
+                                {
+                                   (void) iv_nm_groups[j].allocate(
+                                        alloc_size_req * 2);
+                                }
+                            }
+                        }
+                        else if (iv_mirror_policy ==
+                                 ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL)
+                        {
+                            if (alloc_groups[i]->iv_partner_group_id != 0xFF)
+                            {
+                                FAPI_DBG("Registering allocation with partner mirrored group");
+                                for (uint8_t j = 0; j < iv_m_groups.size(); j++)
+                                {
+                                    if (alloc_groups[i]->iv_partner_group_id ==
+                                        iv_m_groups[j].iv_group_id)
+                                    {
+                                        (void) iv_m_groups[j].allocate(
+                                            alloc_size_req / 2);
+                                    }
+                                }
+                            }
+                        }
+                        // if allocation is not completely satisfied, compute
+                        // size request for next iteration
+                        if (!alloc_done)
+                        {
+                            alloc_size_req -= alloc_groups[i]->iv_size_exposed;
+                        }
+                        else
+                        {
+                            iv_alloc_base[r] = alloc_groups[i]->iv_base +
+                                               alloc_groups[i]->iv_size_exposed;
+                        }
+                    }
+                    if (!alloc_done)
+                    {
+                        const uint8_t& ALLOC_INDEX = r;
+                        FAPI_ERR("Unable to satisfy %s memory request, size requested exceeds available memory!",
+                                 (r == 0)?("HTM"):("OCC"));
+                        FAPI_SET_HWP_ERROR(rc, RC_OPT_MEMMAP_ALLOC_ERR);
+                        break;
+                    }
+                }
+            }
+        } while(0);
 
-            FAPI_INF("  round_size = %016llX", round_size);
+        return rc;
+    }
 
-            // save the proc's target and effective size
-            ProcBase l_procBase(&(*l_iter), round_size, l_pos);
-            l_procBases.push_back(l_procBase);
-        }
+    // flush group state back to attributes
+    ReturnCode flushAttributes()
+    {
+        ReturnCode rc;
+        uint64_t l_mem_bases[OPT_MEMMAP_MAX_NM_REGIONS];
+        uint64_t l_mem_sizes[OPT_MEMMAP_MAX_NM_REGIONS];
+        uint64_t l_mirror_bases[OPT_MEMMAP_MAX_M_REGIONS];
+        uint64_t l_mirror_sizes[OPT_MEMMAP_MAX_M_REGIONS];
+        uint32_t l_mss_mcs_group_32[OPT_MEMMAP_GROUP_32_DIM1][OPT_MEMMAP_GROUP_32_DIM2];
 
-        while (rc.ok() && !i_init)
+        do
         {
-            std::sort(l_procBases.begin(), l_procBases.end());
-            uint64_t cur_mem_base = 0;
-            uint64_t cur_mir_base = 0x0002000000000000LL;  // 512TB
+            // init attribute arrays
+            for (uint8_t i = 0; i < OPT_MEMMAP_MAX_NM_REGIONS; i++)
+            {
+                l_mem_bases[i] = 0;
+                l_mem_sizes[i] = 0;
+            }
+            for (uint8_t i = 0; i < OPT_MEMMAP_MAX_M_REGIONS ; i++)
+            {
+                l_mirror_bases[i] = 0;
+                l_mirror_sizes[i] = 0;
+            }
+            for (uint8_t i = 0; i < OPT_MEMMAP_GROUP_32_DIM1; i++)
+            {
 
-            for (size_t i = l_procBases.size(); i != 0; --i)
+                for (uint8_t j = OPT_MEMMAP_GROUP_32_MCS_SIZE_INDEX;
+                     j <= OPT_MEMMAP_GROUP_32_BASE_INDEX;
+                     j++)
+                {
+                    l_mss_mcs_group_32[i][j] = 0;
+                }
+                for (uint8_t j = OPT_MEMMAP_GROUP_32_MEMBERS_START_INDEX;
+                     j <= OPT_MEMMAP_GROUP_32_MEMBERS_END_INDEX;
+                     j++)
+                {
+                    l_mss_mcs_group_32[i][j] = 0xFF;
+                }
+                for (uint8_t j = OPT_MEMMAP_GROUP_32_ALT_VALID_INDEX;
+                     j <= OPT_MEMMAP_GROUP_32_LARGEST_MBA_INDEX;
+                     j++)
+                {
+                    l_mss_mcs_group_32[i][j] = 0;
+                }
+            }
+
+            // flush attribute data for each group
+            for (uint8_t i = 0; i < iv_nm_groups.size(); i++)
+            {
+                iv_nm_groups[i].flushAttributes(l_mem_bases,
+                                                l_mem_sizes,
+                                                l_mss_mcs_group_32);
+            }
+            for (uint8_t i = 0; i < iv_m_groups.size(); i++)
             {
-                fapi::Target * l_tgt = l_procBases[i-1].iv_tgt;
-                uint64_t size = l_procBases[i-1].iv_size;
-                l_pos = l_procBases[i-1].iv_pos;
+                iv_m_groups[i].flushAttributes(l_mirror_bases,
+                                               l_mirror_sizes,
+                                               l_mss_mcs_group_32);
+            }
 
-                FAPI_INF("proc%d MEM_BASE = %016llX", l_pos, cur_mem_base);
-                FAPI_INF("proc%d MIRROR_BASE = %016llX", l_pos, cur_mir_base);
+            // set base addresses
+            rc = FAPI_ATTR_SET(ATTR_PROC_MEM_BASE,
+                               iv_target,
+                               iv_nm_base);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_PROC_MEM_BASE)");
+                break;
+            }
+
+            rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_BASE,
+                               iv_target,
+                               iv_m_base);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_PROC_MIRROR_BASE)");
+                break;
+            }
+
+            // set non-mirrored region attributes
+            rc = FAPI_ATTR_SET(ATTR_PROC_MEM_BASES,
+                               iv_target,
+                               l_mem_bases);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_PROC_MEM_BASES)");
+                break;
+            }
 
-                rc = FAPI_ATTR_SET(ATTR_PROC_MEM_BASE, l_tgt, cur_mem_base);
-                if (rc)
+            rc = FAPI_ATTR_SET(ATTR_PROC_MEM_SIZES,
+                               iv_target,
+                               l_mem_sizes);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_PROC_MEM_BASES)");
+                break;
+            }
+
+            // set mirrored region attributes
+            rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_BASES,
+                               iv_target,
+                               l_mirror_bases);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_PROC_MIRROR_BASES)");
+                break;
+            }
+
+            rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_SIZES,
+                               iv_target,
+                               l_mirror_sizes);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_PROC_MIRROR_BASES)");
+                break;
+            }
+
+            // set group definition attributes
+            rc = FAPI_ATTR_SET(ATTR_MSS_MCS_GROUP_32,
+                               iv_target,
+                               l_mss_mcs_group_32);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_MSS_MCS_GROUP_32)");
+                break;
+            }
+
+            // set HTM/OCC allocation attributes
+            rc = FAPI_ATTR_SET(ATTR_PROC_HTM_BAR_BASE_ADDR,
+                               iv_target,
+                               iv_alloc_base[PROC_CHIP_MEMMAP_HTM_ALLOC_INDEX]);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_PROC_HTM_BAR_BASE_ADDR)");
+                break;
+            }
+
+            rc = FAPI_ATTR_SET(ATTR_PROC_OCC_SANDBOX_BASE_ADDR,
+                               iv_target,
+                               iv_alloc_base[PROC_CHIP_MEMMAP_OCC_ALLOC_INDEX]);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_PROC_OCC_SANDBOX_BASE_ADDR)");
+                break;
+            }
+        } while(0);
+
+        return rc;
+    }
+};
+
+
+ReturnCode opt_memmap(std::vector<fapi::Target> & i_procs, bool i_init)
+{
+    ReturnCode rc;
+    std::vector<ProcChipMemmap> l_system_memmap;
+    uint8_t l_mirror_policy;
+
+    do
+    {
+        // retrieve mirroring placement policy attribute
+        rc = FAPI_ATTR_GET(ATTR_MEM_MIRROR_PLACEMENT_POLICY,
+                           NULL,
+                           l_mirror_policy);
+        if (!rc.ok())
+        {
+            FAPI_ERR("Error querying ATTR_MEM_MIRROR_PLACEMENT_POLICY");
+            break;
+        }
+
+        FAPI_INF("opt_memmap called with i_init = %d, mirror_policy: %d",
+                 (i_init)?(1):(0), l_mirror_policy);
+
+        // first pass of execution
+        if (i_init)
+        {
+            // loop across all chips in system, set common
+            // base for non-mirrored/mirrored memory on each chip in preparation
+            // for mss_eff_grouping call
+            for (std::vector<fapi::Target>::iterator l_iter = i_procs.begin();
+                 l_iter != i_procs.end();
+                 ++l_iter)
+            {
+                uint64_t mem_base = OPT_MEMMAP_BASE_ORIGIN;
+                rc = FAPI_ATTR_SET(ATTR_PROC_MEM_BASE,
+                                   &(*l_iter),
+                                   mem_base);
+                if (!rc.ok())
                 {
-                    FAPI_ERR("Error reading ATTR_PROC_MEM_BASE");
+                    FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_PROC_MEM_BASE)!");
                     break;
                 }
 
-                rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_BASE, l_tgt, cur_mir_base);
-                if (rc)
+                uint64_t mirror_base = OPT_MEMMAP_OFFSET_ORIGIN;
+                rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_BASE,
+                                   &(*l_iter),
+                                   mirror_base);
+                if (!rc.ok())
                 {
-                    FAPI_ERR("Error reading ATTR_PROC_MIRROR_BASE");
+                    FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_PROC_MIRROR_BASE)!");
                     break;
                 }
-                cur_mem_base += size;
-                cur_mir_base += size / 2;
+            }
+            if (!rc.ok())
+            {
+                break;
+            }
+        }
+        // second pass of execution
+        // reorder chips based on their effective size
+        else
+        {
+            // loop across all chips in system, consume results of
+            // mss_eff_grouping call
+            for (std::vector<fapi::Target>::iterator l_iter = i_procs.begin();
+                 l_iter != i_procs.end();
+                 ++l_iter)
+            {
+                ProcChipMemmap p(&(*l_iter), l_mirror_policy);
+                rc = p.processAttributes();
+                if (!rc.ok())
+                {
+                    FAPI_ERR("Error from processAttributes");
+                    break;
+                }
+                l_system_memmap.push_back(p);
+            }
+            if (!rc.ok())
+            {
+                break;
             }
 
-            break;
+            // sort chips based on their effective stackable size
+            std::sort(l_system_memmap.begin(), l_system_memmap.end());
+
+            // establish base for alignment of mirrored/non-mirrored regions
+            uint64_t l_m_base_curr;
+            uint64_t l_nm_base_curr;
+            if (l_mirror_policy ==
+                ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL)
+            {
+                // non-mirrored at zero, mirrored at offset
+                l_nm_base_curr = OPT_MEMMAP_BASE_ORIGIN;
+                l_m_base_curr  = OPT_MEMMAP_OFFSET_ORIGIN;
+            }
+            else if (l_mirror_policy ==
+                     ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_FLIPPED)
+            {
+                // mirrored at zero, non-mirrored at offset
+                l_nm_base_curr = OPT_MEMMAP_OFFSET_ORIGIN;
+                l_m_base_curr  = OPT_MEMMAP_BASE_ORIGIN;
+            }
+            else
+            {
+                // start at zero, mirrored region will stack on top
+                // of non-mirrored address space, handle offset in loop
+                l_nm_base_curr = OPT_MEMMAP_BASE_ORIGIN;
+                l_m_base_curr  = OPT_MEMMAP_BASE_ORIGIN;
+            }
+
+            // walk through chips, from largest->smallest effective size &
+            // assign base addresses for each group
+            for (uint8_t i = l_system_memmap.size(); i != 0; --i)
+            {
+                FAPI_DBG("Stacking chip n%d:p%d (eff nm size = %lld GB, eff m size = %lld GB)...",
+                         l_system_memmap[i-1].iv_node_id,
+                         l_system_memmap[i-1].iv_chip_id,
+                         l_system_memmap[i-1].iv_nm_eff_size / OPT_MEMMAP_GB,
+                         l_system_memmap[i-1].iv_m_eff_size / OPT_MEMMAP_GB);
+
+                if (l_mirror_policy ==
+                    ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_SELECTIVE)
+                {
+                    l_m_base_curr += l_system_memmap[i-1].iv_nm_eff_size;
+                }
 
+                // establish base addresses for this chip & realign
+                // all groups on this chip to reflect this
+                l_system_memmap[i-1].setNMBase(l_nm_base_curr);
+                l_system_memmap[i-1].setMBase(l_m_base_curr);
+                FAPI_DBG("nm base: %016llX", l_nm_base_curr);
+                FAPI_DBG("m base: %016llX", l_m_base_curr);
+                if (l_mirror_policy ==
+                    ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL)
+                {
+                    l_nm_base_curr += l_system_memmap[i-1].iv_nm_eff_size;
+                    l_m_base_curr += l_system_memmap[i-1].iv_nm_eff_size / 2;
+                }
+                else if (l_mirror_policy ==
+                         ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_FLIPPED)
+                {
+                    l_nm_base_curr += l_system_memmap[i-1].iv_nm_eff_size;
+                    l_m_base_curr += l_system_memmap[i-1].iv_m_eff_size;
+                }
+                else
+                {
+                    l_nm_base_curr += PowerOf2Roundedup(
+                        l_system_memmap[i-1].iv_nm_eff_size +
+                        l_system_memmap[i-1].iv_m_eff_size);
+                    l_m_base_curr = l_nm_base_curr;
+                }
+
+                // allocate HTM/OCC memory requests for this chip
+                rc = l_system_memmap[i-1].allocate();
+                if (!rc.ok())
+                {
+                    FAPI_ERR("Error from allocate");
+                    break;
+                }
+
+                // flush attributes for this chip
+                rc = l_system_memmap[i-1].flushAttributes();
+                if (!rc.ok())
+                {
+                    FAPI_ERR("Error from flushAttributes");
+                    break;
+                }
+            }
+            if (!rc.ok())
+            {
+                break;
+            }
         }
+    } while(0);
+
+    return rc;
+}
 
-        return rc;
-    }
 
 } //end extern C
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.H
index db8e96cba..35d0790e8 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.H
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.H
@@ -20,46 +20,92 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: opt_memmap.H,v 1.3 2013/02/20 23:13:30 vanlee Exp $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//------------------------------------------------------------------------------
-// *! TITLE       : opt_memmap.H
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Girisankar Paulraj     Email: gpaulraj@in.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// Header file for opt_memmap
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
+// $Id: opt_memmap.H,v 1.4 2013/05/06 15:14:25 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/opt_memmap.H,v $      */
+
+
 //------------------------------------------------------------------------------
 // CHANGE HISTORY:
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
-//  1.1    | vanlee   | 12/01/12| Initial version
-//  1.2    | vanlee   | 01/04/13| Added version string
+//  1.4    | jmcgill  | 04/28/13| Shift constant definitions
 //  1.3    | vanlee   | 02/20/13| Added i_init parameter
+//  1.2    | vanlee   | 01/04/13| Added version string
+//  1.1    | vanlee   | 12/01/12| Initial version
 
 #ifndef MSS_OPT_MEMMAP_H_
 #define MSS_OPT_MEMMAP_H_
 
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
 #include <fapi.H>
 
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+
+// conversion factor definitions
+const uint64_t OPT_MEMMAP_GB = 0x0000000040000000ULL;
+
+// default origin for non-mirrored/mirrored address regions
+const uint64_t OPT_MEMMAP_BASE_ORIGIN   = 0;                     // 0
+const uint64_t OPT_MEMMAP_OFFSET_ORIGIN = 0x0002000000000000LL;  // 512TB
+
+// maximum non-mirrored/mirrored regions supported
+const uint8_t OPT_MEMMAP_MAX_NM_REGIONS = 8;
+const uint8_t OPT_MEMMAP_MAX_M_REGIONS  = 4;
+
+// attribute index constants
+// first array dimension (group ID)
+const uint8_t OPT_MEMMAP_GROUP_32_NM_START_INDEX = 0;
+const uint8_t OPT_MEMMAP_GROUP_32_NM_END_INDEX   = 7;
+const uint8_t OPT_MEMMAP_GROUP_32_M_START_INDEX  = 8;
+const uint8_t OPT_MEMMAP_GROUP_32_M_END_INDEX    = 15;
+
+const uint8_t OPT_MEMMAP_GROUP_32_DIM1 = (OPT_MEMMAP_GROUP_32_M_END_INDEX-
+                                          OPT_MEMMAP_GROUP_32_NM_START_INDEX)+1;
+
+// second array dimension (group definition)
+const uint8_t OPT_MEMMAP_GROUP_32_MCS_SIZE_INDEX      = 0;
+const uint8_t OPT_MEMMAP_GROUP_32_MCS_IN_GROUP_INDEX  = 1;
+const uint8_t OPT_MEMMAP_GROUP_32_SIZE_INDEX          = 2;
+const uint8_t OPT_MEMMAP_GROUP_32_BASE_INDEX          = 3;
+const uint8_t OPT_MEMMAP_GROUP_32_MEMBERS_START_INDEX = 4;
+const uint8_t OPT_MEMMAP_GROUP_32_MEMBERS_END_INDEX   = 11;
+const uint8_t OPT_MEMMAP_GROUP_32_ALT_VALID_INDEX     = 12;
+const uint8_t OPT_MEMMAP_GROUP_32_ALT_SIZE_INDEX      = 13;
+const uint8_t OPT_MEMMAP_GROUP_32_ALT_BASE_INDEX      = 14;
+const uint8_t OPT_MEMMAP_GROUP_32_LARGEST_MBA_INDEX   = 15;
+
+const uint8_t OPT_MEMMAP_GROUP_32_DIM2 = (OPT_MEMMAP_GROUP_32_LARGEST_MBA_INDEX-
+                                          OPT_MEMMAP_GROUP_32_MCS_SIZE_INDEX)+1;
+
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+// function pointer typedef definition for HWP call support
 typedef fapi::ReturnCode (*opt_memmap_FP_t)(std::vector<fapi::Target> & i_procs,
-                          bool i_init);
+                                            bool i_init);
 
 extern "C"
 {
 
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
 // i_init = true  : initialize all ATTR_PROC_MEM_BASE attributes to 0
 //        = false : perform memory map optimization
 fapi::ReturnCode opt_memmap(std::vector<fapi::Target> & i_procs, bool i_init);
 
+
 } // extern "C"
 
 #endif // MSS_OPT_MEMMAP_H_
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap_errors.xml b/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap_errors.xml
new file mode 100644
index 000000000..c87ce3f27
--- /dev/null
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap_errors.xml
@@ -0,0 +1,64 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap_errors.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Error definitions for proc_setup_bars -->
+<hwpErrors>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_OPT_MEMMAP_MEM_BASE_ERR</rc>
+    <description>Unexpected value for ATTR_PROC_MEM_BASE returned after mss_eff_grouping execution.</description>
+    <ffdc>ADDR</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_OPT_MEMMAP_MIRROR_BASE_ERR</rc>
+    <description>Unexpected value for ATTR_PROC_MIRROR_BASE returned after mss_eff_grouping execution.</description>
+    <ffdc>ADDR</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_OPT_MEMMAP_NON_MIRROR_GROUP_ERR</rc>
+    <description>Inconsistent non-mirrored group content.</description>
+    <ffdc>GROUP</ffdc>
+    <ffdc>MEM_BASES</ffdc>
+    <ffdc>MEM_SIZES</ffdc>
+    <ffdc>GROUP_BASE</ffdc>
+    <ffdc>GROUP_SIZE</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_OPT_MEMMAP_MIRROR_GROUP_ERR</rc>
+    <description>Inconsistent mirrored group content.</description>
+    <ffdc>GROUP</ffdc>
+    <ffdc>MIRROR_BASES</ffdc>
+    <ffdc>MIRROR_SIZES</ffdc>
+    <ffdc>GROUP_BASE</ffdc>
+    <ffdc>GROUP_SIZE</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_OPT_MEMMAP_GROUP_PARTNER_ERR</rc>
+    <description>Unable to find find non-mirrored group partner for mirrored group.</description>
+    <ffdc>GROUP</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_OPT_MEMMAP_ALLOC_ERR</rc>
+    <description>Unable to satisfy allocatio request based on available free memory on this chip.</description>
+    <ffdc>ALLOC_INDEX</ffdc>
+  </hwpError>
+</hwpErrors>