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authorThi Tran <thi@us.ibm.com>2014-08-04 14:29:51 -0500
committerA. Patrick Williams III <iawillia@us.ibm.com>2014-08-13 15:20:37 -0500
commit76fc214b0add778c2dc3d7866e5e627b9cddee46 (patch)
treeaadaa7cca0d76542224665df00a42ab21c5b82db /src/usr/hwpf/hwp/slave_sbe
parent2f89769eb7f06b4c13f0cd90d2df3d5139fd487b (diff)
downloadtalos-hostboot-76fc214b0add778c2dc3d7866e5e627b9cddee46.tar.gz
talos-hostboot-76fc214b0add778c2dc3d7866e5e627b9cddee46.zip
SW261816: INITPROC: Add callouts for SBE errors - originally found in SW261688
CQ:SW261816 Change-Id: Ic534ffa59624223dc2f27f187758ad8077faaa43 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/12459 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/12615 Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com> Tested-by: Jenkins Server
Diffstat (limited to 'src/usr/hwpf/hwp/slave_sbe')
-rw-r--r--src/usr/hwpf/hwp/slave_sbe/makefile5
-rw-r--r--src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_check_slave_sbe_seeprom_complete.C14
-rw-r--r--src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.C144
-rw-r--r--src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.H86
-rw-r--r--src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.xml119
-rw-r--r--src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.C558
-rw-r--r--src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.H97
-rw-r--r--src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state_errors.xml93
-rw-r--r--src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.C550
-rw-r--r--src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.H88
-rw-r--r--src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.xml59
-rw-r--r--src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C886
-rw-r--r--src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.H146
-rw-r--r--src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc_errors.xml694
14 files changed, 2341 insertions, 1198 deletions
diff --git a/src/usr/hwpf/hwp/slave_sbe/makefile b/src/usr/hwpf/hwp/slave_sbe/makefile
index 9e8c71cf4..2ee5fe406 100644
--- a/src/usr/hwpf/hwp/slave_sbe/makefile
+++ b/src/usr/hwpf/hwp/slave_sbe/makefile
@@ -45,6 +45,8 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_cen_ref_clk_enable
EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_spless_sbe_startWA
EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/proc_mailbox_utils
EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_tp_collect_dbg_data
+EXTRAINCDIR += ${ROOTPATH}/src/usr/pore/poreve/porevesrc
+EXTRAINCDIR += ${ROOTPATH}/src/usr/pore/poreve/model/
## NOTE: add new object files when you add a new HWP
OBJS += slave_sbe.o
@@ -58,6 +60,9 @@ OBJS += proc_spless_sbe_startWA.o
OBJS += proc_reset_i2cm_bus_fence.o
OBJS += proc_check_master_sbe_seeprom.o
OBJS += proc_tp_collect_dbg_data.o
+OBJS += proc_extract_pore_engine_state.o
+OBJS += proc_extract_pore_base_ffdc.o
+OBJS += proc_extract_pore_halt_ffdc.o
## NOTE: add a new directory onto the vpaths when you add a new HWP
VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_cen_ref_clk_enable
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_check_slave_sbe_seeprom_complete.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_check_slave_sbe_seeprom_complete.C
index 86d92eec0..373a6a49e 100644
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_check_slave_sbe_seeprom_complete.C
+++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_check_slave_sbe_seeprom_complete.C
@@ -23,7 +23,7 @@
/* */
/* IBM_PROLOG_END_TAG */
// -*- mode: C++; c-file-style: "linux"; -*-
-// $Id: proc_check_slave_sbe_seeprom_complete.C,v 1.14 2014/06/10 12:41:40 dsanner Exp $
+// $Id: proc_check_slave_sbe_seeprom_complete.C,v 1.15 2014/07/23 19:30:59 jmcgill Exp $
// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_check_slave_sbe_seeprom_complete.C,v $
//------------------------------------------------------------------------------
// *|
@@ -61,7 +61,7 @@ const uint8_t SBE_EXIT_SUCCESS_0xF = 0xF;
const uint64_t NS_TO_FINISH = 10000000; //(10 ms)
const uint64_t MS_TO_FINISH = NS_TO_FINISH/1000000;
const uint64_t SIM_CYCLES_TO_FINISH = 10000000;
-//Should really be 19.6*NS_TO_FINISH, but sim runs at about 11 hours per
+//Should really be 19.6*NS_TO_FINISH, but sim runs at about 11 hours per
//simulated second which is longer than we want to wait in error cases
@@ -242,7 +242,7 @@ extern "C"
do
{
//Check if the SBE is still running. Loop until stopped
- //or loop time is exceeded.
+ //or loop time is exceeded.
bool still_running = true;
size_t loop_time = 0;
rc = proc_check_slave_sbe_seeprom_complete_check_running(
@@ -327,12 +327,12 @@ extern "C"
if( halt_code != SBE_EXIT_SUCCESS_0xF )
{
FAPI_ERR(
- "SBE halted with error %i (istep 0x%X, substep %i)",
+ "SBE halted with error %i (istep 0x%X, substep %i)",
halt_code,
istep_num,
substep_num);
//Get the error code from the SBE code
- FAPI_EXEC_HWP(rc, proc_extract_sbe_rc, i_target, i_pSEEPROM, SBE);
+ FAPI_EXEC_HWP(rc, proc_extract_sbe_rc, i_target, NULL, i_pSEEPROM, SBE);
break;
}
//Halt code was success
@@ -343,7 +343,7 @@ extern "C"
( istep_num != PROC_SBE_EX_HOST_RUNTIME_SCOM_MAGIC_ISTEP_NUM ))
{
FAPI_ERR(
- "SBE halted in wrong istep (istep 0x%X, substep %i)",
+ "SBE halted in wrong istep (istep 0x%X, substep %i)",
istep_num,
substep_num);
const fapi::Target & CHIP_IN_ERROR = i_target;
@@ -362,7 +362,7 @@ extern "C"
( substep_num != SUBSTEP_ENABLE_PNOR_SLAVE_CHIP )))
{
FAPI_ERR(
- "SBE halted in wrong substep (istep 0x%X, substep %i)",
+ "SBE halted in wrong substep (istep 0x%X, substep %i)",
istep_num,
substep_num);
const fapi::Target & CHIP_IN_ERROR = i_target;
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.C
new file mode 100644
index 000000000..f6103356a
--- /dev/null
+++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.C
@@ -0,0 +1,144 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.C $ */
+/* */
+/* OpenPOWER HostBoot Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2014 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+// $Id: proc_extract_pore_base_ffdc.C,v 1.1 2014/07/23 19:38:05 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_pore_base_ffdc.C,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2012
+// *! All Rights Reserved -- Property of IBM
+// *! *** ***
+// *|
+// *! TITLE : proc_extract_pore_base_ffdc.C
+// *! DESCRIPTION : Log base FFDC for SBE/SLW errors
+// *!
+// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com
+// *! BACKUP NAME : Johannes Koesters Email: koesters@de.ibm.com
+// *!
+// *! Overview:
+// *! - Dump state of SBE/SLW engine
+// *! - Extract additional FFDC based on engine type
+// *!
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <p8_scom_addresses.H>
+#include <proc_extract_pore_base_ffdc.H>
+#include <proc_tp_collect_dbg_data.H>
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+extern "C"
+{
+
+
+/**
+ * proc_extract_pore_engine_state - HWP entry point, log PORE engine state
+ *
+ * @param[in] i_pore_state - struct holding PORE state
+ * @param[in] i_pore_sbe_state - struct holding PORE SBE specific state
+ * @param[out] o_rc - target return code for extra FFDC
+ *
+ * @retval fapi::ReturnCode = SUCCESS
+ */
+fapi::ReturnCode proc_extract_pore_base_ffdc(const por_base_state & i_pore_state,
+ const por_sbe_base_state & i_pore_sbe_state,
+ fapi::ReturnCode & o_rc)
+
+{
+ // return code
+ fapi::ReturnCode rc;
+
+ FAPI_INF("proc_extract_pore_base_ffdc: Start");
+
+ do
+ {
+ // append to return code
+ const fapi::Target & CHIP = i_pore_state.target;
+ const por_engine_t & ENGINE = i_pore_state.engine;
+ const bool & VIRTUAL = i_pore_state.is_virtual;
+ const uint64_t & PORE_VITAL_REG = i_pore_state.vital_state.getDoubleWord(0);
+ const uint64_t & PORE_STATUS_REG = i_pore_state.engine_state.getDoubleWord(PORE_STATUS_OFFSET);
+ const uint64_t & PORE_CONTROL_REG = i_pore_state.engine_state.getDoubleWord(PORE_CONTROL_OFFSET);
+ const uint64_t & PORE_RESET_REG = i_pore_state.engine_state.getDoubleWord(PORE_RESET_OFFSET);
+ const uint64_t & PORE_ERR_MASK_REG = i_pore_state.engine_state.getDoubleWord(PORE_ERR_MASK_OFFSET);
+ const uint64_t & PORE_P0_REG = i_pore_state.engine_state.getDoubleWord(PORE_P0_OFFSET);
+ const uint64_t & PORE_P1_REG = i_pore_state.engine_state.getDoubleWord(PORE_P1_OFFSET);
+ const uint64_t & PORE_A0_REG = i_pore_state.engine_state.getDoubleWord(PORE_A0_OFFSET);
+ const uint64_t & PORE_A1_REG = i_pore_state.engine_state.getDoubleWord(PORE_A1_OFFSET);
+ const uint64_t & PORE_TBL_BASE_REG = i_pore_state.engine_state.getDoubleWord(PORE_TBL_BASE_OFFSET);
+ const uint64_t & PORE_EXE_TRIGGER_REG = i_pore_state.engine_state.getDoubleWord(PORE_EXE_TRIGGER_OFFSET);
+ const uint64_t & PORE_CTR_REG = i_pore_state.engine_state.getDoubleWord(PORE_CTR_OFFSET);
+ const uint64_t & PORE_D0_REG = i_pore_state.engine_state.getDoubleWord(PORE_D0_OFFSET);
+ const uint64_t & PORE_D1_REG = i_pore_state.engine_state.getDoubleWord(PORE_D1_OFFSET);
+ const uint64_t & PORE_IBUF0_REG = i_pore_state.engine_state.getDoubleWord(PORE_IBUF0_OFFSET);
+ const uint64_t & PORE_IBUF1_REG = i_pore_state.engine_state.getDoubleWord(PORE_IBUF1_OFFSET);
+ const uint64_t & PORE_DEBUG0_REG = i_pore_state.engine_state.getDoubleWord(PORE_DEBUG0_OFFSET);
+ const uint64_t & PORE_DEBUG1_REG = i_pore_state.engine_state.getDoubleWord(PORE_DEBUG1_OFFSET);
+ const uint64_t & PORE_STACK0_REG = i_pore_state.engine_state.getDoubleWord(PORE_STACK0_OFFSET);
+ const uint64_t & PORE_STACK1_REG = i_pore_state.engine_state.getDoubleWord(PORE_STACK1_OFFSET);
+ const uint64_t & PORE_STACK2_REG = i_pore_state.engine_state.getDoubleWord(PORE_STACK2_OFFSET);
+ const uint64_t & PORE_IDFLAGS_REG = i_pore_state.engine_state.getDoubleWord(PORE_IDFLAGS_OFFSET);
+ const uint64_t & PORE_SPRG0_REG = i_pore_state.engine_state.getDoubleWord(PORE_SPRG0_OFFSET);
+ const uint64_t & PORE_MRR_REG = i_pore_state.engine_state.getDoubleWord(PORE_MRR_OFFSET);
+ const uint64_t & PORE_I2CE0_REG = i_pore_state.engine_state.getDoubleWord(PORE_I2CE0_OFFSET);
+ const uint64_t & PORE_I2CE1_REG = i_pore_state.engine_state.getDoubleWord(PORE_I2CE1_OFFSET);
+ const uint64_t & PORE_I2CE2_REG = i_pore_state.engine_state.getDoubleWord(PORE_I2CE2_OFFSET);
+ const uint64_t & PORE_PC = i_pore_state.pc;
+ const uint64_t & PORE_RC = i_pore_state.rc;
+ FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_PROC_EXTRACT_PORE_BASE_FFDC_ENGINE_STATE);
+
+
+ //
+ // collect additional FFDC based on engine type
+ //
+
+ if (i_pore_state.target.getType() == fapi::TARGET_TYPE_PROC_CHIP)
+ {
+ if (i_pore_state.engine == SBE)
+ {
+ const uint64_t & PNOR_ECCB_STATUS = i_pore_sbe_state.pnor_eccb_status.getDoubleWord(0);
+ const uint64_t & SEEPROM_ECCB_STATUS = i_pore_sbe_state.i2cm_eccb_status.getDoubleWord(0);
+ const uint8_t & SOFT_ERROR_STATUS = i_pore_sbe_state.soft_err;
+ const bool & ATTN_REPORTED = i_pore_sbe_state.reported_attn;
+ FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_PROC_EXTRACT_PORE_BASE_FFDC_SBE);
+ }
+ else
+ {
+ FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_PROC_EXTRACT_PORE_BASE_FFDC_SLW);
+ }
+ }
+ } while(0);
+
+ FAPI_INF("proc_extract_pore_base_ffdc: End");
+ return rc;
+}
+
+
+} // extern "C"
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.H b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.H
new file mode 100644
index 000000000..10424d9f8
--- /dev/null
+++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.H
@@ -0,0 +1,86 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.H $ */
+/* */
+/* OpenPOWER HostBoot Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2014 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+// $Id: proc_extract_pore_base_ffdc.H,v 1.1 2014/07/23 19:38:05 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_pore_base_ffdc.H,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2012
+// *! All Rights Reserved -- Property of IBM
+// *! *** ***
+// *|
+// *! TITLE : proc_extract_pore_base_ffdc.C
+// *! DESCRIPTION : Log base FFDC for SBE/SLW errors
+// *!
+// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com
+// *! BACKUP NAME : Johannes Koesters Email: koesters@de.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+#ifndef _PROC_EXTRACT_PORE_BASE_FFDC_H_
+#define _PROC_EXTRACT_PORE_BASE_FFDC_H_
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <fapi.H>
+#include <proc_extract_sbe_rc.H>
+
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+// function pointer typedef definition for HWP call support
+typedef fapi::ReturnCode (*proc_extract_pore_base_ffdc_FP_t)(const por_base_state &,
+ const por_sbe_base_state &,
+ fapi::ReturnCode &);
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+
+extern "C"
+{
+
+/**
+ * proc_extract_pore_engine_state - HWP entry point, log PORE engine state
+ *
+ * @param[in] i_pore_state - struct holding PORE state
+ * @param[in] i_pore_sbe_state - struct holding PORE SBE specific state
+ * @param[out] o_rc - target return code for extra FFDC
+ *
+ * @retval fapi::ReturnCode = SUCCESS
+ */
+fapi::ReturnCode proc_extract_pore_base_ffdc(const por_base_state & i_pore_state,
+ const por_sbe_base_state & i_pore_sbe_state,
+ fapi::ReturnCode & o_rc);
+
+
+
+} // extern "C"
+
+#endif // _PROC_EXTRACT_PORE_BASE_FFDC_H_
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.xml b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.xml
new file mode 100644
index 000000000..a28556771
--- /dev/null
+++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.xml
@@ -0,0 +1,119 @@
+<!-- IBM_PROLOG_BEGIN_TAG -->
+<!-- This is an automatically generated prolog. -->
+<!-- -->
+<!-- $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.xml $ -->
+<!-- -->
+<!-- OpenPOWER HostBoot Project -->
+<!-- -->
+<!-- Contributors Listed Below - COPYRIGHT 2014 -->
+<!-- [+] International Business Machines Corp. -->
+<!-- -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
+<!-- implied. See the License for the specific language governing -->
+<!-- permissions and limitations under the License. -->
+<!-- -->
+<!-- IBM_PROLOG_END_TAG -->
+<!-- $Id: proc_extract_pore_base_ffdc.xml,v 1.1 2014/07/23 19:43:18 jmcgill Exp $ -->
+<!-- Error definitions for proc_extract_pore_base_ffdc procedure -->
+<hwpErrors>
+ <!-- *********************************************************************** -->
+ <hwpError>
+ <rc>RC_PROC_EXTRACT_PORE_BASE_FFDC</rc>
+ <description>
+ Base error code used to invoke PORE engine state FFDC logging function
+ </description>
+ <collectFfdc>proc_extract_pore_base_ffdc, pore_state, pore_sbe_state</collectFfdc>
+ </hwpError>
+ <!-- *********************************************************************** -->
+ <hwpError>
+ <rc>RC_PROC_EXTRACT_PORE_BASE_FFDC_ENGINE_STATE</rc>
+ <description>
+ PORE engine state collected on all SBE/SLW fails
+ </description>
+ <!-- target/engine type -->
+ <ffdc>CHIP</ffdc>
+ <ffdc>ENGINE</ffdc>
+ <ffdc>VIRTUAL</ffdc>
+ <!-- SBE/SLW vital state -->
+ <ffdc>PORE_VITAL_REG</ffdc>
+ <!-- PORE register state -->
+ <ffdc>PORE_STATUS_REG</ffdc>
+ <ffdc>PORE_CONTROL_REG</ffdc>
+ <ffdc>PORE_RESET_REG</ffdc>
+ <ffdc>PORE_ERR_MASK_REG</ffdc>
+ <ffdc>PORE_P0_REG</ffdc>
+ <ffdc>PORE_P1_REG</ffdc>
+ <ffdc>PORE_A0_REG</ffdc>
+ <ffdc>PORE_A1_REG</ffdc>
+ <ffdc>PORE_TBL_BASE_REG</ffdc>
+ <ffdc>PORE_EXE_TRIGGER_REG</ffdc>
+ <ffdc>PORE_CTR_REG</ffdc>
+ <ffdc>PORE_D0_REG</ffdc>
+ <ffdc>PORE_D1_REG</ffdc>
+ <ffdc>PORE_IBUF0_REG</ffdc>
+ <ffdc>PORE_IBUF1_REG</ffdc>
+ <ffdc>PORE_DEBUG0_REG</ffdc>
+ <ffdc>PORE_DEBUG1_REG</ffdc>
+ <ffdc>PORE_STACK0_REG</ffdc>
+ <ffdc>PORE_STACK1_REG</ffdc>
+ <ffdc>PORE_STACK2_REG</ffdc>
+ <ffdc>PORE_IDFLAGS_REG</ffdc>
+ <ffdc>PORE_SPRG0_REG</ffdc>
+ <ffdc>PORE_MRR_REG</ffdc>
+ <ffdc>PORE_I2CE0_REG</ffdc>
+ <ffdc>PORE_I2CE1_REG</ffdc>
+ <ffdc>PORE_I2CE2_REG</ffdc>
+ <!-- PORE engine PC -->
+ <ffdc>PORE_PC</ffdc>
+ <!-- RC associated with SBE/SLW halt point -->
+ <ffdc>PORE_RC</ffdc>
+ </hwpError>
+ <!-- *********************************************************************** -->
+ <hwpError>
+ <rc>RC_PROC_EXTRACT_PORE_BASE_FFDC_SBE</rc>
+ <description>
+ SBE specific register FFDC to collect (via chip target) on all fails
+ </description>
+ <ffdc>PNOR_ECCB_STATUS</ffdc>
+ <ffdc>SEEPROM_ECCB_STATUS</ffdc>
+ <ffdc>SOFT_ERROR_STATUS</ffdc>
+ <ffdc>ATTN_REPORTED</ffdc>
+ <collectRegisterFfdc>
+ <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
+ <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
+ <target>CHIP</target>
+ </collectRegisterFfdc>
+ <collectFfdc>proc_tp_collect_dbg_data, CHIP</collectFfdc>
+ </hwpError>
+ <!-- *********************************************************************** -->
+ <hwpError>
+ <rc>RC_PROC_EXTRACT_PORE_BASE_FFDC_SLW</rc>
+ <description>
+ SLW specific register FFDC to collect (via chip target) on all fails
+ </description>
+ <collectRegisterFfdc>
+ <id>REG_FFDC_PROC_SLW_PBA_REGISTERS</id>
+ <id>REG_FFDC_PROC_SLW_FIR_REGISTERS</id>
+ <id>REG_FFDC_PROC_SLW_PMC_REGISTERS</id>
+ <target>CHIP</target>
+ </collectRegisterFfdc>
+ <collectRegisterFfdc>
+ <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id>
+ <basedOnPresentChildren>
+ <target>CHIP</target>
+ <childType>TARGET_TYPE_EX_CHIPLET</childType>
+ <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier>
+ </basedOnPresentChildren>
+ </collectRegisterFfdc>
+ </hwpError>
+ <!-- *********************************************************************** -->
+</hwpErrors> \ No newline at end of file
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.C
new file mode 100644
index 000000000..7ca0ad37d
--- /dev/null
+++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.C
@@ -0,0 +1,558 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.C $ */
+/* */
+/* OpenPOWER HostBoot Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2014 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+// $Id: proc_extract_pore_engine_state.C,v 1.3 2014/08/07 15:04:41 thi Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_pore_engine_state.C,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2012
+// *! All Rights Reserved -- Property of IBM
+// *! *** ***
+// *|
+// *! TITLE : proc_extract_pore_engine_state.C
+// *! DESCRIPTION : Extract PORE (SBE/SLW) engine state
+// *!
+// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com
+// *! BACKUP NAME : Johannes Koesters Email: koesters@de.ibm.com
+// *!
+// *! Overview:
+// *! - Dump state of SBE/SLW engine
+// *!
+//------------------------------------------------------------------------------
+
+
+#ifdef FAPIECMD
+ #if FAPIECMD == 1
+ #define PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE 0
+ #else
+ #define PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE 1
+ #endif
+#else
+ #ifdef __HOSTBOOT_MODULE
+ #define PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE 1
+ #else
+ #define PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE 0
+ #endif
+#endif
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <proc_extract_pore_engine_state.H>
+#include <p8_scom_addresses.H>
+#include <proc_extract_sbe_rc.H>
+
+#if PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE == 1
+ #include <poreve.H>
+#endif
+
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+const uint32_t SLW_VITAL_PIBMEM_OFFSET = 0x12;
+
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+extern "C"
+{
+
+
+/**
+ * proc_extract_pore_engine_state_sbe_ffdc - Extract SBE-specific engine state
+ *
+ * @param[in] i_target - target of chip with failed SBE
+ * @param[out] o_pore_sbe_state - PORE SBE-specific state/FFDC content
+ *
+ * @retval fapi::ReturnCode = SUCCESS
+ * @retval fapi::ReturnCode = results of cfam/SCOM access
+ */
+fapi::ReturnCode proc_extract_pore_engine_state_sbe_ffdc(
+ const fapi::Target & i_target,
+ por_sbe_base_state & o_pore_sbe_state)
+{
+ // return codes
+ fapi::ReturnCode rc;
+
+ FAPI_DBG("proc_extract_pore_engine_state_sbe_ffdc: Start");
+
+ do
+ {
+ // check cfam status register for any PIB errors
+ ecmdDataBufferBase cfam_status(32);
+ rc = fapiGetCfamRegister(i_target, CFAM_FSI_STATUS_0x00001007, cfam_status);
+ if (rc)
+ {
+ FAPI_ERR("proc_extract_pore_engine_state_sbe_ffdc: Error from fapiGetCfamRegister (CFAM_FSI_STATUS_0x00001007)");
+ break;
+ }
+
+ // bit 30 indicates SBE reported attention
+ if (cfam_status.isBitSet(30))
+ {
+ FAPI_ERR("proc_extract_pore_engine_state_sbe_ffdc: SBE reported attention to CFAM Status register");
+ o_pore_sbe_state.reported_attn = true;
+ }
+
+ // check ECCB engines (I2C/LPC) for UE/CE conditions
+ // SLW does not use these engines to access main memory, so no need to check
+ rc = fapiGetScom(i_target, PORE_ECCB_STATUS_REGISTER_READ_0x000C0002, o_pore_sbe_state.i2cm_eccb_status);
+ if (rc)
+ {
+ FAPI_ERR("proc_extract_pore_engine_state_sbe_ffdc: Error from fapiGetScom (PORE_ECCB_STATUS_REGISTER_READ_0x000C00002)");
+ break;
+ }
+
+ rc = fapiGetScom(i_target, LPC_STATUS_0x000B0002, o_pore_sbe_state.pnor_eccb_status);
+ if (rc)
+ {
+ FAPI_ERR("proc_extract_pore_engine_state_sbe_ffdc: Error from fapiGetScom (LPC_STATUS_0x000B0002)");
+ break;
+ }
+
+ // determine if either engine has reached threshold of > 128 CEs
+ if (o_pore_sbe_state.i2cm_eccb_status.isBitSet(57))
+ {
+ o_pore_sbe_state.soft_err = eSOFT_ERR_I2CM;
+ }
+
+ if (o_pore_sbe_state.pnor_eccb_status.isBitSet(57))
+ {
+ if (o_pore_sbe_state.soft_err == eSOFT_ERR_I2CM)
+ {
+ o_pore_sbe_state.soft_err = eSOFT_ERR_BOTH;
+ }
+ else
+ {
+ o_pore_sbe_state.soft_err = eSOFT_ERR_PNOR;
+ }
+ }
+ } while(0);
+
+ FAPI_DBG("proc_extract_pore_engine_state_sbe_ffdc: End");
+ return rc;
+}
+
+
+/**
+ * proc_extract_pore_engine_state_hw - Extract PORE engine state from HW
+ *
+ * @param[in] i_target - target of chip with failed SBE/SLW engine
+ * @param[in] i_engine - engine type (SBE/SLW)
+ * @param[out] o_vital_state - data buffer to hold SBE/SLW vital state
+ * @param[out] o_engine_state - data buffer to hold engine FFDC state
+ *
+ * @retval fapi::ReturnCode = SUCCESS
+ * @retval fapi::ReturnCode = results of cfam/SCOM access
+ */
+fapi::ReturnCode proc_extract_pore_engine_state_hw(
+ const fapi::Target & i_target,
+ const por_engine_t i_engine,
+ ecmdDataBufferBase & o_vital_state,
+ ecmdDataBufferBase & o_engine_state)
+{
+ // return codes
+ fapi::ReturnCode rc;
+ uint32_t rc_ecmd = 0x0;
+
+ FAPI_DBG("proc_extract_pore_engine_state_hw: Start");
+
+ do
+ {
+ // collect SBE/SLW vital register value
+ if (i_engine == SBE)
+ {
+ ecmdDataBufferBase cfam_vital_data(32);
+
+ // collect from SBE vital HW register
+ rc = fapiGetCfamRegister(i_target, CFAM_FSI_SBE_VITAL_0x0000281C, cfam_vital_data);
+ if (!rc.ok())
+ {
+ FAPI_ERR("proc_extract_pore_engine_state_hw: Error from fapiGetCfamRegister (CFAM_FSI_SBE_VITAL_0x0000281C)");
+ break;
+ }
+
+ rc_ecmd |= o_vital_state.setWord(0, cfam_vital_data.getWord(0));
+ rc_ecmd |= o_vital_state.setWord(1, 0x0);
+ if (rc_ecmd)
+ {
+ FAPI_ERR("proc_extract_pore_engine_state_hw: Error %x forming SBE Vital FFDC data buffers",
+ rc_ecmd);
+ rc.setEcmdError(rc_ecmd);
+ break;
+ }
+ }
+ else
+ {
+ // collect from PIBMEM (virtual SLW vital state)
+ rc = fapiGetScom(i_target,
+ PIBMEM0_0x00080000 + SLW_VITAL_PIBMEM_OFFSET,
+ o_vital_state);
+ if (!rc.ok())
+ {
+ FAPI_ERR("proc_extract_pore_engine_state_hw: Error from fapiGetCfamRegister (CFAM_FSI_SBE_VITAL_0x0000281C)");
+ break;
+ }
+ }
+
+ // collect SBE/SLW engine state
+ for (uint8_t offset = PORE_STATUS_OFFSET;
+ offset < PORE_NUM_REGS;
+ offset++)
+ {
+ ecmdDataBufferBase reg(64);
+
+ rc = fapiGetScom(i_target,
+ (uint32_t) i_engine + offset,
+ reg);
+ if (!rc.ok())
+ {
+ FAPI_ERR("proc_extract_pore_engine_state_hw: Error from fapiGetScom (0x%08X)",
+ (uint32_t) i_engine + offset);
+ break;
+ }
+
+ rc_ecmd |= o_engine_state.setDoubleWord(offset, reg.getDoubleWord(0));
+ if (rc_ecmd)
+ {
+ FAPI_ERR("proc_extract_pore_engine_state_hw: Error %x inserting engine FFDC data value (DW=%d)",
+ rc_ecmd, offset);
+ rc.setEcmdError(rc_ecmd);
+ break;
+ }
+ }
+ if (!rc.ok())
+ {
+ break;
+ }
+ } while(0);
+
+ FAPI_DBG("proc_extract_pore_engine_state_hw: End");
+ return rc;
+}
+
+
+/**
+ * proc_extract_pore_engine_state_virtual - Extract PORE engine state from virtual engine
+ *
+ * @param[in] i_target - target of chip with failed SBE engine
+ * @param[in] i_poreve - pointer to PoreVe object
+ * @param[out] o_vital_state - data buffer to hold SBE vital state
+ * @param[out] o_engine_state - data buffer to hold engine FFDC state
+ *
+ * @retval fapi::ReturnCode = SUCCESS
+ * @retval fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_MODEL_ERROR
+ * @retval fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_PIB_ERROR
+ */
+#if PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE == 1
+fapi::ReturnCode proc_extract_pore_engine_state_virtual(
+ const fapi::Target & i_target,
+ vsbe::PoreVe * i_poreve,
+ ecmdDataBufferBase & o_vital_state,
+ ecmdDataBufferBase & o_engine_state)
+{
+ // return codes
+ fapi::ReturnCode rc;
+ uint32_t rc_ecmd = 0x0;
+ vsbe::ModelError me;
+
+ FAPI_DBG("proc_extract_pore_engine_state_virtual: Start");
+
+ do
+ {
+ // extract SBE vital state
+ // - for processor chips, this should resolve to a getscom
+ // - for Centaur, the state should be extracted from the virtual model
+ uint64_t vital_data;
+ int pib_rc;
+ me = i_poreve->getscom(MBOX_SBEVITAL_0x0005001C, vital_data, pib_rc);
+ if (me != vsbe::ME_SUCCESS)
+ {
+ FAPI_ERR("proc_extract_pore_engine_state_virtual: Model error %x extracting SBE vital state",
+ (int) me);
+ const fapi::Target & CHIP = i_target;
+ const uint32_t & MODEL_ERROR = (uint32_t) me;
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_MODEL_ERROR);
+ break;
+ }
+ else if (pib_rc)
+ {
+ FAPI_ERR("proc_extract_pore_engine_state_virtual: PIB error getting SBE vital state (error code %d)",
+ pib_rc);
+ const fapi::Target & CHIP = i_target;
+ const int & PIB_ERROR = pib_rc;
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_PIB_ERROR);
+ break;
+ }
+ rc_ecmd = o_vital_state.setDoubleWord(0, vital_data);
+ if (rc_ecmd)
+ {
+ FAPI_ERR("proc_extract_pore_engine_state_virtual: Error %x inserting SBE vital FFDC data value",
+ rc_ecmd);
+ rc.setEcmdError(rc_ecmd);
+ break;
+ }
+
+ // extract engine state from model
+ vsbe::PoreState ve_state;
+ me = i_poreve->iv_pore.extractState(ve_state);
+ if (me != vsbe::ME_SUCCESS)
+ {
+ FAPI_ERR("proc_extract_pore_engine_state_virtual: Model error %x extracting virtual engine state",
+ (int) me);
+ const fapi::Target & CHIP = i_target;
+ const uint32_t & MODEL_ERROR = (uint32_t) me;
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_MODEL_ERROR);
+ break;
+ }
+
+ uint64_t status;
+ ve_state.get(vsbe::PORE_STATUS, status);
+ uint64_t control;
+ ve_state.get(vsbe::PORE_CONTROL, control);
+ uint64_t reset;
+ ve_state.get(vsbe::PORE_RESET, reset);
+ uint64_t table_base;
+ ve_state.get(vsbe::PORE_TABLE_BASE_ADDR, table_base);
+ uint64_t ibuf0, ibuf1;
+ ve_state.get(vsbe::PORE_IBUF_01, ibuf0);
+ ve_state.get(vsbe::PORE_IBUF_2, ibuf1);
+ uint64_t dbg0, dbg1;
+ ve_state.get(vsbe::PORE_DBG0, dbg0);
+ ve_state.get(vsbe::PORE_DBG1, dbg1);
+ uint64_t stack0, stack1, stack2;
+ ve_state.get(vsbe::PORE_PC_STACK0, stack0);
+ ve_state.get(vsbe::PORE_PC_STACK1, stack1);
+ ve_state.get(vsbe::PORE_PC_STACK2, stack2);
+ uint64_t mrr;
+ ve_state.get(vsbe::PORE_MEM_RELOC, mrr);
+ uint64_t i2c_e0, i2c_e1, i2c_e2;
+ ve_state.get(vsbe::PORE_I2C_E0_PARAM, i2c_e0);
+ ve_state.get(vsbe::PORE_I2C_E1_PARAM, i2c_e1);
+ ve_state.get(vsbe::PORE_I2C_E2_PARAM, i2c_e2);
+
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_STATUS_OFFSET, status);
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_CONTROL_OFFSET, control);
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_RESET_OFFSET, reset);
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_ERR_MASK_OFFSET, i_poreve->iv_pore.emr.read());
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_P0_OFFSET, (i_poreve->iv_pore.p0.read() << 32));
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_P1_OFFSET, (i_poreve->iv_pore.p1.read() << 32));
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_A0_OFFSET, i_poreve->iv_pore.a0.read());
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_A1_OFFSET, i_poreve->iv_pore.a1.read());
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_TBL_BASE_OFFSET, table_base);
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_EXE_TRIGGER_OFFSET, i_poreve->iv_pore.etr.read());
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_CTR_OFFSET, i_poreve->iv_pore.ctr.read());
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_D0_OFFSET, i_poreve->iv_pore.d0.read());
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_D1_OFFSET, i_poreve->iv_pore.d1.read());
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_IBUF0_OFFSET, ibuf0);
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_IBUF1_OFFSET, ibuf1);
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_DEBUG0_OFFSET, dbg0);
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_DEBUG1_OFFSET, dbg1);
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_STACK0_OFFSET, stack0);
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_STACK1_OFFSET, stack1);
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_STACK2_OFFSET, stack2);
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_IDFLAGS_OFFSET, i_poreve->iv_pore.ifr.read());
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_SPRG0_OFFSET, i_poreve->iv_pore.sprg0.read());
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_MRR_OFFSET, mrr);
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_I2CE0_OFFSET, i2c_e0);
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_I2CE1_OFFSET, i2c_e1);
+ rc_ecmd |= o_engine_state.setDoubleWord(PORE_I2CE2_OFFSET, i2c_e2);
+
+ if (rc_ecmd)
+ {
+ FAPI_ERR("proc_extract_pore_engine_state_virtual: Error %x inserting engine FFDC data value",
+ rc_ecmd);
+ rc.setEcmdError(rc_ecmd);
+ break;
+ }
+
+ } while(0);
+
+ FAPI_DBG("proc_extract_pore_engine_state_virtual: End");
+ return rc;
+}
+#endif
+
+/**
+ * proc_extract_pore_engine_state - HWP entry point, extract PORE engine state
+ *
+ * @param[in] i_target - chip target, used to collect engine state if
+ * i_poreve is NULL
+ * @param[in] i_poreve - pointer to PoreVe object, used to collect engine
+ * state if non NULL
+ * @param[in] i_engine - engine type to analyze (SBE/SLW)
+ * @param[out] o_pore_state - PORE state/FFDC content
+ * @param[out] o_pore_sbe_state - PORE SBE-specific state/FFDC content (filled
+ * only if i_engine=SBE)
+ *
+ * @retval fapi::ReturnCode = SUCCESS
+ * @retval fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_MODEL_ERROR
+ * @retval fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_PIB_ERROR
+ * @retval fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_UNSUPPORTED_INVOCATION
+ */
+fapi::ReturnCode proc_extract_pore_engine_state(const fapi::Target & i_target,
+ void * i_poreve,
+ const por_engine_t i_engine,
+ por_base_state & o_pore_state,
+ por_sbe_base_state & o_pore_sbe_state)
+{
+ // return code
+ fapi::ReturnCode rc;
+
+ do
+ {
+ //
+ // check arguments
+ //
+
+ // virtual SBE for processor or Centaur OR
+ // real SBE/SLW for processor
+ bool is_virtual = (i_poreve != NULL);
+#if PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE == 1
+ bool is_virtual_supported = true;
+ vsbe::PoreVe * ve = reinterpret_cast<vsbe::PoreVe *>(i_poreve);
+#else
+ bool is_virtual_supported = false;
+#endif
+ bool is_processor = (i_target.getType() == fapi::TARGET_TYPE_PROC_CHIP);
+ bool is_centaur = (i_target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP);
+ bool is_sbe = (i_engine == SBE);
+ bool is_slw = (i_engine == SLW);
+
+ o_pore_state.target = i_target;
+ o_pore_state.engine = i_engine;
+ o_pore_state.is_virtual = is_virtual;
+
+ if (!((is_virtual && is_virtual_supported && (is_processor || is_centaur) && is_sbe) ||
+ (!is_virtual && is_processor && (is_sbe || is_slw))))
+ {
+ FAPI_ERR("proc_extract_pore_engine_state: Unsupported invocation for target: %s, engine type: %s, virtual: %d",
+ i_target.toEcmdString(), ((i_engine == SBE)?("SBE"):("SLW")), is_virtual);
+ const fapi::Target & CHIP = i_target;
+ const por_engine_t & ENGINE = i_engine;
+ const bool & VIRTUAL = is_virtual;
+ const bool & VIRTUAL_IS_SUPPORTED = is_virtual_supported;
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_ENGINE_STATE_UNSUPPORTED_INVOCATION);
+ break;
+ }
+
+
+ //
+ // extract engine state
+ //
+
+ FAPI_INF("proc_extract_pore_engine_state: Extracting PORE engine FFDC for target: %s, engine type: %s, virtual: %d",
+ i_target.toEcmdString(), ((i_engine == SBE)?("SBE"):("SLW")), is_virtual);
+
+ // collect engine state from virtual PORE engine
+ if (is_virtual)
+ {
+#if PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE == 1
+ rc = proc_extract_pore_engine_state_virtual(i_target,
+ ve,
+ o_pore_state.vital_state,
+ o_pore_state.engine_state);
+ if (!rc.ok())
+ {
+ FAPI_ERR("proc_extract_pore_engine_state: Error from proc_extract_pore_engine_state_virtual");
+ break;
+ }
+#endif
+ }
+ // HW
+ else
+ {
+ rc = proc_extract_pore_engine_state_hw(i_target,
+ i_engine,
+ o_pore_state.vital_state,
+ o_pore_state.engine_state);
+ if (!rc.ok())
+ {
+ FAPI_ERR("proc_extract_pore_engine_state: Error from proc_extract_pore_engine_state_hw");
+ break;
+ }
+ }
+
+ FAPI_INF("proc_extract_pore_engine_state: PORE_VITAL = 0x%016llX", o_pore_state.vital_state.getDoubleWord(0));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_STATUS = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_STATUS_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_CONTROL = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_CONTROL_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_RESET = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_RESET_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_ERR_MASK = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_ERR_MASK_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_P0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_P0_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_P1 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_P1_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_A0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_A0_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_A1 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_A1_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_TBL_BASE = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_TBL_BASE_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_EXE_TRIGGER = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_EXE_TRIGGER_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_CTR = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_CTR_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_D0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_D0_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_D1 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_D1_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_IBUF0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_IBUF0_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_IBUF1 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_IBUF1_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_DEBUG0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_DEBUG0_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_DEBUG1 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_DEBUG1_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_STACK0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_STACK0_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_STACK1 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_STACK1_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_STACK2 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_STACK2_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_IDFLAGS = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_IDFLAGS_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_SPRG0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_SPRG0_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_MRR = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_MRR_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_I2CE0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_I2CE0_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_I2CE1 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_I2CE1_OFFSET));
+ FAPI_INF("proc_extract_pore_engine_state: PORE_I2CE2 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_I2CE2_OFFSET));
+
+ o_pore_state.pc = (o_pore_state.engine_state.getDoubleWord(PORE_STATUS_OFFSET) & 0x0000FFFFFFFFFFFFULL);
+ FAPI_INF("proc_extract_pore_engine_state: PORE_PC = 0x%016llX", o_pore_state.pc);
+
+ //
+ // processor SBE specific state collection
+ //
+
+ if (is_processor && is_sbe)
+ {
+ rc = proc_extract_pore_engine_state_sbe_ffdc(i_target,
+ o_pore_sbe_state);
+ if (!rc.ok())
+ {
+ FAPI_ERR("proc_extract_pore_engine_state: Error from proc_extract_pore_engine_state_sbe_ffdc");
+ break;
+ }
+
+ FAPI_INF("proc_extract_pore_engine_state: SBE SEEPROM ECCB = %016llX", o_pore_sbe_state.i2cm_eccb_status.getDoubleWord(0));
+ FAPI_INF("proc_extract_pore_engine_state: SBE PNOR ECCB = %016llX", o_pore_sbe_state.pnor_eccb_status.getDoubleWord(0));
+ FAPI_INF("proc_extract_pore_engine_state: SBE soft error = %d", o_pore_sbe_state.soft_err);
+ FAPI_INF("proc_extract_pore_engine_state: SBE attn = %d", o_pore_sbe_state.reported_attn);
+ }
+ } while(0);
+
+ FAPI_INF("proc_extract_pore_engine_state: End");
+ return rc;
+}
+
+
+} // extern "C"
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.H b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.H
new file mode 100644
index 000000000..6a2b7fc42
--- /dev/null
+++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.H
@@ -0,0 +1,97 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.H $ */
+/* */
+/* OpenPOWER HostBoot Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2014 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+// $Id: proc_extract_pore_engine_state.H,v 1.2 2014/07/24 03:16:22 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_pore_engine_state.H,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2012
+// *! All Rights Reserved -- Property of IBM
+// *! *** ***
+// *|
+// *! TITLE : proc_extract_pore_engine_state.H
+// *! DESCRIPTION : Extract PORE (SBE/SLW) engine state
+// *!
+// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com
+// *! BACKUP NAME : Johannes Koesters Email: koesters@de.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+#ifndef _PROC_EXTRACT_PORE_ENGINE_STATE_H_
+#define _PROC_EXTRACT_PORE_ENGINE_STATE_H_
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <fapi.H>
+#include <proc_extract_sbe_rc.H>
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+// function pointer typedef definition for HWP call support
+typedef fapi::ReturnCode (*proc_extract_pore_engine_state_FP_t)(const fapi::Target &,
+ void *,
+ const por_engine_t,
+ por_base_state &,
+ por_sbe_base_state &);
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+
+extern "C"
+{
+
+
+/**
+ * proc_extract_pore_engine_state - HWP entry point, extract PORE engine state
+ *
+ * @param[in] i_target - chip target, used to collect engine state if
+ * i_poreve is NULL
+ * @param[in] i_poreve - pointer to PoreVe object, used to collect engine
+ * state if non NULL
+ * @param[in] i_engine - engine type to analyze (SBE/SLW)
+ * @param[out] o_pore_state - PORE state/FFDC content
+ * @param[out] o_pore_sbe_state - PORE SBE-specific state/FFDC content (filled
+ * only if i_engine=SBE)
+ *
+ * @retval fapi::ReturnCode = SUCCESS
+ * @retval fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_MODEL_ERROR
+ * @retval fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_PIB_ERROR
+ * @retval fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_UNSUPPORTED_INVOCATION
+ */
+fapi::ReturnCode proc_extract_pore_engine_state(const fapi::Target & i_target,
+ void *,
+ const por_engine_t i_engine,
+ por_base_state & o_pore_state,
+ por_sbe_base_state & o_pore_sbe_state);
+
+
+} // extern "C"
+
+#endif // _PROC_EXTRACT_PORE_ENGINE_STATE_H_
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state_errors.xml b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state_errors.xml
new file mode 100644
index 000000000..711e5119e
--- /dev/null
+++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state_errors.xml
@@ -0,0 +1,93 @@
+<!-- IBM_PROLOG_BEGIN_TAG -->
+<!-- This is an automatically generated prolog. -->
+<!-- -->
+<!-- $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state_errors.xml $ -->
+<!-- -->
+<!-- OpenPOWER HostBoot Project -->
+<!-- -->
+<!-- Contributors Listed Below - COPYRIGHT 2014 -->
+<!-- [+] International Business Machines Corp. -->
+<!-- -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
+<!-- implied. See the License for the specific language governing -->
+<!-- permissions and limitations under the License. -->
+<!-- -->
+<!-- IBM_PROLOG_END_TAG -->
+<!-- $Id: proc_extract_pore_engine_state_errors.xml,v 1.2 2014/07/24 03:11:21 jmcgill Exp $ $ -->
+<!-- Error definitions for proc_extract_pore_engine_state HWP -->
+<hwpErrors>
+ <!-- *********************************************************************** -->
+ <hwpError>
+ <rc>RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_MODEL_ERROR</rc>
+ <description>
+ Procedure: proc_extract_pore_engine_state
+ Virtual SBE model error occurred when attempting to access SBE vital state.
+ </description>
+ <ffdc>CHIP</ffdc>
+ <ffdc>MODEL_ERROR</ffdc>
+ <callout>
+ <target>CHIP</target>
+ <priority>HIGH</priority>
+ </callout>
+ <callout>
+ <procedure>CODE</procedure>
+ <priority>LOW</priority>
+ </callout>
+ <deconfigure>
+ <target>CHIP</target>
+ </deconfigure>
+ <gard>
+ <target>CHIP</target>
+ </gard>
+ </hwpError>
+ <!-- *********************************************************************** -->
+ <hwpError>
+ <rc>RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_PIB_ERROR</rc>
+ <description>
+ Procedure: proc_extract_pore_engine_state
+ PIB error occurred when attempting to access SBE vital state from virtual SBE model.
+ </description>
+ <ffdc>CHIP</ffdc>
+ <ffdc>PIB_ERROR</ffdc>
+ <callout>
+ <target>CHIP</target>
+ <priority>HIGH</priority>
+ </callout>
+ <callout>
+ <procedure>CODE</procedure>
+ <priority>LOW</priority>
+ </callout>
+ <deconfigure>
+ <target>CHIP</target>
+ </deconfigure>
+ <gard>
+ <target>CHIP</target>
+ </gard>
+ </hwpError>
+ <!-- *********************************************************************** -->
+ <hwpError>
+ <rc>RC_PROC_EXTRACT_PORE_ENGINE_STATE_UNSUPPORTED_INVOCATION</rc>
+ <description>
+ Procedure: proc_extract_pore_engine_state
+ Unsupported engine type presented for analysis.
+ </description>
+ <ffdc>CHIP</ffdc>
+ <ffdc>ENGINE</ffdc>
+ <ffdc>VIRTUAL</ffdc>
+ <ffdc>VIRTUAL_IS_SUPPORTED</ffdc>
+ <callout>
+ <procedure>CODE</procedure>
+ <priority>HIGH</priority>
+ </callout>
+ </hwpError>
+ <!-- *********************************************************************** -->
+</hwpErrors> \ No newline at end of file
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.C
new file mode 100644
index 000000000..aaf28f372
--- /dev/null
+++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.C
@@ -0,0 +1,550 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.C $ */
+/* */
+/* OpenPOWER HostBoot Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2014 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+// $Id: proc_extract_pore_halt_ffdc.C,v 1.2 2014/08/07 13:32:17 thi Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_pore_halt_ffdc.C,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2012
+// *! All Rights Reserved -- Property of IBM
+// *! *** ***
+// *|
+// *! TITLE : proc_extract_pore_halt_ffdc.C
+// *! DESCRIPTION : Extract halt-fail related FFDC for selected SBE/SLW errors
+// *!
+// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <p8_scom_addresses.H>
+#include <proc_extract_pore_halt_ffdc.H>
+
+
+// -----------------------------------------------------------------------------
+// Constant definitions
+// -----------------------------------------------------------------------------
+
+// X Clock Adjust Set register bit/field definitions
+const uint32_t X_CLK_ADJ_SET_REG_SYNC_BIT = 2;
+const uint32_t X_CLK_ADJ_SET_REG_RLM_SELECT_BIT = 5;
+const uint32_t X_CLK_ADJ_SET_REG_CMD_START_BIT = 6;
+const uint32_t X_CLK_ADJ_SET_REG_CMD_END_BIT = 9;
+const uint32_t X_CLK_ADJ_SET_REG_DATA_START_BIT = 21;
+const uint32_t X_CLK_ADJ_SET_REG_DATA_END_BIT = 28;
+
+const uint8_t X_CLK_ADJ_CMD_TYPE_READ = 0xE;
+
+
+const uint64_t scan_ffdc_addr_arr[] =
+{
+ GENERIC_CLK_SYNC_CONFIG_0x00030000,
+ GENERIC_OPCG_CNTL0_0x00030002,
+ GENERIC_OPCG_CNTL1_0x00030003,
+ GENERIC_OPCG_CNTL2_0x00030004,
+ GENERIC_OPCG_CNTL3_0x00030005,
+ GENERIC_CLK_REGION_0x00030006,
+ GENERIC_CLK_SCANSEL_0x00030007,
+ GENERIC_CLK_STATUS_0x00030008,
+ GENERIC_CLK_ERROR_0x00030009,
+ GENERIC_CLK_SCANDATA0_0x00038000
+};
+
+const uint64_t instruct_start_ffdc_addr_arr[] =
+{
+ EX_PERV_TCTL0_R_MODE_0x10013001,
+ EX_PERV_TCTL0_R_STAT_0x10013002,
+ EX_PERV_TCTL0_POW_STAT_0x10013004,
+ EX_PCNE_REG0_HOLD_OUT_0x1001300D,
+ EX_PERV_THREAD_ACTIVE_0x1001310E,
+ EX_CORE_FIR_0x10013100,
+ EX_SPATTN_0x10040004,
+ PM_SPECIAL_WKUP_FSP_0x100F010B,
+ PM_SPECIAL_WKUP_OCC_0x100F010C,
+ PM_SPECIAL_WKUP_PHYP_0x100F010D,
+ EX_OHA_RO_STATUS_REG_0x1002000B,
+ EX_OHA_MODE_REG_RWx1002000D,
+ EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011,
+ EX_OHA_RO_STATUS_REG_0x1002000B,
+ EX_OHA_AISS_IO_REG_0x10020014,
+ EX_GP3_0x100F0012,
+ EX_PMGP0_0x100F0100,
+ EX_PMGP1_0x100F0103,
+ EX_PFET_CTL_REG_0x100F0106,
+ EX_PFET_STAT_REG_0x100F0107,
+ EX_PFET_CTL_REG_0x100F010E,
+ EX_PMSTATEHISTPERF_REG_0x100F0113,
+ EX_PCBS_FSM_MONITOR1_REG_0x100F0170,
+ EX_PCBS_FSM_MONITOR2_REG_0x100F0171,
+ EX_PMErr_REG_0x100F0109,
+ EX_PCBS_DPLL_STATUS_REG_100F0161,
+ EX_DPLL_CPM_PARM_REG_0x100F0152
+};
+
+const uint64_t dpll_lock_ffdc_addr_arr[] =
+{
+ EX_DPLL_CPM_PARM_REG_0x100F0152,
+ EX_PMGP0_0x100F0100,
+ EX_GP3_0x100F0012
+};
+
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+extern "C"
+{
+
+
+/**
+ * proc_extract_pore_halt_ffdc_unicast - collect FFDC data for one chiplet
+ *
+ * @param[in] i_target - target for FFDC collection
+ * @param[in] i_halt_type - FFDC type, for logging
+ * @param[in] i_ffdc_addrs - FFDC addresses to log
+ * @param[in] i_base_scom_addr - base SCOM address (XX000000) to apply
+ * to entries of i_ffdc_addrs_log
+ * @param[out] o_rc - target return code for extra FFDC
+ *
+ * @retval fapi::ReturnCode = SUCCESS
+ */
+fapi::ReturnCode proc_extract_pore_halt_ffdc_unicast(const fapi::Target & i_target,
+ const por_halt_type_t i_halt_type,
+ const std::vector<uint64_t> * i_ffdc_addrs,
+ const uint32_t i_base_scom_addr,
+ fapi::ReturnCode & o_rc)
+{
+ // return code
+ fapi::ReturnCode rc;
+ uint32_t rc_ecmd = 0x0;
+
+ // FFDC collection
+ ecmdDataBufferBase ffdc_reg_addrs(64*(i_ffdc_addrs->size()));
+ ecmdDataBufferBase ffdc_reg_data(64*(i_ffdc_addrs->size()));
+ uint8_t dw_index = 0;
+
+ FAPI_INF("proc_extract_pore_halt_ffdc_unicast: Start (target = %s, base = 0x%08X)",
+ i_target.toEcmdString(), i_base_scom_addr);
+
+ do
+ {
+ rc_ecmd |= ffdc_reg_addrs.flushTo1();
+ rc_ecmd |= ffdc_reg_data.flushTo1();
+ if (rc_ecmd)
+ {
+ FAPI_ERR("proc_extract_pore_halt_ffdc_unicast: Error %x flushing FFDC data buffers", rc_ecmd);
+ rc.setEcmdError(rc_ecmd);
+ break;
+ }
+
+ for (std::vector<uint64_t>::const_iterator i = i_ffdc_addrs->begin();
+ i != i_ffdc_addrs->end();
+ i++)
+ {
+ ecmdDataBufferBase data(64);
+ uint32_t scom_addr = (uint32_t) (*i);
+ scom_addr &= 0x0FFFFFFF;
+ scom_addr += i_base_scom_addr;
+
+ FAPI_DBG("proc_extract_pore_halt_ffdc_unicast: Dumping 0x%08X on %s",
+ scom_addr, i_target.toEcmdString());
+
+ // explicitly ignore return code, attempt to collect all FFDC registers
+ rc = fapiGetScom(i_target, scom_addr, data);
+ rc_ecmd |= ffdc_reg_addrs.setDoubleWord(dw_index, scom_addr);
+ if (rc.ok())
+ {
+ rc_ecmd |= ffdc_reg_data.setDoubleWord(dw_index, data.getDoubleWord(0));
+ }
+ else
+ {
+ rc = fapi::FAPI_RC_SUCCESS;
+ }
+
+ if (rc_ecmd)
+ {
+ FAPI_ERR("proc_extract_pore_halt_ffdc_unicast: Error %x forming FFDC data buffers", rc_ecmd);
+ rc.setEcmdError(rc_ecmd);
+ break;
+ }
+ dw_index++;
+ }
+ if (!rc.ok())
+ {
+ break;
+ }
+
+ } while(0);
+
+ const fapi::Target & TARGET = i_target;
+ const por_halt_type_t & PORE_HALT_TYPE = i_halt_type;
+ const ecmdDataBufferBase & FFDC_ADDRESSES = ffdc_reg_addrs;
+ const ecmdDataBufferBase & FFDC_DATA = ffdc_reg_data;
+ FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_PROC_EXTRACT_PORE_HALT_FFDC);
+
+ FAPI_INF("proc_extract_pore_halt_ffdc_unicast: End");
+ return rc;
+}
+
+
+/**
+ * proc_extract_pore_halt_ffdc_skew_adjust - collect FFDC data for XBUS skew adjust halt
+ *
+ * @param[in] i_target - target for FFDC collection
+ * @param[in] i_halt_type - FFDC type, for logging
+ * @param[out] o_rc - target return code for extra FFDC
+ *
+ * @retval fapi::ReturnCode = SUCCESS
+ */
+fapi::ReturnCode proc_extract_pore_halt_ffdc_skew_adjust(const fapi::Target & i_target,
+ const por_halt_type_t i_halt_type,
+ fapi::ReturnCode & o_rc)
+{
+ // return code
+ fapi::ReturnCode rc;
+ uint32_t rc_ecmd = 0x0;
+
+ // FFDC collection
+ const uint8_t READ_REGS = 16;
+ ecmdDataBufferBase ffdc_reg_addrs(64*READ_REGS);
+ ecmdDataBufferBase ffdc_reg_data(64*READ_REGS);
+
+ FAPI_INF("proc_extract_pore_halt_ffdc_skew_adjust: Start (target = %s)",
+ i_target.toEcmdString());
+
+ for (uint8_t dw_index = 0; dw_index < READ_REGS; dw_index++)
+ {
+ ecmdDataBufferBase data(64);
+ bool iter_valid = true;
+
+ // write set register with sync bit asserted
+ rc_ecmd |= data.setBit(X_CLK_ADJ_SET_REG_SYNC_BIT);
+ rc_ecmd |= data.setBit(X_CLK_ADJ_SET_REG_RLM_SELECT_BIT);
+ rc_ecmd |= data.insertFromRight(
+ X_CLK_ADJ_CMD_TYPE_READ,
+ X_CLK_ADJ_SET_REG_CMD_START_BIT,
+ (X_CLK_ADJ_SET_REG_CMD_END_BIT-
+ X_CLK_ADJ_SET_REG_CMD_START_BIT+1));
+ rc_ecmd |= data.insertFromRight(
+ dw_index,
+ X_CLK_ADJ_SET_REG_DATA_START_BIT,
+ (X_CLK_ADJ_SET_REG_DATA_END_BIT-
+ X_CLK_ADJ_SET_REG_DATA_START_BIT+1));
+ if (rc_ecmd)
+ {
+ FAPI_ERR("proc_extract_pore_halt_ffdc_skew_adjust: Error %x forming X CLK Adjust Set register data buffer (set)",
+ rc_ecmd);
+ rc.setEcmdError(rc_ecmd);
+ break;
+ }
+
+ rc = fapiPutScom(i_target, X_CLK_ADJ_SET_0x040F0016, data);
+ if (!rc.ok())
+ {
+ FAPI_ERR("proc_extract_pore_halt_ffdc_skew_adjust: Error from fapiPutScom (X_CLK_ADJ_SET_0x040F0016)");
+ iter_valid = false;
+ }
+
+ // write set register with sync bit cleared
+ rc_ecmd |= data.clearBit(X_CLK_ADJ_SET_REG_SYNC_BIT);
+ if (rc_ecmd)
+ {
+ FAPI_ERR("proc_extract_pore_halt_ffdc_skew_adjust: Error %x forming X CLK Adjust Set register data buffer (clear)",
+ rc_ecmd);
+ rc.setEcmdError(rc_ecmd);
+ break;
+ }
+
+ rc = fapiPutScom(i_target, X_CLK_ADJ_SET_0x040F0016, data);
+ if (!rc.ok())
+ {
+ FAPI_ERR("proc_extract_pore_halt_ffdc_skew_adjust: Error from fapiPutScom (X_CLK_ADJ_SET_0x040F0016)");
+ iter_valid = false;
+ }
+
+ rc = fapiGetScom(i_target, X_CLK_ADJ_DAT_REG_0x040F0015, data);
+ if (!rc.ok())
+ {
+ FAPI_ERR("proc_extract_pore_halt_ffdc_skew_adjust: Error from fapiGetScom (X_CLK_ADJ_DAT_REG_0x040F0015)");
+ iter_valid = false;
+ }
+
+ rc_ecmd |= ffdc_reg_addrs.setDoubleWord(dw_index, dw_index);
+ if (iter_valid)
+ {
+ rc_ecmd |= ffdc_reg_data.setDoubleWord(dw_index, data.getDoubleWord(0));
+ }
+ else
+ {
+ rc_ecmd |= ffdc_reg_data.setDoubleWord(dw_index, 0xFFFFFFFFFFFFFFFFULL);
+ rc = fapi::FAPI_RC_SUCCESS;
+ }
+ if (rc_ecmd)
+ {
+ FAPI_ERR("proc_extract_pore_halt_ffdc_skew_adjust: Error %x forming FFDC data buffers", rc_ecmd);
+ rc.setEcmdError(rc_ecmd);
+ break;
+ }
+ }
+
+ const fapi::Target & TARGET = i_target;
+ const por_halt_type_t & PORE_HALT_TYPE = i_halt_type;
+ const ecmdDataBufferBase & FFDC_ADDRESSES = ffdc_reg_addrs;
+ const ecmdDataBufferBase & FFDC_DATA = ffdc_reg_data;
+ FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_PROC_EXTRACT_PORE_HALT_FFDC);
+
+ FAPI_INF("proc_extract_pore_halt_ffdc_skew_adjust: End");
+ return rc;
+}
+
+
+
+/**
+ * proc_extract_pore_halt_ffdc - HWP entry point, log PORE fail FFDC
+ *
+ * @param[in] i_pore_state - struct holding PORE state
+ * @param[in] i_halt_type - FFDC type to collect
+ * @param[in] i_offset - offset to apply to FFDC registers for
+ * i_halt_type (constant/value of PORE
+ * pervasive base registers/none)
+ * @param[out] o_rc - target return code for extra FFDC
+ *
+ * @retval fapi::ReturnCode = SUCCESS
+ */
+fapi::ReturnCode proc_extract_pore_halt_ffdc(const por_base_state & i_pore_state,
+ const por_halt_type_t i_halt_type,
+ const por_ffdc_offset_t i_offset,
+ fapi::ReturnCode & o_rc)
+{
+ // return code
+ fapi::ReturnCode rc;
+ uint32_t rc_ecmd = 0x0;
+
+ // FFDC register collection pointer
+ const std::vector<uint64_t> *p = NULL;
+ std::vector<uint64_t> scan_ffdc_addr(scan_ffdc_addr_arr, scan_ffdc_addr_arr + (sizeof(scan_ffdc_addr_arr) / sizeof(scan_ffdc_addr_arr[0])));
+ std::vector<uint64_t> instruct_start_ffdc_addr(instruct_start_ffdc_addr_arr, instruct_start_ffdc_addr_arr + (sizeof(instruct_start_ffdc_addr_arr) / sizeof(instruct_start_ffdc_addr_arr[0])));
+ std::vector<uint64_t> dpll_lock_ffdc_addr(dpll_lock_ffdc_addr_arr, dpll_lock_ffdc_addr_arr + (sizeof(dpll_lock_ffdc_addr_arr) / sizeof(dpll_lock_ffdc_addr_arr[0])));
+
+ FAPI_INF("proc_extract_pore_halt_ffdc: Start");
+
+ do
+ {
+ const fapi::Target & TARGET = i_pore_state.target;
+ const por_halt_type_t & PORE_HALT_TYPE = i_halt_type;
+
+ if (i_halt_type == PORE_HALT_SKEW_ADJUST_FAIL)
+ {
+ FAPI_DBG("proc_extract_pore_halt_ffdc: Collecting skew adjust FFDC");
+ if (i_pore_state.target.getType() == fapi::TARGET_TYPE_PROC_CHIP)
+ {
+ rc = proc_extract_pore_halt_ffdc_skew_adjust(i_pore_state.target,
+ i_halt_type,
+ o_rc);
+ if (!rc.ok())
+ {
+ FAPI_ERR("proc_extract_pore_halt_ffdc: Error from proc_extract_pore_halt_ffdc_skew_adjust");
+ break;
+ }
+ }
+ else
+ {
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_HALT_FFDC_BAD_TYPE);
+ break;
+ }
+ }
+ else if (i_halt_type == PORE_HALT_FIR_FAIL)
+ {
+ FAPI_DBG("proc_extract_pore_halt_ffdc: Collecting FIR FFDC");
+ if (i_pore_state.target.getType() == fapi::TARGET_TYPE_PROC_CHIP)
+ {
+ FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_PROC_FIR_FFDC);
+ break;
+ }
+ else if (i_pore_state.target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP)
+ {
+ FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_CEN_FIR_FFDC);
+ break;
+ }
+ else
+ {
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_HALT_FFDC_BAD_TYPE);
+ break;
+ }
+ }
+ else
+ {
+ // set pointer based on halt type
+ switch (i_halt_type)
+ {
+ case PORE_HALT_SCAN_FAIL:
+ case PORE_HALT_SCAN_FLUSH_FAIL:
+ case PORE_HALT_ARRAYINIT_FAIL:
+ p = &(scan_ffdc_addr);
+ FAPI_DBG("proc_extract_pore_halt_ffdc: Pointer set to scan FFDC array");
+ break;
+ case PORE_HALT_INSTRUCT_FAIL:
+ p = &(instruct_start_ffdc_addr);
+ FAPI_DBG("proc_extract_pore_halt_ffdc: Pointer set to instruction start FFDC array");
+ break;
+ case PORE_HALT_DPLL_LOCK_FAIL:
+ p = &(dpll_lock_ffdc_addr);
+ FAPI_DBG("proc_extract_pore_halt_ffdc: Pointer set to DPLL lock FFDC array");
+ break;
+ default:
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_HALT_FFDC_BAD_TYPE);
+ break;
+ }
+ if (!rc.ok())
+ {
+ break;
+ }
+
+ // determine chiplet ID offset to apply to FFDC registers collected
+ // for this halt type
+ uint32_t chiplet_id = i_offset;
+ if ((i_offset == POR_FFDC_OFFSET_USE_P0) ||
+ (i_offset == POR_FFDC_OFFSET_USE_P1))
+ {
+ chiplet_id = 0x0;
+ // chiplet addressed is stored in one of the PORE pervasive base registers
+ // use the value of that register to form the chiplet portion of the FFDC
+ // SCOM addresses
+ rc_ecmd |= i_pore_state.engine_state.extractPreserve(
+ &chiplet_id,
+ (64*(i_offset)) + 24,
+ 8,
+ 0);
+
+ if (rc_ecmd)
+ {
+ FAPI_ERR("proc_extract_pore_halt_ffdc: Error %x extracting P%d pervasive base content",
+ rc_ecmd, (i_offset == POR_FFDC_OFFSET_USE_P0)?(0):(1));
+ rc.setEcmdError(rc_ecmd);
+ break;
+ }
+ }
+
+ // multicast address
+ // only support EX multicast unrolling for processor chip targets
+ if (chiplet_id & 0x40000000)
+ {
+ uint8_t mc_group = (chiplet_id >> 24) & 0x3;
+ std::vector<fapi::Target> ex_chiplets;
+
+ if ((i_pore_state.target.getType() == fapi::TARGET_TYPE_PROC_CHIP) &&
+ ((mc_group == 1) || (mc_group == 2)))
+ {
+ // determine set of EX chiplets
+ rc = fapiGetChildChiplets(i_pore_state.target,
+ fapi::TARGET_TYPE_EX_CHIPLET,
+ ex_chiplets,
+ fapi::TARGET_STATE_FUNCTIONAL);
+ if (!rc.ok())
+ {
+ FAPI_ERR("proc_extract_pore_halt_ffdc: Error from fapiGetChildChiplets");
+ break;
+ }
+
+ // collect FFDC for chiplets which are part of the multicast group
+ for (std::vector<fapi::Target>::iterator i = ex_chiplets.begin();
+ i != ex_chiplets.end();
+ i++)
+ {
+ ecmdDataBufferBase mc_config_data(64);
+ uint64_t mc_group_addr = (mc_group == 1)?(EX_MCGR2_0x100F0002):(EX_MCGR3_0x100F0003);
+ uint8_t mc_group_listen;
+
+ rc = fapiGetScom(*i, mc_group_addr, mc_config_data);
+ if (!rc.ok())
+ {
+ FAPI_ERR("proc_extract_pore_halt_ffdc: Error from fapiGetScom (EX_MCGR%d_0x%08llX)",
+ mc_group+1, mc_group_addr);
+ break;
+ }
+
+ rc_ecmd |= mc_config_data.extractToRight(&mc_group_listen, 3, 3);
+ if (rc_ecmd)
+ {
+ FAPI_ERR("proc_extract_pore_halt_ffdc: Error %x extracting multicast group listen configuration", rc_ecmd);
+ rc.setEcmdError(rc_ecmd);
+ break;
+ }
+
+ if (mc_group_listen == mc_group)
+ {
+ rc = proc_extract_pore_halt_ffdc_unicast(*i, i_halt_type, p, 0x10000000, o_rc);
+ if (!rc.ok())
+ {
+ if (!rc.ok())
+ {
+ FAPI_ERR("proc_extract_pore_halt_ffdc: Error from proc_extract_pore_halt_ffdc_unicast");
+ break;
+ }
+ }
+ }
+ else
+ {
+ FAPI_INF("proc_extract_pore_halt_ffdc: Skipping %s, not part of multicast group",
+ i->toEcmdString());
+ }
+ }
+ if (!rc.ok())
+ {
+ break;
+ }
+ }
+ else
+ {
+ FAPI_ERR("proc_extract_halt_ffdc: Unsupported multicast extraction for target: %s, group: %d",
+ i_pore_state.target.toEcmdString(), mc_group);
+ const uint8_t & CHIPLET_ID = chiplet_id;
+ const uint8_t & MC_GROUP = mc_group;
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_HALT_FFDC_BAD_MULTICAST);
+ break;
+ }
+ }
+ // unicast address
+ else
+ {
+ rc = proc_extract_pore_halt_ffdc_unicast(i_pore_state.target, i_halt_type, p, chiplet_id, o_rc);
+ if (!rc.ok())
+ {
+ FAPI_ERR("proc_extract_pore_halt_ffdc: Error from proc_extract_pore_halt_ffdc_unicast");
+ break;
+ }
+ }
+ }
+ } while(0);
+
+ FAPI_INF("proc_extract_pore_halt_ffdc: End");
+ return rc;
+}
+
+
+} // extern "C"
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.H b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.H
new file mode 100644
index 000000000..1e9d4e2d3
--- /dev/null
+++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.H
@@ -0,0 +1,88 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.H $ */
+/* */
+/* OpenPOWER HostBoot Project */
+/* */
+/* Contributors Listed Below - COPYRIGHT 2014 */
+/* [+] International Business Machines Corp. */
+/* */
+/* */
+/* Licensed under the Apache License, Version 2.0 (the "License"); */
+/* you may not use this file except in compliance with the License. */
+/* You may obtain a copy of the License at */
+/* */
+/* http://www.apache.org/licenses/LICENSE-2.0 */
+/* */
+/* Unless required by applicable law or agreed to in writing, software */
+/* distributed under the License is distributed on an "AS IS" BASIS, */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
+/* implied. See the License for the specific language governing */
+/* permissions and limitations under the License. */
+/* */
+/* IBM_PROLOG_END_TAG */
+// $Id: proc_extract_pore_halt_ffdc.H,v 1.1 2014/07/23 19:38:06 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_pore_halt_ffdc.H,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2012
+// *! All Rights Reserved -- Property of IBM
+// *! *** ***
+// *|
+// *! TITLE : proc_extract_pore_halt_ffdc.C
+// *! DESCRIPTION : Extract SBE/SLW halt-fail related FFDC
+// *!
+// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+#ifndef _PROC_EXTRACT_PORE_HALT_FFDC_H_
+#define _PROC_EXTRACT_PORE_HALT_FFDC_H_
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <fapi.H>
+#include <proc_extract_sbe_rc.H>
+
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+// function pointer typedef definition for HWP call support
+typedef fapi::ReturnCode (*proc_extract_pore_halt_ffdc_FP_t)(const por_base_state &,
+ const por_halt_type_t,
+ const por_ffdc_offset_t,
+ fapi::ReturnCode &);
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+
+extern "C"
+{
+
+/**
+ * proc_extract_pore_halt_ffdc - HWP entry point, log PORE fail FFDC
+ *
+ * @param[in] i_pore_state - struct holding PORE state
+ * @param[in] i_halt_type - FFDC type to collect
+ * @param[in] i_offset - offset to apply to FFDC registers for
+ * i_halt_type (constant/value of PORE
+ * pervasive base registers/none)
+ * @param[out] o_rc - target return code for extra FFDC
+ *
+ * @retval fapi::ReturnCode = SUCCESS
+ */
+fapi::ReturnCode proc_extract_pore_halt_ffdc(const por_base_state & i_pore_state,
+ const por_halt_type_t i_halt_type,
+ const por_ffdc_offset_t i_offset,
+ fapi::ReturnCode & o_rc);
+
+} // extern "C"
+
+#endif // _PROC_EXTRACT_PORE_HALT_FFDC_H_
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.xml b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.xml
new file mode 100644
index 000000000..99afc14dc
--- /dev/null
+++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.xml
@@ -0,0 +1,59 @@
+<!-- IBM_PROLOG_BEGIN_TAG -->
+<!-- This is an automatically generated prolog. -->
+<!-- -->
+<!-- $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.xml $ -->
+<!-- -->
+<!-- OpenPOWER HostBoot Project -->
+<!-- -->
+<!-- Contributors Listed Below - COPYRIGHT 2014 -->
+<!-- [+] International Business Machines Corp. -->
+<!-- -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
+<!-- implied. See the License for the specific language governing -->
+<!-- permissions and limitations under the License. -->
+<!-- -->
+<!-- IBM_PROLOG_END_TAG -->
+<!-- $Id: proc_extract_pore_halt_ffdc.xml,v 1.1 2014/07/23 19:43:18 jmcgill Exp $ -->
+<!-- Error definitions for proc_extract_pore_halt_ffdc procedure -->
+<hwpErrors>
+ <!-- *********************************************************************** -->
+ <hwpError>
+ <rc>RC_PROC_EXTRACT_PORE_HALT_FFDC</rc>
+ <description>
+ FFDC collected on selected PORE engine halt failures
+ </description>
+ <ffdc>TARGET</ffdc>
+ <ffdc>PORE_HALT_TYPE</ffdc>
+ <ffdc>FFDC_ADDRESSES</ffdc>
+ <ffdc>FFDC_DATA</ffdc>
+ </hwpError>
+ <!-- *********************************************************************** -->
+ <hwpError>
+ <rc>RC_PROC_EXTRACT_PORE_HALT_FFDC_BAD_MULTICAST</rc>
+ <description>
+ Unsupported multicast analysis requested
+ </description>
+ <ffdc>TARGET</ffdc>
+ <ffdc>CHIPLET_ID</ffdc>
+ <ffdc>MC_GROUP</ffdc>
+ </hwpError>
+ <!-- *********************************************************************** -->
+ <hwpError>
+ <rc>RC_PROC_EXTRACT_PORE_HALT_FFDC_BAD_TYPE</rc>
+ <description>
+ Unsupported halt type analysis requested
+ </description>
+ <ffdc>TARGET</ffdc>
+ <ffdc>PORE_HALT_TYPE</ffdc>
+ </hwpError>
+ <!-- *********************************************************************** -->
+</hwpErrors> \ No newline at end of file
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C
index d4151fa40..aefae9a5f 100644
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C
+++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C
@@ -22,19 +22,19 @@
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
-// -*- mode: C++; c-file-style: "linux"; -*-
-// $Id: proc_extract_sbe_rc.C,v 1.18 2014/06/30 14:32:05 bgeukes Exp $
+// $Id: proc_extract_sbe_rc.C,v 1.20 2014/07/24 03:13:59 jmcgill Exp $
// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_sbe_rc.C,v $
//------------------------------------------------------------------------------
// *|
// *! (C) Copyright International Business Machines Corp. 2012
// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
+// *! *** ***
// *|
// *! TITLE : proc_extract_sbe_rc.C
-// *! DESCRIPTION : Create a return code for an SBE/SLW error
+// *! DESCRIPTION : Create return code for PORE (SBE/SLW) error
// *!
-// *! OWNER NAME : Johannes Koesters Email: koesters@de.ibm.com
+// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com
+// *! BACKUP NAME : Johannes Koesters Email: koesters@de.ibm.com
// *!
// *! Overview:
// *! - Analyze error state of SBE/SLW engine
@@ -53,44 +53,26 @@
//------------------------------------------------------------------------------
#include <proc_extract_sbe_rc.H>
#include <proc_reset_i2cm_bus_fence.H>
-#include <p8_scom_addresses.H>
-#include <proc_tp_collect_dbg_data.H>
+#include <proc_extract_pore_engine_state.H>
+#include <proc_extract_pore_base_ffdc.H>
+#include <proc_extract_pore_halt_ffdc.H>
//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-enum soft_error_t
-{
- eNO_ERROR = 0,
- eSOFT_ERR_I2CM=1,
- eSOFT_ERR_PNOR=2,
- eSOFT_ERR_BOTH=3
-};
-
-//------------------------------------------------------------------------------
// Constant definitions
//------------------------------------------------------------------------------
-// address space/alignment masks
-const uint64_t SBE_ADDR_MASK = 0x0000FFFFFFFFFFFFULL;
-const uint64_t FOURBYTE_ALIGNMENT_MASK = 0x0000000000000003ULL;
+// address space masks
+const uint64_t PORE_ADDR_MASK = 0x0000FFFFFFFFFFFFULL;
const uint64_t INTERNAL_ADDR_MASK = 0x000000007FFFFFFFULL;
const uint64_t ADDR_TYPE_MASK = 0x0000FFFF80000000ULL;
const uint64_t OTPROM_ADDR_TYPE = 0x0000000100000000ULL;
const uint64_t PIBMEM_ADDR_TYPE = 0x0000000800000000ULL;
const uint64_t SEEPROM_ADDR_TYPE = 0x0000800C80000000ULL;
-const uint32_t ALIGN_FOUR_BYTE = 0xFFFFFFFC;
-
-// common SCOM register offsets for SBE/SLW engines
-const uint32_t STATUS_OFFSET_0x00 = 0x00000000;
-const uint32_t IBUF_OFFSET_0x0D = 0x0000000D;
-const uint32_t DEBUG0_OFFSET_0x0F = 0x0000000F;
-const uint32_t DEBUG1_OFFSET_0x10 = 0x00000010;
+const uint64_t SLW_ADDR_TYPE = 0x0000800080000000ULL;
// illegal instruction encoding for SW detected halt
-const uint32_t HALT_WITH_ERROR_INSTRUCTION = (('h' << 24) | ('a' << 16) | ('l' << 8) | ('t'));
+const uint32_t PORE_HALT_WITH_ERROR_INSTRUCTION = (('h' << 24) | ('a' << 16) | ('l' << 8) | ('t'));
//------------------------------------------------------------------------------
@@ -100,506 +82,211 @@ const uint32_t HALT_WITH_ERROR_INSTRUCTION = (('h' << 24) | ('a' << 16) | ('l' <
extern "C"
{
-//------------------------------------------------------------------------------
-// subroutine:
-// reads the word at the given address in SEEPROM pointer
-//
-// parameters: i_target => target of chip with failed SBE/SLW engine
-// i_pSEEPROM => pointer to a memory-mapped SEEPROM image
-// i_address => SEEPROM address to read
-// i_engine => type of engine that failed (SBE/SLW)
-// i_soft_err => engine soft error status, for FFDC
-// o_data => return data
-//
-// returns: fapi::ReturnCode with the error, or fapi::FAPI_RC_SUCCESS
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_extract_sbe_rc_read_SEEPROM(const fapi::Target & i_target,
- const void * i_pSEEPROM,
- const uint32_t i_address,
- const por_engine_t i_engine,
- const soft_error_t i_soft_err,
- uint32_t & o_data)
-{
- // return codes
- fapi::ReturnCode rc;
-
- do
- {
- if (i_pSEEPROM == NULL)
- {
- FAPI_ERR("Need to extract SEEPROM address 0x%08X, but pointer to SEEPROM image content is NULL", i_address);
- const fapi::Target & CHIP_IN_ERROR = i_target;
- const uint32_t & PC = i_address;
- if (i_engine == SBE)
- {
- const soft_error_t & SOFT_ERR_STATUS = i_soft_err;
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL_SBE);
- }
- else
- {
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL_SLW);
- }
- break;
- }
- // copy the data out of the image pointer
- uint8_t * p_errorCode = (uint8_t *)i_pSEEPROM + (i_address & ALIGN_FOUR_BYTE);
- o_data =
- (p_errorCode[0] << 3*8) |
- (p_errorCode[1] << 2*8) |
- (p_errorCode[2] << 1*8) |
- (p_errorCode[3]);
- } while(0);
-
- return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// subroutine:
-// Returns the PC of the given engine
-//
-// parameters: i_target => target of chip with failed SBE/SLW engine
-// i_engine => type of engine that failed (SBE/SLW)
-// i_soft_err => engine soft error status, for FFDC
-// o_pc => referenee to the uint64_t containing the PC
-//
-// returns: fapi::ReturnCode with the error, or fapi::FAPI_RC_SUCCESS
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_extract_sbe_rc_get_pc(const fapi::Target & i_target,
- const por_engine_t i_engine,
- const soft_error_t i_soft_err,
- uint64_t & o_pc)
-{
- // return codes
- fapi::ReturnCode rc;
-
- // data buffer to hold register values
- ecmdDataBufferBase data(64);
-
- do
- {
- // read PC from the Status Register
- rc = fapiGetScom(i_target, i_engine + STATUS_OFFSET_0x00, data);
- if (rc)
- {
- FAPI_ERR("Error from fapiGetScom (STATUS_REG_0x%08X)", i_engine + STATUS_OFFSET_0x00);
- break;
- }
-
- o_pc = (data.getDoubleWord(0) & SBE_ADDR_MASK);
-
- if (o_pc & FOURBYTE_ALIGNMENT_MASK)
- {
- FAPI_ERR("Address isn't 4-byte aligned");
- const fapi::Target & CHIP_IN_ERROR = i_target;
- const uint64_t & PC = o_pc;
- if (i_engine == SBE)
- {
- const soft_error_t & SOFT_ERR_STATUS = i_soft_err;
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SBE);
- }
- else
- {
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SLW);
- }
- break;
- }
- } while(0);
-
- return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// subroutine:
-// Returns the return code indicated by the PC of the engine
-//
-// parameters: i_target => target of chip with failed SBE/SLW engine
-// i_pSEEPROM => pointer to a memory-mapped SEEPROM image
-// i_engine => type of engine that failed (SBE/SLW)
-// i_soft_err => engine soft error status, for FFDC
-//
-// returns: fapi::ReturnCode with the error
-// This procedure will NEVER return SUCCESS
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_extract_sbe_rc_from_address(const fapi::Target & i_target,
- const void * i_pSEEPROM,
- const por_engine_t i_engine,
- const soft_error_t i_soft_err)
-{
- // return codes
- fapi::ReturnCode rc;
-
- // data buffer to hold register values
- ecmdDataBufferBase data(64);
- uint64_t address_64;
-
- do
- {
- // read PC
- rc = proc_extract_sbe_rc_get_pc(i_target, i_engine, i_soft_err, address_64);
- if (rc)
- {
- FAPI_ERR("Error from proc_extract_sbe_rc_get_pc");
- break;
- }
-
- // add 4 because address_64 is pointing at the halt instruction
- uint32_t internal_address = (uint32_t)(address_64 & INTERNAL_ADDR_MASK) + 4;
- // error code to emit
- uint32_t error_code = 0;
-
- if ((address_64 & ADDR_TYPE_MASK) == SEEPROM_ADDR_TYPE)
- {
- // get the error code from that location in the SEEPROM image
- FAPI_INF("Extracting the error code from address "
- "0x%X in the SEEPROM", internal_address);
-
- rc = proc_extract_sbe_rc_read_SEEPROM(i_target, i_pSEEPROM, internal_address, i_engine, i_soft_err, error_code);
- if (rc)
- {
- FAPI_ERR("Error from proc_extract_sbe_rc_read_SEEPROM (address = 0x%08X)", internal_address);
- break;
- }
- }
- else if ((address_64 & ADDR_TYPE_MASK) == PIBMEM_ADDR_TYPE)
- {
- // get the error code from that location in the PIBMEM
- FAPI_INF("Extracting the error code from address "
- "0x%X in the PIBMEM", internal_address);
-
- rc = fapiGetScom(i_target, PIBMEM0_0x00080000 + (internal_address >>3), data);
- if (rc)
- {
- FAPI_ERR("Error from fapiGetScom (PIBMEM address 0x%08X)", (uint32_t)PIBMEM0_0x00080000 + (internal_address >>3));
- break;
- }
-
- error_code = data.getWord((internal_address & 0x04)?1:0);
- }
- else
- {
- FAPI_ERR("Address (0x%012llX) isn't in a known memory address space", address_64);
- const fapi::Target & CHIP_IN_ERROR = i_target;
- const uint64_t & PC = address_64;
- if (i_engine == SBE)
- {
- const soft_error_t & SOFT_ERR_STATUS = i_soft_err;
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SBE);
- }
- else
- {
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SLW);
- }
- break;
- }
-
- // look up specified error code
- FAPI_ERR("SBE got error code 0x%06X", error_code);
- const fapi::Target CHIP_IN_ERROR = i_target;
- const fapi::Target CHIP = i_target;
- FAPI_SET_SBE_ERROR(rc, error_code);
- } while(0);
-
- //Make sure the code doesn't return SUCCESS
- if (rc.ok())
- {
- FAPI_ERR("proc_extract_sbe_rc_from_addr tried to return SUCCESS,"
- " which should be impossible. Must be a code bug.");
- const fapi::Target & CHIP_IN_ERROR = i_target;
- const uint64_t & PC = address_64;
- if (i_engine == SBE)
- {
- const soft_error_t & SOFT_ERR_STATUS = i_soft_err;
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG_SBE);
- }
- else
- {
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG_SLW);
- }
- }
- return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function:
-// Return an RC indicating the SBE/SLW error
-//
-// parameters: i_target => Target of chip with failed SBE/SLW
-// i_pSEEPROM => pointer to a memory-mapped SEEPROM image
-// i_engine => The type of engine that failed (SBE/SLW)
-//
-// returns: fapi::ReturnCode with the error
-// This procedure will NEVER return SUCCESS
-//------------------------------------------------------------------------------
+/**
+ * proc_extract_sbe_rc - HWP entry point, return RC indicating SBE/SLW error
+ *
+ * @param[in] i_target - target of chip with failed SBE/SLW engine
+ * @param[in] i_poreve - pointer to PoreVe object, used to collect engine
+ * state if non NULL
+ * @param[in] i_image - pointer to memory-mapped PORE image
+ * @param[in] i_engine - type of engine that failed (SBE/SLW)
+ *
+ * @retval fapi::ReturnCode - The error code the SBE hit, or the error hit
+ * while trying to get the error code
+ */
fapi::ReturnCode proc_extract_sbe_rc(const fapi::Target & i_target,
- const void * i_pSEEPROM,
- const por_engine_t i_engine)
+ void * i_poreve,
+ const void * i_image,
+ const por_engine_t i_engine)
{
// return codes
fapi::ReturnCode rc;
+ uint32_t rc_ecmd = 0x0;
- // data buffer to hold register values
- ecmdDataBufferBase data(64);
- ecmdDataBufferBase pnor_eccb_status(64);
- ecmdDataBufferBase i2cm_eccb_status(64);
- ecmdDataBufferBase fsi_data(32);
- ecmdDataBufferBase sbe_data0(64);
- ecmdDataBufferBase sbe_data1(64);
-
- // PC value
- uint64_t pc = 0x0ULL;
-
- // SBE PNOR/SEEPROM soft error status
- soft_error_t soft_err = eNO_ERROR;
+ // common state for analysis/FFDC
+ const fapi::Target & CHIP = i_target;
+ por_base_state pore_state;
+ // SBE specific state for analysis/FFDC
+ por_sbe_base_state pore_sbe_state;
- // SBE attn status
- bool sbe_reported_attn = false;
+ // process arguments
+ bool is_processor = (i_target.getType() == fapi::TARGET_TYPE_PROC_CHIP);
+ bool is_sbe = (i_engine == SBE);
+ bool is_slw = (i_engine == SLW);
do
{
- // check engine type
- if ((i_engine != SBE) &&
- (i_engine != SLW))
+ //
+ // all engine types -- extract engine state
+ //
+
+ FAPI_INF("proc_extract_sbe_rc: Processing PORE engine for target: %s, engine type: %s, virtual: %d",
+ i_target.toEcmdString(),
+ ((i_engine == SBE)?("SBE"):("SLW")),
+ (i_poreve == NULL)?(0):(1));
+
+ FAPI_EXEC_HWP(rc, proc_extract_pore_engine_state,
+ i_target, i_poreve, i_engine, pore_state, pore_sbe_state);
+ if (!rc.ok())
{
- FAPI_ERR("Unknown engine type %i", i_engine);
- const fapi::Target & CHIP_IN_ERROR = i_target;
- const por_engine_t ENGINE = i_engine;
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNKNOWN_ENGINE);
+ FAPI_ERR("proc_extract_sbe_rc: Error from proc_extract_pore_engine_state");
break;
}
- FAPI_INF("Processing %s error", ((i_engine == SBE)?("SBE"):("SLW")));
- // if analyzing SBE engine failure
- // - make sure I2C master bus fence is released before proceeding
- // - check ECCB engines (I2C/LPC) for UE/CE conditions (SLW does not use
- // these engines, so no need to check)
- if (i_engine == SBE)
+ //
+ // processor SBE -- return SEEPROM/PNOR UE as highest priority callouts
+ //
+
+ if (is_processor && is_sbe)
{
+ // ensure I2C master bus fence is released before proceeding
FAPI_EXEC_HWP(rc, proc_reset_i2cm_bus_fence, i_target);
if (!rc.ok())
{
- FAPI_ERR("Error from proc_reset_i2cm_bus_fence");
- break;
- }
-
- // check on FSI 1007 for any PIB Access Error
- rc = fapiGetCfamRegister(i_target, CFAM_FSI_STATUS_0x00001007, fsi_data);
- if (rc)
- {
- FAPI_ERR("Error from fapiGetCfamRegister (CFAM_FSI_STATUS_0x00001007)");
+ FAPI_ERR("proc_extract_sbe_rc: Error from proc_reset_i2cm_bus_fence");
break;
}
- if (fsi_data.getNumBitsSet(17,3) != 0)
- {
- FAPI_ERR("Error during PIB Access");
- const fapi::Target & CHIP_IN_ERROR = i_target;
- const ecmdDataBufferBase & FSI_STATUS = fsi_data;
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_PIB_ERROR_SBE);
- break;
- }
-
- if (fsi_data.isBitSet(30))
- {
- FAPI_ERR("SELFBOOT_ENGINE_ATTENTION - SBE reported attention to FSI2PIB status register");
- sbe_reported_attn = true;
- }
-
- // check on ECCB Error for I2C engine
- rc = fapiGetScom(i_target, PORE_ECCB_STATUS_REGISTER_READ_0x000C0002, i2cm_eccb_status);
- if (rc)
+ // return error if either ECCB engine reports an unrecoverable ECC error
+ if (pore_sbe_state.i2cm_eccb_status.isBitClear(41,2) && pore_sbe_state.i2cm_eccb_status.isBitSet(43))
{
- FAPI_ERR("Error from fapiGetScom (PORE_ECCB_STATUS_REGISTER_READ_0x000C00002)");
+ FAPI_ERR("proc_extract_sbe_rc: SBE encountered Unrecoverable ECC error on I2C Access");
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_SEEPROM);
break;
}
- // check on ECCB Engine for PNOR Access
- rc = fapiGetScom(i_target, LPC_STATUS_0x000B0002, pnor_eccb_status);
- if (rc)
+ if (pore_sbe_state.pnor_eccb_status.isBitClear(41,2) && pore_sbe_state.pnor_eccb_status.isBitSet(43))
{
- FAPI_ERR("Error from fapiGetScom (LPC_STATUS_0x000B0002)");
+ FAPI_ERR("proc_extract_sbe_rc: SBE encountered Unrecoverable ECC error on PNOR Access");
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_PNOR);
break;
}
-
- // determine if either engine has reached threshold of > 128 CEs
- if (i2cm_eccb_status.isBitSet(57))
- {
- soft_err = eSOFT_ERR_I2CM;
- }
-
- if (pnor_eccb_status.isBitSet(57))
- {
- if (soft_err == eSOFT_ERR_I2CM)
- {
- soft_err = eSOFT_ERR_BOTH;
- }
- else
- {
- soft_err = eSOFT_ERR_PNOR;
- }
- }
}
- // read engine PC value
- rc = proc_extract_sbe_rc_get_pc(i_target, i_engine, soft_err, pc);
- if (rc)
- {
- FAPI_ERR("Error from proc_extract_sbe_rc_get_pc");
- break;
- }
- if (i_engine == SBE)
- {
- // return error if either engine reports an unrecoverable ECC error
- if (i2cm_eccb_status.isBitClear(41,2) && i2cm_eccb_status.isBitSet(43))
- {
- FAPI_ERR("Unrecoverable ECC error on I2C Access");
- const fapi::Target & CHIP_IN_ERROR = i_target;
- const uint64_t & PC = pc;
- const ecmdDataBufferBase & ECCB_STATUS = i2cm_eccb_status;
- const soft_error_t & SOFT_ERR_STATUS = soft_err;
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_I2C_SBE);
- break;
- }
-
- if (pnor_eccb_status.isBitClear(41,2) && pnor_eccb_status.isBitSet(43))
- {
- FAPI_ERR("Unrecoverable ECC error on PNOR Access");
- const fapi::Target & CHIP_IN_ERROR = i_target;
- const uint64_t & PC = pc;
- const ecmdDataBufferBase & ECCB_STATUS = pnor_eccb_status;
- const soft_error_t & SOFT_ERR_STATUS = soft_err;
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_PNOR_SBE);
- break;
- }
- } // if (i_engine == SBE)
+ //
+ // all engine types -- process PORE Debug0/Debug1 registers for HW detected/SW generated errors
+ //
+ ecmdDataBufferBase pore_debug0_reg;
+ ecmdDataBufferBase pore_debug1_reg;
- // read Debug1 register state, check for any HW error
- rc = fapiGetScom(i_target, i_engine + DEBUG1_OFFSET_0x10, sbe_data1);
- if (rc)
+ rc_ecmd |= pore_state.engine_state.extractToRight(pore_debug0_reg, 64*PORE_DEBUG0_OFFSET, 64);
+ rc_ecmd |= pore_state.engine_state.extractToRight(pore_debug1_reg, 64*PORE_DEBUG1_OFFSET, 64);
+ if (rc_ecmd)
{
- FAPI_ERR("Error from fapiGetScom (DEBUG1_REG_0x%08X)", i_engine + DEBUG1_OFFSET_0x10);
+ FAPI_ERR("proc_extract_sbe_rc: Error %x extracting PORE engine debug register state", rc_ecmd);
+ rc.setEcmdError(rc_ecmd);
break;
}
- if (sbe_data1.isBitSet(63)) // SBE ANYERROR
+ // any HW error will cause DBG_LOCK bit to be set
+ if (pore_debug1_reg.isBitSet(63))
{
- FAPI_ERR("PIBMS_DBG_LOCK - error set");
-
- // read Debug0 register state
- rc = fapiGetScom(i_target, i_engine + DEBUG0_OFFSET_0x0F, sbe_data0);
- if (rc)
- {
- FAPI_ERR("Error from fapiGetScom (DEBUG0_REG_0x%08X)", i_engine + DEBUG0_OFFSET_0x0F);
- break;
- }
+ FAPI_ERR("proc_extract_sbe_rc: PIBMS_DBG_LOCK - error set");
// print bitwise messages for error log, unique errors will be grouped/combined into callouts below
- // grouping is done per guideance provided by Andreas Koenig
- if (sbe_data1.isBitSet(48))
+ // grouping is done per guidance provided by Andreas Koenig
+ if (pore_debug1_reg.isBitSet(48))
{
- FAPI_ERR("OCI_DATA_READ_P_ERR - Parity error in read data from OCI");
+ FAPI_ERR("proc_extract_sbe_rc: ERR_DATA_READ_P_ERR - Parity error in read data from OCI");
}
- uint8_t oci_rc = (sbe_data0.getByte(7) >> 5) & 0x7;
+ uint8_t oci_rc = (pore_debug0_reg.getByte(7) >> 5) & 0x7;
if (oci_rc)
{
- FAPI_ERR("Last return code from OCI SBE got return code %i", oci_rc);
+ FAPI_ERR("proc_extract_sbe_rc: Last return code from OCI received return code %i", oci_rc);
}
- if (sbe_data1.isBitSet(52))
+ if (pore_debug1_reg.isBitSet(52))
{
- FAPI_ERR("BAD_PAR - bad instruction parity");
+ FAPI_ERR("proc_extract_sbe_rc: BAD_PAR - bad instruction parity");
}
- if (sbe_data1.isBitSet(53))
+ if (pore_debug1_reg.isBitSet(53))
{
- FAPI_ERR("BAD_INSTRUCTION - invalid instruction");
+ FAPI_ERR("proc_extract_sbe_rc: BAD_INSTRUCTION - invalid instruction");
}
- if (sbe_data1.isBitSet(54))
+ if (pore_debug1_reg.isBitSet(54))
{
- FAPI_ERR("BAD_PC - PC overflow/underflow");
+ FAPI_ERR("proc_extract_sbe_rc: BAD_PC - PC overflow/underflow");
}
- if (sbe_data1.isBitSet(55))
+ if (pore_debug1_reg.isBitSet(55))
{
- FAPI_ERR("SCAN_DATA_CRC - Scan data CRC error");
+ FAPI_ERR("proc_extract_sbe_rc: SCAN_DATA_CRC - Scan data CRC error");
}
- if (sbe_data1.isBitSet(56))
+ if (pore_debug1_reg.isBitSet(56))
{
- FAPI_ERR("PC_STACK_ERR - PC stack PUSH error or POP error");
+ FAPI_ERR("proc_extract_sbe_rc: PC_STACK_ERR - PC stack PUSH error or POP error");
}
- if (sbe_data1.isBitSet(57))
+ if (pore_debug1_reg.isBitSet(57))
{
- FAPI_ERR("INSTR_FETCH_ERROR - Non-zero return code or read sbe_data1 parity error was received when during fetch - phase");
+ FAPI_ERR("proc_extract_sbe_rc: INSTR_FETCH_ERROR - Non-zero return code or read DEBUG1 parity error was received when during fetch phase");
}
- if (sbe_data1.isBitSet(58))
+ if (pore_debug1_reg.isBitSet(58))
{
- FAPI_ERR("BAD_OPERAND - Invalid Instruction Operand");
+ FAPI_ERR("proc_extract_sbe_rc: BAD_OPERAND - Invalid Instruction Operand");
}
- if (sbe_data1.isBitSet(59))
+ if (pore_debug1_reg.isBitSet(59))
{
- FAPI_ERR("BAD_INSTRUCTION_PATH - Invalid Instruction Path (e.g. FI2C parameter miss)");
+ FAPI_ERR("proc_extract_sbe_rc: BAD_INSTRUCTION_PATH - Invalid Instruction Path (e.g. FI2C parameter miss)");
}
- if (sbe_data1.isBitSet(60))
+ if (pore_debug1_reg.isBitSet(60))
{
- FAPI_ERR("BAD_START_VECTOR_TRIGGER - Invalid Start Vector triggered");
+ FAPI_ERR("proc_extract_sbe_rc: BAD_START_VECTOR_TRIGGER - Invalid Start Vector triggered");
}
- if (sbe_data1.isBitSet(61))
+ if (pore_debug1_reg.isBitSet(61))
{
- FAPI_ERR("FI2C_PROTOCOL_HANG - Fast I2C protocol hang detected - exceeded poll limit for FI2C engine");
+ FAPI_ERR("proc_extract_sbe_rc: FI2C_PROTOCOL_HANG - Fast I2C protocol hang detected - exceeded poll limit for FI2C engine");
}
- if (sbe_data1.isBitSet(62))
+ if (pore_debug1_reg.isBitSet(62))
{
- FAPI_ERR("ROL_INVALID - rotate invalid");
+ FAPI_ERR("proc_extract_sbe_rc: ROL_INVALID - rotate invalid");
}
-
- if (sbe_data0.isBitSet(32))
+ if (pore_debug0_reg.isBitSet(32))
{
- FAPI_ERR("PIB_DATA_READ_P_ERR - Parity error in read data from PRV PIB");
+ FAPI_ERR("proc_extract_sbe_rc: PIB_DATA_READ_P_ERR - Parity error in read data from PRV PIB");
}
- uint8_t pcb_error = (sbe_data0.getByte(4) >> 4) & 0x7;
- uint32_t scom_address = sbe_data0.getWord(0);
+ uint8_t pcb_error = (pore_debug0_reg.getByte(4) >> 4) & 0x7;
+ uint32_t scom_address = pore_debug0_reg.getWord(0);
if (pcb_error)
{
- FAPI_ERR("SBE got PCB error %i accessing scom address 0x%08X", pcb_error, scom_address);
+ FAPI_ERR("proc_extract_sbe_rc: PORE engine got PCB error %i accessing scom address 0x%08X", pcb_error, scom_address);
}
- if (sbe_data0.isBitSet(36))
+ if (pore_debug0_reg.isBitSet(36))
{
- FAPI_ERR("I2C_BAD_STATUS_0 - I2CM internal errors including parity errors");
+ FAPI_ERR("proc_extract_sbe_rc: I2C_BAD_STATUS_0 - I2CM internal errors including parity errors");
}
- if (sbe_data0.isBitSet(37))
+ if (pore_debug0_reg.isBitSet(37))
{
- FAPI_ERR("I2C_BAD_STATUS_1 - bad PIB response code error for ECCAX to I2CM communication");
+ FAPI_ERR("proc_extract_sbe_rc: I2C_BAD_STATUS_1 - bad PIB response code error for ECCAX to I2CM communication");
}
- if (sbe_data0.isBitSet(38))
+ if (pore_debug0_reg.isBitSet(38))
{
- FAPI_ERR("I2C_BAD_STATUS_2 - ECCAX internal errors (UCE or PIB master resets)");
+ FAPI_ERR("proc_extract_sbe_rc: I2C_BAD_STATUS_2 - ECCAX internal errors (UCE or PIB master resets)");
}
- if (sbe_data0.isBitSet(39))
+ if (pore_debug0_reg.isBitSet(39))
{
- FAPI_ERR("I2C_BAD_STATUS_3 - I2C bus issues (I2C bus busy, NACK, stop bit error)");
+ FAPI_ERR("proc_extract_sbe_rc: I2C_BAD_STATUS_3 - I2C bus issues (I2C bus busy, NACK, stop bit error)");
}
- if (sbe_data0.isBitSet(40))
+ if (pore_debug0_reg.isBitSet(40))
{
- FAPI_ERR("GROUP_PARITY_ERROR_0 - parity error from debug or status or error mask or pc stack regs");
+ FAPI_ERR("proc_extract_sbe_rc: GROUP_PARITY_ERROR_0 - parity error from DEBUG or STATUS or ERROR MASK or PC STACK regs");
}
- if (sbe_data0.isBitSet(41))
+ if (pore_debug0_reg.isBitSet(41))
{
- FAPI_ERR("GROUP_PARITY_ERROR_1 - parity error from control or exe trigger or exe t_mask or i2c param regs");
+ FAPI_ERR("proc_extract_sbe_rc: GROUP_PARITY_ERROR_1 - parity error from CONTROL or EXE TRIGGER or EXE T_MASK or I2C PARAM regs");
}
- if (sbe_data0.isBitSet(42))
+ if (pore_debug0_reg.isBitSet(42))
{
- FAPI_ERR("GROUP_PARITY_ERROR_2 - parity error from perv/oci base addr or table base addr or memory reloc");
+ FAPI_ERR("proc_extract_sbe_rc: GROUP_PARITY_ERROR_2 - parity error from PERV/OCI BASE ADDR or TABLE BASE ADDR or MEMORY RELOC regs");
}
- if (sbe_data0.isBitSet(43))
+ if (pore_debug0_reg.isBitSet(43))
{
- FAPI_ERR("GROUP_PARITY_ERROR_3 - parity error from scr0 or scr1 or scr2 or sbe_data0 scr0 reg");
+ FAPI_ERR("proc_extract_sbe_rc: GROUP_PARITY_ERROR_3 - parity error from SCR0 or SCR1 or SCR2 or DEBUG0 SCR0 reg");
}
- if (sbe_data0.isBitSet(44))
+ if (pore_debug0_reg.isBitSet(44))
{
- FAPI_ERR("GROUP_PARITY_ERROR_4 - parity error from ibuf regs");
+ FAPI_ERR("proc_extract_sbe_rc: GROUP_PARITY_ERROR_4 - parity error from IBUF regs");
}
//
@@ -607,237 +294,242 @@ fapi::ReturnCode proc_extract_sbe_rc(const fapi::Target & i_target,
//
// "Internal Error" bucket (Error Event 3)
- if ((sbe_data0.getNumBitsSet(40,5) != 0) || sbe_data1.isBitSet(55))
- {
- FAPI_ERR("Internal %s Error", ((i_engine == SBE)?("SBE"):("SLW")));
- const fapi::Target & CHIP_IN_ERROR = i_target;
- const uint64_t & PC = pc;
- const uint8_t & GROUP_PARITY_ERROR_0_4 = (sbe_data0.getByte(5) >> 3) & 0x1F;
- const bool & SCAN_DATA_CRC_ERROR = sbe_data1.isBitSet(55);
- if (i_engine == SBE)
- {
- const soft_error_t & SOFT_ERR_STATUS = soft_err;
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INTERNAL_ERROR_SBE);
- }
- else
- {
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INTERNAL_ERROR_SLW);
- }
+ if ((pore_debug0_reg.getNumBitsSet(40,5) != 0) || pore_debug1_reg.isBitSet(55))
+ {
+ FAPI_ERR("proc_extract_sbe_rc: Internal Error (Event 3)");
+ const uint8_t & GROUP_PARITY_ERROR_0_4 = (pore_debug0_reg.getByte(5) >> 3) & 0x1F;
+ const bool & SCAN_DATA_CRC_ERROR = pore_debug1_reg.isBitSet(55);
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INTERNAL_ERROR);
break;
}
// "I2C Error" bucket (Error Event 0)
- if ((sbe_data0.getNumBitsSet(36,4) != 0) || (sbe_data1.isBitSet(61)))
+ if ((pore_debug0_reg.getNumBitsSet(36,4) != 0) || (pore_debug1_reg.isBitSet(61)))
{
- FAPI_ERR("%s failed I2C Master operation", ((i_engine == SBE)?("SBE"):("SLW")));
- const fapi::Target & CHIP_IN_ERROR = i_target;
- const uint64_t & PC = pc;
- const uint8_t & I2C_BAD_STATUS_0_3 = sbe_data0.getHalfWord(10);
- const bool & FI2C_HANG = sbe_data1.isBitSet(61);
-
- if (i_engine == SBE)
- {
- const soft_error_t & SOFT_ERR_STATUS = soft_err;
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_I2C_ERROR_SBE);
- }
- else
- {
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_I2C_ERROR_SLW);
- }
+ FAPI_ERR("proc_extract_sbe_rc: I2C Error (Event 0)");
+ const uint8_t & I2C_BAD_STATUS_0_3 = pore_debug0_reg.getHalfWord(10);
+ const bool & FI2C_HANG = pore_debug1_reg.isBitSet(61);
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_I2C_ERROR);
break;
}
- // "SCOM Error" bucket (Error Event 0), raise in presence of no instruction execution error
- if ((sbe_data0.getNumBitsSet(32,4) != 0) && (sbe_data1.getNumBitsSet(52,9) == 0) && (sbe_data1.isBitClear(62)))
+ // "SCOM Error" bucket (Error Event 0), raise only if no instruction execution error is present
+ if ((pore_debug0_reg.getNumBitsSet(32,4) != 0) && (pore_debug1_reg.getNumBitsSet(52,9) == 0) && (pore_debug1_reg.isBitClear(62)))
{
- FAPI_ERR("%s failed SCOM operation", ((i_engine == SBE)?("SBE"):("SLW")));
- const fapi::Target & CHIP_IN_ERROR = i_target;
- const uint64_t & PC = pc;
+ FAPI_ERR("proc_extract_sbe_rc: SCOM operation failed (Event 0)");
const uint32_t & SCOM_ADDRESS = scom_address;
const uint8_t & PIB_ERROR_CODE = pcb_error;
- const bool & PIB_DATA_READ_PARITY_ERROR = sbe_data0.isBitSet(32);
- if (i_engine == SBE)
- {
- const soft_error_t & SOFT_ERR_STATUS = soft_err;
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SCOM_ERROR_SBE);
- }
- else
- {
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SCOM_ERROR_SLW);
- }
+ const bool & PIB_DATA_READ_PARITY_ERROR = pore_debug0_reg.isBitSet(32);
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SCOM_ERROR);
break;
}
// "OCI Error" bucket (Error Event 1)
- if ((i_engine == SLW) && (sbe_data1.getNumBitsSet(48,4) != 0))
+ if (is_slw && (pore_debug1_reg.getNumBitsSet(48,4) != 0))
{
- FAPI_ERR("%s failed OCI Master operation", ((i_engine == SBE)?("SBE"):("SLW")));
- const fapi::Target & CHIP_IN_ERROR = i_target;
- const uint64_t & PC = pc;
+ FAPI_ERR("proc_extract_sbe_rc: OCI Master operation failed (Event 1)");
const uint8_t & OCI_ERROR_CODE = oci_rc;
- const bool & OCI_DATA_READ_PARITY_ERROR = sbe_data1.isBitSet(48);
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_OCI_ERROR_SLW);
+ const bool & OCI_DATA_READ_PARITY_ERROR = pore_debug1_reg.isBitSet(48);
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_OCI_ERROR);
break;
}
- // check for the execution of an invalid instruction
- // if present, check if the SBE stopped at a code detected error (instruction = 'halt')
- if (sbe_data1.isBitSet(53) || sbe_data1.isBitSet(62))
+ // check for PORE code generated halt
+ // code detected errors will result in the the execution of an invalid instruction -> ASCII 'halt'
+ if (pore_debug1_reg.isBitSet(53) || pore_debug1_reg.isBitSet(62))
{
- rc = fapiGetScom(i_target, i_engine + IBUF_OFFSET_0x0D, data);
- if (rc)
+ // check alignment of PC value
+ if (pore_state.pc & 0x3ULL)
{
- // fail through to "Instruction Execution Error" bucket below
- FAPI_ERR("Error from fapiGetScom(IBUF_REG_0x%08X)", i_engine + IBUF_OFFSET_0x0D);
- FAPI_ERR("SBE reported an invalid instruction error, but unable to determine if it was a code-detected error or not");
+ FAPI_ERR("proc_extract_sbe_rc: Unexpected address alignment");
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED);
+ break;
}
- else
+
+ // examine first word of IBUF register
+ uint32_t instruction = pore_state.engine_state.getWord(2*PORE_IBUF0_OFFSET);
+ if (instruction == PORE_HALT_WITH_ERROR_INSTRUCTION)
{
- // lookup return code identifying halt from image, based on PC value
- const uint32_t instruction = data.getWord(0);
- if (instruction == HALT_WITH_ERROR_INSTRUCTION)
- {
- rc = proc_extract_sbe_rc_from_address(i_target, i_pSEEPROM, i_engine, soft_err);
- break;
- }
+ // halt encountered
+ // RC indicating unique exit point will be contained in next word
+ // retrieve RC from appropriate memory space
+ uint64_t rc_addr = (pore_state.pc & INTERNAL_ADDR_MASK)+4;
+
+ if ((is_processor &&
+ (((pore_state.pc & ADDR_TYPE_MASK) == SEEPROM_ADDR_TYPE) ||
+ ((pore_state.pc & ADDR_TYPE_MASK) == SLW_ADDR_TYPE))) ||
+ (!is_processor))
+ {
+ if (i_image == NULL)
+ {
+ FAPI_ERR("proc_extract_sbe_rc: PORE image pointer is NULL");
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL);
+ break;
+ }
+
+ FAPI_INF("proc_extract_sbe_rc: Extracting the error code from address 0x%llX in PORE image", rc_addr);
+ uint8_t * p_errorCode = (uint8_t *) i_image + rc_addr;
+ pore_state.rc =
+ (p_errorCode[0] << 3*8) |
+ (p_errorCode[1] << 2*8) |
+ (p_errorCode[2] << 1*8) |
+ (p_errorCode[3]);
+ }
+ else if (is_processor && ((pore_state.pc & ADDR_TYPE_MASK) == PIBMEM_ADDR_TYPE))
+ {
+ FAPI_INF("proc_extract_sbe_rc: Extracting the error code from address 0x%llX in the PIBMEM", rc_addr);
+ ecmdDataBufferBase pibmem_data(64);
+ rc = fapiGetScom(i_target, PIBMEM0_0x00080000 + (rc_addr >>3), pibmem_data);
+ if (rc)
+ {
+ FAPI_ERR("proc_extract_sbe_rc: Error from fapiGetScom (PIBMEM address 0x%08X)", (uint32_t) (PIBMEM0_0x00080000 + (rc_addr >>3)));
+ break;
+ }
+ pore_state.rc = pibmem_data.getWord((rc_addr & 0x04)?1:0);
+ }
+ else
+ {
+ FAPI_ERR("proc_extract_sbe_rc: Address (0x%012llX) isn't in a known memory address space", pore_state.pc);
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED);
+ break;
+ }
+
+ // invoke platform function to return XML defined RC associated with PORE state
+ FAPI_ERR("proc_extract_sbe_rc: PORE got error code 0x%06X", pore_state.rc);
+ FAPI_SET_SBE_ERROR(rc, pore_state.rc);
+
+ // ensure that error is generated in this code path
+ if (rc.ok())
+ {
+ FAPI_ERR("proc_extract_sbe_rc: PORE got error code 0x%06X, but this did not resolve to any return code!", pore_state.rc);
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG);
+ }
+ break;
}
}
// "Instruction Execution Error" bucket (Error Event 2)
- if ((sbe_data1.getNumBitsSet(52,9) != 0) || (sbe_data1.isBitSet(62)))
- {
- FAPI_ERR("SBE encountered instruction execution error");
- const fapi::Target & CHIP_IN_ERROR = i_target;
- const uint64_t & PC = pc;
- const bool & INSTRUCTION_PARITY_ERROR = sbe_data1.isBitSet(52);
- const bool & INVALID_INSTRUCTION_NON_ROTATE = sbe_data1.isBitSet(53);
- const bool & PC_OVERFLOW_UNDERFLOW = sbe_data1.isBitSet(54);
+ if ((pore_debug1_reg.getNumBitsSet(52,9) != 0) || (pore_debug1_reg.isBitSet(62)))
+ {
+ FAPI_ERR("proc_extract_sbe_rc: Instruction execution error (Event 2)");
+ const bool & INSTRUCTION_PARITY_ERROR = pore_debug1_reg.isBitSet(52);
+ const bool & INVALID_INSTRUCTION_NON_ROTATE = pore_debug1_reg.isBitSet(53);
+ const bool & PC_OVERFLOW_UNDERFLOW = pore_debug1_reg.isBitSet(54);
// bit 55 covered by Internal Error check
- const bool & PC_STACK_ERROR = sbe_data1.isBitSet(56);
- const bool & INSTRUCTION_FETCH_ERROR = sbe_data1.isBitSet(57);
- const bool & INVALID_OPERAND = sbe_data1.isBitSet(58);
- const bool & I2C_ENGINE_MISS = sbe_data1.isBitSet(59);
- const bool & INVALID_START_VECTOR = sbe_data1.isBitSet(60);
- const bool & INVALID_INSTRUCTION_ROTATE = sbe_data1.isBitSet(62);
-
- if (i_engine == SBE)
- {
- const soft_error_t & SOFT_ERR_STATUS = soft_err;
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INSTRUCTION_ERROR_SBE);
- }
- else
- {
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INSTRUCTION_ERROR_SLW);
- }
+ const bool & PC_STACK_ERROR = pore_debug1_reg.isBitSet(56);
+ const bool & INSTRUCTION_FETCH_ERROR = pore_debug1_reg.isBitSet(57);
+ const bool & INVALID_OPERAND = pore_debug1_reg.isBitSet(58);
+ const bool & I2C_ENGINE_MISS = pore_debug1_reg.isBitSet(59);
+ const bool & INVALID_START_VECTOR = pore_debug1_reg.isBitSet(60);
+ const bool & INVALID_INSTRUCTION_ROTATE = pore_debug1_reg.isBitSet(62);
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INSTRUCTION_ERROR);
break;
}
- } // SBE ANYERROR debug(63)
+ }
+
- // no error bits are set, check PC to check execution progress
- // check for real halt (wait 0) instruction in OTPROM
- if ((i_engine == SBE) && ((pc & ADDR_TYPE_MASK) == OTPROM_ADDR_TYPE))
+ //
+ // processor SBE -- check for real halt in OTPROM
+ //
+
+ // for processor SBE only, check for real halt (wait 0) instruction in OTPROM
+ if (is_processor && is_sbe && ((pore_state.pc & ADDR_TYPE_MASK) == OTPROM_ADDR_TYPE))
{
// Note: OTPROM halts are actual halt instructions, which means the
// SBE updated the PC before the halt.
// Thus we have to subtract 4 to get back to the address of the halt
- uint32_t internal_address = (uint32_t)(pc & INTERNAL_ADDR_MASK) - 4;
+ uint32_t pc_m4 = (uint32_t)(pore_state.pc & INTERNAL_ADDR_MASK)-4;
// map the OTPROM address to the known error at that location
// the OTPROM is write-once at mfg test, so addresses should remain fixed in this code
- FAPI_INF("Determining the OTPROM error based on the address "
- "0x%X", internal_address);
- const fapi::Target & CHIP_IN_ERROR = i_target;
- const uint64_t & PC = internal_address;
-
- switch (internal_address)
+ FAPI_INF("proc_extract_sbe_rc: Determining OTPROM error at address 0x%X", pc_m4);
+ switch (pc_m4)
{
case (0x400fc): // original OTPROM version
case (0x40118): // updated OTPROM version
- FAPI_ERR("Chip not identified as Murano or Venice");
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_BAD_CHIP_TYPE_SBE);
+ FAPI_ERR("proc_extract_sbe_rc: Chip was not identified as Murano or Venice");
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_BAD_CHIP_TYPE);
break;
case (0x401c0):
- FAPI_ERR("SEEPROM magic number didn't match \"XIP SEPM\"");
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SEEPROM_MAGIC_NUMBER_MISMATCH_SBE);
+ FAPI_ERR("proc_extract_sbe_rc: SEEPROM magic number didn't match \"XIP SEPM\"");
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SEEPROM_MAGIC_NUMBER_MISMATCH);
break;
case (0x401ec):
- FAPI_ERR("Branch to SEEPROM didn't happen");
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_BRANCH_TO_SEEPROM_FAIL_SBE);
+ FAPI_ERR("proc_extract_sbe_rc: Branch to SEEPROM didn't happen");
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_BRANCH_TO_SEEPROM_FAIL);
break;
default:
- FAPI_ERR("Halted in OTPROM, but not at an expected halt location");
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNEXPECTED_OTPROM_HALT_SBE);
+ FAPI_ERR("proc_extract_sbe_rc: Halted in OTPROM, but not at an expected halt location");
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNEXPECTED_OTPROM_HALT);
break;
}
- break;
}
- // check to see if engine was never started
- if (((pc & SBE_ADDR_MASK) == 0x0000800000000000ULL) ||
- ((pc & SBE_ADDR_MASK) == 0x0000000000000000ULL))
- {
- FAPI_ERR("PC is all zeros, which means %s was probably never started", ((i_engine == SBE)?("SBE"):("SLW")));
- const fapi::Target & CHIP_IN_ERROR = i_target;
- const uint64_t & PC = pc;
- if (i_engine == SBE)
- {
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_NEVER_STARTED_SBE);
- break;
- }
- else
- {
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_NEVER_STARTED_SLW);
- break;
- }
+ //
+ // all engine types -- validate execution progress of PC
+ //
+
+ // determine if engine was ever started
+ if (((pore_state.pc & PORE_ADDR_MASK) == 0x0000800000000000ULL) ||
+ ((pore_state.pc & PORE_ADDR_MASK) == 0x0000000000000000ULL))
+ {
+ FAPI_ERR("proc_extract_sbe_rc: PC is all zeros, which means PORE engine was probably never started");
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_NEVER_STARTED);
+ break;
}
- // return soft error with lowest priority
- if ((i_engine == SBE) && (soft_err != eNO_ERROR))
+
+ //
+ // processor SBE -- return soft error with lowest priority
+ //
+
+ if (is_processor && is_sbe && (pore_sbe_state.soft_err != eNO_ERROR))
{
- const fapi::Target & CHIP_IN_ERROR = i_target;
- if (soft_err == eSOFT_ERR_I2CM)
+ if (pore_sbe_state.soft_err == eSOFT_ERR_I2CM)
{
- FAPI_ERR("Recoverable ECC Error on I2C Access");
- const ecmdDataBufferBase & I2C_ECCB_STATUS = i2cm_eccb_status;
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_I2C_SBE);
+ FAPI_ERR("proc_extract_sbe_rc: SBE encountered Recoverable ECC Error on I2C Access");
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_SEEPROM);
break;
}
- else if (soft_err == eSOFT_ERR_PNOR)
+ else if (pore_sbe_state.soft_err == eSOFT_ERR_PNOR)
{
- FAPI_ERR("Recoverable ECC Error on PNOR Access");
- const ecmdDataBufferBase & PNOR_ECCB_STATUS = pnor_eccb_status;
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_PNOR_SBE);
+ FAPI_ERR("proc_extract_sbe_rc: SBE encountered Recoverable ECC Error on PNOR Access");
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_PNOR);
break;
}
else // (soft_err == eSOFT_ERR_BOTH)
{
- FAPI_ERR("Recoverable ECC Error on PNOR Access");
- FAPI_ERR("Recoverable ECC Error on I2C Access");
- const ecmdDataBufferBase & PNOR_ECCB_STATUS = pnor_eccb_status;
- const ecmdDataBufferBase & I2C_ECCB_STATUS = i2cm_eccb_status;
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_I2C_AND_PNOR_SBE);
+ FAPI_ERR("proc_extract_sbe_rc: SBE encountered Recoverable ECC Error on I2C Access");
+ FAPI_ERR("proc_extract_sbe_rc: SBE encountered Recoverable ECC Error on PNOR Access");
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_SEEPROM_AND_PNOR);
break;
}
}
} while(0);
- // if SBE, make sure that the code doesn't return FAPI_RC_SUCCESS
- // if the engine reported an attn to the FSI2PIB status register
- if (rc.ok() && (i_engine == SBE) && (sbe_reported_attn))
+ //
+ // processor SBE -- ensure HWP doesn't return FAPI_RC_SUCCESS if the engine reported attn
+ //
+ if (rc.ok() && is_processor && is_sbe && pore_sbe_state.reported_attn)
{
- FAPI_ERR("SBE reported attention, but proc_extract_sbe_rc tried to return SUCCESS,"
- " which should be impossible. Must be a code bug.");
- const fapi::Target & CHIP_IN_ERROR = i_target;
- const uint64_t & PC = pc;
- FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_CODE_BUG_SBE);
+ FAPI_ERR("proc_extract_sbe_rc: SBE reported attention, but proc_extract_sbe_rc tried to return SUCCESS!");
+ FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_CODE_BUG);
}
+
+ //
+ // all engine types -- append engine specific base FFDC to any non-zero return code
+ //
+
+ if (!rc.ok())
+ {
+ FAPI_ADD_INFO_TO_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_BASE_FFDC);
+ }
+
+ FAPI_INF("proc_extract_sbe_rc: End");
return rc;
}
} // extern "C"
-/* Local Variables: */
-/* c-basic-offset: 4 */
-/* End: */
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.H b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.H
index 8571d3de3..3e2114749 100644
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.H
+++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.H
@@ -22,7 +22,7 @@
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
-// $Id: proc_extract_sbe_rc.H,v 1.7 2014/03/18 14:09:28 jmcgill Exp $
+// $Id: proc_extract_sbe_rc.H,v 1.9 2014/07/24 03:13:59 jmcgill Exp $
// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_sbe_rc.H,v $
//------------------------------------------------------------------------------
// *|
@@ -31,31 +31,145 @@
// *! *** ***
// *|
// *! TITLE : proc_extract_sbe_rc.H
-// *! DESCRIPTION : Create a return code for an SBE/SLW error.
+// *! DESCRIPTION : Create return code for PORE (SBE/SLW) error
// *!
-// *! OWNER NAME : Johannes Koesters Email: koesters@de.ibm.com
+// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com
+// *! BACKUP NAME : Johannes Koesters Email: koesters@de.ibm.com
// *!
//------------------------------------------------------------------------------
#ifndef _PROC_EXTRACT_SBE_RC_H_
#define _PROC_EXTRACT_SBE_RC_H_
+
//------------------------------------------------------------------------------
// Includes
//------------------------------------------------------------------------------
#include <fapi.H>
#include <p8_scom_addresses.H>
+#include <cen_scom_addresses.H>
+
//------------------------------------------------------------------------------
// Structure definitions
//------------------------------------------------------------------------------
+
+// engine types
enum por_engine_t {
- SBE = PORE_SBE_0x000E0000,
- SLW = PORE_SLW_0x00068000
+ SBE = PORE_SBE_0x000E0000,
+ SLW = PORE_SLW_0x00068000
+};
+
+// common SCOM register offsets for SBE/SLW engines
+enum por_reg_offset_t {
+ PORE_STATUS_OFFSET = 0x00,
+ PORE_CONTROL_OFFSET = 0x01,
+ PORE_RESET_OFFSET = 0x02,
+ PORE_ERR_MASK_OFFSET = 0x03,
+ PORE_P0_OFFSET = 0x04,
+ PORE_P1_OFFSET = 0x05,
+ PORE_A0_OFFSET = 0x06,
+ PORE_A1_OFFSET = 0x07,
+ PORE_TBL_BASE_OFFSET = 0x08,
+ PORE_EXE_TRIGGER_OFFSET = 0x09,
+ PORE_CTR_OFFSET = 0x0A,
+ PORE_D0_OFFSET = 0x0B,
+ PORE_D1_OFFSET = 0x0C,
+ PORE_IBUF0_OFFSET = 0x0D,
+ PORE_IBUF1_OFFSET = 0x0E,
+ PORE_DEBUG0_OFFSET = 0x0F,
+ PORE_DEBUG1_OFFSET = 0x10,
+ PORE_STACK0_OFFSET = 0x11,
+ PORE_STACK1_OFFSET = 0x12,
+ PORE_STACK2_OFFSET = 0x13,
+ PORE_IDFLAGS_OFFSET = 0x14,
+ PORE_SPRG0_OFFSET = 0x15,
+ PORE_MRR_OFFSET = 0x16,
+ PORE_I2CE0_OFFSET = 0x17,
+ PORE_I2CE1_OFFSET = 0x18,
+ PORE_I2CE2_OFFSET = 0x19,
+ PORE_NUM_REGS = 0x1A
+};
+
+// SBE soft error types
+enum por_sbe_soft_error_t
+{
+ eNO_ERROR = 0,
+ eSOFT_ERR_I2CM=1,
+ eSOFT_ERR_PNOR=2,
+ eSOFT_ERR_BOTH=3
+};
+
+enum por_halt_type_t
+{
+ PORE_HALT_SCAN_FAIL = 0,
+ PORE_HALT_SCAN_FLUSH_FAIL = 1,
+ PORE_HALT_ARRAYINIT_FAIL = 2,
+ PORE_HALT_SKEW_ADJUST_FAIL = 3,
+ PORE_HALT_FIR_FAIL = 4,
+ PORE_HALT_INSTRUCT_FAIL = 5,
+ PORE_HALT_DPLL_LOCK_FAIL = 6
+};
+
+enum por_ffdc_offset_t
+{
+ POR_FFDC_OFFSET_NONE = 0x0,
+ POR_FFDC_OFFSET_TP_CHIPLET = TP_CHIPLET_0x01000000,
+ POR_FFDC_OFFSET_NEST_CHIPLET = NEST_CHIPLET_0x02000000,
+ POR_FFDC_OFFSET_MEM_CHIPLET = MEM_CHIPLET_0x03000000,
+ POR_FFDC_OFFSET_XBUS_CHIPLET = X_BUS_CHIPLET_0x04000000,
+ POR_FFDC_OFFSET_ABUS_CHIPLET = A_BUS_CHIPLET_0x08000000,
+ POR_FFDC_OFFSET_PCIE_CHIPLET = PCIE_CHIPLET_0x09000000,
+ POR_FFDC_OFFSET_EX_CHIPLET = EX00_CHIPLET_0x10000000,
+ POR_FFDC_OFFSET_USE_P0 = PORE_P0_OFFSET,
+ POR_FFDC_OFFSET_USE_P1 = PORE_P1_OFFSET
+};
+
+
+// structure to encapsulate PORE state/FFDC content
+struct por_base_state
+{
+ fapi::Target target; // chip target associated with failed engine
+ por_engine_t engine; // engine type (SBE/SLW)
+ bool is_virtual; // virtual engine?
+ ecmdDataBufferBase vital_state; // SBE/SLW vital state
+ ecmdDataBufferBase engine_state; // SBE/SLW engine state
+ uint64_t pc; // SBE/SLW engine PC
+ uint32_t rc; // RC associated with SBE/SLW halt point
+
+ por_base_state()
+ {
+ vital_state.setDoubleWordLength(1);
+ vital_state.flushTo1();
+ engine_state.setDoubleWordLength(PORE_NUM_REGS);
+ engine_state.flushTo1();
+ pc = 0xFFFFFFFFFFFFFFFFULL;
+ rc = 0x0;
+ }
+};
+
+// structure to encapsulate PORE SBE-specific base FFDC content
+struct por_sbe_base_state
+{
+ ecmdDataBufferBase pnor_eccb_status; // PNOR ECCB status register state
+ ecmdDataBufferBase i2cm_eccb_status; // SEEPROM ECCB status register state
+ por_sbe_soft_error_t soft_err; // PNOR/SEEPROM soft error state
+ bool reported_attn; // SBE generated attention?
+
+ por_sbe_base_state()
+ {
+ pnor_eccb_status.setDoubleWordLength(1);
+ pnor_eccb_status.flushTo1();
+ i2cm_eccb_status.setDoubleWordLength(1);
+ i2cm_eccb_status.flushTo1();
+ soft_err = eNO_ERROR;
+ reported_attn = false;
+ }
};
// function pointer typedef definition for HWP call support
typedef fapi::ReturnCode (*proc_extract_sbe_rc_FP_t)(const fapi::Target &,
+ void *,
const void *,
const por_engine_t);
@@ -68,17 +182,21 @@ extern "C"
{
/**
- * @brief Create a return code based off the current SBE/SLW RC.
+ * proc_extract_sbe_rc - HWP entry point, return RC indicating SBE/SLW error
+ *
+ * @param[in] i_target - target of chip with failed SBE/SLW engine
+ * @param[in] i_poreve - pointer to PoreVe object, used to collect engine
+ * state if non NULL
+ * @param[in] i_image - pointer to memory-mapped PORE image
+ * @param[in] i_engine - type of engine that failed (SBE/SLW)
*
- * @param[in] i_target Reference to processor target containing the SBE/SLW engine
- * @param[in] i_pSEEPROM Pointer to a memory-mapped SEEPROM image (or NULL)
- * @param[in] i_engine The POR engine type (SBE/SLW)
- * @return ReturnCode The error code the SBE hit, or the error hit
- * while trying to get the error code
+ * @retval fapi::ReturnCode - The error code the SBE hit, or the error hit
+ * while trying to get the error code
*/
- fapi::ReturnCode proc_extract_sbe_rc(const fapi::Target & i_target,
- const void * i_pSEEPROM,
- const por_engine_t i_engine);
+fapi::ReturnCode proc_extract_sbe_rc(const fapi::Target & i_target,
+ void * i_poreve,
+ const void * i_image,
+ const por_engine_t i_engine);
} // extern "C"
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc_errors.xml b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc_errors.xml
index a51a4a61f..3abfd4275 100644
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc_errors.xml
+++ b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc_errors.xml
@@ -22,223 +22,143 @@
<!-- permissions and limitations under the License. -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
-<!-- $Id: proc_extract_sbe_rc_errors.xml,v 1.15 2014/06/30 14:33:53 bgeukes Exp $ -->
+<!-- $Id: proc_extract_sbe_rc_errors.xml,v 1.16 2014/07/23 19:51:48 jmcgill Exp $ -->
<!-- Error definitions for proc_extract_sbe_rc procedure -->
<hwpErrors>
<!-- *********************************************************************** -->
<hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL_SBE</rc>
+ <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED</rc>
<description>
Procedure: proc_extract_sbe_rc
- NULL image pointer prevented extraction of SBE error code
+ The PORE engine PC isn't properly aligned
</description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
- <ffdc>SOFT_ERR_STATUS</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
- <id>REG_FFDC_PROC_SBE_REGISTERS</id>
- <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
<callout>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
<priority>HIGH</priority>
</callout>
- <callout>
- <procedure>CODE</procedure>
- <priority>LOW</priority>
- </callout>
<deconfigure>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</deconfigure>
<gard>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</gard>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL_SLW</rc>
+ <rc>RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_SEEPROM</rc>
<description>
Procedure: proc_extract_sbe_rc
- NULL image pointer prevented extraction of SLW error code
+ ECCB indicates unrecoverable ECC error from I2C during SBE execution
+ Reload/update of SEEPROM required
</description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_SLW_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
<callout>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
<priority>HIGH</priority>
</callout>
- <callout>
- <procedure>CODE</procedure>
- <priority>LOW</priority>
- </callout>
- <deconfigure>
- <target>CHIP_IN_ERROR</target>
- </deconfigure>
- <gard>
- <target>CHIP_IN_ERROR</target>
- </gard>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SBE</rc>
+ <rc>RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_PNOR</rc>
<description>
Procedure: proc_extract_sbe_rc
- The SBE stop address isn't properly aligned
+ ECCB indicates unrecoverable ECC error from PNOR during SBE execution
+ Reload/Update of PNOR required
</description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
- <ffdc>SOFT_ERR_STATUS</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
- <id>REG_FFDC_PROC_SBE_REGISTERS</id>
- <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
<callout>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
<priority>HIGH</priority>
</callout>
- <deconfigure>
- <target>CHIP_IN_ERROR</target>
- </deconfigure>
- <gard>
- <target>CHIP_IN_ERROR</target>
- </gard>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED_SLW</rc>
+ <rc>RC_PROC_EXTRACT_SBE_RC_INTERNAL_ERROR</rc>
<description>
Procedure: proc_extract_sbe_rc
- The SLW stop address isn't properly aligned
+ PORE engine encountered an internal HW error
</description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_SLW_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
+ <ffdc>GROUP_PARITY_ERROR_0_4</ffdc>
+ <ffdc>SCAN_DATA_CRC_ERROR</ffdc>
<callout>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
<priority>HIGH</priority>
</callout>
<deconfigure>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</deconfigure>
<gard>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</gard>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SBE</rc>
+ <rc>RC_PROC_EXTRACT_SBE_RC_I2C_ERROR</rc>
<description>
Procedure: proc_extract_sbe_rc
- The SBE stop address isn't in a recognized address space
+ PORE engine encountered a I2C interface/setup error
</description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
- <ffdc>SOFT_ERR_STATUS</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
- <id>REG_FFDC_PROC_SBE_REGISTERS</id>
- <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
+ <ffdc>I2C_BAD_STATUS_0_3</ffdc>
+ <ffdc>FI2C_HANG</ffdc>
<callout>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
<priority>HIGH</priority>
</callout>
- <callout>
- <procedure>CODE</procedure>
- <priority>LOW</priority>
- </callout>
<deconfigure>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</deconfigure>
<gard>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</gard>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED_SLW</rc>
+ <rc>RC_PROC_EXTRACT_SBE_RC_SCOM_ERROR</rc>
<description>
Procedure: proc_extract_sbe_rc
- The SLW stop address isn't in a reognized address space
+ PORE engine encountered a SCOM error
</description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_SLW_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
+ <ffdc>SCOM_ADDRESS</ffdc>
+ <ffdc>PIB_ERROR_CODE</ffdc>
+ <ffdc>PIB_DATA_READ_PARITY_ERROR</ffdc>
<callout>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
<priority>HIGH</priority>
</callout>
- <callout>
- <procedure>CODE</procedure>
- <priority>LOW</priority>
- </callout>
<deconfigure>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</deconfigure>
<gard>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</gard>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG_SBE</rc>
+ <rc>RC_PROC_EXTRACT_SBE_RC_OCI_ERROR</rc>
<description>
Procedure: proc_extract_sbe_rc
- Extract RC from address subroutine tried to return SUCCESS for SBE, which isn't allowed
+ PORE SLW engine encountered error on OCI interface
</description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
- <ffdc>SOFT_ERR_STATUS</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
- <id>REG_FFDC_PROC_SBE_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
+ <ffdc>OCI_ERROR_CODE</ffdc>
+ <ffdc>OCI_DATA_READ_PARITY_ERROR</ffdc>
<callout>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
<priority>HIGH</priority>
</callout>
- <callout>
- <procedure>CODE</procedure>
- <priority>LOW</priority>
- </callout>
<deconfigure>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</deconfigure>
<gard>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</gard>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG_SLW</rc>
+ <rc>RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL</rc>
<description>
Procedure: proc_extract_sbe_rc
- Extract RC from address subroutine tried to return SUCCESS for SLW, which isn't allowed
+ PORE image pointer provided was NULL.
</description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_SLW_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
<callout>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
<priority>HIGH</priority>
</callout>
<callout>
@@ -246,22 +166,21 @@
<priority>LOW</priority>
</callout>
<deconfigure>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</deconfigure>
<gard>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</gard>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_UNKNOWN_ENGINE</rc>
+ <rc>RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED</rc>
<description>
Procedure: proc_extract_sbe_rc
- Tried to extract error from unknown engine type
+ The PORE halt address isn't in a recognized address space
</description>
- <ffdc>ENGINE</ffdc>
<callout>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
<priority>HIGH</priority>
</callout>
<callout>
@@ -269,328 +188,58 @@
<priority>LOW</priority>
</callout>
<deconfigure>
- <target>CHIP_IN_ERROR</target>
- </deconfigure>
- </hwpError>
- <!-- *********************************************************************** -->
- <hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_PIB_ERROR_SBE</rc>
- <description>
- Procedure: proc_extract_sbe_rc
- Error during PIB access for SBE
- </description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>FSI_STATUS</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
- <id>REG_FFDC_PROC_SBE_REGISTERS</id>
- <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
- <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc>
- <callout>
- <target>CHIP_IN_ERROR</target>
- <priority>HIGH</priority>
- </callout>
- <deconfigure>
- <target>CHIP_IN_ERROR</target>
- </deconfigure>
- <gard>
- <target>CHIP_IN_ERROR</target>
- </gard>
- </hwpError>
- <!-- *********************************************************************** -->
- <hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_I2C_SBE</rc>
- <description>
- Procedure: proc_extract_sbe_rc
- ECCB indicates unrecoverable ECC error from I2C during SBE execution
- Reload/update of SEEPROM required
- </description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
- <ffdc>ECCB_STATUS</ffdc>
- <ffdc>SOFT_ERR_STATUS</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
- <id>REG_FFDC_PROC_SBE_REGISTERS</id>
- <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
- <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc>
- <callout>
- <target>CHIP_IN_ERROR</target>
- <priority>HIGH</priority>
- </callout>
- </hwpError>
- <!-- *********************************************************************** -->
- <hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_PNOR_SBE</rc>
- <description>
- Procedure: proc_extract_sbe_rc
- ECCB indicates unrecoverable ECC error from PNOR during SBE execution
- Reload/Update of PNOR required
- </description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
- <ffdc>ECCB_STATUS</ffdc>
- <ffdc>SOFT_ERR_STATUS</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
- <id>REG_FFDC_PROC_SBE_REGISTERS</id>
- <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
- <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc>
- <callout>
- <target>CHIP_IN_ERROR</target>
- <priority>HIGH</priority>
- </callout>
- </hwpError>
- <!-- *********************************************************************** -->
- <hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_INTERNAL_ERROR_SBE</rc>
- <description>
- Procedure: proc_extract_sbe_rc
- SBE engine encountered an internal error
- </description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
- <ffdc>GROUP_PARITY_ERROR_0_4</ffdc>
- <ffdc>SCAN_DATA_CRC_ERROR</ffdc>
- <ffdc>SOFT_ERR_STATUS</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
- <id>REG_FFDC_PROC_SBE_REGISTERS</id>
- <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
- <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc>
- <callout>
- <target>CHIP_IN_ERROR</target>
- <priority>HIGH</priority>
- </callout>
- <deconfigure>
- <target>CHIP_IN_ERROR</target>
- </deconfigure>
- <gard>
- <target>CHIP_IN_ERROR</target>
- </gard>
- </hwpError>
- <!-- *********************************************************************** -->
- <hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_INTERNAL_ERROR_SLW</rc>
- <description>
- Procedure: proc_extract_sbe_rc
- SLW engine encountered an internal error
- </description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
- <ffdc>GROUP_PARITY_ERROR_0_4</ffdc>
- <ffdc>SCAN_DATA_CRC_ERROR</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_SLW_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
- <callout>
- <target>CHIP_IN_ERROR</target>
- <priority>HIGH</priority>
- </callout>
- <deconfigure>
- <target>CHIP_IN_ERROR</target>
- </deconfigure>
- <gard>
- <target>CHIP_IN_ERROR</target>
- </gard>
- </hwpError>
- <!-- *********************************************************************** -->
- <hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_SCOM_ERROR_SBE</rc>
- <description>
- Procedure: proc_extract_sbe_rc
- SBE engine encountered a SCOM error
- </description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
- <ffdc>SCOM_ADDRESS</ffdc>
- <ffdc>PIB_ERROR_CODE</ffdc>
- <ffdc>PIB_DATA_READ_PARITY_ERROR</ffdc>
- <ffdc>SOFT_ERR_STATUS</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
- <id>REG_FFDC_PROC_SBE_REGISTERS</id>
- <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
- <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc>
- <callout>
- <target>CHIP_IN_ERROR</target>
- <priority>HIGH</priority>
- </callout>
- <deconfigure>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</deconfigure>
<gard>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</gard>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_SCOM_ERROR_SLW</rc>
+ <rc>RC_SBE_UNKNOWN_ERROR</rc>
<description>
Procedure: proc_extract_sbe_rc
- SLW engine encountered a SCOM error
+ FAPI_SET_SBE_ERROR did not resolve PORE halt code to known return code
+ May be caused by platform attempting to resolve engine state with mismatched binary image.
</description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
- <ffdc>SCOM_ADDRESS</ffdc>
- <ffdc>PIB_ERROR_CODE</ffdc>
- <ffdc>PIB_DATA_READ_PARITY_ERROR</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_SLW_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
- <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc>
<callout>
- <target>CHIP_IN_ERROR</target>
- <priority>HIGH</priority>
+ <target>CHIP</target>
+ <priority>LOW</priority>
</callout>
- <deconfigure>
- <target>CHIP_IN_ERROR</target>
- </deconfigure>
- <gard>
- <target>CHIP_IN_ERROR</target>
- </gard>
- </hwpError>
- <!-- *********************************************************************** -->
- <hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_OCI_ERROR_SLW</rc>
- <description>
- Procedure: proc_extract_sbe_rc
- SLW engine encountered error on OCI interface
- </description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
- <ffdc>OCI_ERROR_CODE</ffdc>
- <ffdc>OCI_DATA_READ_PARITY_ERROR</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_SLW_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
- <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc>
<callout>
- <target>CHIP_IN_ERROR</target>
+ <procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
- <deconfigure>
- <target>CHIP_IN_ERROR</target>
- </deconfigure>
- <gard>
- <target>CHIP_IN_ERROR</target>
- </gard>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_I2C_ERROR_SBE</rc>
+ <rc>RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG</rc>
<description>
Procedure: proc_extract_sbe_rc
- SBE engine encountered a I2C interface/setup error
+ Failed to association PORE halt code with known return code
</description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
- <ffdc>I2C_BAD_STATUS_0_3</ffdc>
- <ffdc>FI2C_HANG</ffdc>
- <ffdc>SOFT_ERR_STATUS</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
- <id>REG_FFDC_PROC_SBE_REGISTERS</id>
- <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
- <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc>
<callout>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
<priority>HIGH</priority>
</callout>
- <deconfigure>
- <target>CHIP_IN_ERROR</target>
- </deconfigure>
- <gard>
- <target>CHIP_IN_ERROR</target>
- </gard>
- </hwpError>
- <!-- *********************************************************************** -->
- <hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_I2C_ERROR_SLW</rc>
- <description>
- Procedure: proc_extract_sbe_rc
- SLW engine encountered a I2C interface/setup error
- </description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
- <ffdc>I2C_BAD_STATUS_0_3</ffdc>
- <ffdc>FI2C_HANG</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_SLW_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
- <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc>
<callout>
- <target>CHIP_IN_ERROR</target>
- <priority>HIGH</priority>
- </callout>
- <deconfigure>
- <target>CHIP_IN_ERROR</target>
- </deconfigure>
- <gard>
- <target>CHIP_IN_ERROR</target>
- </gard>
- </hwpError>
- <!-- *********************************************************************** -->
- <hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_INSTRUCTION_ERROR_SBE</rc>
- <description>
- Procedure: proc_extract_sbe_rc
- SBE engine encountered an instruction fetch/decode/execution error
- </description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
- <ffdc>INSTRUCTION_PARITY_ERROR</ffdc>
- <ffdc>INVALID_INSTRUCTION_NON_ROTATE</ffdc>
- <ffdc>PC_OVERFLOW_UNDERFLOW</ffdc>
- <ffdc>PC_STACK_ERROR</ffdc>
- <ffdc>INSTRUCTION_FETCH_ERROR</ffdc>
- <ffdc>INVALID_OPERAND</ffdc>
- <ffdc>I2C_ENGINE_MISS</ffdc>
- <ffdc>INVALID_START_VECTOR</ffdc>
- <ffdc>INVALID_INSTRUCTION_ROTATE</ffdc>
- <ffdc>SOFT_ERR_STATUS</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
- <id>REG_FFDC_PROC_SBE_REGISTERS</id>
- <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
- <callout>
- <target>CHIP_IN_ERROR</target>
- <priority>HIGH</priority>
+ <procedure>CODE</procedure>
+ <priority>LOW</priority>
</callout>
<deconfigure>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</deconfigure>
<gard>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</gard>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_INSTRUCTION_ERROR_SLW</rc>
+ <rc>RC_PROC_EXTRACT_SBE_RC_INSTRUCTION_ERROR</rc>
<description>
Procedure: proc_extract_sbe_rc
- SLW engine encountered an instruction fetch/decode/execution error
+ PORE engine encountered an instruction fetch/decode/execution error
</description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
<ffdc>INSTRUCTION_PARITY_ERROR</ffdc>
<ffdc>INVALID_INSTRUCTION_NON_ROTATE</ffdc>
<ffdc>PC_OVERFLOW_UNDERFLOW</ffdc>
@@ -600,151 +249,119 @@
<ffdc>I2C_ENGINE_MISS</ffdc>
<ffdc>INVALID_START_VECTOR</ffdc>
<ffdc>INVALID_INSTRUCTION_ROTATE</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_SLW_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
<callout>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
<priority>HIGH</priority>
</callout>
<deconfigure>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</deconfigure>
<gard>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</gard>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_BAD_CHIP_TYPE_SBE</rc>
+ <rc>RC_PROC_EXTRACT_SBE_RC_BAD_CHIP_TYPE</rc>
<description>
Procedure: proc_extract_sbe_rc
- SBE execution of OTPROM code failed chip type (Murano/Venice) check
+ PORE SBE execution of OTPROM code failed chip type (Murano/Venice) check
</description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
<collectRegisterFfdc>
- <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
- <id>REG_FFDC_PROC_SBE_REGISTERS</id>
- <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
<id>REG_FFDC_PROC_FIRST_OTPROM_INSTRUCTIONS</id>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</collectRegisterFfdc>
<callout>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
<priority>HIGH</priority>
</callout>
<deconfigure>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</deconfigure>
<gard>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</gard>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_SEEPROM_MAGIC_NUMBER_MISMATCH_SBE</rc>
+ <rc>RC_PROC_EXTRACT_SBE_RC_SEEPROM_MAGIC_NUMBER_MISMATCH</rc>
<description>
Procedure: proc_extract_sbe_rc
- SBE execution of OTPROM code failed SEEPROM magic number check
+ PORE SBE execution of OTPROM code failed SEEPROM magic number check
</description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
<collectRegisterFfdc>
- <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
- <id>REG_FFDC_PROC_SBE_REGISTERS</id>
- <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
<id>REG_FFDC_PROC_FIRST_OTPROM_INSTRUCTIONS</id>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</collectRegisterFfdc>
- <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc>
<callout>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
<priority>HIGH</priority>
</callout>
<deconfigure>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</deconfigure>
<gard>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</gard>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_BRANCH_TO_SEEPROM_FAIL_SBE</rc>
+ <rc>RC_PROC_EXTRACT_SBE_RC_BRANCH_TO_SEEPROM_FAIL</rc>
<description>
Procedure: proc_extract_sbe_rc
- SBE execution of OTPROM code failed to branch to SEEPROM
+ PORE SBE execution of OTPROM code failed to branch to SEEPROM
</description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
<collectRegisterFfdc>
- <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
- <id>REG_FFDC_PROC_SBE_REGISTERS</id>
- <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
<id>REG_FFDC_PROC_FIRST_OTPROM_INSTRUCTIONS</id>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</collectRegisterFfdc>
<callout>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
<priority>HIGH</priority>
</callout>
<deconfigure>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</deconfigure>
<gard>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</gard>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_UNEXPECTED_OTPROM_HALT_SBE</rc>
+ <rc>RC_PROC_EXTRACT_SBE_RC_UNEXPECTED_OTPROM_HALT</rc>
<description>
Procedure: proc_extract_sbe_rc
- SBE execution of OTPROM code halted at an unexpected location
+ PORE SBE execution of OTPROM code halted at an unexpected location
</description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
<collectRegisterFfdc>
- <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
- <id>REG_FFDC_PROC_SBE_REGISTERS</id>
- <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
<id>REG_FFDC_PROC_FIRST_OTPROM_INSTRUCTIONS</id>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</collectRegisterFfdc>
<callout>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
<priority>HIGH</priority>
</callout>
<deconfigure>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</deconfigure>
<gard>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</gard>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_NEVER_STARTED_SBE</rc>
+ <rc>RC_PROC_EXTRACT_SBE_RC_NEVER_STARTED</rc>
<description>
Procedure: proc_extract_sbe_rc
- Procedure was called when no error bits were set and PC is all zeros. SBE
- was probably never started.
+ Procedure was called when no error bits were set and PC is all zeros.
+ PORE engine was probably never started.
</description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
<collectRegisterFfdc>
- <id>REG_FFDC_PROC_CFAM_REGISTERS</id>
- <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
- <id>REG_FFDC_PROC_SBE_REGISTERS</id>
- <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
<id>REG_FFDC_PROC_FIRST_OTPROM_INSTRUCTIONS</id>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</collectRegisterFfdc>
- <collectFfdc>proc_tp_collect_dbg_data,CHIP_IN_ERROR</collectFfdc>
<callout>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
<priority>HIGH</priority>
</callout>
<callout>
@@ -752,153 +369,70 @@
<priority>LOW</priority>
</callout>
<deconfigure>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</deconfigure>
<gard>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</gard>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_NEVER_STARTED_SLW</rc>
- <description>
- Procedure: proc_extract_sbe_rc
- Procedure was called when no error bits were set and PC is all zeros. SLW
- was probably never started.
- </description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_SLW_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
- <callout>
- <target>CHIP_IN_ERROR</target>
- <priority>HIGH</priority>
- </callout>
- <callout>
- <procedure>CODE</procedure>
- <priority>LOW</priority>
- </callout>
- <deconfigure>
- <target>CHIP_IN_ERROR</target>
- </deconfigure>
- <gard>
- <target>CHIP_IN_ERROR</target>
- </gard>
- </hwpError>
- <!-- *********************************************************************** -->
- <hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_I2C_SBE</rc>
+ <rc>RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_SEEPROM</rc>
<description>
Procedure: proc_extract_sbe_rc
ECCB indicates correctable ECC error threshold from I2C was exceeded during SBE execution
Reload/update of SEEPROM required
</description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>I2C_ECCB_STATUS</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
- <id>REG_FFDC_PROC_SBE_REGISTERS</id>
- <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
<callout>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
<priority>LOW</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_PNOR_SBE</rc>
+ <rc>RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_PNOR</rc>
<description>
Procedure: proc_extract_sbe_rc
ECCB indicates correctable ECC error threshold from PNOR was exceeded during SBE execution
Reload/update of PNOR required
</description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PNOR_ECCB_STATUS</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
- <id>REG_FFDC_PROC_SBE_REGISTERS</id>
- <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
<callout>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
<priority>LOW</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_I2C_AND_PNOR_SBE</rc>
+ <rc>RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_SEEPROM_AND_PNOR</rc>
<description>
Procedure: proc_extract_sbe_rc
ECCB indicates correctable ECC error threshold from both I2C and PNOR was exceeded during SBE execution
Reload/update of SEEPROM/PNOR required
</description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>I2C_ECCB_STATUS</ffdc>
- <ffdc>PNOR_ECCB_STATUS</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
- <id>REG_FFDC_PROC_SBE_REGISTERS</id>
- <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
<callout>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
<priority>LOW</priority>
</callout>
</hwpError>
<!-- *********************************************************************** -->
<hwpError>
- <rc>RC_PROC_EXTRACT_SBE_RC_CODE_BUG_SBE</rc>
+ <rc>RC_PROC_EXTRACT_SBE_RC_CODE_BUG</rc>
<description>
Procedure: proc_extract_sbe_rc
- SBE reported attention, but procedure attempted to return SUCCESS
+ PORE SBE reported attention, but procedure attempted to return SUCCESS
</description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <ffdc>PC</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
- <id>REG_FFDC_PROC_SBE_REGISTERS</id>
- <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
<callout>
<procedure>CODE</procedure>
<priority>LOW</priority>
</callout>
<deconfigure>
- <target>CHIP_IN_ERROR</target>
+ <target>CHIP</target>
</deconfigure>
</hwpError>
<!-- *********************************************************************** -->
- <hwpError>
- <rc>RC_SBE_UNKNOWN_ERROR</rc>
- <description>
- Procedure: proc_extract_sbe_rc
- FAPI_SET_SBE_ERROR did not resolve SBE/SLW PC to known RC.
- May be caused by platform attempting to resolve engine state with mismatched binary image.
- </description>
- <ffdc>CHIP_IN_ERROR</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id>
- <id>REG_FFDC_PROC_SBE_REGISTERS</id>
- <id>REG_FFDC_PROC_MBOX_REGISTERS</id>
- <target>CHIP_IN_ERROR</target>
- </collectRegisterFfdc>
- <callout>
- <target>CHIP_IN_ERROR</target>
- <priority>LOW</priority>
- </callout>
- <callout>
- <procedure>CODE</procedure>
- <priority>HIGH</priority>
- </callout>
- </hwpError>
- <!-- *********************************************************************** -->
</hwpErrors>
+
+
+
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