diff options
author | Adam Muhle <armuhle@us.ibm.com> | 2013-04-26 10:07:20 -0500 |
---|---|---|
committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-05-15 12:57:32 -0500 |
commit | 722ff9bff1f0d7830ef166822e32500accc421f9 (patch) | |
tree | a20c45f23d8433cf70cc73898177318b0da57d20 /src/usr/hwpf/hwp/occ/occ_procedures | |
parent | cdf07e157ef6173e5b4d1f3f39556ffad2884d0e (diff) | |
download | talos-hostboot-722ff9bff1f0d7830ef166822e32500accc421f9.tar.gz talos-hostboot-722ff9bff1f0d7830ef166822e32500accc421f9.zip |
AVP OCC Enable & Procedure Refresh
Refreshed OCC Procedures
Enabled OCC in AVP mode for all processors
Merged SLW and OCC to common HOMER image
RTC:50987
Change-Id: I08d9128dfcb572367c145ee0296a48292584a480
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4340
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp/occ/occ_procedures')
31 files changed, 6797 insertions, 5652 deletions
diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.C new file mode 100644 index 000000000..239541921 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.C @@ -0,0 +1,441 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: p8_cpu_special_wakeup.C,v 1.7 2013/04/16 12:14:14 pchatnah Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_cpu_special_wakeup.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Greg Still Email: stillgs@us.ibm.com +// *! +/// \file p8_cpu_special_wakeup.C +/// \brief Put targeted EX chiplets into special wake-up +/// +/// add to required proc ENUM requests +/// +/// High-level procedure flow: +/// \verbatim +/// +/// Based on "entity" parameter (OCC, FSP, PHYP), write the +/// appropriate Special Wakeup bit (different address) +/// +/// Poll for SPECIAL WAKEUP DONE +/// Polling timeouts need to account for the following (future version): +/// 1) All the chiplets are not in a Deep Idle state and will awaken in +/// < 1us (eg no PORE assistance needed) +/// +/// 2) All the chiplets are not in a Deep Sleep or less (run of nap) in +/// which case all can be in special wake-up in ~5ms state +/// +/// 3) Some chiplets are in Deep Sleep and some are in Deep Winkle +/// which case there is a serialization of the two exits (5ms (Sleep) +/// and 10ms (Winkle). +/// +/// Thus, do a progressive poll (in a future version). +/// Wait 1us +/// poll +/// if done, exit +/// pollcount=0 +/// do +/// wait 5ms +/// poll +/// if done, exit +/// pollcount++ +/// while pollcount<5 (eg 25ms) +/// flag timout error /// Timeouts on polling are progressive +/// +/// +/// Procedure Prereq: +/// - System clocks are running +/// \endverbatim +/// +//------------------------------------------------------------------------------ + + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- + +#include "p8_pm.H" +#include "p8_cpu_special_wakeup.H" +#include <ecmdDataBufferBase.H> +//#include <ecmdClientCapi.H> +#include <fapi.H> + + +extern "C" { + +using namespace fapi; + + +/// \param[in] i_target EX Target +/// \param[in] i_operation ENABLE, DISABLE, INIT +/// \param[in] entity Entity bit to use (OCC, PHYP, FSP) + +/// \retval PM_SUCCESS if something good happens, +/// \retval PM_PROCPM_SPCWKUP* otherwise +fapi::ReturnCode +p8_cpu_special_wakeup( const fapi::Target& i_target, + PROC_SPCWKUP_OPS i_operation , + PROC_SPCWKUP_ENTITY i_entity ) + +{ + fapi::ReturnCode l_rc; + uint32_t e_rc = 0; + ecmdDataBufferBase data(64); + ecmdDataBufferBase polldata(64); + //TODO RTC: 71328 - hack to indicate unused + bool __attribute__((unused)) error_flag = false; + //TODO RTC: 71328 - needs to be const + const char* PROC_SPCWKUP_ENTITY_NAMES[] = + { + "HOST", + "FSP", + "OCC", + "PHYP", + "SPW_ALL" + }; + + + + //TODO RTC: 71328 - needs to be const + const char* PROC_SPCWKUP_OPS_NAMES[] = + { + "DISABLE", + "ENABLE", + "INIT" + }; + + + uint32_t special_wakeup_max_polls; + + /// Time (binary in milliseconds) for the first poll check (running/nap + /// case. + /// uint32_t special_wakeup_quick_poll_time = 1; + + /// Get an attribute that defines the maximum special wake-up polling + /// timing (binary in milliseconds). + + uint32_t special_wakeup_timeout = 25; + + /// Get an attribute that defines the special wake-up polling interval + /// (binary in milliseconds). + uint32_t special_wakeup_poll_interval = 5; + + uint32_t pollcount = 0; + uint32_t count = 0; + + std::vector<fapi::Target> l_chiplets; + std::vector<Target>::iterator itr; + + uint64_t SP_WKUP_REG_ADDRS; + + //-------------------------------------------------------------------------- + // Read the counts of different ENTITY (FSP,OCC,PHYP) from the Attributes + //-------------------------------------------------------------------------- + + uint32_t PHYP_SPWKUP_COUNT = 0; + uint32_t FSP_SPWKUP_COUNT = 0; + uint32_t OCC_SPWKUP_COUNT = 0; + + do + { + + FAPI_INF("Executing p8_cpu_special_wakeup %s for %s ...", + PROC_SPCWKUP_OPS_NAMES[i_operation], + PROC_SPCWKUP_ENTITY_NAMES[i_entity]); + + // Initialize the attributes to 0. + if (i_operation == SPCWKUP_INIT) + { + FAPI_INF("Initializing ATTR_PM_SPWUP_FSP"); + l_rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_FSP, &i_target, FSP_SPWKUP_COUNT); + if (l_rc) + { + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_FSP with l_rc = 0x%x", (uint32_t)l_rc); + } + + FAPI_INF("Initializing ATTR_PM_SPWUP_OCC"); + l_rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OCC, &i_target, OCC_SPWKUP_COUNT); + if (l_rc) + { + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_OCC with l_rc = 0x%x", (uint32_t)l_rc); + break; + } + + FAPI_INF("Initializing ATTR_PM_SPWUP_PHYP"); + l_rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_PHYP, &i_target, PHYP_SPWKUP_COUNT); + if (l_rc) + { + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_PHYP with l_rc = 0x%x", (uint32_t)l_rc); + break; + } + + // Leave the procedure + break; + } + + //-------------------------------------------------------------------------- + // Checking the ENTITY who raised this OPERATION + //-------------------------------------------------------------------------- + + fapi::Target l_parentTarget; + uint8_t attr_chip_unit_pos = 0; + + // Get the parent chip to target the registers + l_rc = fapiGetParentChip(i_target, l_parentTarget); + if (l_rc) + { + break; // throw error + } + + // Check whether system is checkstopped + l_rc=fapiGetScom(l_parentTarget, PCBMS_INTERRUPT_TYPE_REG_0x000F001A, data); + if( data.isBitSet( 2 ) ) + { + FAPI_ERR( "This chip is xstopped, so ignoring the special wakeup request\n" ); + FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_CHKSTOP); + break; + } + + // Get the core number + l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, attr_chip_unit_pos); + if (l_rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with l_rc = 0x%x", (uint32_t)l_rc); + break; + } + // CORE_NUM = attr_chip_unit_pos; + FAPI_DBG("Core number = %d", attr_chip_unit_pos); + + // Read the Attributes to know the Special_wake counts form each entities . + // This should be different for different EX chiplets. + l_rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_FSP, &i_target, FSP_SPWKUP_COUNT); + if (l_rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_FSP with l_rc = 0x%x", (uint32_t)l_rc); + break; + } + + l_rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_OCC, &i_target, OCC_SPWKUP_COUNT ); + if (l_rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_FSP with l_rc = 0x%x", (uint32_t)l_rc); + break; + } + + l_rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_PHYP,&i_target , PHYP_SPWKUP_COUNT ); + if (l_rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_FSP with l_rc = 0x%x", (uint32_t)l_rc); + break; + } + + /// Calculate the maximum number of polls until a timeout is thrown + special_wakeup_max_polls = special_wakeup_timeout / special_wakeup_poll_interval; + + uint64_t EX_PMGP0_0x1X0F0100 = EX_PMGP0_0x100F0100 + + (attr_chip_unit_pos * 0x01000000); + + // Process counts based on the calling entity + if (i_entity == OCC) + { + count = OCC_SPWKUP_COUNT ; + FAPI_INF("OCC count before = %d" , count); + SP_WKUP_REG_ADDRS = PM_SPECIAL_WKUP_OCC_0x100F010C + + (attr_chip_unit_pos * 0x01000000) ; + } + else if (i_entity == FSP) + { + count = FSP_SPWKUP_COUNT ; + FAPI_INF("FSP count before = %d" , count); + SP_WKUP_REG_ADDRS = PM_SPECIAL_WKUP_FSP_0x100F010B + + (attr_chip_unit_pos * 0x01000000); + } + else if (i_entity == PHYP) + { + count = PHYP_SPWKUP_COUNT ; + FAPI_INF("PHYP count before = %d" , count); + SP_WKUP_REG_ADDRS = PM_SPECIAL_WKUP_PHYP_0x100F010D + + (attr_chip_unit_pos * 0x01000000); + } + else + { + FAPI_ERR("Unknown entity passed to proc_special_wakeup. Entity %x ....", i_entity); + // I_ENTITY = i_entity; + PROC_SPCWKUP_ENTITY & I_ENTITY = i_entity ; + FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_SPCWKUP_CODE_BAD_ENTITY); + break; + } + + ///////////////////////////////////////////////////////////////////////////// + // Checking the type of OPERATION and process the request + ///////////////////////////////////////////////////////////////////////////// + + l_rc=fapiGetScom(l_parentTarget, EX_PMGP0_0x1X0F0100, data); + if(l_rc) + { + break; + } + + if (i_operation == SPCWKUP_ENABLE) + { + FAPI_INF("Setting Special Wake-up ...") ; + + // FAPI_INF("Count value after the increment is %x ...", count); + if (count == 0) + { + + GETSCOM(i_target, SP_WKUP_REG_ADDRS, data); + + e_rc = data.flushTo0(); + e_rc |= data.setBit(0); + E_RC_CHECK(e_rc, l_rc); + + PUTSCOM(i_target, SP_WKUP_REG_ADDRS, data); + + // poll for the set completion + pollcount = 0; + e_rc=data.flushTo0(); + E_RC_CHECK(e_rc, l_rc); + + while (data.isBitClear(31) && pollcount < special_wakeup_max_polls) + { + GETSCOM(l_parentTarget, EX_PMGP0_0x1X0F0100, data); + FAPI_DBG(" Loop get for PMGP0(31) to goto 1 => 0x%16llx", data.getDoubleWord(0)); + + fapiDelay(special_wakeup_poll_interval*1000, 1000000); + pollcount ++ ; + + } + if (data.isBitClear(31)) + { + FAPI_ERR("Timed out in setting the CPU in Special wakeup ... "); + FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_SPCWKUP_TIMEOUT); + break; + } + GETSCOM(l_parentTarget, EX_PMGP0_0x1X0F0100, data); + FAPI_DBG(" Special Wake-up Done asserted (PMGP0(31)!! =>0x%16llx", data.getDoubleWord(0)); + + GETSCOM(i_target, EX_OHA_RO_STATUS_REG_0x1002000B, data); + FAPI_DBG(" Special Wake-up complete (OHA_RO_STATUS(1)!! => 0x%16llx", data.getDoubleWord(0)); + + GETSCOM(l_parentTarget, SP_WKUP_REG_ADDRS , data); + FAPI_DBG(" After set of SPWKUP_REG (0x%08llx) => 0x%16llx", SP_WKUP_REG_ADDRS, data.getDoubleWord(0)); + + } + count++ ; + + } + else if (i_operation == SPCWKUP_DISABLE) + { + + FAPI_INF("Clearing Special Wake-up..."); + + if ( count == 1 ) + { + GETSCOM(l_parentTarget, SP_WKUP_REG_ADDRS , data); + FAPI_DBG(" Before clear of SPWKUP_REG (0x%08llx) => =>0x%16llx", SP_WKUP_REG_ADDRS, data.getDoubleWord(0)); + + e_rc=data.flushTo0(); + E_RC_CHECK(e_rc, l_rc); + + PUTSCOM(l_parentTarget, SP_WKUP_REG_ADDRS , data); + FAPI_DBG(" After clear putscom of SPWKUP_REG (0x%08llx) => 0x%16llx", SP_WKUP_REG_ADDRS, data.getDoubleWord(0)); + + // This puts an inherent delay in the propagation of the reset transition. + GETSCOM(l_parentTarget, SP_WKUP_REG_ADDRS , data); + FAPI_DBG(" After read (delay) of SPWKUP_REG (0x%08llx) 0x%16llx", SP_WKUP_REG_ADDRS, data.getDoubleWord(0)); + + count -- ; + } + else if ( count > 1 ) + { + FAPI_INF("Other processes having clear Special Wake-up pending. Chiplet is still in Special Wake-up state."); + count -- ; + } + else + { + FAPI_ERR("Illegal Special wake up operation : already Disabled on this platform %x", i_entity); + FAPI_ERR (" FSP_COUNT = %d , OCC_COUNT = %d , PHYP_COUNT = %d ", FSP_SPWKUP_COUNT ,OCC_SPWKUP_COUNT ,PHYP_SPWKUP_COUNT); + PROC_SPCWKUP_OPS & I_OPERATION = i_operation ; + FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_SPCWKUP_CODE_BAD_OP); + break; + } + + GETSCOM(l_parentTarget, SP_WKUP_REG_ADDRS , data); + FAPI_DBG(" After configuring SPWKUP_REG value =>0x%16llx", data.getDoubleWord(0)); + + } + else + { + FAPI_ERR("Please specify operation either ENABLE or DISABLE. Operation %x", i_operation ); + PROC_SPCWKUP_OPS & I_OPERATION = i_operation ; + FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_SPCWKUP_CODE_BAD_OP); + break; + } + + ///////////////////////////////////////////////// + // Update the attributes + ///////////////////////////////////////////////// + + if ( i_entity == OCC ) + { + OCC_SPWKUP_COUNT = count ; + l_rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OCC, &i_target, OCC_SPWKUP_COUNT ); + if (l_rc) + { + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_OCC with l_rc = 0x%x", (uint32_t)l_rc); + break; + } + } + else if (i_entity == FSP) + { + FSP_SPWKUP_COUNT = count ; + l_rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_FSP, &i_target, FSP_SPWKUP_COUNT ); + if (l_rc) + { + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_FSP with l_rc = 0x%x", (uint32_t)l_rc); + break; + } + } + else if (i_entity == PHYP) + { + PHYP_SPWKUP_COUNT = count; + l_rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_PHYP, &i_target, PHYP_SPWKUP_COUNT ); + if (l_rc) + { + FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_PHYP1 with l_rc = 0x%x", (uint32_t)l_rc); + break; + } + } + + FAPI_INF (" FSP_COUNT = %d , OCC_COUNT = %d , PHYP_COUNT = %d ", FSP_SPWKUP_COUNT ,OCC_SPWKUP_COUNT ,PHYP_SPWKUP_COUNT); + } while (0); + + return l_rc ; +} + + +} //end extern C diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.H new file mode 100644 index 000000000..99b3686de --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.H @@ -0,0 +1,112 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_cpu_special_wakeup.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: p8_cpu_special_wakeup.H,v 1.5 2013/04/16 12:14:35 pchatnah Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_cpu_special_wakeup.H,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : proc_cpu_special_wakeup.H +// *! DESCRIPTION : Set the EX chiplet into Special Wake-up via one of the +// *! entity bits provided +// *! +// *! OWNER NAME : Greg Still Email: stillgs@us.ibm.com +// *! BACKUP NAME : Pradeep CN Email: padeepcn@in.ibm.com +// *! +//------------------------------------------------------------------------------ + +#ifndef _PROC_CPUSPECWKUP_H_ +#define _PROC_CPUSPECWKUP_H_ + + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +#ifndef _PROC_SPCWKUP_ENTITY +#define _PROC_SPCWKUP_ENTITY + +#define NUM_SPCWKUP_ENTITIES 4 +enum PROC_SPCWKUP_ENTITY +{ + HOST, + FSP, + OCC, + PHYP = HOST, + SPW_ALL +}; + + + +#define NUM_SPCWKUP_OPS 3 +enum PROC_SPCWKUP_OPS +{ + SPCWKUP_DISABLE, + SPCWKUP_ENABLE, + SPCWKUP_INIT +}; + + +#endif // _PROC_SPCWKUP_TGTS + + + + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*p8_cpu_special_wakeup_FP_t) ( + const fapi::Target&, + PROC_SPCWKUP_OPS, + PROC_SPCWKUP_ENTITY ); + +extern "C" { + +//------------------------------------------------------------------------------ +// Parameter structure definitions +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Function prototype +//------------------------------------------------------------------------------ +/// \param[in] i_target EX target +/// \param[in] i_entity Entity bit to use (OCC, PHYP, FSP) +/// \param[in] i_operation operation to use (SPCWKUP_ENABLE, SPCWKUP_DISABLE) + + +/// \retval ECMD_SUCCESS if something good happens, +/// \retval BAD_RETURN_CODE otherwise +fapi::ReturnCode +p8_cpu_special_wakeup( const fapi::Target& i_target, + PROC_SPCWKUP_OPS i_operation , + PROC_SPCWKUP_ENTITY i_entity ); + +} // extern "C" + +#endif // _PROC_CPUSPECWKUP_H_ diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_ocb_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_ocb_init.C index c85979e01..59745ec57 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_ocb_init.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_ocb_init.C @@ -20,25 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_ocb_init.C,v 1.3 2012/10/11 13:49:00 jimyac Exp $ -// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_ocb_init.C,v $ +// $Id: p8_ocb_init.C,v 1.5 2013/04/23 16:30:58 jimyac Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_ocb_init.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 // *! All Rights Reserved -- Property of IBM @@ -598,6 +581,149 @@ ReturnCode proc_ocb_reset(const Target& i_target) { } } // end for loop + // ----------------------------------------- + // Set Interrupt Source Mask Registers 0 & 1 + // OIMR0/1 @ 0X0006A006 & 0X0006A016 + // ----------------------------------------- + l_ecmdRc = data.flushTo1(); + if (l_ecmdRc) { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc); + rc.setEcmdError(l_ecmdRc); + return rc; + } + + rc = fapiPutScom(i_target, OCC_ITP_MASK0_MASK_OR_0x0006A006, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCC Interrupt Source Mask Register0 (OIMR0)"); + return rc; + } + + rc = fapiPutScom(i_target, OCC_ITP_MASK1_MASK_OR_0x0006A016, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCC Interrupt Source Mask Register1 (OIMR1)"); + return rc; + } + + // --------------------------------------------------------------------------------- + // Clear OCC Interrupt Controller Registers + // - OITR0/1 Interrupt Type 0/1 @ 0x0006A008 & 0x0006A018 + // - OIEPR0/1 Interrupt Edge Polarity 0/1 @ 0x0006A009 & 0x0006A019 + // - OISR0/1 Interrupt Source 0/1 @ 0x0006A001 & 0x0006A011 + // - OCIR0/1 Interrupt Critical Enable 0/1 @ 0x0006A00A & 0x0006A01A + // - ODHER0/1 Interrupt Debug Halt Enable 0/1 @ 0x0006A00A & 0x0006A01A + // - OUDER0/1 Interrupt Unconditional Debug Event Enable @ 0x0006A00C & 0x0006A01C + // --------------------------------------------------------------------------------- + l_ecmdRc = data.flushTo0(); + if (l_ecmdRc) { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc); + rc.setEcmdError(l_ecmdRc); + return rc; + } + + rc = fapiPutScom(i_target, OCC_ITP_TYPE0_0x0006A008, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCC Interrupt Type Register0 (OITR0)"); + return rc; + } + + rc = fapiPutScom(i_target, OCC_ITP_TYPE1_0x0006A018, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCC Interrupt Type Register1 (OITR1)"); + return rc; + } + + + rc = fapiPutScom(i_target, OCC_ITP_EDGE_POLARITY0_0x0006A009, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCC Interrupt Edge Polarity Register0 (OIEPR0)"); + return rc; + } + + rc = fapiPutScom(i_target, OCC_ITP_EDGE_POLARITY1_0x0006A019, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCC Interrupt Edge Polarity Register1 (OIEPR1)"); + return rc; + } + + + rc = fapiPutScom(i_target, OCC_ITP_SOURCE0_MASK_AND_0x0006A001, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCC Interrupt Source Register0 (OISR0)"); + return rc; + } + + rc = fapiPutScom(i_target, OCC_ITP_SOURCE1_MASK_AND_0x0006A011, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCC Interrupt Source Register1 (OISR1)"); + return rc; + } + + + rc = fapiPutScom(i_target, OCC_ITP_CRITICAL_EN0_0x0006A00A, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCC Interrupt Critical Enable Register0 (OCIR0)"); + return rc; + } + + rc = fapiPutScom(i_target, OCC_ITP_CRITICAL_EN1_0x0006A01A, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCC Interrupt Critical Enable Register1 (OCIR1)"); + return rc; + } + + + rc = fapiPutScom(i_target, OCC_ITP_DEBUG_HALT_EN0_0x0006A00E, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCC Interrupt Debug Halt Enable Register0 (ODHER0)"); + return rc; + } + + rc = fapiPutScom(i_target, OCC_ITP_DEBUG_HALT_EN1_0x0006A01E, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCC Interrupt Debug Halt Enable Register1 (ODHER1)"); + return rc; + } + + + rc = fapiPutScom(i_target, OCC_ITP_UNCOND_DEBUG_EN0_0x0006A00C, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCC Unconditional Debug Event Enable Register0 (OUDER0)"); + return rc; + } + + rc = fapiPutScom(i_target, OCC_ITP_UNCOND_DEBUG_EN1_0x0006A01C, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCC Unconditional Debug Event Enable Register1 (OUDER1)"); + return rc; + } + + // ---------------------------------------------------------- + // Clear OCC Interrupt Timer Registers 0 & 1 + // OTR0/1 @ 0x0006A100 & 0x0006A101 + // ---------------------------------------------------------- + // clear OTR0/1 0x0006A100 & 0x0006A101 need bits 0&1 set to clear register + l_ecmdRc = data.flushTo0(); + l_ecmdRc |= data.setBit(0); + l_ecmdRc |= data.setBit(1); + + if (l_ecmdRc) { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc); + rc.setEcmdError(l_ecmdRc); + return rc; + } + + rc = fapiPutScom(i_target, OCC_ITP_TIMER0_0x0006A100, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCC Interrupt Timer0 Register (OTR0)"); + return rc; + } + + rc = fapiPutScom(i_target, OCC_ITP_TIMER1_0x0006A101, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCC Interrupt Timer1 Register (OTR1)"); + return rc; + } + return rc; } diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_ocb_init.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_ocb_init.H index ff43dac94..8e1f58ec8 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_ocb_init.H +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_ocb_init.H @@ -20,23 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ +// $Id: p8_ocb_init.H,v 1.4 2012/11/27 18:11:50 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_ocb_init.H,v $ #ifndef _P8_OCB_INIT_H_ #define _P8_OCB_INIT_H_ diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_control.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_control.H index a96336002..38183828e 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_control.H +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_control.H @@ -20,23 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ +// $Id: p8_occ_control.H,v 1.3 2013/01/08 13:52:08 jimyac Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_occ_control.H,v $ #ifndef _P8_OCC_CONTROL_H_ #define _P8_OCC_CONTROL_H_ @@ -68,9 +53,9 @@ const uint8_t PPC405_BOOT_SRAM = 0x01; const uint8_t PPC405_BOOT_MEM = 0x02; const uint8_t PPC405_BOOT_OLD = 0x03; -const uint32_t PPC405_BRANCH_SRAM_INSTR = 0x4BF80012; // Branch Absolute 0xFFF80010 => ba 0xfff80010 (boot from sram) -const uint32_t PPC405_BRANCH_MEM_INSTR = 0x48000012; // Branch Absolute 0x00000010 => ba 0x00000010 (boot from memory) -const uint32_t PPC405_BRANCH_OLD_INSTR = 0x4BFFFFF0; // Branch Relative -16 (boot from sram) +const uint32_t PPC405_BRANCH_SRAM_INSTR = 0x4BF80042; // Branch Absolute 0xFFF80040 (boot from sram) +const uint32_t PPC405_BRANCH_MEM_INSTR = 0x48000042; // Branch Absolute 0x00000040 (boot from memory) +const uint32_t PPC405_BRANCH_OLD_INSTR = 0x4BFFFFF0; // Branch Relative -16 (boot from sram) } // extern "C" diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_sram_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_sram_init.C index ca6f1e787..e31d02d77 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_sram_init.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_sram_init.C @@ -20,25 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_occ_sram_init.C,v 1.2 2012/10/04 03:41:35 jimyac Exp $ -// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_occ_sram_init.C,v $ +// $Id: p8_occ_sram_init.C,v 1.3 2013/04/01 04:11:52 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_occ_sram_init.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -100,8 +83,7 @@ p8_occ_sram_init(const Target& i_target, uint32_t mode) //ecmdDataBufferBase mask; - FAPI_INF(""); - FAPI_INF("Executing p8_occ_sram_init in mode %x ....\n", mode); + FAPI_INF("Executing p8_occ_sram_init in mode %x ...", mode); /// ------------------------------- /// Configuration: perform translation of any Platform Attributes into Feature Attributes @@ -109,9 +91,8 @@ p8_occ_sram_init(const Target& i_target, uint32_t mode) if (mode == PM_CONFIG) { - FAPI_INF("OCC SRAM configuration...\n"); - - FAPI_INF("---> None defined...\n"); + FAPI_INF("OCC SRAM configuration..."); + FAPI_INF("---> None defined..."); } @@ -121,7 +102,7 @@ p8_occ_sram_init(const Target& i_target, uint32_t mode) else if (mode == PM_INIT) { - FAPI_INF("OCC SRAM initialization...\n"); + FAPI_INF("OCC SRAM initialization..."); } @@ -131,7 +112,7 @@ p8_occ_sram_init(const Target& i_target, uint32_t mode) else if (mode == PM_RESET) { - FAPI_INF("OCC SRAM reset...\n"); + FAPI_INF("OCC SRAM reset..."); } @@ -140,7 +121,7 @@ p8_occ_sram_init(const Target& i_target, uint32_t mode) else { - FAPI_ERR("Unknown mode passed to p8_occ_sram_init. Mode %x ....\n", mode); + FAPI_ERR("Unknown mode passed to p8_occ_sram_init. Mode %x ....", mode); FAPI_SET_HWP_ERROR(rc, RC_PROCPM_OCCSRAM_CODE_BAD_MODE); } diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_sram_init.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_sram_init.H index e7cfd9e4a..cea66dee2 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_sram_init.H +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_sram_init.H @@ -20,25 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ // $Id: p8_occ_sram_init.H,v 1.1 2012/08/23 16:35:37 jimyac Exp $ -// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_occ_sram_init.H,v $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_occ_sram_init.H,v $ //------------------------------------------------------------------------------ // *| // *! (C) Copyright International Business Machines Corp. 2011 diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.C index 303aef3d4..a524b71a4 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.C @@ -20,25 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_oha_init.C,v 1.3 2012/10/04 10:23:00 rmaier Exp $ -// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_oha_init.C,v $ +// $Id: p8_oha_init.C,v 1.8 2013/03/26 12:13:04 pchatnah Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_oha_init.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -47,7 +30,7 @@ // *! OWNER NAME: Ralf Maier Email: ralf.maier@de.ibm.com // *! // *! General Description: -// *! +// *! // *! The purpose of this procedure is to do a initial setup of OHA // *! // *! Procedure Prereq: @@ -86,16 +69,9 @@ /// \version -------------------------------------------------------------------------- /// \version 1.4 rmaier 03/13/12 Added modes-structure /// \version -------------------------------------------------------------------------- -/// \version 1.0 rmaier 12/01/11 Initial Version +/// \version 1.0 rmaier 12/01/11 Initial Version /// \version --------------------------------------------------------------------------- /// -/// -/// -/// -/// -/// -/// -/// /// High-level procedure flow: /// /// \verbatim @@ -104,43 +80,41 @@ /// - completed istep procedure /// /// -/// loop over all valid chiplets { -/// -/// Setup aiss hang time in oha_mode_reg -/// set aiss_timeout to max -- oha_mode_reg (11:14) , ADR 1002000D (SCOM) -/// -- 9 => longest time 512 ms -/// Setup low activity in oha_low_activity_detect_mode_reg -/// -- oha_low_activity_detect_mode_reg, ADR 10020003 (SCOM) -/// \todo when should we enable the low activity detection or just setup the ranges?? -/// set lad_enable = 1?? -/// set lad_entry = 16 -- bit index of a 24 bit counter based on base counter 0: longest, 23: shortest interval -/// set lad_exit = 17 -- bit index of a 24 bit counter based on base counter 0: longest, 23: shortest interval -/// -/// -/// Setup Power Proxy Trace in activity_sample_mode_reg -/// set ppt_int_timer_select -- activity_sample_mode_reg (36:37) ADR 10020000 (SCOM) -/// -- select precounter for ppt timer ( 0=0.25us, 1=0.5us, 2=1us, 3=2us ) -/// /// if PM_CONFIG { -/// -/// convert_ppt_time() - Convert Power Proxy Trace Time to Power Proxy Trace Time Select and Match feature attributes -/// With ATTR_PM_POWER_PROXY_TRACE_TIMER (binary in nanoseconds) to produce ATTR_PM_PPT_TIMER_MATCH_VALUE and ATTR_PM_PPT_TIMER_TICK -/// 0=0.25us , 1=0.5us, 2=1us, and 3=2us +/// +/// convert_ppt_time() - Convert Power Proxy Trace Time to Power Proxy Trace Time Select and Match feature attributes +/// With ATTR_PM_POWER_PROXY_TRACE_TIMER (binary in nanoseconds) to produce ATTR_PM_PPT_TIMER_MATCH_VALUE and ATTR_PM_PPT_TIMER_TICK +/// 0=0.25us , 1=0.5us, 2=1us, and 3=2us /// /// else if PM_INIT { +/// loop over all valid chiplets { +/// Check if OHA is accessible as chiplet may not be enabled or are in winkle /// -/// Timer settings if not able to be done in the init file -/// - PPT timer -/// - AISS hang timer +/// Setup aiss hang time in oha_mode_reg +/// Set aiss_timeout to max -- oha_mode_reg (11:14) , ADR 1002000D (SCOM) +/// -- 9 => longest time 512 ms +/// Setup low activity in oha_low_activity_detect_mode_reg +/// -- oha_low_activity_detect_mode_reg, ADR 10020003 (SCOM) +/// \todo when should we enable the low activity detection or just setup the ranges?? +/// Set lad_enable = 1?? +/// Set lad_entry = 16 -- bit index of a 24 bit counter based on base counter 0: longest, 23: shortest interval +/// Set lad_exit = 17 -- bit index of a 24 bit counter based on base counter 0: longest, 23: shortest interval /// -/// } else if PM_RESET { /// -/// AISS reset +/// Setup Power Proxy Trace in activity_sample_mode_reg +/// Set ppt_int_timer_select -- activity_sample_mode_reg (36:37) ADR 10020000 (SCOM) +/// -- select precounter for ppt timer ( 0=0.25us, 1=0.5us, 2=1us, 3=2us ) +/// +/// ) +/// } else if PM_RESET { +/// loop over all valid chiplets { +/// Check if OHA is accessible as chiplet may not be enabled or are in winkle /// +/// AISS reset +/// } /// } //end PM_RESET -mode /// /// - /// \endverbatim /// //------------------------------------------------------------------------------ @@ -152,18 +126,15 @@ // ---------------------------------------------------------------------- // Includes // ---------------------------------------------------------------------- -#include <fapi.H> + #include "p8_pm.H" #include "p8_scom_addresses.H" #include "p8_oha_init.H" - - +#include "p8_pcb_scom_errors.H" extern "C" { - - - + using namespace fapi; //------------------------------------------------------------------------------ @@ -189,12 +160,14 @@ typedef struct { // Function definitions // ---------------------------------------------------------------------- -// Reset function -fapi::ReturnCode p8_oha_init_reset (const Target &i_target, uint32_t i_mode); +// Reset function +fapi::ReturnCode p8_oha_init_reset( const fapi::Target& i_target, + uint32_t i_mode); // Config function -fapi::ReturnCode p8_oha_init_config (const fapi::Target& i_target) ; -// INIT -fapi::ReturnCode p8_oha_init_init (const fapi::Target& i_target, struct_i_oha_val_init_type i_oha_val_init) ; +fapi::ReturnCode p8_oha_init_config(const fapi::Target& i_target); +// INIT +fapi::ReturnCode p8_oha_init_init( const fapi::Target& i_target, + struct_i_oha_val_init_type i_oha_val_init); // ---------------------------------------------------------------------- @@ -204,521 +177,597 @@ fapi::ReturnCode p8_oha_init_init (const fapi::Target& i_target, struct_i_oh fapi::ReturnCode p8_oha_init(const fapi::Target &i_target, uint32_t i_mode) { - fapi::ReturnCode rc; - - - - - - if ( i_mode == PM_CONFIG ) { - - FAPI_DBG("*************************************"); - FAPI_INF("MODE: CONFIG , Calling: p8_oha_init_config"); - FAPI_DBG("*************************************"); - rc=p8_oha_init_config(i_target); - - if (rc) { - FAPI_ERR(" p8_oha_init_config failed. With rc = 0x%x", (uint32_t)rc); return rc; - } - - } else if ( i_mode == PM_INIT ) { - - - FAPI_DBG("*************************************"); - FAPI_INF("MODE: INIT , Calling: p8_oha_init_init"); - FAPI_DBG("*************************************"); - - // ****************************************************************** - /// \todo should this values be attributes?? The get those attributes here - //#ifndef ATTRIBUTES_AVAIL - - //Declare parms struct - struct_i_oha_val_init_type i_oha_val_init; - - //Assign values to parms in struct - // should come from MRWB - i_oha_val_init.AISS_HANG_DETECT_TIMER_SEL = 9; // oha_mode_reg (11:14) - 0=1ms, 1=2ms, 3=4ms, ...9=512ms. others illegal - i_oha_val_init.PPT_TIMER_SELECT = 3; // activity_sample_mode_reg (36:37) 0=0.25us, 1=0.5us, 2=1us, and 3=2us - i_oha_val_init.LAD_ENTRY = 16; - i_oha_val_init.LAD_EXIT = 17; - - - //#else - // FAPI_ATTR_GET("IVRMS_ENABLED", i_target,(unit8_t) ivrms_enabled); //VENICE or SALERNO - - //#endif - - // ****************************************************************** - - - - rc=p8_oha_init_init(i_target, i_oha_val_init); - - if (rc) { - FAPI_ERR(" p8_oha_init_init failed. With rc = 0x%x", (uint32_t)rc); return rc; - } - - - } else if ( i_mode == PM_RESET ) { - FAPI_DBG("*************************************"); - FAPI_INF("MODE: RESET"); - FAPI_DBG("*************************************"); - - - - - //Declare parms struct - struct_i_oha_val_init_type __attribute__((unused)) i_oha_val_init; // HACK - - //Assign values to parms in struct - // should come from MRWB - i_oha_val_init.AISS_HANG_DETECT_TIMER_SEL = 9; // oha_mode_reg (11:14) - 0=1ms, 1=2ms, 3=4ms, ...9=512ms. others illegal - i_oha_val_init.PPT_TIMER_SELECT = 3; // activity_sample_mode_reg (36:37) 0=0.25us, 1=0.5us, 2=1us, and 3=2us - i_oha_val_init.LAD_ENTRY = 16; - i_oha_val_init.LAD_EXIT = 17; - - // ****************************************************************** - /// \todo should this values be attributes?? The get those attributes here - - #ifndef ATTRIBUTES_AVAIL + fapi::ReturnCode rc; + if ( i_mode == PM_CONFIG ) + { - #else - // FAPI_ATTR_GET("IVRMS_ENABLED", i_target,(unit8_t) ivrms_enabled); //VENICE or SALERNO + FAPI_INF("<p8_oha_init> : MODE: CONFIG Calling p8_oha_init_config"); + + rc=p8_oha_init_config(i_target); + if (rc) + { + FAPI_ERR(" p8_oha_init_config failed. With rc = 0x%x", (uint32_t)rc); return rc; + } - #endif + } else if ( i_mode == PM_INIT ) { - // ****************************************************************** + FAPI_INF("<p8_oha_init> : MODE: INIT Calling p8_oha_init_init"); + //Declare parms struct + struct_i_oha_val_init_type i_oha_val_init; + //Assign values to parms in struct + // should come from MRWB + i_oha_val_init.AISS_HANG_DETECT_TIMER_SEL = 9; // oha_mode_reg (11:14) - 0=1ms, 1=2ms, 3=4ms, ...9=512ms. others illegal + i_oha_val_init.PPT_TIMER_SELECT = 3; // activity_sample_mode_reg (36:37) 0=0.25us, 1=0.5us, 2=1us, and 3=2us + i_oha_val_init.LAD_ENTRY = 16; + i_oha_val_init.LAD_EXIT = 17; - //FAPI_DBG("*************************************"); - FAPI_INF("Calling: p8_oha_init_reset"); - //FAPI_DBG("*************************************"); - rc = p8_oha_init_reset( i_target, i_mode); + rc=p8_oha_init_init(i_target, i_oha_val_init); + if (rc) + { + FAPI_ERR(" p8_oha_init_init failed. With rc = 0x%x", (uint32_t)rc); + return rc; + } - if (rc) { - FAPI_ERR(" p8_oha_init_reset failed. With rc = 0x%x", (uint32_t)rc); return rc; - } + } + else if ( i_mode == PM_RESET ) + { + + FAPI_INF("<p8_oha_init> : MODE: RESET Calling p8_oha_init_reset"); - } else { - //FAPI_DBG("*************************************"); - FAPI_ERR("Unknown mode passed to p8_oha_init. Mode %x ....\n", i_mode); - FAPI_SET_HWP_ERROR(rc, RC_PROC_OHA_CODE_BAD_MODE); - //FAPI_DBG("*************************************"); - }; + //Declare parms struct + //TODO RTC: 71328 - hack to indicate unused + struct_i_oha_val_init_type __attribute__((unused)) i_oha_val_init; + //Assign values to parms in struct + // should come from MRWB + i_oha_val_init.AISS_HANG_DETECT_TIMER_SEL = 9; // oha_mode_reg (11:14) - 0=1ms, 1=2ms, 3=4ms, ...9=512ms. others illegal + i_oha_val_init.PPT_TIMER_SELECT = 3; // activity_sample_mode_reg (36:37) 0=0.25us, 1=0.5us, 2=1us, and 3=2us + i_oha_val_init.LAD_ENTRY = 16; + i_oha_val_init.LAD_EXIT = 17; + // ****************************************************************** + /// \todo should this values be attributes?? The get those attributes here + // FAPI_ATTR_GET("IVRMS_ENABLED", i_target,(unit8_t) ivrms_enabled); + + rc = p8_oha_init_reset( i_target, i_mode); + if (rc) + { + FAPI_ERR(" p8_oha_init_reset failed. With rc = 0x%x", (uint32_t)rc); + return rc; + } + } + else + { - return rc; + FAPI_ERR("<p8_oha_init> : Unknown mode %x ....\n", i_mode); + FAPI_SET_HWP_ERROR(rc, RC_PROC_OHA_CODE_BAD_MODE); -} + }; + return rc; + +} +//------------------------------------------------------------------------------ +// OHA Config Function +//------------------------------------------------------------------------------ fapi::ReturnCode -p8_oha_init_config(const fapi::Target& i_target) +p8_oha_init_config(const fapi::Target& i_target) { - fapi::ReturnCode rc; - + fapi::ReturnCode rc; + uint8_t attr_pm_aiss_timeout; uint32_t attr_pm_power_proxy_trace_timer; uint32_t attr_pm_ppt_timer_tick; uint32_t attr_pm_ppt_timer_match_value; + + FAPI_INF("<p8_oha_init> : Executing config ....\n"); + + // ****************************************************************** + // Get Attributes for OHA Timers Delay + // ****************************************************************** + // set defaults if not available + + attr_pm_ppt_timer_tick = 2; // Default 2: 1us + + /// \todo PLAT attr ... not there yet + attr_pm_aiss_timeout = 5; // Default 5: 32ms + // rc = FAPI_ATTR_GET(ATTR_PM_AISS_TIMEOUT, &i_target, attr_pm_aiss_timeout); + // if (rc) + // { + // FAPI_ERR("fapiGetAttribute of ATTR_PM_AISS_TIMEOUT with rc = 0x%x", (uint32_t)rc); + // return rc; + // } + // + + /// \todo PLAT attr ... not there yet + attr_pm_power_proxy_trace_timer = 64000; // Default 1us,,, 32us...64ms + // rc = FAPI_ATTR_GET(ATTR_PM_POWER_PROXY_TRACE_TIMER, &i_target, attr_pm_power_proxy_trace_timer); + // if (rc) + //..{ + // FAPI_ERR("fapiGetAttribute of ATTR_PM_POWER_PROXY_TRACE_TIMER with rc = 0x%x", (uint32_t)rc); + // return rc; + // } + // ****************************************************************** + // Calculate OHA timer settings + // ****************************************************************** - // ****************************************************************** - // Get Attributes for OHA Timers Delay - // ****************************************************************** - // set defaults if not available - - attr_pm_ppt_timer_tick = 2; // Default 2: 1us - - - - /// \todo PLAT attr ... not there yet - attr_pm_aiss_timeout = 5; // Default 5: 32ms - // rc = FAPI_ATTR_GET(ATTR_PM_AISS_TIMEOUT, &i_target, attr_pm_aiss_timeout); - // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_AISS_TIMEOUT with rc = 0x%x", (uint32_t)rc); return rc; } - // - - /// \todo PLAT attr ... not there yet - attr_pm_power_proxy_trace_timer = 64000; // Default 1us,,, 32us...64ms - // rc = FAPI_ATTR_GET(ATTR_PM_POWER_PROXY_TRACE_TIMER, &i_target, attr_pm_power_proxy_trace_timer); - // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_POWER_PROXY_TRACE_TIMER with rc = 0x%x", (uint32_t)rc); return rc; } - - - - - // ****************************************************************** - // Calculate OHA timer settings - // ****************************************************************** - //FAPI_DBG("*************************************"); - FAPI_DBG("Calculate OHA timer settings"); - //FAPI_DBG("*************************************"); - //FAPI_DBG("*************************************"); - FAPI_DBG("Calculate:"); - FAPI_DBG(" ATTR_PM_PPT_TIMER_MATCH_VALUE"); - FAPI_DBG(" ATTR_PM_PPT_TIMER_TICK"); - FAPI_DBG("using:"); - FAPI_DBG(" ATTR_PM_POWER_PROXY_TRACE_TIMER"); - //FAPI_DBG("**************************************************************************"); - FAPI_DBG(" Set ATTR_PM_AISS_TIMEOUT to 5 (32ms)"); - //FAPI_DBG("**************************************************************************"); - - - - - // - attr_pm_ppt_timer_match_value = attr_pm_power_proxy_trace_timer / 32 ; //time in us / 32us - - - - - - FAPI_DBG("*************************************"); - FAPI_DBG("attr_pm_aiss_timeout : %X", attr_pm_aiss_timeout); - FAPI_DBG("attr_pm_ppt_timer_match_value : %X", attr_pm_ppt_timer_match_value); - FAPI_DBG("*************************************"); - - - // ****************************************************************** - // Set Attributes for OHA timers - // ****************************************************************** - - // rc = FAPI_ATTR_SET(ATTR_PM_AISS_TIMEOUT, &i_target, attr_pm_aiss_timeout); - // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_AISS_TIMEOUT with rc = 0x%x", (uint32_t)rc); return; } + FAPI_DBG("<p8_oha_init> : Calculate OHA timer settings"); + FAPI_DBG("<p8_oha_init> : Calculate:"); + FAPI_DBG("<p8_oha_init> : ATTR_PM_PPT_TIMER_MATCH_VALUE"); + FAPI_DBG("<p8_oha_init> : ATTR_PM_PPT_TIMER_TICK"); + FAPI_DBG("<p8_oha_init> : using:"); + FAPI_DBG("<p8_oha_init> : ATTR_PM_POWER_PROXY_TRACE_TIMER"); + + FAPI_DBG("<p8_oha_init> : Set ATTR_PM_AISS_TIMEOUT to 5 (32ms)"); + attr_pm_ppt_timer_match_value = attr_pm_power_proxy_trace_timer / 32 ; //time in us / 32us - rc = FAPI_ATTR_SET(ATTR_PM_PPT_TIMER_MATCH_VALUE, &i_target, attr_pm_ppt_timer_match_value); - if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_PPT_TIMER_MATCH_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } - rc = FAPI_ATTR_SET(ATTR_PM_PPT_TIMER_TICK, &i_target, attr_pm_ppt_timer_tick); - if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_PPT_TIMER_TICK with rc = 0x%x", (uint32_t)rc); return rc; } + FAPI_DBG("<p8_oha_init> : attr_pm_aiss_timeout : %X", attr_pm_aiss_timeout); + FAPI_DBG("<p8_oha_init> : attr_pm_ppt_timer_match_value : %X", attr_pm_ppt_timer_match_value); + // ****************************************************************** + // Set Attributes for OHA timers + // ****************************************************************** - return rc; + // rc = FAPI_ATTR_SET(ATTR_PM_AISS_TIMEOUT, &i_target, attr_pm_aiss_timeout); + // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_AISS_TIMEOUT with rc = 0x%x", (uint32_t)rc); return; } + rc = FAPI_ATTR_SET(ATTR_PM_PPT_TIMER_MATCH_VALUE, &i_target, attr_pm_ppt_timer_match_value); + if (rc) + { + FAPI_ERR("fapiSetAttribute of ATTR_PM_PPT_TIMER_MATCH_VALUE with rc = 0x%x", (uint32_t)rc); + return rc; + } + + rc = FAPI_ATTR_SET(ATTR_PM_PPT_TIMER_TICK, &i_target, attr_pm_ppt_timer_tick); + if (rc) + { + FAPI_ERR("fapiSetAttribute of ATTR_PM_PPT_TIMER_TICK with rc = 0x%x", (uint32_t)rc); + return rc; + } + + FAPI_INF(""); + FAPI_INF("<p8_oha_init> : Finished config ....\n"); + + return rc; + } //end CONFIG - - - +//------------------------------------------------------------------------------ +// OHA Init Function +//------------------------------------------------------------------------------ fapi::ReturnCode -p8_oha_init_init(const fapi::Target& i_target, struct_i_oha_val_init_type i_oha_val_init) +p8_oha_init_init(const fapi::Target& i_target, struct_i_oha_val_init_type i_oha_val_init) { fapi::ReturnCode rc; - - ecmdDataBufferBase data(64); - ecmdDataBufferBase mask(64); - - std::vector<fapi::Target> l_chiplets; - std::vector<Target>::iterator itr; - - - // Variables -//TODO RTC: 68461 - refresh procedures uint32_t c = 0 ; uint32_t l_rc; + + ecmdDataBufferBase data(64); + ecmdDataBufferBase mask(64); + + std::vector<fapi::Target> l_exChiplets; +// std::vector<Target>::iterator itr; + uint8_t l_functional = 0; + uint8_t l_ex_number = 0; + + uint8_t attr_pm_aiss_timeout; + uint32_t attr_pm_tod_pulse_count_match_val = 1024; + uint32_t attr_pm_ppt_timer_tick; + uint32_t attr_pm_ppt_timer_match_value; + + FAPI_INF("<p8_oha_init> : Executing init ....\n"); - - uint8_t attr_pm_aiss_timeout; - uint32_t attr_pm_ppt_timer_tick; - uint32_t attr_pm_ppt_timer_match_value; - - FAPI_INF(""); - //FAPI_DBG("********* ******************* *********"); - FAPI_INF("Executing ....p8_oha_init"); - //FAPI_DBG("********* ******************* *********"); - FAPI_INF(""); - - - - - rc = fapiGetChildChiplets (i_target, TARGET_TYPE_EX_CHIPLET, l_chiplets); if (rc) return rc; - FAPI_DBG(" chiplet vector size => %u", l_chiplets.size()); - - - - - //FAPI_DBG("***********************************************"); - FAPI_INF(" Welcome to p8_oha_init INIT-mode "); - //FAPI_DBG("***********************************************"); - - - - // ****************************************************************** - // Get Attributes for OHA Timers Delay + // ****************************************************************** + // Get Attributes for OHA Timers Delay + // ****************************************************************** + #ifndef ATTRIBUTES_AVAIL // ****************************************************************** - #ifndef ATTRIBUTES_AVAIL - // ****************************************************************** - // set defaults if not available - attr_pm_ppt_timer_tick = 2; // Default 2: 1us - attr_pm_ppt_timer_match_value = 0x7FF; // Default 0x7FF: 64ms - attr_pm_aiss_timeout = 5; // Default 5: 32ms - #else -/// \todo PLAT attr ... not there yet - //rc = FAPI_ATTR_GET(ATTR_PM_AISS_TIMEOUT, &i_target, attr_pm_aiss_timeout); - //if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_AISS_TIMEOUT with rc = 0x%x", (uint32_t)rc); return rc; } - rc = FAPI_ATTR_GET(ATTR_PM_PPT_TIMER_TICK, &i_target, attr_pm_ppt_timer_tick); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PPT_TIMER_TICK with rc = 0x%x", (uint32_t)rc); return rc; } - rc = FAPI_ATTR_GET(ATTR_PM_PPT_TIMER_MATCH_VALUE, &i_target, attr_pm_ppt_timer_match_value); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PPT_TIMER_MATCH_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } - #endif - - - + // set defaults if not available + attr_pm_ppt_timer_tick = 2; // Default 2: 1us + attr_pm_ppt_timer_match_value = 0x7FF; // Default 0x7FF: 64ms + attr_pm_aiss_timeout = 5; // Default 5: 32ms + #else + /// \todo PLAT attr ... not there yet + //rc = FAPI_ATTR_GET(ATTR_PM_AISS_TIMEOUT, &i_target, attr_pm_aiss_timeout); + //if (rc) + //{ + // FAPI_ERR("fapiGetAttribute of ATTR_PM_AISS_TIMEOUT with rc = 0x%x", (uint32_t)rc); + // return rc; + //} + + rc = FAPI_ATTR_GET(ATTR_PM_PPT_TIMER_TICK, &i_target, attr_pm_ppt_timer_tick); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_PM_PPT_TIMER_TICK with rc = 0x%x", (uint32_t)rc); + return rc; + } + rc = FAPI_ATTR_GET(ATTR_PM_PPT_TIMER_MATCH_VALUE, &i_target, attr_pm_ppt_timer_match_value); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_PM_PPT_TIMER_MATCH_VALUE with rc = 0x%x", (uint32_t)rc); + return rc; + } + #endif + // ****************************************************************** // initialize all oha_reg with scan-zero values upfront // ****************************************************************** - - - - for (itr = l_chiplets.begin(); itr != l_chiplets.end(); itr++){ - - - // HACK - FAPI_DBG("Content Loop Variable C : %d ", c); - - - - // ****************************************************************** - // AISS hang timer setup - // ****************************************************************** - // ****************************************************************** - - // - set aiss_timeout to max time - // ****************************************************************** - //FAPI_DBG("**********************************************"); - FAPI_INF(" Setup aiss hang time in oha_mode_reg 1002000D"); - //FAPI_DBG("**********************************************"); - - // Read register content - rc = fapiGetScom( (*itr), EX_OHA_MODE_REG_RWx1002000D , data ); - if (rc) {FAPI_ERR("fapiGetScom(EX_OHA_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - FAPI_DBG ("Content of EX_OHA_MODE_REG_0x1002000D : %016llX", data.getDoubleWord(0)); - - - - - //data.flushTo0(); - l_rc = data.insertFromRight(attr_pm_aiss_timeout ,11,4); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - rc = fapiPutScom( (*itr), EX_OHA_MODE_REG_RWx1002000D , data ); - if (rc) { - FAPI_ERR("fapiPutScom(EX_OHA_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } - - - - - // ****************************************************************** - // Low Activity Detect (LAD) setup - // ****************************************************************** - // ****************************************************************** - // - enable LAD - // - set LAD for entry - // - set LAD for exit - // ****************************************************************** - //FAPI_DBG("**********************************************************************************************"); - FAPI_INF(" Setup Low Activity Detect (LAD) in oha_low_activity_detect_mode_reg 10020003, but NOT ENABLED"); - //FAPI_DBG("**********************************************************************************************"); - - // Read register content - //if (VERBOSE) { - rc = fapiGetScom( (*itr), EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003 , data ); - if (rc) { FAPI_ERR("fapiGetScom(EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - FAPI_DBG(" Pre write content of EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003 : %016llX", data.getDoubleWord(0)); - //} - - // - l_rc = data.setByte(0, i_oha_val_init.LAD_ENTRY); // 16 - l_rc |= data.setByte(1, i_oha_val_init.LAD_EXIT); // 17 - l_rc |= data.shiftRight(1); // LAD entry/exit starts at bit 1 - l_rc |= data.clearBit(0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - //FAPI_DBG(" !!!!!!!!!!!!!!!!!!!!!!returncode : %d", rc); - - - - - - rc = fapiPutScom((*itr), EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003 , data ); - if (rc) { - FAPI_ERR("fapiGetScom(EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } - - // if debug mode read back - //if (VERBOSE) { - // rc = fapiGetScom((*itr), EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003, data); if (rc) return rc; - // FAPI_DBG(" Post write content of EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003 : %016llX", data.getDoubleWord(0)); - //} - FAPI_INF ("Done LAD setup. LAD Disabled " ); - - - - // ****************************************************************** - // Power Proxy Trace (PPT) setup - // ****************************************************************** - // ****************************************************************** - // - set ppt_timer_select - // - set ppt_trace_timer_match_val - // ****************************************************************** - //FAPI_DBG("********************************************************************************"); - FAPI_INF(" Setup Power Proxy Trace (PPT) in oha_activity_sample_mode_reg 10020000"); - //FAPI_DBG("********************************************************************************"); - - // Read register content - rc = fapiGetScom( (*itr), EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000 , data ); - if (rc) { - FAPI_ERR("fapiGetScom(EX_OHA_ACTIVITY_SAMPLE_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } - FAPI_DBG(" Pre write content of EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000 : %016llX", data.getDoubleWord(0)); - - - // set ppt_int_timer_select to longest interval "11" = 2us - //l_rc = data.setBit(36); - //if (l_rc) { FAPI_ERR("Bit operation failed."); FAPI_SET_HWP_ERROR(rc, RC_PROC_OHA_CODE_BITOP_FAILED); } - //l_rc = data.setBit(37); - //if (l_rc) { FAPI_ERR("Bit operation failed."); FAPI_SET_HWP_ERROR(rc, RC_PROC_OHA_CODE_BITOP_FAILED); } - - l_rc = data.insertFromRight(attr_pm_ppt_timer_match_value ,24,11); - l_rc |= data.insertFromRight(attr_pm_ppt_timer_tick ,36,2); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - - - rc = fapiPutScom((*itr), EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000 , data ); - if (rc) { - FAPI_ERR("fapiGetScom(EX_OHA_ACTIVITY_SAMPLE_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } - - // if debug mode read back - //if (VERBOSE) { - rc = fapiGetScom((*itr), EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000, data); if (rc) return rc; - FAPI_DBG(" Post write content of EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000 : %016llX", data.getDoubleWord(0)); - //} - FAPI_INF ("Done PPT timer setup." ); + + rc = fapiGetChildChiplets ( i_target, + TARGET_TYPE_EX_CHIPLET, + l_exChiplets, + TARGET_STATE_FUNCTIONAL); + if (rc) + { + FAPI_ERR("Error from fapiGetChildChiplets!"); + return rc; + } + FAPI_DBG("<p8_oha_init> : Number of chiplets => %u", l_exChiplets.size()); + + // Iterate through the returned chiplets + //for (itr = l_exChiplets.begin(); itr != l_exChiplets.end(); itr++) + for (uint8_t c=0; c < l_exChiplets.size(); c++) + { + // Determine if it's functional + //rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, itr, l_functional); + rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_exChiplets[c], l_functional); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL error"); + break; + } + + // With TARGET_STATE_FUNCTIONAL above, this check may be redundant + if ( l_functional ) + { + // Get the core number + //rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, itr, c); + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[c], l_ex_number); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS error"); + break; + } + + FAPI_DBG("<p8_oha_init> : Processing core : %d ", l_ex_number); + + // ****************************************************************** + // AISS hang timer setup + // ****************************************************************** + // - set aiss_timeout to max time + // ****************************************************************** + //FAPI_DBG("**********************************************"); + FAPI_INF(" Setup aiss hang time in oha_mode_reg 1002000D"); + //FAPI_DBG("**********************************************"); + + // Read register content + //rc = fapiGetScom( (*itr), EX_OHA_MODE_REG_RWx1002000D , data ); + rc = fapiGetScom( l_exChiplets[c], EX_OHA_MODE_REG_RWx1002000D , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(EX_OHA_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); + return rc; + } + + FAPI_DBG ("Content of EX_OHA_MODE_REG_0x1002000D : %016llX", data.getDoubleWord(0)); + + //data.flushTo0(); + l_rc = data.insertFromRight(attr_pm_aiss_timeout ,11,4); + l_rc |= data.insertFromRight(attr_pm_tod_pulse_count_match_val ,17,14); + if (l_rc) + { + FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); + return rc; + } + + // rc = fapiPutScom( (*itr), EX_OHA_MODE_REG_RWx1002000D , data ); + rc = fapiPutScom( l_exChiplets[c], EX_OHA_MODE_REG_RWx1002000D , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(EX_OHA_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } + + + // ****************************************************************** + // Low Activity Detect (LAD) setup + // ****************************************************************** + // ****************************************************************** + // - enable LAD + // - set LAD for entry + // - set LAD for exit + // ****************************************************************** + //FAPI_DBG("**********************************************************************************************"); + FAPI_INF(" Setup Low Activity Detect (LAD) in oha_low_activity_detect_mode_reg 10020003, but NOT ENABLED"); + //FAPI_DBG("**********************************************************************************************"); + + // Read register content + // rc = fapiGetScom( (*itr), EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003 , data ); + rc = fapiGetScom( l_exChiplets[c], EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003) failed. With rc = 0x%x", (uint32_t)rc); + return rc; + } + FAPI_DBG(" Pre write content of EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003 : %016llX", data.getDoubleWord(0)); + + l_rc = data.setByte(0, i_oha_val_init.LAD_ENTRY); // 16 + l_rc |= data.setByte(1, i_oha_val_init.LAD_EXIT); // 17 + l_rc |= data.shiftRight(1); // LAD entry/exit starts at bit 1 + l_rc |= data.clearBit(0); + if (l_rc) + { + FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); + rc.setEcmdError(l_rc); + return rc; + } + + // rc = fapiPutScom((*itr), EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003 , data ); + rc = fapiPutScom( l_exChiplets[c], EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); + return rc; + } + + FAPI_INF ("Done LAD setup. LAD Disabled " ); + + // ****************************************************************** + // Power Proxy Trace (PPT) setup + // ****************************************************************** + // ****************************************************************** + // - set ppt_timer_select + // - set ppt_trace_timer_match_val + // ****************************************************************** + //FAPI_DBG("********************************************************************************"); + FAPI_INF(" Setup Power Proxy Trace (PPT) in oha_activity_sample_mode_reg 10020000"); + //FAPI_DBG("********************************************************************************"); + + // Read register content + // rc = fapiGetScom( (*itr), EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000 , data ); + rc = fapiGetScom( l_exChiplets[c], EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(EX_OHA_ACTIVITY_SAMPLE_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); + return rc; + } + FAPI_DBG(" Pre write content of EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000 : %016llX", data.getDoubleWord(0)); + + + // set ppt_int_timer_select to longest interval "11" = 2us + //l_rc = data.setBit(36); + //if (l_rc) + //{ + // FAPI_ERR("Bit operation failed."); + // FAPI_SET_HWP_ERROR(rc, RC_PROC_OHA_CODE_BITOP_FAILED); + //} + //l_rc = data.setBit(37); + //if (l_rc) + //{ + // FAPI_ERR("Bit operation failed."); + // FAPI_SET_HWP_ERROR(rc, RC_PROC_OHA_CODE_BITOP_FAILED); + //} + + l_rc = data.insertFromRight(attr_pm_ppt_timer_match_value ,24,11); + l_rc |= data.insertFromRight(attr_pm_ppt_timer_tick ,36,2); + if (l_rc) + { + FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); + rc.setEcmdError(l_rc); + return rc; + } + + // rc = fapiPutScom((*itr), EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000 , data ); + rc = fapiPutScom( l_exChiplets[c], EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(EX_OHA_ACTIVITY_SAMPLE_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); + return rc; + } + + FAPI_INF ("<p8_oha_init> : Done PPT timer setup." ); + } } + + FAPI_INF("<p8_oha_init> : Finished init ....\n"); - - + return rc; - + } //end INIT - -ReturnCode +//------------------------------------------------------------------------------ +// OHA Reset Function +//------------------------------------------------------------------------------ +fapi::ReturnCode p8_oha_init_reset(const Target &i_target, uint32_t i_mode) { - ReturnCode rc; - -//std::string PROCEDURE = "p8_oha_init"; // procedure name -//std::string REVISION = "$Revision: 1.3 $"; // procedure CVS revision - - - ecmdDataBufferBase data(64); - ecmdDataBufferBase mask(64); - - std::vector<fapi::Target> l_chiplets; - std::vector<Target>::iterator itr; - - - // Variables -//TODO RTC: 68461 - refresh procedures uint32_t c = 0 ; - uint32_t l_rc; - - FAPI_DBG(""); - //FAPI_DBG("********* ******************* *********"); - FAPI_INF("Executing p8_oha_init..."); - //FAPI_DBG("********* ******************* *********"); - FAPI_DBG(""); - - - - - - - // rc = fapiGetExistingChiplets (i_target, TARGET_TYPE_EX_CHIPLET, l_chiplets); if (rc) return rc; - rc = fapiGetChildChiplets (i_target, TARGET_TYPE_EX_CHIPLET, l_chiplets); if (rc) return rc; - FAPI_DBG(" chiplet vector size => %u", l_chiplets.size()); - - - - - - - //FAPI_DBG("***********************************************"); - FAPI_INF(" Welcome to p8_oha_init_reset "); - //FAPI_DBG("***********************************************"); - - -for (itr = l_chiplets.begin(); itr != l_chiplets.end(); itr++){ - - - // HACK - FAPI_DBG("Content Loop Variable C : %d ", c); - - - + fapi::ReturnCode rc; + uint32_t l_rc = 0; + + ecmdDataBufferBase data(64); + ecmdDataBufferBase mask(64); + + +// std::vector<Target>::iterator itr; + std::vector<fapi::Target> l_exChiplets; + uint8_t l_functional = 0; + uint8_t l_ex_number = 0; + + + FAPI_INF("<p8_oha_init> : Executing reset ....\n");; + + rc = fapiGetChildChiplets ( i_target, + TARGET_TYPE_EX_CHIPLET, + l_exChiplets, + TARGET_STATE_FUNCTIONAL); + if (rc) + { + FAPI_ERR("Error from fapiGetChildChiplets!"); + return rc; + } + FAPI_DBG("<p8_oha_init> : Number of chiplets => %u", l_exChiplets.size()); + + // Iterate through the returned chiplets + //for (itr = l_exChiplets.begin(); itr != l_exChiplets.end(); itr++) + for (uint8_t c=0; c < l_exChiplets.size(); c++) + { + // Determine if it's functional + //rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, itr, l_functional); + rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_exChiplets[c], l_functional); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL error"); + break; + } + + // With TARGET_STATE_FUNCTIONAL above, this check may be redundant + if ( l_functional ) + { + // Get the core number + //rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, itr, c); + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[c], l_ex_number); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS error"); + break; + } + + FAPI_DBG("<p8_oha_init> : Processing core : %d ", l_ex_number); + + + + // -------------------------------------- + // Check if SBE code has already cleared the OHA override. + // As chiplets may be enabled but offline (eg in Winkle) + // treat SCOM errors as off-line (eg skip it). If online + // and set, clear the override. + + // GSS: removed as Cronus always puts a message out of (PCB_OFFLINE) + // even though this code is meant to handle it. As this messge + // can cause confusion in the lab, the check is being removed. + bool oha_accessible = true; + uint32_t fsierror = 0; + const uint32_t IDLE_STATE_OVERRIDE_EN = 6; + + + rc = fapiGetScom(l_exChiplets[c], EX_OHA_MODE_REG_RWx1002000D, data); + if(!rc.ok()) + { + FAPI_ERR("Error reading EX_OHA_MODE_REG_RWx1002000D . Further debugging"); + rc = fapiGetCfamRegister( i_target, CFAM_FSI_STATUS_0x00001007, data ); + if(!rc.ok()) + { + FAPI_ERR("Error reading CFAM FSI Status Register"); + break; + } + FAPI_INF( "CFAM_FSI_STATUS_0x00001007: 0x%X", data.getWord(0)); + l_rc |= data.extractToRight( &fsierror, 17, 3 ); + if ( l_rc ) + { + rc.setEcmdError(l_rc); + break; + } + if (fsierror == PIB_OFFLINE_ERROR) + { + FAPI_INF( "Chiplet offline error detected. Skipping OHA Override clearing"); + oha_accessible = false; + } + else + { + FAPI_ERR("Scom reading OHA_MODE"); + break; + } + } + // Process if OHA accessible. + if (oha_accessible) + { + if (data.isBitSet(IDLE_STATE_OVERRIDE_EN)) + { + + FAPI_INF("\tClear the OHA Idle State Override for EX %x", l_ex_number); + l_rc |= data.clearBit(IDLE_STATE_OVERRIDE_EN); + if (l_rc) + { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_rc); + rc.setEcmdError(l_rc); + break; + } + + rc = fapiPutScom(l_exChiplets[c], EX_OHA_MODE_REG_RWx1002000D, data); + if(!rc.ok()) + { + FAPI_ERR("Scom error writing OHA_MODE"); + break; + } + } + } + // End of check removal + + + + + + + FAPI_INF("Reset AISS "); + FAPI_INF("Write to register OHA_ARCH_IDLE_STATE_REG "); + + // rc = fapiGetScom( (*itr), EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011, data); + rc = fapiGetScom( l_exChiplets[c], EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011, data); + if (rc) + { + FAPI_ERR("fapiGetScom(EX_OHA_ARCH_IDLE_STATE_REG) failed. With rc = 0x%x", (uint32_t)rc); + return rc; + } + FAPI_DBG(" Pre write content of EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 : %016llX", data.getDoubleWord(0) ); + + l_rc = data.setBit(9); //reset_idle_state_sequencer_in ... reset pulse gets generated. Not unsetting required + if (l_rc) + { + FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); + rc.setEcmdError(l_rc); + return rc; + } + + // rc = fapiPutScom((*itr), EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 , data ); + rc = fapiPutScom( l_exChiplets[c], EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(EX_OHA_ARCH_IDLE_STATE_REG) failed. With rc = 0x%x", (uint32_t)rc); + return rc; + } + + // rc = fapiGetScom( (*itr), EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011, data); + rc = fapiGetScom( l_exChiplets[c], EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011, data); + if (rc) return rc; + FAPI_DBG(" Post write content of EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 : %016llX", data.getDoubleWord(0) ); + //} + if (rc) + { + FAPI_ERR("fapiGetScom(EX_OHA_ARCH_IDLE_STATE_REG) failed. With rc = 0x%x", (uint32_t)rc); + return rc; + } + } + else + { + FAPI_INF("<p8_oha_init> : Skipping non-functional core. Number unknown at this time!"); + } + } + + FAPI_INF("<p8_oha_init> : Finished reset ....\n"); - - //FAPI_DBG("*************************************"); - FAPI_INF("Reset AISS "); - FAPI_INF("Write to register OHA_ARCH_IDLE_STATE_REG "); - //FAPI_DBG("*************************************"); - - - - rc = fapiGetScom( (*itr), EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011, data); - if (rc) { - FAPI_ERR("fapiGetScom(EX_OHA_ARCH_IDLE_STATE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } - FAPI_DBG(" Pre write content of EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 : %016llX", data.getDoubleWord(0) ); - - l_rc = data.setBit(9); //reset_idle_state_sequencer_in ... reset pulse gets generated. Not unsetting required - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - rc = fapiPutScom((*itr), EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 , data ); - if (rc) { - FAPI_ERR("fapiPutScom(EX_OHA_ARCH_IDLE_STATE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } - - // if debug mode read back - //if (VERBOSE) { - rc = fapiGetScom( (*itr), EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011, data); if (rc) return rc; - FAPI_DBG(" Post write content of EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 : %016llX", data.getDoubleWord(0) ); - //} - if (rc) { - FAPI_ERR("fapiGetScom(EX_OHA_ARCH_IDLE_STATE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } - - - - - - -} - - - - FAPI_INF(""); - FAPI_INF("Executing proc_OHA_init ....\n"); - - - return rc; + return rc; } - - - - - - - - } //end extern C - + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.H index 687320f1c..558c923e2 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.H +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.H @@ -20,24 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ - +// $Id: p8_oha_init.H,v 1.2 2012/11/27 18:11:53 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_oha_init.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -52,13 +36,9 @@ //------------------------------------------------------------------------------ // - - // function pointer typedef definition for HWP call support typedef fapi::ReturnCode (*p8_oha_init_FP_t) (const fapi::Target&, uint32_t); - - extern "C" { @@ -73,7 +53,6 @@ extern "C" fapi::ReturnCode p8_oha_init (const fapi::Target& i_target, uint32_t i_mode); - } diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pba_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pba_init.C index 6c4048ace..aa1b4dd8c 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pba_init.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pba_init.C @@ -20,25 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_pba_init.C,v 1.7 2012/10/25 11:59:45 kgungl Exp $ -// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pba_init.C,v $ +// $Id: p8_pba_init.C,v 1.11 2013/04/01 04:11:57 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pba_init.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -89,13 +72,11 @@ #include <fapi.H> #include "p8_scom_addresses.H" #include "p8_pba_init.H" -#include "pba_firmware_register.H" #include "p8_pm.H" -#include <ecmdDataBufferBase.H> // get the constants from here -// #include "pgp_pba.h" -// #include "pgp_common.h" +#include "pgp_pba.h" +#include "pgp_common.h" extern "C" { @@ -104,89 +85,6 @@ using namespace fapi; // ---------------------------------------------------------------------- // Constant definitions // ---------------------------------------------------------------------- -// constant definitions are currently in the *.h files, need to consolidate? - -// move the following to p8_scom_addresses.H -// CONST_UINT64_T( PBAXSNDTX_00064020 , ULL(0x00064020) ); -// CONST_UINT64_T( PBAXCFG_00064021 , ULL(0x00064021) ); -// CONST_UINT64_T( PBAXSHBR0_00064026 , ULL(0x00064026) ); -// CONST_UINT64_T( PBAXSHBR1_0006402A , ULL(0x0006402A) ); - - // from "pgp_pba.h" "pgp_common.h" -//////////////////////////////////// -// Macros for fields of PBA_SLVCTLn -//////////////////////////////////// - -// PBA write Ttypes - -#define PBA_WRITE_TTYPE_DMA_PR_WR 0x0 /// DMA Partial Write -#define PBA_WRITE_TTYPE_LCO_M 0x1 /// L3 LCO, Tsize denotes chiplet -#define PBA_WRITE_TTYPE_ATOMIC_RMW 0x2 /// Atomic operations -#define PBA_WRITE_TTYPE_CACHE_INJECT 0x3 /// ? -#define PBA_WRITE_TTYPE_CI_PR_W 0x4 /// Cache-inhibited partial write for Centaur putscom(). - -#define PBA_WRITE_TTYPE_DC PBA_WRITE_TTYPE_DMA_PR_WR // Don't care - -#define PBA_OCI_REGION 0 - -#define PBA_BCE_OCI_TRANSACTION_32_BYTES 0 -#define PBA_BCE_OCI_TRANSACTION_64_BYTES 1 -#define PBA_BCE_OCI_TRANSACTION_8_BYTES 2 - -#define PBA_OCI_MARKER_BASE 0x40070000 - -#define PBA_SLAVE_PORE_GPE 0 /* GPE0/1, but only 1 can access mainstore */ -#define PBA_SLAVE_OCC 1 /* 405 I- and D-cache */ -#define PBA_SLAVE_PORE_SLW 2 -#define PBA_SLAVE_OCB 3 - -#define OCI_MASTER_ID_PORE_GPE 0 -#define OCI_MASTER_ID_PMC 1 -#define OCI_MASTER_ID_PBA 2 -#define OCI_MASTER_ID_UNUSED 3 -#define OCI_MASTER_ID_PORE_SLW 4 -#define OCI_MASTER_ID_OCB 5 -#define OCI_MASTER_ID_OCC_ICU 6 -#define OCI_MASTER_ID_OCC_DCU 7 - -// PBA write gather timeouts are defined in terms of the number of 'pulses'. A -// pulse occurs every 64 OCI cycles. The timing of the last write of a -// sequence is variable, so the timeout will occur somewhere between (N - 1) * -// 64 and N * 64 OCI cycles. If write gather timeouts are disabled, the PBA -// holds the data until some condition occurs that causes it to disgorge the -// data. Slaves using cache-inhibited partial write never gather write -// data. Note from spec. : "Write gather timeouts must NOT be disabled if -// multiple masters are enabled to write through the PBA". The only case -// where write gather timeouts will be disabled is for the IPL-time injection -// of data into the L3 caches. - -#define PBA_WRITE_GATHER_TIMEOUT_DISABLE 0x0 -#define PBA_WRITE_GATHER_TIMEOUT_2_PULSES 0x4 -#define PBA_WRITE_GATHER_TIMEOUT_4_PULSES 0x5 -#define PBA_WRITE_GATHER_TIMEOUT_8_PULSES 0x6 -#define PBA_WRITE_GATHER_TIMEOUT_16_PULSES 0x7 - -/// PBA write gather timeout don't care assignment -#define PBA_WRITE_GATHER_TIMEOUT_DC PBA_WRITE_GATHER_TIMEOUT_2_PULSES - - -// PBA read Ttype - -#define PBA_READ_TTYPE_CL_RD_NC 0x0 /// Cache line read -#define PBA_READ_TTYPE_CI_PR_RD 0x1 /// Cache-inhibited partial read for Centaur getscom(). - -/// PBA read TTYPE don't care assignment -#define PBA_READ_TTYPE_DC PBA_READ_TTYPE_CL_RD_NC - - -// PBA read prefetch options - -#define PBA_READ_PREFETCH_AUTO_EARLY 0x0 /// Aggressive prefetch -#define PBA_READ_PREFETCH_NONE 0x1 /// No prefetch -#define PBA_READ_PREFETCH_AUTO_LATE 0x2 /// Non-aggressive prefetch - -/// PBA read prefetch don't care assignment -#define PBA_READ_PREFETCH_DC PBA_READ_PREFETCH_NONE // ---------------------------------------------------------------------- @@ -197,15 +95,16 @@ using namespace fapi; // ---------------------------------------------------------------------- // local Function definitions / prototypes // ---------------------------------------------------------- -ReturnCode p8_pba_init_PM_CONFIG ( const Target& i_target ); -ReturnCode p8_pba_init_PM_INIT ( const Target& i_target ); -ReturnCode p8_pba_init_PM_RESET ( const Target& i_target ); +fapi::ReturnCode p8_pba_init_PM_CONFIG ( const Target& i_target ); +fapi::ReturnCode p8_pba_init_PM_INIT ( const Target& i_target ); +fapi::ReturnCode p8_pba_init_PM_RESET ( const Target& i_target ); -ReturnCode pba_slave_setup_init ( const Target& i_target ); -ReturnCode pba_slave_setup_reset ( const Target& i_target ); +fapi::ReturnCode pba_slave_setup_init ( const Target& i_target ); +fapi::ReturnCode pba_slave_setup_reset ( const Target& i_target ); +fapi::ReturnCode pba_slave_reset(const Target& i_target); - // from pgp_pba.h -int pba_slave_reset(int id); +// from pgp_pba.h +//int pba_slave_reset(int id); // ********************************************************************************************** @@ -213,412 +112,419 @@ int pba_slave_reset(int id); // function: // set the pba registers depending on "mode", no default mode // returns: fapi return codes -ReturnCode +fapi::ReturnCode p8_pba_init(const Target& i_target, uint64_t mode ) { -ReturnCode rc; -// calling the selected function from here + fapi::ReturnCode rc; + // calling the selected function from here - if (mode == PM_CONFIG) { - rc = p8_pba_init_PM_CONFIG(i_target); - } else { - if (mode == PM_INIT) { + if (mode == PM_CONFIG) + { + rc = p8_pba_init_PM_CONFIG(i_target); + } + else if (mode == PM_INIT) + { rc = p8_pba_init_PM_INIT(i_target); - } else { - if (mode == PM_RESET) { - rc = p8_pba_init_PM_RESET(i_target); - } else { - FAPI_SET_HWP_ERROR(rc,RC_P8_PBA_INIT_INCORRECT_MODE); - } // endif + } + else if (mode == PM_RESET) + { + rc = p8_pba_init_PM_RESET(i_target); + } + else + { + FAPI_ERR("Unknown mode passed to p8_pba_init. Mode %08llx ", mode); + FAPI_SET_HWP_ERROR(rc,RC_P8_PBA_INIT_INCORRECT_MODE); } // endif - } // endif - return rc; + + return rc; } // ********************************************************************************************** // ******************************************************** mode = PM_RESET ******************** -ReturnCode - p8_pba_init_PM_RESET(const Target& i_target) - { - - ReturnCode rc; - ecmdDataBufferBase data(64); - uint32_t l_rc; // local returncode - - - // if (mode == PM_RESET) { - FAPI_INF("mode = PM_RESET..\n"); - l_rc = data.setDoubleWord(0, 0x0); - if (l_rc) - { - FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; - } // end if - +fapi::ReturnCode +p8_pba_init_PM_RESET(const Target& i_target) +{ - // For reset phase, write these with 0x0 - // No content for config or init phase as all initialization is done by OCC FW - rc = fapiPutScom(i_target, PBA_BCDE_CTL_0x00064010 , data); - if (rc) - { - FAPI_ERR("fapiPutScom(PBA_BCDE_CTL_0x00064010 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_BCDE_CTL_0x00064010 \n "); - } // end if-else - - rc = fapiPutScom(i_target, PBA_BCDE_SET_0x00064011 , data); - if (rc) - { - FAPI_ERR("fapiPutScom( PBA_BCDE_SET_0x00064011 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_BCDE_SET_0x00064011 \n "); - } // end if-else - - rc = fapiPutScom(i_target, PBA_BCDE_STAT_0x00064012 , data); - if (rc) - { - FAPI_ERR("fapiPutScom( PBA_BCDE_STAT_0x00064012 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_BCDE_STAT_0x00064012 \n "); - } // end if-else - - rc = fapiPutScom(i_target, PBA_BCDE_PBADR_0x00064013 , data); - if (rc) - { - FAPI_ERR("fapiPutScom( PBA_BCDE_PBADR_0x00064013 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_BCDE_PBADR_0x00064013 \n "); - } - - rc = fapiPutScom(i_target, PBA_BCDE_OCIBAR_0x00064014 , data); - if (rc) - { - FAPI_ERR("fapiPutScom( PBA_BCDE_OCIBAR_0x00064014 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_BCDE_OCIBAR_0x00064014 \n "); - } - - rc = fapiPutScom(i_target, PBA_BCUE_CTL_0x00064015 , data); - if (rc) - { - FAPI_ERR("fapiPutScom( PBA_BCUE_CTL_0x0006401 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_BCUE_CTL_0x00064015 \n "); - } - - rc = fapiPutScom(i_target, PBA_BCUE_SET_0x00064016 , data); - if (rc) - { - FAPI_ERR("fapiPutScom( PBA_BCUE_SET_0x00064016 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_BCUE_SET_0x00064016 \n "); - } // end if-else - - rc = fapiPutScom(i_target, PBA_BCUE_STAT_0x00064017 , data); - if (rc) - { - FAPI_ERR("fapiPutScom(PBA_BCUE_STAT_0x00064017 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_BCUE_STAT_0x00064017 \n "); - } // end if-else - - rc = fapiPutScom(i_target, PBA_BCUE_PBADR_0x00064018 , data); - if (rc) - { - FAPI_ERR("fapiPutScom(PBA_BCUE_PBADR_0x00064018 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_BCUE_PBADR_0x00064018 \n "); - } // end if-else - - rc = fapiPutScom(i_target, PBA_BCUE_OCIBAR_0x00064019 , data); - if (rc) - { - FAPI_ERR("fapiPutScom( PBA_BCUE_OCIBAR_0x00064019 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_BCUE_OCIBAR_0x00064019 \n "); - } // end if-else - - // For reset, written with 0x0s to restore to fresh value. - rc = fapiPutScom(i_target, PBA_SLVCTL0_0x00064004 , data); - if (rc) - { - FAPI_ERR("fapiPutScom( PBA_SLVCTL0_0x00064004 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_SLVCTL0_0x0006400 \n "); - } // end if-else - - rc = fapiPutScom(i_target, PBA_SLVCTL1_0x00064005 , data); - if (rc) - { - FAPI_ERR("fapiPutScom( PBA_SLVCTL1_0x00064005 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_SLVCTL1_0x00064005 \n "); - } // end if-else - - rc = fapiPutScom(i_target, PBA_SLVCTL2_0x00064006 , data); - if (rc) - { - FAPI_ERR("fapiPutScom( PBA_SLVCTL2_0x00064006 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_SLVCTL2_0x00064006 \n "); - } // end if-else - - rc = fapiPutScom(i_target, PBA_SLVCTL3_0x00064007 , data); - if (rc) - { - FAPI_ERR("fapiPutScom( PBA_SLVCTL3_0x00064007 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_SLVCTL3_0x00064007 \n "); - } // end if-else - - // Clear the PBA FIR (Reset) only - l_rc = data.setDoubleWord(0, 0x0); - if (l_rc) - { - FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; - } // end if - rc = fapiPutScom(i_target, PBA_FIR_0x02010840 , data); - if (rc) - { - FAPI_ERR("fapiPutScom( PBA_FIR_0x02010840 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_DBG("Done with PBA_FIR_0x02010840 \n "); - } // end if-else - - // For reset, this register should be written with the value from figtree to restore the initial hardware state. - // Therefore fix this constant: - // For init, needs detailing for performance and/or CHSW enable/disable - // reset case - // data still 0 - rc = fapiPutScom(i_target, PBA_CONFIG_0x0201084B , data); - if (rc) - { - FAPI_ERR("fapiPutScom( PBA_CONFIG_0x0201084B ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with, PBA_CONFIG_0x0201084B \n "); - } // end if-else - - // pba slave register handling for PM_RESET - rc = pba_slave_setup_reset(i_target); - if (rc) - { - FAPI_ERR("pba_slave_setup_reset failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with, pba_slave_setup_reset \n "); - } // end if-else - - // For reset, written with 0x0s to restore to fresh value. - rc = fapiPutScom(i_target, PBA_ERR_RPT0_0x0201084C , data); - if (rc) - { - FAPI_ERR("fapiPutScom( PBA_ERR_RPT0_0x0201084C ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_ERR_RPT0_0x0201084C \n "); - } // end if-else - // the following operations are not required, keep this in mind, don't erase them here - // l_rc = fapiPutScom(i_target, PBA_ERR_RPT1_0x0201084D , data); - // if(l_rc) { FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_INIT_PUTSCOM_FAILED); return l_rc; } - // else {FAPI_INF("Done with PBA_ERR_RPT1_0x0201084D \n ") }; - - // l_rc = fapiPutScom(i_target, PBA_ERR_RPT2_0x0201084E , data); - // if(l_rc) { FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_INIT_PUTSCOM_FAILED); return l_rc; } - // else {FAPI_INF("Done with PBA_ERR_RPT2_0x0201084E \n ") }; - - - // The following apply to Reset mode ( - rc = fapiPutScom(i_target, PBA_SLVRST_0x00064001 , data); - if (rc) { FAPI_ERR("fapiPutScom( PBA_SLVRST_0x00064001 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - else {FAPI_INF("Done with PBA_SLVRST_0x00064001 \n "); } - - // last step: pba slave setup for reset - rc = pba_slave_setup_reset (i_target); - if (rc) { FAPI_ERR("fapi pba_slave_setup_reset failed. With rc = 0x%x", (uint32_t)rc); return rc; } - else {FAPI_INF("Done with fapi pba_slave_setup_reset \n "); } + fapi::ReturnCode rc; + ecmdDataBufferBase data(64); + uint32_t l_rc; // local returncode - return rc; + do + { + + // Reset each slave and wait for completion. + rc = pba_slave_reset(i_target); + if (rc) + { + FAPI_ERR("pba_slave_reset failed."); + break; + } + + + FAPI_INF("mode = PM_RESET..."); + l_rc = data.setDoubleWord(0, 0x0); + if (l_rc) + { + FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); + rc.setEcmdError(l_rc); + break; + } // end if + + + // For reset phase, write these with 0x0 + // No content for config or init phase as all initialization is done by OCC FW + rc = fapiPutScom(i_target, PBA_BCDE_CTL_0x00064010 , data); + if (rc) + { + FAPI_ERR("fapiPutScom(PBA_BCDE_CTL_0x00064010 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + rc = fapiPutScom(i_target, PBA_BCDE_SET_0x00064011 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_BCDE_SET_0x00064011 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + rc = fapiPutScom(i_target, PBA_BCDE_STAT_0x00064012 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_BCDE_STAT_0x00064012 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + rc = fapiPutScom(i_target, PBA_BCDE_PBADR_0x00064013 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_BCDE_PBADR_0x00064013 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + rc = fapiPutScom(i_target, PBA_BCDE_OCIBAR_0x00064014 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_BCDE_OCIBAR_0x00064014 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + rc = fapiPutScom(i_target, PBA_BCUE_CTL_0x00064015 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_BCUE_CTL_0x0006401 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + rc = fapiPutScom(i_target, PBA_BCUE_SET_0x00064016 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_BCUE_SET_0x00064016 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + rc = fapiPutScom(i_target, PBA_BCUE_STAT_0x00064017 , data); + if (rc) + { + FAPI_ERR("fapiPutScom(PBA_BCUE_STAT_0x00064017 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + rc = fapiPutScom(i_target, PBA_BCUE_PBADR_0x00064018 , data); + if (rc) + { + FAPI_ERR("fapiPutScom(PBA_BCUE_PBADR_0x00064018 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + rc = fapiPutScom(i_target, PBA_BCUE_OCIBAR_0x00064019 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_BCUE_OCIBAR_0x00064019 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + // For reset, written with 0x0s to restore to fresh value. + rc = fapiPutScom(i_target, PBA_SLVCTL0_0x00064004 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVCTL0_0x00064004 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + rc = fapiPutScom(i_target, PBA_SLVCTL1_0x00064005 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVCTL1_0x00064005 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + rc = fapiPutScom(i_target, PBA_SLVCTL2_0x00064006 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVCTL2_0x00064006 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + rc = fapiPutScom(i_target, PBA_SLVCTL3_0x00064007 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVCTL3_0x00064007 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + // Clear the PBA FIR (Reset) only + l_rc = data.setDoubleWord(0, 0x0); + if (l_rc) + { + FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); + rc.setEcmdError(l_rc); + break; + } // end if + + rc = fapiPutScom(i_target, PBA_FIR_0x02010840 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_FIR_0x02010840 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + // For reset, this register should be written with the value from figtree + // to restore the initial hardware state. Therefore fix this constant. + // For init, needs detailing for performance and/or CHSW enable/disable + // reset case + // data still 0 + rc = fapiPutScom(i_target, PBA_CONFIG_0x0201084B , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_CONFIG_0x0201084B ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + // pba slave register handling for PM_RESET + rc = pba_slave_setup_reset(i_target); + if (rc) + { + FAPI_ERR("pba_slave_setup_reset failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + // For reset, written with 0x0s to restore to fresh value. + rc = fapiPutScom(i_target, PBA_ERR_RPT0_0x0201084C , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_ERR_RPT0_0x0201084C ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + // the following operations are not required, keep this in mind, don't erase them here + // l_rc = fapiPutScom(i_target, PBA_ERR_RPT1_0x0201084D , data); + // if(l_rc) { FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_INIT_PUTSCOM_FAILED); return l_rc; } + // else {FAPI_INF("Done with PBA_ERR_RPT1_0x0201084D \n ") }; + + // l_rc = fapiPutScom(i_target, PBA_ERR_RPT2_0x0201084E , data); + // if(l_rc) { FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_INIT_PUTSCOM_FAILED); return l_rc; } + // else {FAPI_INF("Done with PBA_ERR_RPT2_0x0201084E \n ") }; + + + // The following apply to Reset mode + rc = fapiPutScom(i_target, PBA_SLVRST_0x00064001 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVRST_0x00064001 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + // last step: pba slave setup for reset + rc = pba_slave_setup_reset (i_target); + if (rc) + { + FAPI_ERR("fapi pba_slave_setup_reset failed. With rc = 0x%x", (uint32_t)rc); + break; + } + } while(0); + + return rc; } // endif (mode == PM_RESET) - // *********************************************************************************************** - // ************************************************************ mode = PM_INIT ******************* - // call pba_slave_setup - ReturnCode - p8_pba_init_PM_INIT(const Target& i_target) - { - - ReturnCode rc; - ecmdDataBufferBase data(64); - uint32_t l_rc; // local returncode - - uint8_t ATTR_PM_PBAX_RCV_RESERV_TIMEOUT_value = 0 ; - uint8_t ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE_value = 0 ; - uint8_t ATTR_PM_PBAX_SND_RETRY_THRESHOLD_value = 0 ; - uint8_t ATTR_PM_PBAX_SND_RESERV_TIMEOUT_value = 0 ; - - pbaxcfg_t pbaxcfg_setup ; - - // if (mode == PM_INIT) { - FAPI_INF("mode = PM_INIT..\n"); - l_rc = data.setDoubleWord(0, 0x0); - if (l_rc) - { - FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; - } // end if - // For reset, this register should be written with the value from figtree to restore the - // initial hardware state. - // For init, needs detailing for performance and/or CHSW enable/disable TODO - // init case - rc = fapiPutScom(i_target, PBA_CONFIG_0x0201084B , data); - if (rc) - { - FAPI_ERR("fapiPutScom( PBA_CONFIG_0x0201084B ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with, PBA_CONFIG_0x0201084B \n "); - } // end if-else - - // Clear the PBA FIR (Reset) only - // data still 0 - rc = fapiPutScom(i_target, PBA_FIR_0x02010840 , data); - if (rc) - { - FAPI_ERR("fapiPutScom( PBA_FIR_0x02010840 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_DBG("Done with PBA_FIR_0x02010840 \n "); - } // end if-else - - // The following registers are ROX, hence need not be touched: - // PBA_RBUFVAL0_0x02010850 - // PBA_RBUFVAL1_0x02010851 - // PBA_RBUFVAL2_0x02010852 - // PBA_RBUFVAL3_0x02010853 - // PBA_RBUFVAL4_0x02010854 - // PBA_RBUFVAL5_0x02010855 - // PBA_WBUFVAL0_0x02010858 - // PBA_WBUFVAL1_0x02010859 - - // These PowerBus Overcommit regs are read-only, therefore no action required: - // PBA_PBOCR0_0x00064020 - // PBA_PBOCR1_0x00064021 - // PBA_PBOCR2_0x00064022 - // PBA_PBOCR3_0x00064023 - // PBA_PBOCR4_0x00064024 - // PBA_PBOCR5_0x0006402 - - // The PBA BARs and their associated Masks are done outside of this FAPI set. Thus, during - // a reset, the BARS/MASKS are retained. this applies to - // PBA_BAR0_0x02013F00 - // PBA_BARMSK0_0x02013F04 - // PBA_BARMSK1_0x02013F05 - // PBA_BAR1_0x02013F01 - // PBA_BAR2_0x02013F02 - // PBA_BAR3_0x02013F03 - // PBA_TRUSTMODE_0x02013F08 - - // any checkreads => NO - - rc = FAPI_ATTR_GET ( ATTR_PM_PBAX_RCV_RESERV_TIMEOUT , &i_target, ATTR_PM_PBAX_RCV_RESERV_TIMEOUT_value ); - if (rc) - { - FAPI_ERR("fapi_attr_get( ATTR_PM_PBAX_RCV_RESERV_TIMEOUT ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } // end if +// *********************************************************************************************** +// ************************************************************ mode = PM_INIT ******************* +// call pba_slave_setup +fapi::ReturnCode +p8_pba_init_PM_INIT(const Target& i_target) +{ - rc = FAPI_ATTR_GET ( ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE , &i_target, ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE_value ); - if (rc) - { - FAPI_ERR("fapi_attr_get( ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABL ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } // end if + fapi::ReturnCode rc; + ecmdDataBufferBase data(64); + uint32_t l_rc; // local returncode - rc = FAPI_ATTR_GET ( ATTR_PM_PBAX_SND_RETRY_THRESHOLD , &i_target, ATTR_PM_PBAX_SND_RETRY_THRESHOLD_value ); - if (rc) - { - FAPI_ERR("fapi_attr_get( ATTR_PM_PBAX_SND_RETRY_THRESHOLD ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } // end if + uint8_t ATTR_PM_PBAX_RCV_RESERV_TIMEOUT_value = 0 ; + uint8_t ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE_value = 0 ; + uint8_t ATTR_PM_PBAX_SND_RETRY_THRESHOLD_value = 0 ; + uint8_t ATTR_PM_PBAX_SND_RESERV_TIMEOUT_value = 0 ; - rc = FAPI_ATTR_GET ( ATTR_PM_PBAX_SND_RESERV_TIMEOUT , &i_target, ATTR_PM_PBAX_SND_RESERV_TIMEOUT_value ); - if (rc) - { - FAPI_ERR("fapi_attr_get( ATTR_PM_PBAX_SND_RESERV_TIMEOU ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } // end if - - // assemble the attributes - // 20:24, ATTR_PM_PBAX_RCV_RESERV_TIMEOUT_value - // 27; ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE_value - // 28:35; ATTR_PM_PBAX_SND_RETRY_THRESHOLD_value - // 36:40 ATTR_PM_PBAX_SND_RESERV_TIMEOUT_value - pbaxcfg_setup.fields.ATTR_PM_PBAX_RCV_RESERV_TIMEOUT = ATTR_PM_PBAX_RCV_RESERV_TIMEOUT_value; - pbaxcfg_setup.fields.ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE = ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE_value; - pbaxcfg_setup.fields.ATTR_PM_PBAX_SND_RETRY_THRESHOLD = ATTR_PM_PBAX_SND_RETRY_THRESHOLD_value; - pbaxcfg_setup.fields.ATTR_PM_PBAX_SND_RESERV_TIMEOUT = ATTR_PM_PBAX_SND_RESERV_TIMEOUT_value; - - // put the attribute values into PBAXCFG - l_rc = data.setDoubleWord(0, pbaxcfg_setup.value); - if (l_rc) - { - FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; - } // end if - rc = fapiPutScom(i_target, PBAXCFG_00064021 , data); - if (rc) - { - FAPI_ERR("fapiPutScom(PBAXCFG_00064021) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with attr_pbaxsndtx_value "); - } // end if-else - - // last step: pba slave setup for init - rc = pba_slave_setup_init (i_target); - if (rc) - { - FAPI_ERR("fapi pba_slave_setup_init failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else + pbaxcfg_t pbaxcfg_setup ; + pbaxcfg_setup.value = 0; + do { - FAPI_INF("Done with api_pba_slave_init \n "); - } // end if-else + // if (mode == PM_INIT) { + FAPI_INF("mode = PM_INIT..."); + l_rc = data.setDoubleWord(0, 0x0); + if (l_rc) + { + FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); + rc.setEcmdError(l_rc); + break; + } // end if + + // For reset, this register should be written with the value from figtree to restore the + // initial hardware state. + // For init, needs detailing for performance and/or CHSW enable/disable TODO + // init case + FAPI_INF("flusing PBA_CONFIG register "); + + rc = fapiPutScom(i_target, PBA_CONFIG_0x0201084B , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_CONFIG_0x0201084B ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + // Clear the PBA FIR (Reset) only + // data still 0 + FAPI_INF("flusing PBA_FIR register "); + rc = fapiPutScom(i_target, PBA_FIR_0x02010840 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_FIR_0x02010840 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + // The following registers are ROX, hence need not be touched: + // PBA_RBUFVAL0_0x02010850 + // PBA_RBUFVAL1_0x02010851 + // PBA_RBUFVAL2_0x02010852 + // PBA_RBUFVAL3_0x02010853 + // PBA_RBUFVAL4_0x02010854 + // PBA_RBUFVAL5_0x02010855 + // PBA_WBUFVAL0_0x02010858 + // PBA_WBUFVAL1_0x02010859 + + // These PowerBus Overcommit regs are read-only, therefore no action required: + // PBA_PBOCR0_0x00064020 + // PBA_PBOCR1_0x00064021 + // PBA_PBOCR2_0x00064022 + // PBA_PBOCR3_0x00064023 + // PBA_PBOCR4_0x00064024 + // PBA_PBOCR5_0x0006402 + + // The PBA BARs and their associated Masks are done outside of this FAPI set. Thus, during + // a reset, the BARS/MASKS are retained. this applies to + // PBA_BAR0_0x02013F00 + // PBA_BARMSK0_0x02013F04 + // PBA_BARMSK1_0x02013F05 + // PBA_BAR1_0x02013F01 + // PBA_BAR2_0x02013F02 + // PBA_BAR3_0x02013F03 + // PBA_TRUSTMODE_0x02013F08 + + // any checkreads => NO + + rc = FAPI_ATTR_GET ( ATTR_PM_PBAX_RCV_RESERV_TIMEOUT , &i_target, ATTR_PM_PBAX_RCV_RESERV_TIMEOUT_value ); + if (rc) + { + FAPI_ERR("fapi_attr_get( ATTR_PM_PBAX_RCV_RESERV_TIMEOUT ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } // end if + + rc = FAPI_ATTR_GET ( ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE , &i_target, ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE_value ); + if (rc) + { + FAPI_ERR("fapi_attr_get( ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } // end if + + rc = FAPI_ATTR_GET ( ATTR_PM_PBAX_SND_RETRY_THRESHOLD , &i_target, ATTR_PM_PBAX_SND_RETRY_THRESHOLD_value ); + if (rc) + { + FAPI_ERR("fapi_attr_get( ATTR_PM_PBAX_SND_RETRY_THRESHOLD ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } // end if + + rc = FAPI_ATTR_GET ( ATTR_PM_PBAX_SND_RESERV_TIMEOUT , &i_target, ATTR_PM_PBAX_SND_RESERV_TIMEOUT_value ); + if (rc) + { + FAPI_ERR("fapi_attr_get( ATTR_PM_PBAX_SND_RESERV_TIMEOUT ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } // end if + + + + // assemble the attributes + // 20:24, ATTR_PM_PBAX_RCV_RESERV_TIMEOUT_value + // 27; ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE_value + // 28:35; ATTR_PM_PBAX_SND_RETRY_THRESHOLD_value + // 36:40 ATTR_PM_PBAX_SND_RESERV_TIMEOUT_value + pbaxcfg_setup.fields.ATTR_PM_PBAX_RCV_RESERV_TIMEOUT = ATTR_PM_PBAX_RCV_RESERV_TIMEOUT_value; + pbaxcfg_setup.fields.ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE = ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE_value; + pbaxcfg_setup.fields.ATTR_PM_PBAX_SND_RETRY_THRESHOLD = ATTR_PM_PBAX_SND_RETRY_THRESHOLD_value; + pbaxcfg_setup.fields.ATTR_PM_PBAX_SND_RESERV_TIMEOUT = ATTR_PM_PBAX_SND_RESERV_TIMEOUT_value; + + // put the attribute values into PBAXCFG + l_rc = data.setDoubleWord(0, pbaxcfg_setup.value); + if (l_rc) + { + FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); + rc.setEcmdError(l_rc); + break; + } // end if + + rc = fapiPutScom(i_target, PBAXCFG_00064021 , data); + if (rc) + { + FAPI_ERR("fapiPutScom(PBAXCFG_00064021) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + // last step: pba slave setup for init + rc = pba_slave_setup_init (i_target); + if (rc) + { + FAPI_ERR("fapi pba_slave_setup_init failed. With rc = 0x%x", (uint32_t)rc); + break; + } + } while(0); return rc; - } // end PM_INIT +} // end PM_INIT - // ************************************************************************************************* - // ************************************************************* mode = PM_CONFIG ****************** - // - /// Configuration: perform translation of any Platform Attributes into - /// Feature Attributes that are applied during Initalization of PBAX - ReturnCode - p8_pba_init_PM_CONFIG(const Target& i_target) - { - ReturnCode rc; +// ************************************************************************************************* +// ************************************************************* mode = PM_CONFIG ****************** +// +/// Configuration: perform translation of any Platform Attributes into +/// Feature Attributes that are applied during Initalization of PBAX +fapi::ReturnCode +p8_pba_init_PM_CONFIG(const Target& i_target) +{ + fapi::ReturnCode rc; ecmdDataBufferBase data(64); uint32_t l_rc; // local returncode - FAPI_INF("mode = PM_CONFIG..\n"); + FAPI_INF("mode = PM_CONFIG..."); l_rc = data.setDoubleWord(0, 0x0); - if (l_rc) { FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + if (l_rc) + { + FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); + rc.setEcmdError(l_rc); + return rc; + } FAPI_INF("PBAX configuration..."); FAPI_INF("Getting PBAX configuration values via attribute settings."); @@ -675,12 +581,12 @@ ReturnCode /// /// \bug The dis_slvmatch_order bit is going away -ReturnCode +fapi::ReturnCode pba_slave_setup_init(const Target& i_target) { pba_mode_t pm; pba_slvctln_t ps; - ReturnCode rc; + fapi::ReturnCode rc; uint32_t l_rc; // local returncode ecmdDataBufferBase data(64); @@ -705,19 +611,18 @@ pba_slave_setup_init(const Target& i_target) l_rc = data.setDoubleWord(0, pm.value); if (l_rc) { - FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; + FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); + rc.setEcmdError(l_rc); + return rc; } // write the prepared value rc = fapiPutScom(i_target, PBA_MODE_0x00064000 , data); if (rc) { - FAPI_ERR("fapiPutScom( PBA_MODE_0x00064000 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_MODE \n "); - } // end if-else - + FAPI_ERR("fapiPutScom( PBA_MODE_0x00064000 ) failed. With rc = 0x%x", (uint32_t)rc); + return rc; + } // Slave 0 (PORE-GPE). This is a read/write slave. We only do 'static' // setup here. Dynamic setup will be done by each GPE program that needs @@ -736,16 +641,16 @@ pba_slave_setup_init(const Target& i_target) l_rc = data.setDoubleWord(0, ps.value); if (l_rc) { - FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; + FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); + return rc; } // end if + rc = fapiPutScom(i_target, PBA_SLVCTL0_0x00064004 , data); if (rc) { - FAPI_ERR("fapiPutScom( PBA_SLVCTL0_0x00064004 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_MODE \n "); - } // end if-else + FAPI_ERR("fapiPutScom( PBA_SLVCTL0_0x00064004 ) failed. With rc = 0x%x", (uint32_t)rc); + return rc; + } // Slave 1 (405 ICU/DCU). This is a read/write slave. Write gethering is // allowed, but with the shortest possible timeout. This slave is @@ -764,21 +669,22 @@ pba_slave_setup_init(const Target& i_target) ps.fields.buf_alloc_b = 1; ps.fields.buf_alloc_c = 1; ps.fields.buf_alloc_w = 1; + l_rc = data.setDoubleWord(0, ps.value); if (l_rc) { - FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; + FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); + rc.setEcmdError(l_rc); + return rc; } // end if + rc = fapiPutScom(i_target, PBA_SLVCTL1_0x00064005 , data); if (rc) { - FAPI_ERR("fapiPutScom( PBA_SLVCTL1_0x00064005 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_MODE \n "); - } // end if-else - - + FAPI_ERR("fapiPutScom( PBA_SLVCTL1_0x00064005 ) failed. With rc = 0x%x", (uint32_t)rc); + return rc; + } + // Slave 2 (PORE-SLW). This is a read/write slave. Write gathering is // allowed, but with the shortest possible timeout. The slave is set up // to allow normal reads and writes at initialization. The 24x7 code may @@ -801,17 +707,17 @@ pba_slave_setup_init(const Target& i_target) l_rc = data.setDoubleWord(0, ps.value); if (l_rc) { - FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; + FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); + rc.setEcmdError(l_rc); + return rc; } // end if + rc = fapiPutScom(i_target, PBA_SLVCTL2_0x00064006 , data); if (rc) { - FAPI_ERR("fapiPutScom( PBA_SLVCTL2_0x00064006 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_MODE \n "); - } // end if-else - + FAPI_ERR("fapiPutScom( PBA_SLVCTL2_0x00064006 ) failed. With rc = 0x%x", (uint32_t)rc); + return rc; + } // Slave 3 (OCB). This is a read/write slave. Write gathering is // allowed, but with the shortest possible timeout. @@ -829,84 +735,164 @@ pba_slave_setup_init(const Target& i_target) ps.fields.buf_alloc_b = 1; ps.fields.buf_alloc_c = 1; ps.fields.buf_alloc_w = 1; + l_rc = data.setDoubleWord(0, ps.value); if (l_rc) { FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } // end if + rc = fapiPutScom(i_target, PBA_SLVCTL3_0x00064007 , data); if (rc) { FAPI_ERR("fapiPutScom( PBA_SLVCTL3_0x00064007 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - - FAPI_INF("Done with PBA_MODE \n "); - } // end if-else + } return rc; } // end pba_slave_setup_init +// ************************************************************************************************ +// **************************************************** pba_slave_setup_reset ********************* // for reset, set all register contents to zero -ReturnCode +fapi::ReturnCode pba_slave_setup_reset(const Target& i_target) { - ReturnCode rc; + fapi::ReturnCode rc; uint32_t l_rc; // local returncode ecmdDataBufferBase data(64); - l_rc= data.setDoubleWord(0, 0x00000000); - if (l_rc) - { - FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; - } // end if - - rc = fapiPutScom(i_target, PBA_MODE_0x00064000 , data); - if (rc) - { - FAPI_ERR("fapiPutScom( PBA_MODE_0x00064000 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else + do { - FAPI_INF("Done with PBA_MODE \n "); - } // end if-else + l_rc= data.setDoubleWord(0, 0x00000000); + if (l_rc) + { + FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); + rc.setEcmdError(l_rc); + break; + } // end if + + rc = fapiPutScom(i_target, PBA_MODE_0x00064000 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_MODE_0x00064000 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + rc = fapiPutScom(i_target, PBA_SLVCTL0_0x00064004 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVCTL0_0x00064004 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + rc = fapiPutScom(i_target, PBA_SLVCTL1_0x00064005 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVCTL1_0x00064005 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + rc = fapiPutScom(i_target, PBA_SLVCTL2_0x00064006 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVCTL2_0x00064006 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + + rc = fapiPutScom(i_target, PBA_SLVCTL3_0x00064007 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVCTL3_0x00064007 ) failed. With rc = 0x%x", (uint32_t)rc); + break; + } + } while(0); + + return rc; - rc = fapiPutScom(i_target, PBA_SLVCTL0_0x00064004 , data); - if (rc) - { - FAPI_ERR("fapiPutScom( PBA_SLVCTL0_0x00064004 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_MODE \n "); - } // end if-else +} // end pba_slave_setup_reset - rc = fapiPutScom(i_target, PBA_SLVCTL1_0x00064005 , data); - if (rc) - { - FAPI_ERR("fapiPutScom( PBA_SLVCTL1_0x00064005 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_MODE \n "); - } // end if-else - rc = fapiPutScom(i_target, PBA_SLVCTL2_0x00064006 , data); - if (rc) - { - FAPI_ERR("fapiPutScom( PBA_SLVCTL2_0x00064006 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_MODE \n "); - } // end if-else - rc = fapiPutScom(i_target, PBA_SLVCTL3_0x00064007 , data); - if (rc) - { - FAPI_ERR("fapiPutScom( PBA_SLVCTL3_0x00064007 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } else - { - FAPI_INF("Done with PBA_MODE \n "); - } // end if-else +// ************************************************************************************************ +// **************************************************** pba_slave_reset *************************** +// Walk each slave to hit the respective reset and then poll for completion +fapi::ReturnCode +pba_slave_reset(const Target& i_target) +{ + fapi::ReturnCode rc; + ecmdDataBufferBase data(64); + bool error_flag = false; + bool poll_failure = false; + + + do + { + for (int s=0; s<= 3; s++) + { + + FAPI_INF("Reseting PBA Slave %x", s); + poll_failure = true; + // for (int p=0; p<MAX_PBA_RESET_POLLS; p++) + for (int p=0; p<=16; p++) + { + + // Set the reset for the selected slave + data.setDoubleWord(0, PBA_SLVRESETs[s]); + + rc = fapiPutScom(i_target, PBA_SLVRST_0x00064001 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVRST_0x00064001 ) failed. With rc = 0x%x", (uint32_t)rc); + break ; + } + + // Read the reset register to check for reset completion + rc = fapiGetScom(i_target, PBA_SLVRST_0x00064001 , data); + if (rc) + { + FAPI_ERR("fapiGetPutScom( PBA_SLVRST_0x00064001 ) failed. With rc = 0x%x", (uint32_t)rc); + error_flag = true; + break; + } + FAPI_DBG("Slave %x reset poll data = 0x%16llu", s, data.getDoubleWord(0)); + + // If slave reset in progress, wait and then poll + if (data.isBitClear(4+s)) + { + poll_failure = false; + break; + } + else + { + rc = fapiDelay(PBA_RESET_POLL_DELAY*1000, 200000); // In microseconds + } + + } + if (error_flag) + { + break; + } + + if (poll_failure) + { + FAPI_ERR("fapiGetPutScom( PBA_SLVRST_0x00064001 ) failed. With rc = 0x%x", (uint32_t)rc); + // NEED SET RC + break; + } + + // Check if the slave is still actually busy. Consider whether this should be polled + if (data.isBitSet(8+s)) + { + FAPI_ERR("Slave %x still busy after reset", s); + // NEED SET RC + break; + } + + } + + } while(0); + return rc; } // end pba_slave_setup_reset diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C index 2dba473e6..3b2bd2996 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C @@ -20,25 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_pcbs_init.C,v 1.6 2012/10/12 15:33:19 rmaier Exp $ -// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pcbs_init.C,v $ +// $Id: p8_pcbs_init.C,v 1.15 2013/04/12 01:31:59 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pcbs_init.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -47,13 +30,13 @@ // *! OWNER NAME: Ralf Maier Email: ralf.maier@de.ibm.com // *! // *! General Description: -// *! +// *! // *! The purpose of this procedure is to establish the safe setting for PCBSLV -// *! o set psafe value +// *! o set psafe value // *! o set PMIN clip/Pmax clip -// *! o PMCR default values +// *! o PMCR default values // *! o PMICR default values -// *! +// *! // *! // *! Procedure Prereq: // *! o System clocks are running @@ -65,6 +48,10 @@ /// /// /// \version -------------------------------------------------------------------------- +/// \version 1.8 rmaier 12/07/12 Removed PFET delay value calculation from p8_pcbs_init_config since this is moved to p8_pfet_init.C +/// \version -------------------------------------------------------------------------- +/// \version 1.7 rmaier 10/25/12 Removed PMGP1_REG Idle-Configuration since this function moved to p8_poreslw_init.C +/// \version -------------------------------------------------------------------------- /// \version 1.6 rmaier 10/12/12 Removed not needed scan0 writes to EX_PCBS_Pstate_Step_Target_Register EX_PCBS_OCC_Heartbeat_Reg /// \version -------------------------------------------------------------------------- /// \version 1.5 rmaier 10/10/12 Changed value of EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165_scan0 @@ -79,7 +66,7 @@ /// \version -------------------------------------------------------------------------- /// \version 1.15 rmaier 08/15/12 Included review feedback Set7 (removed conditional compile statements ) /// \version -------------------------------------------------------------------------- -/// \version 1.14 rmaier 08/03/12 Included review feedback Set4 +/// \version 1.14 rmaier 08/03/12 Included review feedback Set4 /// \version -------------------------------------------------------------------------- /// \version 1.13 rmaier 08/02/12 Included review feedback Set4 partial /// \version -------------------------------------------------------------------------- @@ -106,18 +93,12 @@ /// \version 1.0 rmaier 10/17/11 Initial Version - RESET mode /// \version --------------------------------------------------------------------------- /// -/// -/// -/// -/// -/// -/// \todo command order +/// \todo command order /// \todo next -- > initialize all pm_reg with scan-zero values upfront /// \todo Clear definition/doc of parms and attributes required at the beginning. /// \todo GP3 Changes Winkle fence changes /// \todo Review /// -/// /// High-level procedure flow: /// /// \verbatim @@ -127,118 +108,112 @@ /// - completed multicast setup /// /// -/// if PM_CONFIG { -/// PState translation -/// convert_safe_freq() -/// Resonant Clocking settings (band definitions from frequency to Pstate) -/// convert_resclk_freqs_to_pstates() -/// PFET Sequencing Delays -/// convert_pfet_delays() +/// if PM_CONFIG { +/// PState translation +/// convert_safe_freq() +/// Resonant Clocking settings (band definitions from frequency to Pstate) +/// convert_resclk_freqs_to_pstates() +/// PFET Sequencing Delays +/// convert_pfet_delays() /// -/// else if PM_INIT { +/// else if PM_INIT { /// -/// set CPM_FILTER_ENABLE = 0 -- #110f0152, DPLL_CPM_PARM_REG[10] = 0 -/// -- PMGP1_REG WOX_OR 150f0105 -/// ATTR_PM_SLEEP_ENTRY (Assisted or Hardware) bit0 0=assisted -/// ATTR_PM_SLEEP_EXIT (Assisted or Hardware) bit1 0=assisted -/// ATTR_PM_SLEEP_TYPE (Deep or Fast) bit2 0=fast -/// ATTR_PM_WINKLE_ENTRY (Assisted or Hardware) bit3 -/// ATTR_PM_WINKLE_EXIT (Assisted or Hardware) bit4 -/// ATTR_PM_WINKLE_TYPE (Deep or Fast) bit5 +/// set CPM_FILTER_ENABLE = 0 -- #110f0152, DPLL_CPM_PARM_REG[10] = 0 +/// -- PMGP1_REG WOX_OR 150f0105 /// -/// set PMCR[0:39] = 0 -- PMCR default value adjustment -/// -- (Hardware flush 0 -> restore to 0 for reset case) -/// -- #110f0159, PCBS_POWER_MANAGEMENT_CONTROL_REG +/// set PMCR[0:39] = 0 -- PMCR default value adjustment +/// -- (Hardware flush 0 -> restore to 0 for reset case) +/// -- #110f0159, PCBS_POWER_MANAGEMENT_CONTROL_REG /// -/// pm_spr_override_en must be set to write this reg!! -/// set PMICR[0:47] = 0 -- PMICR default value adjustment -/// -- (Hardware flush 0 -> restore to TBD for reset case) -/// -- #110f0158, PCBS_POWER_MANAGEMENT_IDLE_CONTROL_REG +/// pm_spr_override_en must be set to write this reg!! +/// set PMICR[0:47] = 0 -- PMICR default value adjustment +/// -- (Hardware flush 0 -> restore to TBD for reset case) +/// -- #110f0158, PCBS_POWER_MANAGEMENT_IDLE_CONTROL_REG /// /// /// -/// } else if PM_RESET { +/// } else if PM_RESET { /// -/// loop over all valid chiplets { +/// loop over all valid chiplets { /// -/// -- TODO check about -/// -- initialize all pm_reg with scan-zero values upfront +/// -- TODO check about +/// -- initialize all pm_reg with scan-zero values upfront /// -/// // Force safe mode -/// set force_safe_mode = 1 -- Force safe mode (uses Psafe Pstate setting) -/// -- XXXX multicast PCBS_PM_PMGP1_REG_1[12] = 1/// -/// // psafe Pstate achived AND FSM-stable ? -/// if psafePstate achived AND FSM-stable { -- Check PCBS-PM state/status that Psafe (Pstate) as been achieved and -/// -- that FSM are in a stable state -/// -- PCBS_POWER_MANAGEMENT_STATUS_REG[33] safe_mode_active -/// -- PCBS_POWER_MANAGEMENT_STATUS_REG[36] all_fsms_in_safe_state -/// } elsif timeout { -/// --BAD RC: timeout - no PsafePstate or FSMs not stable -/// } +/// // Force safe mode +/// set force_safe_mode = 1 -- Force safe mode (uses Psafe Pstate setting) +/// -- XXXX multicast PCBS_PM_PMGP1_REG_1[12] = 1/// +/// // psafe Pstate achived AND FSM-stable ? +/// if psafePstate achived AND FSM-stable { -- Check PCBS-PM state/status that Psafe (Pstate) as been achieved and +/// -- that FSM are in a stable state +/// -- PCBS_POWER_MANAGEMENT_STATUS_REG[33] safe_mode_active +/// -- PCBS_POWER_MANAGEMENT_STATUS_REG[36] all_fsms_in_safe_state +/// } elsif timeout { +/// --BAD RC: timeout - no PsafePstate or FSMs not stable +/// } /// -/// // DPLL settings -/// set dpll_freq_override_enable = 1 -- PCBS_PM_PMGP1_REG_1[10] = 1 -/// -- only in override mode is a write to FREQ_CTRL_REG possible +/// // DPLL settings +/// set dpll_freq_override_enable = 1 -- PCBS_PM_PMGP1_REG_1[10] = 1 +/// -- only in override mode is a write to FREQ_CTRL_REG possible /// -/// set minPstate = min(Psafe,global actual pstate) -- PCBS_OCC_Heartbeat_Reg[17..24] Psafe -/// -- PCBS_POWER_MANAGEMENT_STATUS_REG[0..7] global actual pstate -/// set dpll_min = fnom + minPstate(signed) -- FREQ_CTRL_REG[20..27] pstate_dpll_fnom +/// set minPstate = min(Psafe,global actual pstate) -- PCBS_OCC_Heartbeat_Reg[17..24] Psafe +/// -- PCBS_POWER_MANAGEMENT_STATUS_REG[0..7] global actual pstate +/// set dpll_min = fnom + minPstate(signed) -- FREQ_CTRL_REG[20..27] pstate_dpll_fnom /// /// -/// set dpll_fmin -- FREQ_CTRL_REG[0..7] scaninit: 00110010 -/// set dpll_fmax -- FREQ_CTRL_REG[8..15] scaninit: 00110010 +/// set dpll_fmin -- FREQ_CTRL_REG[0..7] scaninit: 00110010 +/// set dpll_fmax -- FREQ_CTRL_REG[8..15] scaninit: 00110010 /// -/// set pm_spr_override_en = 1 -- Force OCC SPR Mode -/// -- XXXX multicast PCBS_PM_PMGP1_REG_1[11] = 1 +/// set pm_spr_override_en = 1 -- Force OCC SPR Mode +/// -- XXXX multicast PCBS_PM_PMGP1_REG_1[11] = 1 /// -/// set enable_Pstate_mode = 0 -- PCBSPM_MODE_REG[0] ....multicast +/// set enable_Pstate_mode = 0 -- PCBSPM_MODE_REG[0] ....multicast /// -/// set enable_global_pstate_req = 0 -- Force *global_en PState to off to cease interrupts to PMC....multicast -/// -- PCBSPM_MODE_REG[2] +/// set enable_global_pstate_req = 0 -- Force *global_en PState to off to cease interrupts to PMC....multicast +/// -- PCBSPM_MODE_REG[2] /// -/// -- Reset Pmin and Pmax to wide open...multicast -/// set Pmin_clip = -128 -- PCBS_Power_Management_Bounds_Reg[0..7] 0b10000000 -/// set Pmax_clip = 127 -- PCBS_Power_Management_Bounds_Reg[8..15] 0b01111111 +/// -- Reset Pmin and Pmax to wide open...multicast +/// set Pmin_clip = -128 -- PCBS_Power_Management_Bounds_Reg[0..7] 0b10000000 +/// set Pmax_clip = 127 -- PCBS_Power_Management_Bounds_Reg[8..15] 0b01111111 /// /// -/// // Settings -/// set resclk_dis = 1 -- Chiplets resonant clocking (via PCBS) disabled -/// -- EH.TPCHIP.NET.PCBSLPREV.GP3_REG[22] -/// -- This is only ROX PCBS_Resonant_Clock_Control_Reg0[0] +/// // Settings +/// set resclk_dis = 1 -- Chiplets resonant clocking (via PCBS) disabled +/// -- EH.TPCHIP.NET.PCBSLPREV.GP3_REG[22] +/// -- This is only ROX PCBS_Resonant_Clock_Control_Reg0[0] /// -/// set occ_heartbeat_enable = 0 -- OCC Heartbeat disable -/// -- PCBS_OCC_Heartbeat_Reg[8] +/// set occ_heartbeat_enable = 0 -- OCC Heartbeat disable +/// -- PCBS_OCC_Heartbeat_Reg[8] /// -/// // IVRM Setup -/// get the mrwb attribute ivrms_enabled -- If '0' Salerno, if '1' Venice -/// if ivrms_enabled { -/// set ivrm_fsm_enable = 0 -- PCBS_iVRM_Control_Status_Reg[0] -/// -- ivrm_fsm_enable have be '0' to enable bypass_b writes -/// set bypass_b mode = 0 -/// --ivrm_core_vdd_bypass_b -- PCBS_iVRM_Control_Status_Reg[4] -/// --ivrm_core_vcs_bypass_b -- PCBS_iVRM_Control_Status_Reg[6] -/// --ivrm_eco_vdd_bypass_b -- PCBS_iVRM_Control_Status_Reg[8] -/// --ivrm_eco_vcs_bypass_b -- PCBS_iVRM_Control_Status_Reg[10] -/// } +/// // IVRM Setup +/// get the mrwb attribute ivrms_enabled -- If '0' Salerno, if '1' Venice +/// if ivrms_enabled { +/// set ivrm_fsm_enable = 0 -- PCBS_iVRM_Control_Status_Reg[0] +/// -- ivrm_fsm_enable have be '0' to enable bypass_b writes +/// set bypass_b mode = 0 +/// --ivrm_core_vdd_bypass_b -- PCBS_iVRM_Control_Status_Reg[4] +/// --ivrm_core_vcs_bypass_b -- PCBS_iVRM_Control_Status_Reg[6] +/// --ivrm_eco_vdd_bypass_b -- PCBS_iVRM_Control_Status_Reg[8] +/// --ivrm_eco_vcs_bypass_b -- PCBS_iVRM_Control_Status_Reg[10] +/// } /// -/// -- Undervolting values reset -/// set Kuv = 0 -- PCBS_UNDERVOLTING_REG[16..21] -/// -- Puv_min and Puv_max to disable -/// set Puv_min = -128 -- PCBS_UNDERVOLTING_REG[0..7] -/// set Puv_max = -128 -- PCBS_UNDERVOLTING_REG[8..15] +/// -- Undervolting values reset +/// set Kuv = 0 -- PCBS_UNDERVOLTING_REG[16..21] +/// -- Puv_min and Puv_max to disable +/// set Puv_min = -128 -- PCBS_UNDERVOLTING_REG[0..7] +/// set Puv_max = -128 -- PCBS_UNDERVOLTING_REG[8..15] /// -/// set enable_LPFT_function = 0 -- Local Pstate Frequency Target mechanism disabled -/// -- PCBS_Local_Pstate_Frequency_Target_Control_Register[20] +/// set enable_LPFT_function = 0 -- Local Pstate Frequency Target mechanism disabled +/// -- PCBS_Local_Pstate_Frequency_Target_Control_Register[20] /// -/// // Issue reset to PCBS-PM -/// set endp_reset_pm_only = 1 -- Issue reset to PCBS-PM -/// -- PMGP1_REG[9] -/// -- unset off reset in the next cycle?? -/// set endp_reset_pm_only = 0 -- PMGP1_REG[9] +/// // Issue reset to PCBS-PM +/// set endp_reset_pm_only = 1 -- Issue reset to PCBS-PM +/// -- PMGP1_REG[9] +/// -- unset off reset in the next cycle?? +/// set endp_reset_pm_only = 0 -- PMGP1_REG[9] /// -/// ] --end loop over all valid chiplets +/// ] --end loop over all valid chiplets /// -/// } //end PM_RESET -mode +/// } //end PM_RESET -mode /// /// /// \endverbatim @@ -273,1883 +248,1090 @@ /// /// CONFIG /// -/// PState translation -/// convert_safe_freq() - With ATTR_PM_SAFE_FREQUENCY (binary in MHz) and ATTR_PM_PSTATE0_FREQUENCY (binary in Mhz) produce ATTR_PM_SAFE_PSTATE -/// Resonant Clocking settings (band definitions from frequency to Pstate) -/// convert_resclk_freqs_to_pstates() - Convert the following frequency platform attributes (binary in MHz) to feature Pstate attributes. The conversion uses ATTR_PM_PSTATE0_FREQUENCY. -/// Input platform attributes -/// ATTR_PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY -/// ATTR_PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY -/// ATTR_PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY -/// ATTR_PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY -/// ATTR_PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY -/// output feature attributes -/// ATTR_PM_RESONANT_CLOCK_FULL_CSB_PSTATE -/// ATTR_PM_RESONANT_CLOCK_LFRLOW_PSTATE -/// ATTR_PM_RESONANT_CLOCK_LFRUPPER_PSTATE -/// ATTR_PM_RESONANT_CLOCK_HFRLOW_PSTATE -/// ATTR_PM_RESONANT_CLOCK_HFRHIGH_PSTATE -/// PFET Sequencing Delays -/// convert_pfet_delays() - Convert the following delays from platform attributes (binary in nanoseconds) to PFET delay value feature attributes. The conversion uses ATTR_PROC_NEST_FREQUENCY. -/// Input platform attributes -/// ATTR_PM_PFET_POWERUP_CORE_DELAY0 -/// ATTR_PM_PFET_POWERUP_CORE_DELAY1 -/// ATTR_PM_PFET_POWERUP_ECO_DELAY0 -/// ATTR_PM_PFET_POWERUP_ECO_DELAY1 -/// ATTR_PM_PFET_POWERDOWN_CORE_DELAY0 -/// ATTR_PM_PFET_POWERDOWN_CORE_DELAY1 -/// ATTR_PM_PFET_POWERDOWN_ECO_DELAY0 -/// ATTR_PM_PFET_POWERDOWN_ECO_DELAY1 -/// output feature attributes -/// ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE -/// ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE -/// ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT -/// ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE -/// ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE -/// ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT -/// ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE -/// ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE -/// ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT -/// ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE -/// ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE -/// ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT -/// -/// -/// +/// PState translation +/// convert_safe_freq() - With ATTR_PM_SAFE_FREQUENCY (binary in MHz) +/// and ATTR_PM_PSTATE0_FREQUENCY (binary in Mhz) produce ATTR_PM_SAFE_PSTATE +/// Resonant Clocking settings (band definitions from frequency to Pstate) +/// convert_resclk_freqs_to_pstates() - Convert the following frequency +/// platform attributes (binary in MHz) to feature Pstate attributes. +/// The conversion uses ATTR_PM_PSTATE0_FREQUENCY. +/// Input platform attributes +/// ATTR_PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY +/// ATTR_PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY +/// ATTR_PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY +/// ATTR_PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY +/// ATTR_PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY +/// output feature attributes +/// ATTR_PM_RESONANT_CLOCK_FULL_CSB_PSTATE +/// ATTR_PM_RESONANT_CLOCK_LFRLOW_PSTATE +/// ATTR_PM_RESONANT_CLOCK_LFRUPPER_PSTATE +/// ATTR_PM_RESONANT_CLOCK_HFRLOW_PSTATE +/// ATTR_PM_RESONANT_CLOCK_HFRHIGH_PSTATE +/// PFET Sequencing Delays +/// convert_pfet_delays() - Convert the following delays from platform +/// attributes (binary in nanoseconds) to PFET delay value feature attributes. +/// The conversion uses ATTR_PROC_NEST_FREQUENCY. +/// Input platform attributes +/// ATTR_PM_PFET_POWERUP_CORE_DELAY0 +/// ATTR_PM_PFET_POWERUP_CORE_DELAY1 +/// ATTR_PM_PFET_POWERUP_ECO_DELAY0 +/// ATTR_PM_PFET_POWERUP_ECO_DELAY1 +/// ATTR_PM_PFET_POWERDOWN_CORE_DELAY0 +/// ATTR_PM_PFET_POWERDOWN_CORE_DELAY1 +/// ATTR_PM_PFET_POWERDOWN_ECO_DELAY0 +/// ATTR_PM_PFET_POWERDOWN_ECO_DELAY1 +/// output feature attributes +/// ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE +/// ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE +/// ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT +/// ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE +/// ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE +/// ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT +/// ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE +/// ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE +/// ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT +/// ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE +/// ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE +/// ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT /// INIT /// /// -Resets DPLL_CPM_PARM_REG.cpm_filter_enable -/// -/// - Sleep configuration -/// -ATTR_PM_SLEEP_TYPE (Deep or Fast) -/// -ATTR_PM_SLEEP_ENTRY (Assisted or Hardware) - depends on di/dt charateristics of the system (Assisted if power off serialization is needed, Hardware if the system can handle the unrelated powering off between cores. Hardware decreases entry latency ) -/// -ATTR_PM_SLEEP_EXIT (Assisted or Hardware) - set to Assisted (for both Fast and Deep). Fast for di/dt management; Deep as this necessary for restore. Setting to Hardware is a test mode for Fast only. -/// - Winkle configuration -/// -ATTR_PM_WINKLE_TYPE (Deep or Fast) -/// -ATTR_PM_WINKLE_ENTRY (Assisted or Hardware) -/// -ATTR_PM_WINKLE_EXIT (Assisted or Hardware) - set to Assisted (for both Fast and Deep). Fast for di/dt management; Deep as this necessary for restore. Setting to Hardware is a test mode for Fast only. -/// - PMCR default value adjustment (Hardware flush 0 -> restore to 0 for reset case) -/// -For reset case, disable all "global_en" bits in PMCR and PMICR; this keeps Global Pstate Request from occuring to the PMC until it has been initialized. OCCFW to be do this. -/// - PMICR default value adjustment (Hardware flush 0 -> restore to TBD for reset ) +/// -For reset case, disable all "global_en" bits in PMCR and PMICR; this +/// keeps Global Pstate Request from occuring to the PMC until it has +/// been initialized. OCCFW to be do this. +/// - PMICR default value adjustment (Hardware flush 0 -> restore to TBD for reset ) /// -How does policy influence the PMICR Pstate values? /// -Base: run at the turbo value fixed -/// -Enhancement: run at the highest Pstate value on the chip. (needs power projection to judge worth). +/// -Enhancement: run at the highest Pstate value on the chip. (needs power +/// projection to judge worth). /// -latency enable /// -Not planned at this time. /// OLD-DOC - Sleep / Winkle -> Fast / Deep configuration /// OLD-DOC - Restore to Deep Sleep and Deep Winkle upon reset -/// OLD-DOC - PMCR default value adjustment (Hardware flush 0 -> restore to 0 for reset case) SCAN0 -/// OLD-DOC -For reset case, disable all “global_en” bits in PMCR and PMICR; this keeps Global Pstate Request from occuring to the PMC until it has been initialized. OCCFW to be do this -/// OLD-DOC - PMICR default value adjustment (Hardware flush 0 -> restore to 0 for reset ) SCAN0 +/// OLD-DOC - PMCR default value adjustment (Hardware flush 0 -> restore to 0 for +/// reset case) SCAN0 +/// OLD-DOC -For reset case, disable all “global_en” bits in PMCR and PMICR; +/// this keeps Global Pstate Request from occuring to the PMC until +/// it has been initialized. OCCFW to be do this +/// OLD-DOC - PMICR default value adjustment (Hardware flush 0 -> restore to 0 for +/// reset ) SCAN0 /// \todo add to required proc ENUM requests /// -// ---------------------------------------------------------------------- +// ----------------------------------------------------------------------------- // Includes -// ---------------------------------------------------------------------- -#include <fapi.H> -#include "p8_scom_addresses.H" -#include "p8_pcbs_init.H" +// ----------------------------------------------------------------------------- #include "p8_pm.H" - -//---------------------------------------------------------------------- -// eCMD Includes -//---------------------------------------------------------------------- -#include <ecmdDataBufferBase.H> - - - +#include "p8_pcbs_init.H" extern "C" { - - using namespace fapi; -// ---------------------------------------------------------------------- +// ----------------------------------------------------------------------------- // Constant definitions -// ---------------------------------------------------------------------- -// Address definition for chiplet EX01 with base address 0x10000000 -// Example: getscom pu.ex 10000001 -c3 ---> scom address 0x13000001 -// CONST_UINT64_T( GP3_REG_0x100F0012 , ULL(0x100F0012) ); -// CONST_UINT64_T( FREQ_CTRL_REG_0x100F0151 , ULL(0x100F0151) ); -// CONST_UINT64_T( PCBS_POWER_MANAGEMENT_STATUS_REG_0x100F0153 , ULL(0x100F0153) ); -// CONST_UINT64_T( PCBS_iVRM_Control_Status_Reg_0x100F0154 , ULL(0x100F0154) ); -// CONST_UINT64_T( PCBSPM_MODE_REG_0x100F0156 , ULL(0x100F0156) ); -// CONST_UINT64_T( PCBS_UNDERVOLTING_REG_0x100F015B , ULL(0x100F015B) ); -// CONST_UINT64_T( PCBS_Power_Management_Bounds_Reg_0x100F015D , ULL(0x100F015D) ); -// CONST_UINT64_T( PCBS_OCC_Heartbeat_Reg_0x100F0164 , ULL(0x100F0164) ); -// CONST_UINT64_T( PCBS_Resonant_Clock_Control_Reg0_0x100F0165 , ULL(0x100F0165) ); -// CONST_UINT64_T( PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168 , ULL(0x100F0168) ); - -// CONST_UINT64_T( EX_GP3_0x100F0012 , ULL(0x100F0012) ); -// CONST_UINT64_T( EX_GP3_AND_0x100F0013 , ULL(0x100F0013) ); -// CONST_UINT64_T( EX_GP3_OR_0x100F0014 , ULL(0x100F0014) ); -// CONST_UINT64_T( EX_PMGP0_0x100F0100 , ULL(0x100F0100) ); -// CONST_UINT64_T( EX_PMGP0_AND_0x100F0101 , ULL(0x100F0101) ); -// CONST_UINT64_T( EX_PMGP0_OR_0x100F0102 , ULL(0x100F0102) ); - - //------------------------------------------------------------------------------ - //Start scan zero value - //------------------------------------------------------------------------------ -/// \todo Review scan0 values - - CONST_UINT64_T( PMGP0_REG_0x100F0100_scan0 , ULL(0x8030010C21000000) ); - CONST_UINT64_T( PMGP1_REG_0x100F0103_scan0 , ULL(0x6C00000000000000) ); - CONST_UINT64_T( EX_PFVddCntlStat_REG_0x100F0106_scan0 , ULL(0x0A00000000000000) ); - CONST_UINT64_T( EX_PFVcsCntlStat_REG_0x100F010E_scan0 , ULL(0xFFF0FFF080800000) ); //1000 0000 1000 000 - CONST_UINT64_T( EX_PMErrMask_REG_0x100F010A_scan0 , ULL(0x00000000)); - CONST_UINT64_T( EX_PMSpcWkupFSP_REG_0x100F010B_scan0 , ULL(0x00000000)); - CONST_UINT64_T( EX_PMSpcWkupOCC_REG_0x100F010C_scan0 , ULL(0x80000000)); //1 - CONST_UINT64_T( EX_PMSpcWkupPHYP_REG_0x100F010D_scan0 , ULL(0x00000000)); - CONST_UINT64_T( EX_CorePFPUDly_REG_0x100F012C_scan0 , ULL(0x00000000)); - CONST_UINT64_T( EX_CorePFPDDly_REG_0x100F012D_scan0 , ULL(0x00000000)); - CONST_UINT64_T( EX_CorePFVRET_REG_0x100F0130_scan0 , ULL(0x00000000)); - CONST_UINT64_T( EX_ECOPFPUDly_REG_0x100F014C_scan0 , ULL(0x00000000)); - CONST_UINT64_T( EX_ECOPFPDDly_REG_0x100F014D_scan0 , ULL(0x00000000)); - CONST_UINT64_T( EX_ECOPFVRET_REG_0x100F0150_scan0 , ULL(0x00000000)); - CONST_UINT64_T( EX_FREQCNTL_0x100F0151_scan0 , ULL(0x32320000)); // "0011 0010 0011 0010 000000000000" ; - CONST_UINT64_T( EX_DPLL_CPM_PARM_REG_0x100F0152_scan0 , ULL(0x00000200)); // "0000 0000 0000 0000 0000 0010 0000000" ; - CONST_UINT64_T( EX_PCBS_iVRM_Control_Status_Reg_0x100F0154_scan0 , ULL(0x00000000)); - CONST_UINT64_T( EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155_scan0 , ULL(0x00000000)); - CONST_UINT64_T( EX_PCBSPM_MODE_REG_0x100F0156_scan0 , ULL(0x01000000)); //"0000 0001 0000 0000 00" ; - CONST_UINT64_T( EX_PCBS_Power_Management_Control_Reg_0x100F0159_scan0 , ULL(0x00000000)) ; - CONST_UINT64_T( EX_PCBS_PMC_VF_CTRL_REG_0x100F015A_scan0 , ULL(0x00000000)); - CONST_UINT64_T( EX_PCBS_UNDERVOLTING_REG_0x100F015B_scan0 , ULL(0x00000000)); - CONST_UINT64_T( EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C_scan0 , ULL(0x00000000)); - CONST_UINT64_T( EX_PCBS_Power_Management_Bounds_Reg_0x100F015D_scan0 , ULL(0x807F0000)); - CONST_UINT64_T( EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E_scan0 , ULL(0x00000000)) ; - CONST_UINT64_T( EX_PCBS_Pstate_Step_Target_Register_0x100F0160_scan0 , ULL(0x00000000)) ; - CONST_UINT64_T( EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162_scan0 , ULL(0x00000000)); - CONST_UINT64_T( EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163_scan0 , ULL(0x00000000)); - CONST_UINT64_T( EX_PCBS_OCC_Heartbeat_Reg_0x100F0164_scan0 , ULL(0x00000000)); - CONST_UINT64_T( EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165_scan0 , ULL(0x4000000000000000)) ; //"0100 00000000000000000000000000000000000000" ; - CONST_UINT64_T( EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166_scan0 , ULL(0x00000000)); - CONST_UINT64_T( EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168_scan0 , ULL(0x00000000)); - - //End scan zero value - +// ----------------------------------------------------------------------------- + +// Macros to enhance readability yet provide for error handling +// Assume the error path is to break out of the current loop. If nested loops +// are employed, the error_flag can be used to break out of the necessary +// levels. +// +// Set Double Word Scan0 +#define SETDWSCAN0(_mi_target, _mi_address, _mi_buffer, _mi_reset_value){ \ + e_rc = data.setDoubleWord(0, _mi_reset_value); \ + if(e_rc) \ + { \ + FAPI_ERR("Set DoubleWord failed. With rc = 0x%x", (uint32_t)e_rc); \ + l_rc.setEcmdError(e_rc); \ + error_flag=true; \ + break; \ + } \ + FAPI_DBG("Scan0 equivalent reset of 0x%08llx to 0x%16llX", \ + _mi_address, _mi_reset_value); \ + l_rc = fapiPutScom(_mi_target, _mi_address, _mi_buffer); \ + if(!l_rc.ok()) \ + { \ + FAPI_ERR("PutScom error to address 0x%08llx", _mi_address); \ + error_flag=true; \ + break; \ + } \ +} +// Set Word Scan0 +#define SETSCAN0(_mi_target, _mi_address, _mi_buffer, _mi_reset_value){ \ + e_rc = data.setWord(0, _mi_reset_value); \ + if(e_rc) \ + { \ + FAPI_ERR("Set Word failed. With rc = 0x%x", (uint32_t)e_rc); \ + l_rc.setEcmdError(e_rc); \ + error_flag=true; \ + break; \ + } \ + FAPI_DBG("Scan0 equivalent reset of 0x%08llx to 0x%08X", \ + _mi_address, _mi_reset_value); \ + l_rc = fapiPutScom(_mi_target, _mi_address, _mi_buffer); \ + if(!l_rc.ok()) \ + { \ + FAPI_ERR("PutScom error to address 0x%08llx", _mi_address); \ + error_flag=true; \ + break; \ + } \ +} +// PCBS EX address +#define EXADDR(_mi_address, _mi_ex){ \ + _mi_address + (_mi_ex * 0x01000000) \ +} +//------------------------------------------------------------------------------ +//Start scan zero value +//------------------------------------------------------------------------------ +/// \todo Review scan0 values + +CONST_UINT64_T( PMGP0_REG_0x100F0100_scan0 , ULL(0x8030010C21000000) ); +CONST_UINT64_T( PMGP1_REG_0x100F0103_scan0 , ULL(0x6C00000000000000) ); +CONST_UINT64_T( EX_PFVddCntlStat_REG_0x100F0106_scan0 , ULL(0x0A00000000000000) ); +CONST_UINT64_T( EX_PFVcsCntlStat_REG_0x100F010E_scan0 , ULL(0xFFF0FFF080800000) ); //1000 0000 1000 000 +CONST_UINT64_T( EX_PMErrMask_REG_0x100F010A_scan0 , ULL(0x00000000)); +CONST_UINT64_T( EX_PMSpcWkupFSP_REG_0x100F010B_scan0 , ULL(0x00000000)); +CONST_UINT64_T( EX_PMSpcWkupOCC_REG_0x100F010C_scan0 , ULL(0x00000000)); // This is different than the hardware +CONST_UINT64_T( EX_PMSpcWkupPHYP_REG_0x100F010D_scan0 , ULL(0x00000000)); +CONST_UINT64_T( EX_CorePFPUDly_REG_0x100F012C_scan0 , ULL(0x00000000)); +CONST_UINT64_T( EX_CorePFPDDly_REG_0x100F012D_scan0 , ULL(0x00000000)); +CONST_UINT64_T( EX_CorePFVRET_REG_0x100F0130_scan0 , ULL(0x00000000)); +CONST_UINT64_T( EX_ECOPFPUDly_REG_0x100F014C_scan0 , ULL(0x00000000)); +CONST_UINT64_T( EX_ECOPFPDDly_REG_0x100F014D_scan0 , ULL(0x00000000)); +CONST_UINT64_T( EX_ECOPFVRET_REG_0x100F0150_scan0 , ULL(0x00000000)); +CONST_UINT64_T( EX_FREQCNTL_0x100F0151_scan0 , ULL(0x32320000)); // "0011 0010 0011 0010 000000000000" ; +CONST_UINT64_T( EX_DPLL_CPM_PARM_REG_0x100F0152_scan0 , ULL(0x00000200)); // "0000 0000 0000 0000 0000 0010 0000000" ; +CONST_UINT64_T( EX_PCBS_iVRM_Control_Status_Reg_0x100F0154_scan0 , ULL(0x00000000)); +CONST_UINT64_T( EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155_scan0 , ULL(0x00000000)); +CONST_UINT64_T( EX_PCBSPM_MODE_REG_0x100F0156_scan0 , ULL(0x01000000)); //"0000 0001 0000 0000 00" ; +CONST_UINT64_T( EX_PCBS_Power_Management_Control_Reg_0x100F0159_scan0 , ULL(0x00000000)) ; +CONST_UINT64_T( EX_PCBS_PMC_VF_CTRL_REG_0x100F015A_scan0 , ULL(0x00000000)); +CONST_UINT64_T( EX_PCBS_UNDERVOLTING_REG_0x100F015B_scan0 , ULL(0x00000000)); +CONST_UINT64_T( EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C_scan0 , ULL(0x00000000)); +CONST_UINT64_T( EX_PCBS_Power_Management_Bounds_Reg_0x100F015D_scan0 , ULL(0x807F0000)); +CONST_UINT64_T( EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E_scan0 , ULL(0x00000000)) ; +CONST_UINT64_T( EX_PCBS_Pstate_Step_Target_Register_0x100F0160_scan0 , ULL(0x00000000)) ; +CONST_UINT64_T( EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162_scan0 , ULL(0x00000000)); +CONST_UINT64_T( EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163_scan0 , ULL(0x00000000)); +CONST_UINT64_T( EX_PCBS_OCC_Heartbeat_Reg_0x100F0164_scan0 , ULL(0x00000000)); +CONST_UINT64_T( EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165_scan0 , ULL(0x4000000000000000)) ; //"0100 00000000000000000000000000000000000000" ; +CONST_UINT64_T( EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166_scan0 , ULL(0x00000000)); +CONST_UINT64_T( EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168_scan0 , ULL(0x00000000)); + + // End scan zero value // ---------------------------------------------------------------------- // Global variables // ---------------------------------------------------------------------- -//fapi::ReturnCode rc; - -//uint32_t SIM_CYCLE_POLL_DELAY = 200000; // simulation cycle delay between status register polls -//uint32_t MAX_POLL_ATTEMPTS = 5; // maximum number of status poll attempts to make before giving up - - // ---------------------------------------------------------------------- // Function prototypes // ---------------------------------------------------------------------- -//ReturnCode p8_pcbs_init_core(Target &i_target, uint64_t mode, struct_pcbs_val_init_type pcbs_val_init); -//ReturnCode pgp_initializeMulticast( Target &i_target, bool VERBOSE ); - -fapi::ReturnCode delay( uint64_t i_nanoSeconds, uint64_t i_simCycles ); - -/// \todo : PSAFE, PUV_MIN, PUV_MAX - Attributes defined as unint8 but should be int8 -typedef struct { - uint8_t ivrms_enabled; // ATTR_IVRMS_ENABLED - uint8_t PSAFE; // ATTR_SAFE_PSTATE PSAFE - uint8_t PUV_MIN; // ATTR_PSTATE_UNDERVOLTING_MINIMUM - uint8_t PUV_MAX; // ATTR_PSTATE_UNDERVOLTING_MAXIMUM - uint32_t MAX_PSAFE_FSM_LOOPS; // max number of times PCBS-PMSR has been checked - uint32_t MAX_DELAY; // max number of Delay - uint32_t MAX_SIM_CYCLES; // max number of SimCycles (will be used when FSP is target) - int8_t GLOBAL_ACTUAL_PSTATE; // Global Actual PSTATE - int8_t MIN_PSTATE; // - int8_t FNOM; // - uint8_t DPLL_FMIN; // - uint8_t DPLL_FMAX; // - int8_t PMIN_CLIP; // - int8_t PMAX_CLIP; // - uint8_t KUV; // -} struct_pcbs_val_init_type; +// Reset function +fapi::ReturnCode +p8_pcbs_init_reset ( const fapi::Target& i_target, + struct_pcbs_val_init_type& pcbs_val_init); +// Config function +fapi::ReturnCode +p8_pcbs_init_config ( const fapi::Target& i_target); + +// Init function +fapi::ReturnCode +p8_pcbs_init_init ( const fapi::Target& i_target); +// SCAN0 function +fapi::ReturnCode +p8_pcbs_init_scan0(const Target &i_target, uint8_t i_ex_number); // ---------------------------------------------------------------------- // Function definitions // ---------------------------------------------------------------------- -// Reset function -fapi::ReturnCode p8_pcbs_init_reset (const fapi::Target& i_target, uint32_t i_mode, struct_pcbs_val_init_type pcbs_val_init); -// Config function -fapi::ReturnCode p8_pcbs_init_config (const fapi::Target& i_target) ; -// INIT -fapi::ReturnCode p8_pcbs_init_init (const fapi::Target& i_target) ; +// ---------------------------------------------------------------------- +/** + * p8_pcbs_init calls the underlying routine based on mode parameter + * + * @param[in] i_target Chip target + * @param[in] mode Control mode for the procedure + * PM_INIT, PM_CONFIG, PM_RESET + * + * @retval ECMD_SUCCESS + * @retval ERROR defined in xml + */ +fapi::ReturnCode +p8_pcbs_init( const Target& i_target, uint32_t i_mode) +{ + fapi::ReturnCode l_rc; + //Declare parms struct + struct_pcbs_val_init_type pcbs_val_init; + FAPI_INF("Executing p8_pcbs_init in mode %x", i_mode); + do + { + + if ( i_mode == PM_CONFIG ) + { + l_rc=p8_pcbs_init_config(i_target); + if (l_rc) + { + FAPI_ERR("p8_pcbs_init_config failed. With l_rc = 0x%x", (uint32_t)l_rc); + break; + } + + } + else if ( i_mode == PM_INIT ) + { + l_rc=p8_pcbs_init_init(i_target); + if (l_rc) + { + FAPI_ERR("p8_pcbs_init_init failed. With l_rc = 0x%x", (uint32_t)l_rc); + break; + } + } + else if ( i_mode == PM_RESET ) + { + // ---------------------------------------------------------------------- + // Assign default values + // ---------------------------------------------------------------------- + + /// \todo CHECK: Review those defaults + pcbs_val_init.MAX_PSAFE_FSM_LOOPS = 20; // PMSR poll attempts + pcbs_val_init.MAX_DELAY = 1000000; // in ns; 1ms + pcbs_val_init.MAX_SIM_CYCLES = 1000; + pcbs_val_init.GLOBAL_ACTUAL_PSTATE = -128; // Global Actual PSTATE + pcbs_val_init.MIN_PSTATE = -128 ; // Default + pcbs_val_init.FNOM = 128; // Default + pcbs_val_init.DPLL_FMIN = 50; // \WHAT? + pcbs_val_init.DPLL_FMAX = 50; // \WHAT? + pcbs_val_init.PMIN_CLIP = -128 ; // Default + pcbs_val_init.PMAX_CLIP = 127 ; // Default + pcbs_val_init.KUV = 0; // Default + pcbs_val_init.ivrms_enabled = 1 ; + + // l_rc = FAPI_ATTR_GET( ATTR_PM_IVRMS_ENABLED, + // &i_target, + // pcbs_val_init.ivrms_enabled); + if (l_rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_PM_IVRMS_ENABLED with rc = 0x%x", (uint32_t)l_rc); + break; + } + +// l_rc = FAPI_ATTR_GET( ATTR_PM_SAFE_PSTATE, +// &i_target, +// pcbs_val_init.PSAFE); + if (l_rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_PM_SAFE_PSTATE with rc = 0x%x", (uint32_t)l_rc); + break; + } + +// l_rc = FAPI_ATTR_GET( ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM, +// &i_target, +// pcbs_val_init.PUV_MIN); + if (l_rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM with rc = 0x%x", (uint32_t)l_rc); + break; + } + + // l_rc = FAPI_ATTR_GET( ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM, +// &i_target, +// pcbs_val_init.PUV_MAX); + if (l_rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM with rc = 0x%x", (uint32_t)l_rc); + break; + } + + l_rc = p8_pcbs_init_reset( i_target, pcbs_val_init); + if (l_rc) + { + FAPI_ERR("p8_pcbs_init_reset failed. With l_rc = 0x%x", (uint32_t)l_rc); + break; + } + } + else + { + FAPI_ERR("Unknown mode passed to p8_pcbs_init. Mode %x ....", i_mode); + //TODO RTC: 71328 - unused variable const uint64_t& MODE = (uint32_t)i_mode; + FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PCBS_CODE_BAD_MODE); + } + } while(0); + FAPI_INF("Exiting p8_pcbs_init ..."); -// ---------------------------------------------------------------------- -// p8_pcbs_init wrapper to fetch the attributes and pass it on to p8_pcbs_init_core -// ---------------------------------------------------------------------- -//ReturnCode p8_pcbs_init( Target &i_target, std::list<uint32_t> &args ) -fapi::ReturnCode p8_pcbs_init( - const Target& i_target, - uint32_t i_mode) -{ - fapi::ReturnCode rc; - - - - //Declare parms struct - struct_pcbs_val_init_type pcbs_val_init; - - - FAPI_DBG(""); - FAPI_DBG("*************************************"); - FAPI_INF("Executing p8_pcbs_init"); - FAPI_DBG("*************************************"); - FAPI_DBG(""); - - FAPI_INF("\t MODE: %d ", i_mode); - - - - - if ( i_mode == PM_CONFIG ) { - FAPI_DBG("*************************************"); - FAPI_INF("MODE: CONFIG , Calling: p8_pcbs_init_config "); - FAPI_DBG("*************************************"); - - rc=p8_pcbs_init_config(i_target); - if (rc) { - FAPI_ERR(" p8_pcbs_init_config failed. With rc = 0x%x", (uint32_t)rc); return rc; - } - - } else if ( i_mode == PM_INIT ) { - FAPI_DBG("*************************************"); - FAPI_INF("MODE: INIT , Calling: p8_pcbs_init_init"); - FAPI_DBG("*************************************"); - - rc=p8_pcbs_init_init(i_target); - if (rc) { - FAPI_ERR(" p8_pcbs_init_init failed. With rc = 0x%x", (uint32_t)rc); return rc; - } - - } else if ( i_mode == PM_RESET ) { - FAPI_DBG("*************************************"); - FAPI_INF("MODE: RESET"); - FAPI_DBG("*************************************"); - - - - // ****************************************************************** - - - - //Assign values to parms in struct - // should come from MRWB - // pcbs_val_init.ivrms_enabled = 1; // ATTR_PM_IVRMS_ENABLED VENICE or SALERNO - // pcbs_val_init.PSAFE = -128 ; // ATTR_PM_SAFE_PSTATE PSAFE - // pcbs_val_init.PUV_MIN = -128 ; // ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM - // pcbs_val_init.PUV_MAX = -128 ; // ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM - - + return l_rc; - rc = FAPI_ATTR_GET(ATTR_PM_IVRMS_ENABLED, &i_target, pcbs_val_init.ivrms_enabled); if (rc) return rc; //VENICE or SALERNO - rc = FAPI_ATTR_GET(ATTR_PM_SAFE_PSTATE, &i_target, pcbs_val_init.PSAFE); if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM, &i_target, pcbs_val_init.PUV_MIN); if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM, &i_target, pcbs_val_init.PUV_MAX); if (rc) return rc; - - - - - - // ---------------------------------------------------------------------- - // Assign default values - // ---------------------------------------------------------------------- - - /// \todo CHECK: Review those defaults - pcbs_val_init.MAX_PSAFE_FSM_LOOPS = 20; // max number of times PCBS-PMSR has been checked - pcbs_val_init.MAX_DELAY = 1000000; - pcbs_val_init.MAX_SIM_CYCLES = 1000; - pcbs_val_init.GLOBAL_ACTUAL_PSTATE = -128 ; // Global Actual PSTATE default - pcbs_val_init.MIN_PSTATE = -128 ; // Default - pcbs_val_init.FNOM = 128; // Default - pcbs_val_init.DPLL_FMIN = 50; // - pcbs_val_init.DPLL_FMAX = 50; // Default - pcbs_val_init.PMIN_CLIP = -128 ; // Default - pcbs_val_init.PMAX_CLIP = 127 ; // Default - pcbs_val_init.KUV = 0; // Default - - // ****************************************************************** - - - - - - FAPI_DBG("*************************************"); - FAPI_INF("Calling: p8_pcbs_init_reset"); - FAPI_DBG("*************************************"); - rc = p8_pcbs_init_reset( i_target, i_mode, pcbs_val_init); - - if (rc) { - FAPI_ERR(" p8_pcbs_init_reset failed. With rc = 0x%x", (uint32_t)rc); return rc; - } - - - } else { - FAPI_DBG("*************************************"); - FAPI_ERR("Unknown mode passed to p8_pcbs_init. Mode %x ....\n", i_mode); - FAPI_SET_HWP_ERROR(rc, RC_PROC_PCBS_CODE_BAD_MODE); - FAPI_DBG("*************************************"); - - }; - - - -FAPI_INF("\t MODE: %d ", i_mode); - - return rc; - -} - - - -uint8_t convert_delay_to_value (uint32_t i_delay, uint32_t i_attr_proc_nest_frequency) -{ - uint8_t pfet_delay_value; - float dly; - //attr_proc_nest_frequency [MHz] - //delay [ns] - //pfet_delay_value = 15 - log2( i_delay * i_attr_proc_nest_frequency/1000); - // since log2 function is not available, this is done manual - //pfet_delay_value = 15 - log2( dly ); - dly = ( i_delay * i_attr_proc_nest_frequency/1000); - - if (dly <= 1.4 ) { pfet_delay_value = 15 - 0 ; } - else if ( ( 1.4 < dly ) && ( dly <= 2.8 ) ) { pfet_delay_value = 15 - 1 ; } - else if ( ( 2.8 < dly ) && ( dly <= 5.6 ) ) { pfet_delay_value = 15 - 2 ; } - else if ( ( 5.6 < dly ) && ( dly <= 11.5 ) ) { pfet_delay_value = 15 - 3 ; } - else if ( ( 11.5 < dly ) && ( dly <= 23 ) ) { pfet_delay_value = 15 - 4 ; } - else if ( ( 23 < dly ) && ( dly <= 46 ) ) { pfet_delay_value = 15 - 5 ; } - else if ( ( 46 < dly ) && ( dly <= 92 ) ) { pfet_delay_value = 15 - 6 ; } - else if ( ( 92 < dly ) && ( dly <= 182 ) ) { pfet_delay_value = 15 - 7 ; } - else if ( ( 182 < dly ) && ( dly <= 364 ) ) { pfet_delay_value = 15 - 8 ; } - else if ( ( 364 < dly ) && ( dly <= 728 ) ) { pfet_delay_value = 15 - 9 ; } - else if ( ( 728 < dly ) && ( dly <= 1456 ) ) { pfet_delay_value = 15 - 10 ; } - else if ( ( 1456 < dly ) && ( dly <= 2912 ) ) { pfet_delay_value = 15 - 11 ; } - else if ( ( 2912 < dly ) && ( dly <= 5824 ) ) { pfet_delay_value = 15 - 12 ; } - else if ( ( 5824 < dly ) && ( dly <= 11648 ) ) { pfet_delay_value = 15 - 13 ; } - else if ( ( 11648 < dly ) && ( dly <= 23296 ) ) { pfet_delay_value = 15 - 14 ; } - else if ( 23296 < dly ) { pfet_delay_value = 15 - 15 ; } - else { pfet_delay_value = 15 - 15 ; } ; - - - - - return (pfet_delay_value); } -// Transform Platform Attribute for PCBS to Feature Attributes +//------------------------------------------------------------------------------ +/** + * Transform Platform Attribute for PCBS to Feature Attributes + * + * @param[in] i_target Chip target + * + * @retval ECMD_SUCCESS + * @retval ERROR defined in xml + */ fapi::ReturnCode -p8_pcbs_init_config(const Target& i_target) +p8_pcbs_init_config(const Target& i_target) { - fapi::ReturnCode rc; - - /// PState translation - /// convert_safe_freq() - With ATTR_PM_SAFE_FREQUENCY (binary in MHz) and ATTR_PM_PSTATE0_FREQUENCY (binary in Mhz) produce ATTR_PM_SAFE_PSTATE - /// Resonant Clocking settings (band definitions from frequency to Pstate) - /// convert_resclk_freqs_to_pstates() - Convert the following frequency platform attributes (binary in MHz) to feature Pstate attributes. The conversion uses ATTR_PM_PSTATE0_FREQUENCY. - /// Input platform attributes - /// ATTR_PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY - /// ATTR_PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY - /// ATTR_PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY - /// ATTR_PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY - /// ATTR_PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY - /// output feature attributes - /// ATTR_PM_RESONANT_CLOCK_FULL_CSB_PSTATE - /// ATTR_PM_RESONANT_CLOCK_LFRLOW_PSTATE - /// ATTR_PM_RESONANT_CLOCK_LFRUPPER_PSTATE - /// ATTR_PM_RESONANT_CLOCK_HFRLOW_PSTATE - /// ATTR_PM_RESONANT_CLOCK_HFRHIGH_PSTATE - /// PFET Sequencing Delays - /// convert_pfet_delays() - Convert the following delays from platform attributes (binary in nanoseconds) to PFET delay value feature attributes. The conversion uses ATTR_PROC_NEST_FREQUENCY. - /// Input platform attributes - /// ATTR_PM_PFET_POWERUP_CORE_DELAY0 - /// ATTR_PM_PFET_POWERUP_CORE_DELAY1 - /// ATTR_PM_PFET_POWERUP_ECO_DELAY0 - /// ATTR_PM_PFET_POWERUP_ECO_DELAY1 - /// ATTR_PM_PFET_POWERDOWN_CORE_DELAY0 - /// ATTR_PM_PFET_POWERDOWN_CORE_DELAY1 - /// ATTR_PM_PFET_POWERDOWN_ECO_DELAY0 - /// ATTR_PM_PFET_POWERDOWN_ECO_DELAY1 - /// output feature attributes - /// ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE - /// ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE - /// ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT - /// ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE - /// ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE - /// ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT - /// ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE - /// ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE - /// ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT - /// ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE - /// ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE - /// ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT - - // ****************************************************************** - // attributes variables - uint32_t attr_proc_refclk_frequency ; - //uint32_t attr_pm_pstate0_frequency; - //uint8_t attr_pm_safe_pstate; - //uint32_t attr_pm_safe_frequency; - - uint32_t attr_pm_pfet_powerup_core_delay0; - uint32_t attr_pm_pfet_powerup_core_delay1; - uint32_t attr_pm_pfet_powerdown_core_delay0; - uint32_t attr_pm_pfet_powerdown_core_delay1; - uint32_t attr_pm_pfet_powerup_eco_delay0; - uint32_t attr_pm_pfet_powerup_eco_delay1; - uint32_t attr_pm_pfet_powerdown_eco_delay0; - uint32_t attr_pm_pfet_powerdown_eco_delay1; - - uint8_t attr_pm_pfet_powerup_core_delay0_value; - uint8_t attr_pm_pfet_powerup_core_delay1_value; - uint32_t attr_pm_pfet_powerup_core_sequence_delay_select; - uint8_t attr_pm_pfet_powerdown_core_delay0_value; - uint8_t attr_pm_pfet_powerdown_core_delay1_value; - uint32_t attr_pm_pfet_powerdown_core_sequence_delay_select; - uint8_t attr_pm_pfet_powerup_eco_delay0_value; - uint8_t attr_pm_pfet_powerup_eco_delay1_value; - uint32_t attr_pm_pfet_powerup_eco_sequence_delay_select; - uint8_t attr_pm_pfet_powerdown_eco_delay0_value; - uint8_t attr_pm_pfet_powerdown_eco_delay1_value; - uint32_t attr_pm_pfet_powerdown_eco_sequence_delay_select; - - - - // ****************************************************************** - // Get Attributes for pFET Delay - // ****************************************************************** - // ****************************************************************** - // set defaults if not available - /// \todo refclk ATTR_PROC_REFCLK_FREQUENCY OR ATTR_PROC_NEST_FREQUENCY ???? - attr_proc_refclk_frequency = 225; - // attr_pm_pfet_powerup_core_delay0 = 100; - // attr_pm_pfet_powerup_core_delay1 = 100; - // attr_pm_pfet_powerdown_core_delay0 = 100; - // attr_pm_pfet_powerdown_core_delay1 = 100; - // attr_pm_pfet_powerup_eco_delay0 = 100; - // attr_pm_pfet_powerup_eco_delay1 = 100; - // attr_pm_pfet_powerdown_eco_delay0 = 100; - // attr_pm_pfet_powerdown_eco_delay1 = 100; - - - - - /// ---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_PFET_POWERUP_CORE_DELAY0, &i_target, attr_pm_pfet_powerup_core_delay0); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERUP_CORE_DELAY0 with rc = 0x%x", (uint32_t)rc); return rc; } - - /// ---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_PFET_POWERUP_CORE_DELAY1, &i_target, attr_pm_pfet_powerup_core_delay1); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERUP_CORE_DELAY1 with rc = 0x%x", (uint32_t)rc); return rc; } - - /// ---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_PFET_POWERDOWN_CORE_DELAY0, &i_target, attr_pm_pfet_powerdown_core_delay0); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERDOWN_CORE_DELAY0 with rc = 0x%x", (uint32_t)rc); return rc; } - - /// ---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_PFET_POWERDOWN_CORE_DELAY1, &i_target, attr_pm_pfet_powerdown_core_delay1); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERDOWN_CORE_DELAY1 with rc = 0x%x", (uint32_t)rc); return rc; } - - /// ---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_PFET_POWERUP_ECO_DELAY0, &i_target, attr_pm_pfet_powerup_eco_delay0); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERUP_ECO_DELAY0 with rc = 0x%x", (uint32_t)rc); return rc; } - - /// ---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_PFET_POWERUP_ECO_DELAY1, &i_target, attr_pm_pfet_powerup_eco_delay1); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERUP_ECO_DELAY1 with rc = 0x%x", (uint32_t)rc); return rc; } - - /// ---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_PFET_POWERDOWN_ECO_DELAY0, &i_target, attr_pm_pfet_powerdown_eco_delay0); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERDOWN_ECO_DELAY0 with rc = 0x%x", (uint32_t)rc); return rc; } - - /// ---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_PFET_POWERDOWN_ECO_DELAY1, &i_target, attr_pm_pfet_powerdown_eco_delay1); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERDOWN_ECO_DELAY1 with rc = 0x%x", (uint32_t)rc); return rc; } - - + fapi::ReturnCode l_rc; - - - // ****************************************************************** - // Calculates Delay values out of pFET Delays - // ****************************************************************** - FAPI_DBG("*************************************"); - FAPI_DBG("Calculates Delay values out of pFET Delays"); - FAPI_DBG("*************************************"); - FAPI_DBG("*************************************"); - FAPI_DBG("Calculate:"); - FAPI_DBG(" ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE"); - FAPI_DBG(" ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE"); - FAPI_DBG(" ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE"); - FAPI_DBG(" ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE"); - FAPI_DBG(" ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE"); - FAPI_DBG(" ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE"); - FAPI_DBG(" ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE"); - FAPI_DBG(" ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE"); - FAPI_DBG("using:"); - FAPI_DBG(" ATTR_PM_PFET_POWERUP_CORE_DELAY0"); - FAPI_DBG(" ATTR_PM_PFET_POWERUP_CORE_DELAY1"); - FAPI_DBG(" ATTR_PM_PFET_POWERUP_ECO_DELAY0"); - FAPI_DBG(" ATTR_PM_PFET_POWERUP_ECO_DELAY1"); - FAPI_DBG(" ATTR_PM_PFET_POWERDOWN_CORE_DELAY0"); - FAPI_DBG(" ATTR_PM_PFET_POWERDOWN_CORE_DELAY1"); - FAPI_DBG(" ATTR_PM_PFET_POWERDOWN_ECO_DELAY0"); - FAPI_DBG(" ATTR_PM_PFET_POWERDOWN_ECO_DELAY1"); - FAPI_DBG("**************************************************************************"); - FAPI_DBG(" Set ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT to 0 (choosing always pfetdelay0 )"); - FAPI_DBG(" Set ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT to 0 (choosing always pfetdelay0 )"); - FAPI_DBG(" Set ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT to 0 (choosing always pfetdelay0 )"); - FAPI_DBG(" Set ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT to 0 (choosing always pfetdelay0 )"); - FAPI_DBG("**************************************************************************"); - - - - - //value = 15 - log2(delay * refclk); - attr_pm_pfet_powerup_core_delay0_value = convert_delay_to_value(attr_pm_pfet_powerup_core_delay0, attr_proc_refclk_frequency); - attr_pm_pfet_powerup_core_delay1_value = convert_delay_to_value(attr_pm_pfet_powerup_core_delay1, attr_proc_refclk_frequency); - attr_pm_pfet_powerdown_core_delay0_value = convert_delay_to_value(attr_pm_pfet_powerdown_core_delay0 , attr_proc_refclk_frequency); - attr_pm_pfet_powerdown_core_delay1_value = convert_delay_to_value(attr_pm_pfet_powerdown_core_delay1 , attr_proc_refclk_frequency); - attr_pm_pfet_powerup_eco_delay0_value = convert_delay_to_value(attr_pm_pfet_powerup_eco_delay0 , attr_proc_refclk_frequency); - attr_pm_pfet_powerup_eco_delay1_value = convert_delay_to_value(attr_pm_pfet_powerup_eco_delay1 , attr_proc_refclk_frequency); - attr_pm_pfet_powerdown_eco_delay0_value = convert_delay_to_value(attr_pm_pfet_powerdown_eco_delay0 , attr_proc_refclk_frequency); - attr_pm_pfet_powerdown_eco_delay1_value = convert_delay_to_value(attr_pm_pfet_powerdown_eco_delay1 , attr_proc_refclk_frequency); - - attr_pm_pfet_powerup_core_sequence_delay_select = 0; // Choosing always delay0 - attr_pm_pfet_powerdown_core_sequence_delay_select = 0; - attr_pm_pfet_powerup_eco_sequence_delay_select = 0; - attr_pm_pfet_powerdown_eco_sequence_delay_select = 0; - - - - - - - FAPI_DBG("*************************************"); - FAPI_DBG("attr_pm_pfet_powerup_core_delay0_value : %X", attr_pm_pfet_powerup_core_delay0_value); - FAPI_DBG("attr_pm_pfet_powerup_core_delay1_value : %X", attr_pm_pfet_powerup_core_delay1_value); - FAPI_DBG("attr_pm_pfet_powerup_core_sequence_delay_select : %X", attr_pm_pfet_powerup_core_sequence_delay_select); - FAPI_DBG("attr_pm_pfet_powerdown_core_delay0_value : %X", attr_pm_pfet_powerdown_core_delay0_value); - FAPI_DBG("attr_pm_pfet_powerdown_core_delay1_value : %X", attr_pm_pfet_powerdown_core_delay1_value); - FAPI_DBG("attr_pm_pfet_powerdown_core_sequence_delay_select : %X", attr_pm_pfet_powerdown_core_sequence_delay_select); - FAPI_DBG("attr_pm_pfet_powerup_eco_delay0_value : %X", attr_pm_pfet_powerup_eco_delay0_value); - FAPI_DBG("attr_pm_pfet_powerup_eco_delay1_value : %X", attr_pm_pfet_powerup_eco_delay1_value); - FAPI_DBG("attr_pm_pfet_powerup_eco_sequence_delay_select : %X", attr_pm_pfet_powerup_eco_sequence_delay_select); - FAPI_DBG("attr_pm_pfet_powerdown_eco_delay0_value : %X", attr_pm_pfet_powerdown_eco_delay0_value); - FAPI_DBG("attr_pm_pfet_powerdown_eco_delay1_value : %X", attr_pm_pfet_powerdown_eco_delay1_value); - FAPI_DBG("attr_pm_pfet_powerdown_eco_sequence_delay_select : %X", attr_pm_pfet_powerdown_eco_sequence_delay_select); - FAPI_DBG("*************************************"); - - - - // ****************************************************************** - // Set Attributes for PFET delays - // ****************************************************************** - - - /// \todo DOUBLE Check ... Shouldn't the DELAY_SELECT -values be only readable??? read above and not written here??? - /// \todo ATTR_PM_PFET_POWERUP/DOWN_CORE/ECO_DELAY0/1_VALUE are defined in the spreadsheet as not writeable ???? - /// ---------------------------------------------------------- - /* rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE, &i_target, attr_pm_pfet_powerup_core_delay0_value); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE with rc = 0x%x", (uint8_t)rc); return rc; } - - /// ---------------------------------------------------------- - rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE, &i_target, attr_pm_pfet_powerup_core_delay1_value); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE with rc = 0x%x", (uint8_t)rc); return rc; } - - /// ---------------------------------------------------------- - rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT, &i_target, attr_pm_pfet_powerup_core_sequence_delay_select); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT with rc = 0x%x", (uint32_t)rc); return rc; } - - /// ---------------------------------------------------------- - rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE, &i_target, attr_pm_pfet_powerdown_core_delay0_value); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE with rc = 0x%x", (uint8_t)rc); return rc; } - - /// ---------------------------------------------------------- - rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE, &i_target, attr_pm_pfet_powerdown_core_delay1_value); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE with rc = 0x%x", (uint8_t)rc); return rc; } + /// Function moved in p8_pfet_int.C + /// FAPI_DBG("*************************************"); + /// FAPI_INF("p8_pcbs_init_config beginning ..."); + /// FAPI_DBG("*************************************"); + /// - /// ---------------------------------------------------------- - rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT, &i_target, attr_pm_pfet_powerdown_core_sequence_delay_select); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT with rc = 0x%x", (uint32_t)rc); return rc; } + return l_rc; - /// ---------------------------------------------------------- - rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE, &i_target, attr_pm_pfet_powerup_eco_delay0_value); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE with rc = 0x%x", (uint8_t)rc); return rc; } - - /// ---------------------------------------------------------- - rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE, &i_target, attr_pm_pfet_powerup_eco_delay1_value); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE with rc = 0x%x", (uint8_t)rc); return rc; } - - /// ---------------------------------------------------------- - rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT, &i_target, attr_pm_pfet_powerup_eco_sequence_delay_select); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT with rc = 0x%x", (uint32_t)rc); return rc; } - - /// ---------------------------------------------------------- - rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE, &i_target, attr_pm_pfet_powerdown_eco_delay0_value); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE with rc = 0x%x", (uint8_t)rc); return rc; } - - /// ---------------------------------------------------------- - rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE, &i_target, attr_pm_pfet_powerdown_eco_delay1_value); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE with rc = 0x%x", (uint8_t)rc); return rc; } - - /// ---------------------------------------------------------- - rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT, &i_target, attr_pm_pfet_powerdown_eco_sequence_delay_select); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT with rc = 0x%x", (uint32_t)rc); return rc; } - */ - - - - - - - return rc; - } //end CONFIG - +//------------------------------------------------------------------------------ +/** + * Initialize the PCBS-PM macro for all functional and enabled EX chiplets + * + * @param[in] i_target Chip target + * + * @retval ECMD_SUCCESS + * @retval ERROR defined in xml + */ fapi::ReturnCode -p8_pcbs_init_init(const Target& i_target) +p8_pcbs_init_init(const Target& i_target) { - fapi::ReturnCode rc; - - - uint32_t l_rc; // local returncode - - ecmdDataBufferBase data(64); - ecmdDataBufferBase mask(64); - - - // Variables - std::vector<fapi::Target> l_exChiplets; - fapi::TargetState l_state = TARGET_STATE_FUNCTIONAL; // TARGET_STATE_PRESENT or TARGET_STATE_FUNCTIONAL. It just depends on what you want to do. - - uint8_t l_functional = 0; - uint8_t l_ex_number = 0; - - - - uint8_t pm_sleep_type; - uint8_t pm_sleep_entry ; - uint8_t pm_sleep_exit ; - uint8_t pm_winkle_type ; - uint8_t pm_winkle_entry ; - uint8_t pm_winkle_exit ; - - - - - // ****************************************************************** - // Getting Attributes - // ****************************************************************** - // pm_sleep_entry = 0; //0=assisted, 1=HW - // pm_sleep_exit = 0; //0=assisted, 1=HW - // pm_sleep_type = 1; //0=fast, 1=deep -/// \todo missing attributes - pm_winkle_entry = 0; - pm_winkle_exit = 0; - // pm_winkle_type = 1; - - - - rc = FAPI_ATTR_GET(ATTR_PM_SLEEP_TYPE, &i_target, pm_sleep_type); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SLEEP_TYPE with rc = 0x%x", (uint32_t)rc); return rc; } - rc = FAPI_ATTR_GET(ATTR_PM_SLEEP_ENTRY, &i_target, pm_sleep_entry); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SLEEP_ENTRY with rc = 0x%x", (uint32_t)rc); return rc; } - rc = FAPI_ATTR_GET(ATTR_PM_SLEEP_EXIT, &i_target, pm_sleep_exit); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SLEEP_EXIT with rc = 0x%x", (uint32_t)rc); return rc; } - rc = FAPI_ATTR_GET(ATTR_PM_WINKLE_TYPE, &i_target, pm_winkle_type); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_WINKLE_TYPE with rc = 0x%x", (uint32_t)rc); return rc; } -// rc = FAPI_ATTR_GET("ATTR_PM_WINKLE_ENTRY", &i_target,(unit8_t) pm_winkle_entry); -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_WINKLE_ENTRY with rc = 0x%x", (uint32_t)rc); return rc; } -// rc = FAPI_ATTR_GET("ATTR_PM_WINKLE_EXIT", &i_target,(unit8_t) pm_winkle_exit); -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_WINKLE_EXIT with rc = 0x%x", (uint32_t)rc); return rc; } - - - - - - - - - - - - rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_EX_CHIPLET, l_exChiplets, l_state); if (rc) return rc; - FAPI_DBG(" chiplet vector size => %u", l_exChiplets.size()); - - - - - - // For each chiplet - - for (uint8_t c=0; c< l_exChiplets.size(); c++) { - FAPI_DBG("********* ******************* *********"); - FAPI_DBG("\t Loop Variable %d ",c); - FAPI_DBG("********* ******************* *********"); - - rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_exChiplets[c], l_functional); - if (rc) - { - FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL with rc = 0x%x", (uint32_t)rc); - return rc; - } else - { - if (l_functional) - { - // The ex is functional let's build the SCOM address - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[c], l_ex_number); - if (rc) - { - FAPI_ERR("No functional chiplets exist"); - FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)rc); - return rc; - } - else - { - - FAPI_DBG("Core number = %d", l_ex_number); - - // ****************************************************************** - // - // ****************************************************************** - - FAPI_DBG("**************************** *********"); - FAPI_INF("Reset CPM_FILTER_ENABLE"); - FAPI_DBG("**************************** *********"); - - // if debug mode read before - //if (VERBOSE) { - // rc = fapiGetScom(i_target, EX_DPLL_CPM_PARM_REG_0x100F0152 + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; - // FAPI_DBG(" Pre write content of EX_DPLL_CPM_PARM_REG_0x1*0F0152 , Loop: %d : %016llX", c, data.getDoubleWord(0) ); - //} - - // Clear buffer - l_rc = data.flushTo0(); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - - rc = fapiPutScom(i_target, EX_DPLL_CPM_PARM_REG_0x100F0152 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom Content of EX_DPLL_CPM_PARM_REG_0x1*0F0152, Loop: %d failed. With rc = 0x%x", c, (uint32_t)rc); return rc; } - - // if debug mode read back - //if (VERBOSE) { - // rc = fapiGetScom(i_target, EX_DPLL_CPM_PARM_REG_0x100F0152 + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; - // FAPI_DBG(" Post write content of EX_DPLL_CPM_PARM_REG_0x1*0F0152 , Loop: %d : %016llX", c, data.getDoubleWord(0) ); - //} - FAPI_INF ("Reset CPM_FILTER_ENABLE, clear bit 0 of EX_DPLL_CPM_PARM_REG_0x1*0F0152 " ); - - - - - // ****************************************************************** - // - set PMGP1_REG - // ****************************************************************** - - FAPI_INF("\t-----------------------------------------------------"); - FAPI_INF("\tPMGP1_REG Configuration "); - FAPI_INF("\t-----------------------------------------------------"); - FAPI_INF("\t pm_sleep_entry => %d ", pm_sleep_entry ); - FAPI_INF("\t pm_sleep_exit => %d ", pm_sleep_exit ); - FAPI_INF("\t pm_sleep_type => %d ", pm_sleep_type ); - FAPI_INF("\t pm_winkle_entry => %d ", pm_winkle_entry ); - FAPI_INF("\t pm_winkle_exit => %d ", pm_winkle_exit ); - FAPI_INF("\t pm_winkle_type => %d ", pm_winkle_type ); - FAPI_INF("\t " ); - FAPI_INF("\t " ); - FAPI_INF("\t-----------------------------------------------------"); - - - FAPI_DBG("*************************************"); - FAPI_INF("Write to register PMGP1_REG "); - FAPI_DBG("*************************************"); - - - // if debug mode read before - //if (VERBOSE) { - // rc = fapiGetScom(i_target, EX_PMGP1_REG_0_RWXx100F0103 + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; - // FAPI_DBG(" Pre write content of EX_PMGP1_REG_0_RWXx1*0F0103 , Loop: %d : %016llX", c, data.getDoubleWord(0) ); - //} - - if (pm_sleep_entry) { - l_rc = data.flushTo0(); - l_rc |= data.setBit(0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WORx100F0105 + (l_ex_number * 0x01000000) , data); - if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - } else { - l_rc = data.flushTo1(); - l_rc |= data.clearBit(0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WANDx100F0104 + (l_ex_number * 0x01000000) , data); - if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WANDx100F0104) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - }; - - if (pm_sleep_exit) { - l_rc = data.flushTo0(); - l_rc |= data.setBit(1); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WORx100F0105 + (l_ex_number * 0x01000000) , data); - if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - } else { - l_rc = data.flushTo1(); - l_rc |= data.clearBit(1); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WANDx100F0104 + (l_ex_number * 0x01000000) , data); - if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - }; - - if (pm_sleep_type) { - l_rc = data.flushTo0(); - l_rc |= data.setBit(2); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WORx100F0105 + (l_ex_number * 0x01000000) , data); - if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - } else { - l_rc = data.flushTo1(); - l_rc |= data.clearBit(2); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WANDx100F0104 + (l_ex_number * 0x01000000) , data); - if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - }; - - if (pm_winkle_entry) { - l_rc = data.flushTo0(); - l_rc |= data.setBit(3); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WORx100F0105 + (l_ex_number * 0x01000000) , data); - if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - } else { - l_rc = data.flushTo1(); - l_rc |= data.clearBit(3); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WANDx100F0104 + (l_ex_number * 0x01000000) , data); - if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - }; - - if (pm_winkle_exit) { - l_rc = data.flushTo0(); - l_rc |= data.setBit(4); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WORx100F0105 + (l_ex_number * 0x01000000) , data); - if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - } else { - l_rc = data.flushTo1(); - l_rc |= data.clearBit(4); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WANDx100F0104 + (l_ex_number * 0x01000000) , data); - if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - }; - - if (pm_winkle_type) { - l_rc = data.flushTo0(); - l_rc |= data.setBit(5); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WORx100F0105 + (l_ex_number * 0x01000000) , data); - if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - } else { - l_rc = data.flushTo1(); - l_rc |= data.clearBit(5); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WANDx100F0104 + (l_ex_number * 0x01000000) , data); - if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - }; - - - - - // if debug mode read back - //if (VERBOSE) { - // rc = fapiGetScom(i_target, EX_PMGP1_REG_0_RWXx100F0103 + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; - // FAPI_DBG(" Post write content of EX_PMGP1_REG_0_RWXx1*0F0103 , Loop: %d : %016llX", c, data.getDoubleWord(0) ); - //} - - - - - - - FAPI_DBG("*************************************"); - FAPI_INF("Write to Power_Management_Control_Reg "); - FAPI_DBG("*************************************"); - - // if debug mode read before - //if (VERBOSE) { - // rc = fapiGetScom(i_target, EX_PCBS_Power_Management_Control_Reg_0x100F0159 + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; - // FAPI_DBG(" Pre write content of EX_PCBS_Power_Management_Control_Reg_0x1*0F0159 , Loop: %d : %s", c, data.getDoubleWord(0) ); - //} - - // Clear buffer - l_rc = data.flushTo0(); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - rc = fapiPutScom(i_target, EX_PCBS_Power_Management_Control_Reg_0x100F0159 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom Content of EX_PCBS_Power_Management_Control_Reg_0x1*0F0159, Loop: %d failed. With rc = 0x%x", c, (uint32_t)rc); return rc; } - - // if debug mode read back - //if (VERBOSE) { - // rc = fapiGetScom(i_target, EX_PCBS_Power_Management_Control_Reg_0x100F0159 + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; - // FAPI_DBG(" Post write content of EX_PCBS_Power_Management_Control_Reg_0x1*0F0159 , Loop: %d : %s", c, data.getDoubleWord(0) ); - //} - FAPI_INF ("PMCR default value adjustment (Hardware flush 0) of EX_PCBS_Power_Management_Control_Reg_0x1*0F0159 " ); - - - - - FAPI_DBG("*************************************"); - FAPI_INF("Write to Power_Management_Idle_Control_Reg "); - FAPI_DBG("*************************************"); - - // if debug mode read before - //if (VERBOSE) { - // rc = fapiGetScom(i_target, EX_PCBS_Power_Management_Idle_Control_Reg_0x100F0158 + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; - // FAPI_DBG(" Pre write content of EX_PCBS_Power_Management_Idle_Control_Reg_0x1*0F0158 , Loop: %d : %s", c, data.getDoubleWord(0) ); - //} - - // Clear buffer - l_rc = data.flushTo0(); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - - rc = fapiPutScom(i_target, EX_PCBS_Power_Management_Idle_Control_Reg_0x100F0158 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom Content of EX_PCBS_Power_Management_Idle_Control_Reg_0x1*0F0158, Loop: %d failed. With rc = 0x%x", c, (uint32_t)rc); return rc; } - - // if debug mode read back - //if (VERBOSE) { - // rc = fapiGetScom(i_target, EX_PCBS_Power_Management_Idle_Control_Reg_0x100F0158 + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; - // FAPI_DBG(" Post write content of EX_PCBS_Power_Management_Idle_Control_Reg_0x1*0F0158 , Loop: %d : %s", c, data.getDoubleWord(0) ); - //} - - FAPI_INF ("PMCR default value adjustment (Hardware flush 0) of EX_PCBS_Power_Management_Idle_Control_Reg_0x1*0F0158 " ); - - - - - } //ELSE IF functional and ATTR_CHIP_UNIT_POS - } else - { - // EX is not functional - FAPI_DBG("Core number = %d is not functional", c); - } //IF functional - }//ELSE IF ATTR_FUNCTIONAL - - } //END FOR - - return rc; - -} //end INIT - - -ReturnCode -p8_pcbs_init_reset(const Target &i_target, uint32_t i_mode, struct_pcbs_val_init_type pcbs_val_init) -{ - fapi::ReturnCode rc; - uint32_t l_rc; // local returncode - - ecmdDataBufferBase data(64); - ecmdDataBufferBase mask(64); + fapi::ReturnCode l_rc; + uint32_t e_rc; // eCmd returncode + ecmdDataBufferBase data(64); + ecmdDataBufferBase mask(64); // Variables - std::vector<fapi::Target> l_exChiplets; - fapi::TargetState l_state = TARGET_STATE_FUNCTIONAL; // TARGET_STATE_PRESENT or TARGET_STATE_FUNCTIONAL. It just depends on what you want to do. - - uint8_t l_functional = 0; - uint8_t l_ex_number = 0; - - uint32_t loopcount = 0; // number of times PCBS-PMSR has been checked - - const uint32_t SCANZERO = 1; // enable scan-zero loading upfront - - - // ****************************************************************** - // Code starts here - // ****************************************************************** - - rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_EX_CHIPLET, l_exChiplets, l_state); if (rc) return rc; - FAPI_DBG(" chiplet vector size => %u", l_exChiplets.size()); - - - + std::vector<fapi::Target> l_exChiplets; + fapi::TargetState l_state = TARGET_STATE_FUNCTIONAL; + uint8_t l_functional = 0; + uint8_t l_ex_number = 0; + uint64_t address; + //TODO RTC: 71328 - hack to indicate unused + bool __attribute__((unused)) error_flag = false; + + FAPI_INF("p8_pcbs_init_init beginning for target %s ...", i_target.toEcmdString()); + + do + { + l_rc = fapiGetChildChiplets(i_target, + fapi::TARGET_TYPE_EX_CHIPLET, + l_exChiplets, + l_state); + if (l_rc) + { + FAPI_ERR("fapiGetChildChiplets with rc = 0x%x", (uint32_t)l_rc); + break; + } - // For each chiplet - for (uint8_t c=0; c< l_exChiplets.size(); c++) { - FAPI_DBG("********* ******************* *********"); - FAPI_DBG("\t Loop Variable %d ",c); - FAPI_DBG("********* ******************* *********"); - - rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_exChiplets[c], l_functional); - if (rc) - { - FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL with rc = 0x%x", (uint32_t)rc); - return rc; - } else - { - if (l_functional) + FAPI_DBG("chiplet vector size => %u", l_exChiplets.size()); + + // For each chiplet in the functional list + for (uint8_t c=0; c< l_exChiplets.size(); c++) { - // The ex is functional let's build the SCOM address - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[c], l_ex_number); - if (rc) - { - FAPI_ERR("No functional chiplets exist"); - FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)rc); - return rc; - } - else - { - - FAPI_DBG("Core number = %d", l_ex_number); - + FAPI_DBG("\tLoop Variable %d ",c); + + l_rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_exChiplets[c], l_functional); + if (l_rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL with rc = 0x%x", (uint32_t)l_rc); + break; + } + + + if (!l_functional) + { + FAPI_DBG("Core number = %d is not functional", c); + // Iterate + continue; + } + + // The ex is functional let's build the SCOM address + l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[c], l_ex_number); + if (l_rc) + { + FAPI_ERR("No functional chiplets exist"); + FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)l_rc); + break; + } + FAPI_DBG("Core number = %d", l_ex_number); + + // Set DPLL Lock Replacement value (15:23) = 2 (eg bit 22 = 1) + FAPI_INF ("Set DPLL Lock Replacement value of EX_DPLL_CPM_PARM_REG_0x1*0F0152 "); - if (SCANZERO) { - // ****************************************************************** - // initialize all pm_reg with scan-zero values upfront - // ****************************************************************** - FAPI_DBG("***********************************************"); - FAPI_INF(" Set all PCBSLV_PM registers to the scan0 value"); - FAPI_DBG("***********************************************"); - - - /// \todo Review if scan0 values can/should be applied - //l_rc = data.setDoubleWord(0, PMGP0_REG_0x100F0100_scan0); - //if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)rc); rc.setEcmdError(l_rc); return rc; } - //rc = fapiPutScom(i_target, EX_PMGP0_0x100F0100 + (l_ex_number * 0x01000000), data ); - //if (l_rc) { FAPI_ERR("fapiGetScom(PMGP0_REG_0_RWXx1*0F0100) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - // Set in Multicast section above - //l_rc = data.setDoubleWord(0, PMGP1_REG_0x100F0103_scan0); - //if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)rc); rc.setEcmdError(l_rc); return rc; } - //rc = fapiPutScom(i_target, EX_PMGP1_REG_0_RWXx100F0103 + (l_ex_number * 0x01000000), data ); - //if (l_rc) { FAPI_ERR("fapiGetScom(PMGP1_REG_0_RWXx1*0F0103) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - l_rc = data.setDoubleWord(0, EX_PFVddCntlStat_REG_0x100F0106_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PFVddCntlStat_REG_0x100F0106 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(PFVddCntlStat_REG_0x1*0F0106) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - l_rc = data.setDoubleWord(0, EX_PFVcsCntlStat_REG_0x100F010E_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PFVcsCntlStat_REG_0x100F010E + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(PFVcsCntlStat_REG_0x1*0F010E) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - l_rc = data.setDoubleWord(0, EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_Resonant_Clock_Control_Reg0_0x1*0F0165) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - // Clear buffer - l_rc = data.flushTo0(); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - l_rc = data.setWord(0, EX_PMErrMask_REG_0x100F010A_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PMErrMask_REG_0x100F010A + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(PMErrMask_REG_0x1*0F010A) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - l_rc = data.setWord(0, EX_PMSpcWkupFSP_REG_0x100F010B_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PMSpcWkupFSP_REG_0x100F010B + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(EX_PMSpcWkupFSP_REG_0x100F010B) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - l_rc = data.setWord(0, EX_PMSpcWkupOCC_REG_0x100F010C_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PMSpcWkupOCC_REG_0x100F010C + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(PMSpcWkupOCC_REG_0x1*0F010C) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - l_rc = data.setWord(0, EX_PMSpcWkupPHYP_REG_0x100F010D_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PMSpcWkupPHYP_REG_0x100F010D + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(PMSpcWkupPHYP_REG_0x1*0F010D) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - - - l_rc = data.setWord(0, EX_CorePFPUDly_REG_0x100F012C_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_CorePFPUDly_REG_0x100F012C + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(CorePFPUDly_REG_0x1*0F012C) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - l_rc = data.setWord(0, EX_CorePFPDDly_REG_0x100F012D_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_CorePFPDDly_REG_0x100F012D + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(CorePFPDDly_REG_0x1*0F012D) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - l_rc = data.setWord(0, EX_CorePFVRET_REG_0x100F0130_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_CorePFVRET_REG_0x100F0130 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(CorePFVRET_REG_0x1*0F0130) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - - - l_rc = data.setWord(0, EX_ECOPFPUDly_REG_0x100F014C_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_ECOPFPUDly_REG_0x100F014C + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(ECOPFPUDly_REG_0x1*0F014C) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - l_rc = data.setWord(0, EX_ECOPFPDDly_REG_0x100F014D_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_ECOPFPDDly_REG_0x100F014D + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(ECOPFPDDly_REG_0x1*0F014D) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - l_rc = data.setWord(0, EX_ECOPFVRET_REG_0x100F0150_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_ECOPFVRET_REG_0x100F0150 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(ECOPFVRET_REG_0x1*0F0150) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - - l_rc = data.setWord(0, EX_FREQCNTL_0x100F0151_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_FREQCNTL_0x100F0151 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(FREQ_CTRL_REG_0x1*0F0151) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - l_rc = data.setWord(0, EX_DPLL_CPM_PARM_REG_0x100F0152_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_DPLL_CPM_PARM_REG_0x100F0152 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(DPLL_CPM_PARM_REG_0x1*0F0152) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - l_rc = data.setWord(0, EX_PCBS_iVRM_Control_Status_Reg_0x100F0154_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_iVRM_Control_Status_Reg_0x1*0F0154) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - l_rc = data.setWord(0, EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_iVRM_Value_Setting_Reg_0x1*0F0155) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - // Scan0 values set per multicast - // l_rc = data.setWord(0, EX_PCBSPM_MODE_REG_0x100F0156_scan0); - // if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)rc); rc.setEcmdError(l_rc); return rc; } - // rc = fapiPutScom(i_target, EX_PCBSPM_MODE_REG_0x100F0156 + (l_ex_number * 0x01000000), data ); - // if (l_rc) { FAPI_ERR("fapiGetScom(PCBSPM_MODE_REG_0x1*0F0156) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - l_rc = data.setWord(0, EX_PCBS_Power_Management_Control_Reg_0x100F0159_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PCBS_Power_Management_Control_Reg_0x100F0159 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_Power_Management_Control_Reg_0x1*0F0159) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - l_rc = data.setWord(0, EX_PCBS_PMC_VF_CTRL_REG_0x100F015A_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PCBS_PMC_VF_CTRL_REG_0x100F015A + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_PMC_VF_CTRL_REG_0x1*0F015A) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - l_rc = data.setWord(0, EX_PCBS_UNDERVOLTING_REG_0x100F015B_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PCBS_UNDERVOLTING_REG_0x100F015B + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_UNDERVOLTING_REG_0x1*0F015B) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - l_rc = data.setWord(0, EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - // Scan0 values set per multicast - //l_rc = data.setWord(0, EX_PCBS_Power_Management_Bounds_Reg_0x100F015D_scan0); - //if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)rc); rc.setEcmdError(l_rc); return rc; } - //rc = fapiPutScom(i_target, EX_PCBS_Power_Management_Bounds_Reg_0x100F015D + (l_ex_number * 0x01000000), data ); - //if (l_rc) { FAPI_ERR("fapiGetScom(PCBS_Power_Management_Bounds_Reg_0x1*0F015D) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - l_rc = data.setWord(0, EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_PSTATE_TABLE_CTRL_REG_0x1*0F015E) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - //l_rc = data.setWord(0, EX_PCBS_Pstate_Step_Target_Register_0x100F0160_scan0); - //if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - //rc = fapiPutScom(i_target, EX_PCBS_Pstate_Step_Target_Register_0x100F0160 + (l_ex_number * 0x01000000), data ); - //if (rc) { FAPI_ERR("fapiGetScom(PCBS_Pstate_Step_Target_Register_0x1*0F0160) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - l_rc = data.setWord(0, EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_iVRM_VID_Control_Reg0_0x1*0F0162) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - l_rc = data.setWord(0, EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_iVRM_VID_Control_Reg1_0x1*0F0163) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - //l_rc = data.setWord(0, EX_PCBS_OCC_Heartbeat_Reg_0x100F0164_scan0); - //if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - //rc = fapiPutScom(i_target, EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 + (l_ex_number * 0x01000000), data ); - //if (rc) { FAPI_ERR("fapiGetScom(PCBS_OCC_Heartbeat_Reg_0x1*0F0164) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - l_rc = data.setWord(0, EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - rc = fapiPutScom(i_target, EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_Resonant_Clock_Control_Reg1_0x1*0F0166) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - /// \todo Regcheck error check at latest model - // l_rc = data.setWord(0, EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168_scan0); - // if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)rc); rc.setEcmdError(l_rc); return rc; } - // rc = fapiPutScom(i_target, EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168 + (l_ex_number * 0x01000000), data ); - // if (l_rc) { FAPI_ERR("fapiGetScom(PCBS_Local_Pstate_Frequency_Target_Control_Register_0x1*0F0168) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - + address = EX_DPLL_CPM_PARM_REG_0x100F0152 + + (l_ex_number * 0x01000000); + GETSCOM(i_target, address, data); - - } - - // ****************************************************************** - // Force safe mode - // ****************************************************************** - // ****************************************************************** - // - set PCBS_PM_PMGP1_REG_1 - // [12] force_safe_mode = 1 - // - // ****************************************************************** - - FAPI_DBG("********* ******************* *********"); - FAPI_INF("Force safe mode"); - FAPI_DBG("********* ******************* *********"); - - // Using Write OR to just set bit11 and bit12 - // Clear buffer - l_rc = data.flushTo0(); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - // set scan0 value - // scan0: 6C00 content after iStep: 4800 - // bit2: 0: Vret (fast sleep) - // 1: Voff (deep sleep) - // bit5: 0: Vret (fast winkle) - // 1: Voff (deep winkle) - /// \todo Review if scan0 values can/should be applied - //l_rc = data.setDoubleWord(0, PMGP1_REG_0x100F0103_scan0); - //if (l_rc) { FAPI_ERR("Bit operation failed."); return rc; } - - l_rc = data.setBit(12); //force_safe_mode = 1 - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - // simaet( "on" ); - rc = fapiPutScom(i_target, EX_WRITE_ALL_EX_PMGP1_REG_0_WORx690F0105, data ); - if (rc) { FAPI_ERR("fapiPutScom multicast (EX_WRITE_ALL_EX_PMGP1_REG_0_WORx690F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - //if (VERBOSE) { - // FAPI_DBG("********* ******************* *********"); - // FAPI_DBG("Multicasted to EX_WRITE_ALL_EX_PMGP1_REG_0_WORx690F0105 : %s", data.getDoubleWord(0)); - // FAPI_DBG("********* ******************* *********"); - //} - - - // manual debug - // getscom p8 -k0 -n0 -s0 -p00 130F0103 -ixl - // returns the expected values0x4818000000000000 - - //rc = fapiGetScom(i_target, 0x130F0103, data); if (l_rc) return rc; - //FAPI_DBG("XXXXXX Content of 0x130F0103 is : %s", data.getDoubleWord(0)); - - - // if debug mode read back - //if (VERBOSE) { - // if (chiplets_valid[c] == 1) { - // rc = fapiGetScom(i_target, EX_PMGP1_REG_0_RWXx100F0103 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; - // FAPI_DBG("Content of PMGP1_REG_0_RWXx1*0F0103 is : %s , Loop: %d ", data.getDoubleWord(0) , c); - // - // //rc = fapiGetScom(i_target, 0x130F0103, data); if (l_rc) return rc; - // //FAPI_DBG(" XXX2 Content of 0x130F0103 is : %s", data.getDoubleWord(0)); - // } - // } - - FAPI_INF("Forced Safe Mode"); - - - // ****************************************************************** - // psafe Pstate achived AND FSM-stable ? - // ****************************************************************** - // ****************************************************************** - // - PCBS_POWER_MANAGEMENT_STATUS_REG[33] safe_mode_active - // - PCBS_POWER_MANAGEMENT_STATUS_REG[36] all_fsms_in_safe_state - // - // ****************************************************************** - FAPI_DBG("**************************** *********"); - FAPI_INF("Psafe Pstate and FSM-stable?"); - FAPI_DBG("**************************** *********"); + e_rc = data.setBit(22); + E_RC_CHECK(e_rc, l_rc); - loopcount = 0; - rc = fapiGetScom( i_target,EX_PCBS_POWER_MANAGEMENT_STATUS_REG_0x100F0153 + (l_ex_number * 0x01000000) , data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_POWER_MANAGEMENT_STATUS_REG_0x1*0F0153) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + PUTSCOM(i_target, address, data); + + // ****************************************************************** + // - Enable DPLL Lock Replacement mode + // ****************************************************************** + FAPI_INF("Set DPLL Lock Replacement mode"); - while( data.isBitClear( 33 ) || data.isBitClear( 36 ) ) { // loop until (safe_mode_active AND all_fsms_in_safe_state) - FAPI_DBG("\t loopcount => %d ",loopcount ); - - if( ++loopcount > pcbs_val_init.MAX_PSAFE_FSM_LOOPS ) // OR timeout .... set to 20 loops - { - FAPI_ERR( "Gave up waiting for Psafe Pstate and FSM-stable!\n" ); - FAPI_SET_HWP_ERROR(rc, RC_PROC_PCBS_CODE_SAFE_FSM_TIMEOUT); - return rc; - } - - - // FAPI_DBG("Read of PCBS_POWER_MANAGEMENT_STATUS_REG_0x1*0F0153 content : %016llX", data.getDoubleWord(0)); - // FAPI_DBG("Read of PCBS_POWER_MANAGEMENT_STATUS_REG_0x1*0F0153 content bit 33 : %s", data.genBinStr(33,1).c_str()); - // FAPI_DBG("Read of PCBS_POWER_MANAGEMENT_STATUS_REG_0x1*0F0153 content bit 36 : %s", data.genBinStr(36,1).c_str()); - - FAPI_INF("Is Psafe Pstate and FSM-stable ? \n"); - FAPI_DBG("\t Wait DELAY: %d ", pcbs_val_init.MAX_DELAY); - FAPI_DBG("\t Wait SimCycles: %d ", pcbs_val_init.MAX_SIM_CYCLES); - - /// \todo once available .. right now no delay - /// \todo fapiDelay( post_flush_cyc_dly, post_flush_timedly ); // delay for each cycle + address = EX_PCBSPM_MODE_REG_0x100F0156 + + (l_ex_number * 0x01000000); - rc = fapiDelay(pcbs_val_init.MAX_DELAY, pcbs_val_init.MAX_SIM_CYCLES); - if (rc) { FAPI_ERR("fapi::delay(MAX_DELAY, MAX_SIM_CYCLES) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - + GETSCOM(i_target, address, data ); - rc = fapiGetScom( i_target,EX_PCBS_POWER_MANAGEMENT_STATUS_REG_0x100F0153 + (l_ex_number * 0x01000000) , data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_POWER_MANAGEMENT_STATUS_REG_0x1*0F0153) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + e_rc |= data.setBit(7); + E_RC_CHECK(e_rc, l_rc); - } + PUTSCOM(i_target, address, data ); + + // ****************************************************************** + // - Power Management Control Reg + // ****************************************************************** + FAPI_INF("Clear Power Management Control Reg"); + + // This can only be done if PMGP1(11) (pm_spr_override_en) is set + e_rc = data.setBit(10); + E_RC_CHECK(e_rc, l_rc); - FAPI_INF("Psafe Pstate and FSM-stable is reached ...\n"); + address = EX_PMGP1_OR_0x100F0105 + (l_ex_number * 0x01000000); + PUTSCOM(i_target, address, data); + // Clear buffer + e_rc = data.flushTo0(); + E_RC_CHECK(e_rc, l_rc); - // ****************************************************************** - // DPLL settings - // ****************************************************************** - // ****************************************************************** - // - enable dpll override - // - PCBS_PM_PMGP1_REG_1[10] dpll_freq_override_enable - // - get Psafe and global actual pstate - // - calculate minPstate - // - calculate dpll_fmin = fnom + minPstate - // - set dpll_fmin - // - set dpll_fmax - // ****************************************************************** - FAPI_DBG("**************************** *********"); - FAPI_INF("DPLL settings"); - FAPI_DBG("**************************** *********"); - - //rc = fapiGetScom( i_target,PMGP1_REG_0_WORx100F00105 + (l_ex_number * 0x01000000) , data ); - //if (l_rc) { FAPI_ERR("fapiGetScom(PMGP1_REG_0_WORx100F00105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - //if (VERBOSE) { - // rc = fapiGetScom(i_target, EX_PMGP1_REG_0_RWXx100F0103 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; - // FAPI_DBG(" Pre Write to PMGP1_REG_0_RWXx1*0F0103 : %016llX", data.getDoubleWord(0)); - //} - - l_rc = data.flushTo0(); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - l_rc = data.setBit(10); //dpll_freq_override_enable - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WORx100F0105 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(PMGP1_REG_0_WORx1*0F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - // if debug mode read back - //if (VERBOSE) { - // rc = fapiGetScom(i_target, EX_PMGP1_REG_0_RWXx100F0103 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; - // FAPI_DBG(" Post Write content of PMGP1_REG_0_RWXx1*0F0103 : %016llX", data.getDoubleWord(0)); - //} - - - FAPI_DBG("*************************************"); - FAPI_INF(" Start calculation of DPLL fmin ...."); - FAPI_DBG("*************************************"); - - - //get PSAFE and GLOBAL ACTUAL PSTATE EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 - - FAPI_INF("DPLL fmin = %d , DPLL fmax = %d set", pcbs_val_init.DPLL_FMIN, pcbs_val_init.DPLL_FMAX); - - - rc = fapiGetScom( i_target,EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 + (l_ex_number * 0x01000000) , data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_OCC_HEARTBEAT_REG_0x1*0F0164) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - FAPI_DBG("Read Psafe [17..24] of PCBS_OCC_HEARTBEAT_REG_0x1*0F0164 content : %016llX", data.getDoubleWord(0)); - - - - l_rc = data.shiftLeft(17); // Psafe is bit 17..24 - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - // assign Psafe to variable - pcbs_val_init.PSAFE = data.getByte(0); // - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - rc = fapiGetScom( i_target,EX_PCBS_POWER_MANAGEMENT_STATUS_REG_0x100F0153 + (l_ex_number * 0x01000000) , data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_POWER_MANAGEMENT_STATUS_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - - FAPI_DBG("Read GLOBAL_ACTUAL_PSTATE [0..7] of PCBS_POWER_MANAGEMENT_STATUS_REG_0x1*0F0153 content : %016llX", data.getDoubleWord(0)); - - - // assign GLOBAL_ACTUAL_PSTATE to variable - pcbs_val_init.GLOBAL_ACTUAL_PSTATE = data.getByte(0); // GLOBAL_ACTUAL_PSTATE is sbit 0..7 - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - FAPI_INF("\t PSAFE => %d ", pcbs_val_init.PSAFE ); - FAPI_INF("\t GLOBAL_ACTUAL_PSTATE => %d ", pcbs_val_init.GLOBAL_ACTUAL_PSTATE ); - - - - // set the min_pstate to the smaller of Psafe and global actual pstate - // minPstate = min(Psafe,global actual pstate) - pcbs_val_init.MIN_PSTATE = pcbs_val_init.PSAFE < pcbs_val_init.GLOBAL_ACTUAL_PSTATE ? pcbs_val_init.PSAFE : pcbs_val_init.GLOBAL_ACTUAL_PSTATE ; - - //if (VERBOSE) { - FAPI_DBG("\t PSAFE => %d ", pcbs_val_init.PSAFE ); - FAPI_DBG("\t GLOBAL_ACTUAL_PSTATE => %d ", pcbs_val_init.GLOBAL_ACTUAL_PSTATE ); - FAPI_DBG("\t => MIN_PSTATE => %x ", pcbs_val_init.MIN_PSTATE ); - //} - - //set dpll_fmin = fnom + minPstate(signed) - /// \todo double check dpll_fmin not dpll_min - pcbs_val_init.DPLL_FMIN = pcbs_val_init.FNOM + pcbs_val_init.MIN_PSTATE ; - - //if (VERBOSE) { - FAPI_DBG("\t DPLL_FMIN = FNOM + MIN_PSTATE " ); - FAPI_DBG("\t DPLL_FMIN => %d ", pcbs_val_init.DPLL_FMIN ); - //} - - FAPI_DBG("*************************************"); - FAPI_INF(" End calculation of DPLL fmin ...."); - FAPI_DBG("*************************************"); - - - // Write calculated values to FREQ_CTRL_REG - rc = fapiGetScom( i_target,EX_FREQCNTL_0x100F0151 + (l_ex_number * 0x01000000) , data ); - if (rc) { FAPI_ERR("fapiGetScom(FREQ_CTRL_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - //if (VERBOSE) { - FAPI_DBG(" Pre write content of FREQ_CTRL_REG_0x1*0F0151 : %016llX", data.getDoubleWord(0)); - //} - - // Clear buffer - l_rc = data.flushTo0(); - l_rc |= data.setByte(0, pcbs_val_init.DPLL_FMIN); - l_rc |= data.setByte(1, pcbs_val_init.DPLL_FMAX); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + address = EX_PCBS_Power_Management_Control_Reg_0x100F0159 + + (l_ex_number * 0x01000000); + PUTSCOM(i_target, address, data); - rc = fapiPutScom(i_target, EX_FREQCNTL_0x100F0151 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(FREQ_CTRL_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + // ****************************************************************** + // - Power Management Idle Control Reg + // ****************************************************************** + FAPI_INF("Clear Power Management Idle Control Reg"); + + // Clear buffer + e_rc = data.flushTo0(); + E_RC_CHECK(e_rc, l_rc); - // if debug mode read back - //if (VERBOSE) { - // rc = fapiGetScom(i_target, EX_FREQCNTL_0x100F0151 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; - // FAPI_DBG(" Post write content of FREQ_CTRL_REG_0x1*0F0151 : %016llX", data.getDoubleWord(0)); - //} + address = EX_PCBS_Power_Management_Idle_Control_Reg_0x100F0158 + + (l_ex_number * 0x01000000); + PUTSCOM(i_target, address, data); - FAPI_INF("DPLL fmin = %d , DPLL fmax = %d set", pcbs_val_init.DPLL_FMIN, pcbs_val_init.DPLL_FMAX); + FAPI_INF ("PMCR default value adjustment (Hardware flush 0) of EX_PCBS_Power_Management_Idle_Control_Reg_0x1*0F0158 " ); + } //END FOR + if (!l_rc.ok() ) + { + break; + } + } while(0); - - - // ****************************************************************** - // OCC SPR Mode - // ****************************************************************** - // ****************************************************************** - // - set PCBS_PM_PMGP1_REG_1 - // [11] PM_SPR_OVERRIDE_EN = 1 - // - // ****************************************************************** - - FAPI_DBG("********* ******************* *********"); - FAPI_INF("Force PM_SPR_OVERRIDE"); - FAPI_DBG("********* ******************* *********"); - - // Using Write OR to just set bit11 and bit12 - // Clear buffer - l_rc = data.flushTo0(); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - // set scan0 value - // scan0: 6C00 content after iStep: 4800 - // bit2: 0: Vret (fast sleep) - // 1: Voff (deep sleep) - // bit5: 0: Vret (fast winkle) - // 1: Voff (deep winkle) - /// \todo Review if scan0 values can/should be applied - //l_rc = data.setDoubleWord(0, PMGP1_REG_0x100F0103_scan0); - //if (l_rc) { FAPI_ERR("Bit operation failed."); return rc; } - - l_rc = data.setBit(11); //Force OCC SPR Mode = 1 - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - // simaet( "on" ); - rc = fapiPutScom(i_target, EX_WRITE_ALL_EX_PMGP1_REG_0_WORx690F0105, data ); - if (rc) { FAPI_ERR("fapiPutScom multicast (EX_WRITE_ALL_EX_PMGP1_REG_0_WORx690F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - - //if (VERBOSE) { - FAPI_DBG("********* ******************* *********"); - FAPI_DBG("Multicasted to EX_WRITE_ALL_EX_PMGP1_REG_0_WORx690F0105 : %016llX", data.getDoubleWord(0)); - FAPI_DBG("********* ******************* *********"); - //} - - - // manual debug - // getscom p8 -k0 -n0 -s0 -p00 130F0103 -ixl - // returns the expected values0x4818000000000000 - - //rc = fapiGetScom(i_target, 0x130F0103, data); if (l_rc) return rc; - //FAPI_DBG("XXXXXX Content of 0x130F0103 is : %016llX", data.getDoubleWord(0)); - - - // if debug mode read back - //if (VERBOSE) { - // if (chiplets_valid[c] == 1) { - // rc = fapiGetScom(i_target, EX_PMGP1_REG_0_RWXx100F0103 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; - // FAPI_DBG("Content of PMGP1_REG_0_RWXx1*0F0103 is : %s , Loop: %016llX ", data.getDoubleWord(0) , c); - // - // //rc = fapiGetScom(i_target, 0x130F0103, data); if (l_rc) return rc; - // //FAPI_DBG(" XXX2 Content of 0x130F0103 is : %016llX", data.getDoubleWord(0)); - // } - //} - - FAPI_INF("Forced OCC SPR Mode"); - - - - - // ****************************************************************** - // - Disable Pstate mode - // - disable Pstate requests - // ****************************************************************** - FAPI_DBG("********* ******************* *********"); - FAPI_INF("Disable Pstate mode and disable Pstate requests"); - FAPI_DBG("********* ******************* *********"); - - //EX_PCBSPM_MODE_REG_0x100F0156_scan0 - /// \todo DoubleCheck: No OR-write available, using scan0 values as base and clearing bit 0 and bit 2 - l_rc = data.setWord(0, EX_PCBSPM_MODE_REG_0x100F0156_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - l_rc = data.clearBit(0); //Disable Pstate mode - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - l_rc = data.clearBit(2); //Disable Pstate requests - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - - - rc = fapiPutScom(i_target, EX_WRITE_ALL_PCBSPM_MODE_REG_0x690F0156, data ); - if (rc) { FAPI_ERR("fapiGetScom(EX_WRITE_ALL_PCBSPM_MODE_REG_0x690F0156) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - FAPI_DBG("Multicasted to EX_WRITE_ALL_PCBSPM_MODE_REG_0x690F0156 is : %016llX", data.getDoubleWord(0)); - - // if debug mode read back - //if (VERBOSE) { - // if (chiplets_valid[c] == 1) { - // rc = fapiGetScom(i_target, EX_PCBSPM_MODE_REG_0x100F0156 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; - // FAPI_DBG(" Content of PCBSPM_MODE_REG_0x1*0F0156 : %016llX", data.getDoubleWord(0)); - // } - //} - FAPI_INF("Disabled Pstate mode"); - - // simaet( "off" ); - - // ****************************************************************** - // - Reset Pmin and Pmax - // ****************************************************************** - FAPI_DBG("********* ******************* *********"); - FAPI_INF("Reset Pmin and Pmax"); - FAPI_DBG("********* ******************* *********"); - // Clear data buffer - l_rc = data.flushTo0(); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - // Set scan0 values - l_rc = data.setWord(0, EX_PCBS_Power_Management_Bounds_Reg_0x100F015D_scan0); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - // - l_rc = data.setByte(0, pcbs_val_init.PMIN_CLIP); //Pmin_clip = -128 - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - l_rc = data.setByte(1, pcbs_val_init.PMAX_CLIP); //Pmax_clip = 127 - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - rc = fapiPutScom(i_target, EX_WRITE_ALL_PCBS_Power_Management_Bounds_Reg_0x690F015D, data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_Power_Management_Bounds_Reg) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - FAPI_DBG("Multicasted to PCBS_Power_Management_Bounds_Reg is : %016llX", data.getDoubleWord(0)); - - // if debug mode read back - //if (VERBOSE) { - // if (chiplets_valid[c] == 1) { - // rc = fapiGetScom(i_target, EX_PCBS_Power_Management_Bounds_Reg_0x100F015D + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; - // FAPI_DBG("Content of PCBS_Power_Management_Bounds_Reg_0x1*0F015D : %016llX", data.getDoubleWord(0)); - // } - //} - FAPI_INF("\t Pmin_clip => %d and Pmax_clip => %d ",pcbs_val_init.PMIN_CLIP,pcbs_val_init.PMAX_CLIP); - - - - - + return l_rc; - // ****************************************************************** - // Settings - // ****************************************************************** - // ****************************************************************** - - // - disable RESCLK - // - OCC Heartbeat disable - // ****************************************************************** - FAPI_DBG("**************************** *********"); - FAPI_INF("Settings about RESCLK"); - FAPI_DBG("**************************** *********"); - - // if debug mode read before - //if (VERBOSE) { - // rc = fapiGetScom(i_target, EX_GP3_0x100F0012 + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; - // FAPI_DBG(" Pre write content of GP3_REG_0_RWXx1*0F0012 , Loop: %d : %016llX", c, data.getDoubleWord(0) ); - //} - - /// \todo : Double Check: Bit modifications in GP3... anything to take care here?? - // Using Write OR to just set bit22 - // Clear buffer - l_rc = data.flushTo0(); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } +} //end INIT - l_rc = data.setBit(22); //disable RESCLK - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } +//------------------------------------------------------------------------------ +/** + * Initialize the PCBS-PM macro for all functional and enabled EX chiplets + * + * @param[in] i_target Chip target + * @param[in] mode Control mode for the procedure + * PM_INIT, PM_CONFIG, PM_RESET + * + * @retval ECMD_SUCCESS + * @retval ERROR defined in xml + */ +fapi::ReturnCode +p8_pcbs_init_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init) +{ + fapi::ReturnCode l_rc; + uint32_t e_rc; // ecmd returncode - rc = fapiPutScom(i_target, EX_GP3_OR_0x100F0014 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom Content of GP3_REG_0_WORx1*0F0014, Loop: %d failed. With rc = 0x%x", c, (uint32_t)rc); return rc; } + ecmdDataBufferBase data(64); + ecmdDataBufferBase mask(64); - // if debug mode read back - //if (VERBOSE) { - // rc = fapiGetScom(i_target, EX_GP3_0x100F0012 + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; - // FAPI_DBG(" Post write content of GP3_REG_0_RWXx1*0F0012 , Loop: %d : %016llX", c, data.getDoubleWord(0) ); - //} - FAPI_INF ("Disabled RESCLK, set bit 22 of GP3_REG_0_RWXx1*0F0012 " ); + // Variables + std::vector<fapi::Target> l_exChiplets; + fapi::TargetState l_state = TARGET_STATE_FUNCTIONAL; + uint8_t l_functional = 0; + uint8_t l_ex_number = 0; + uint64_t address; + //TODO RTC: 71328 - hack to indicate unused + bool __attribute__((unused)) error_flag = false; + uint32_t loopcount = 0; // number of times PCBS-PMSR has been checked + + FAPI_INF("p8_pcbs_init_reset beginning for target %s ...", i_target.toEcmdString()); + do + { + l_rc = fapiGetChildChiplets(i_target, + fapi::TARGET_TYPE_EX_CHIPLET, + l_exChiplets, + l_state); + if (l_rc) + { + FAPI_ERR("fapiGetChildChiplets with rc = 0x%x", (uint32_t)l_rc); + break; + } + FAPI_DBG("Chiplet vector size => %u", l_exChiplets.size()); - //OCC Heartbeat disable - rc = fapiGetScom( i_target, EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 + (l_ex_number * 0x01000000) , data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_OCC_HEARTBEAT_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - //if (VERBOSE) { - FAPI_DBG(" Pre write content of PCBS_OCC_HEARTBEAT_REG_0x1*0F0164 : %016llX", data.getDoubleWord(0)); - //} - - l_rc = data.clearBit(8); //OCC Heartbeat disable - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - + // For each chiplet + for (uint8_t c=0; c< l_exChiplets.size(); c++) + { + FAPI_DBG("\tLoop Variable %d ",c); + + l_rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_exChiplets[c], l_functional); + if (l_rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL with rc = 0x%x", (uint32_t)l_rc); + break; + } + + if (!l_functional) + { + FAPI_DBG("Core number = %d is not functional", c); + // Iterate + continue; + } + + // The ex is functional let's build the SCOM address + l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[c], l_ex_number); + if (l_rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)l_rc); + break; + } + + FAPI_DBG("\tCore number = %d", l_ex_number); + + // ****************************************************************** + // Set the regs back to scan0 state - NO... NOT HERE! + // ****************************************************************** + + l_rc = p8_pcbs_init_scan0(i_target, l_ex_number); + if (l_rc) + { + FAPI_ERR(" p8_pcbs_init_scan0 failed. With l_rc = 0x%x", (uint32_t)l_rc); + error_flag = true; + break; + } + + + // ****************************************************************** + // Force safe mode if Pstates are enabled. + // ****************************************************************** + // - set PCBS_PM_PMGP1_REG_1 + // [12] force_safe_mode = 1 + // ****************************************************************** + + address = EX_PCBSPM_MODE_REG_0x100F0156 + + (l_ex_number * 0x01000000); + GETSCOM(i_target, address, data); + FAPI_DBG("\tPCBS_MODE_REG value 0x%16llX", data.getDoubleWord(0)); + + if (data.isBitSet(0)) // Pstates enabled + { - rc = fapiPutScom(i_target, EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_OCC_HEARTBEAT_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + FAPI_INF("Pstate enabled - Force safe mode"); - // if debug mode read back - //if (VERBOSE) { - // rc = fapiGetScom(i_target, EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; - // FAPI_DBG(" Post write content of PCBS_OCC_HEARTBEAT_REG_0x1*0F0164 : %016llX", data.getDoubleWord(0)); - //} - FAPI_INF ("OCC Heartbeat disabled, cleared bit 8 of PCBS_OCC_HEARTBEAT_REG_0x1*0F0164" ); + // Using Write OR to just set bit12 + // Clear buffer + e_rc = data.flushTo0(); + E_RC_CHECK(e_rc, l_rc); + e_rc = data.setBit(12); // force_safe_mode = 1 + E_RC_CHECK(e_rc, l_rc); + address = EX_PMGP1_OR_0x100F0105 + + (l_ex_number * 0x01000000);; + PUTSCOM(i_target, address, data); + FAPI_INF("Forced Safe Mode"); // ****************************************************************** - // IVRM Setup + // psafe Pstate achived AND FSM-stable ? // ****************************************************************** // ****************************************************************** - // - if Venice ( ivrms_enabled) - // - disable ivrms - // - set bypass mode - // - reset undervolting values - // - disable LPFT + // - PCBS_POWER_MANAGEMENT_STATUS_REG[33] safe_mode_active + // - PCBS_POWER_MANAGEMENT_STATUS_REG[36] all_fsms_in_safe_state + // // ****************************************************************** - FAPI_DBG("**************************** *********"); - FAPI_INF("IVRM Setup"); - FAPI_DBG("**************************** *********"); + FAPI_INF("Psafe Pstate and FSM-stable?"); - if (pcbs_val_init.ivrms_enabled) { // If Venice + loopcount = 0; - // - rc = fapiGetScom( i_target, EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 + (l_ex_number * 0x01000000) , data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_iVRM_Control_Status_Reg) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - //if (VERBOSE) { - FAPI_DBG(" Pre write content of PCBS_iVRM_Control_Status_Reg_0x1*0F0154 : %016llX", data.getDoubleWord(0)); - //} - - l_rc = data.clearBit(0); //disable ivrms - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - l_rc = data.clearBit(4); //ivrm_core_vdd_bypass_b - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - l_rc = data.clearBit(6); //ivrm_core_vcs_bypass_b - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - l_rc = data.clearBit(8); //ivrm_eco_vdd_bypass_b - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - l_rc = data.clearBit(10); //ivrm_eco_vcs_bypass_b - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + address = EX_PCBS_POWER_MANAGEMENT_STATUS_REG_0x100F0153 + + (l_ex_number * 0x01000000); + GETSCOM(i_target, address, data); + // loop until (safe_mode_active AND all_fsms_in_safe_state) + while( data.isBitClear( 33 ) || data.isBitClear( 36 ) ) + { + FAPI_DBG("\t loopcount => %d ",loopcount ); + // OR timeout .... set to 20 loops + if( ++loopcount > pcbs_val_init.MAX_PSAFE_FSM_LOOPS ) + { + FAPI_ERR("Gave up waiting for Psafe Pstate and FSM-stable!" ); + ///TODO RTC: 71328 - unused variable const uint64_t& LOOPCOUNT = (uint32_t)loopcount; + ///TODO RTC: 71328 - unused variable const uint64_t& PMSR = data.getDoubleWord(0); + FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PCBS_CODE_SAFE_FSM_TIMEOUT); +// error_flag = true; + break; + } + + FAPI_DBG("Read of PCBS_POWER_MANAGEMENT_STATUS_REG_0x1*0F0153 content : %016llX", + data.getDoubleWord(0)); + + FAPI_DBG("Is Psafe Pstate and FSM-stable ? "); + FAPI_DBG("\t Wait DELAY: %d ", pcbs_val_init.MAX_DELAY); + FAPI_DBG("\t Wait SimCycles: %d ", pcbs_val_init.MAX_SIM_CYCLES); - rc = fapiPutScom(i_target, EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_iVRM_Control_Status_Reg) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - // Write twice since ivrm_fsm_enable have to be 0 to enable the set the bypass modes - rc = fapiPutScom(i_target, EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_iVRM_Control_Status_Reg) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + l_rc = fapiDelay(pcbs_val_init.MAX_DELAY, pcbs_val_init.MAX_SIM_CYCLES); + if (l_rc) + { + FAPI_ERR("fapiDelay(MAX_DELAY, MAX_SIM_CYCLES) failed. With rc = 0x%x", (uint32_t)l_rc); +// error_flag = true; + break; + } - // if debug mode read back - //if (VERBOSE) { - // rc = fapiGetScom(i_target, EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; - // FAPI_DBG(" Post write content of PCBS_iVRM_Control_Status_Reg_0x1*0F0154 : %016llX", data.getDoubleWord(0)); - //} - FAPI_INF ("This is Venice: iVRMs disabled and in bypass-mode" ); + // Read PMSR again + GETSCOM(i_target, address, data); + } + // if error, break the outer loop + if (!l_rc.ok()) + { + break; + } - }; + FAPI_INF("Psafe Pstate and FSM-stable is reached ..."); + } + + // ****************************************************************** + // DPLL settings + // ****************************************************************** + // ****************************************************************** + // - enable dpll override + // - PCBS_PM_PMGP1_REG_1[10] dpll_freq_override_enable + // + // \bug the following are removed as the pstate protocol would have + // produced Psave anyway. To mode frequency without voltage context + // is not correct. + // - get Psafe and global actual pstate + // - calculate minPstate + // - calculate dpll_fmin = fnom + minPstate + // - set dpll_fmin + // - set dpll_fmax + // ****************************************************************** + + FAPI_INF("Hold the DPLL to the value that the last Pstate represents"); + + // Write calculated values to FREQ_CTRL_REG + address = EX_FREQCNTL_0x100F0151 + (l_ex_number * 0x01000000); + GETSCOM(i_target, address, data); + + FAPI_DBG(" Pre write content of FREQ_CTRL_REG_0x1*0F0151 : %016llX", + data.getDoubleWord(0)); + + // Clear the DPLL bias; did not clear other fields + e_rc = data.clearBit(18, 4); + E_RC_CHECK(e_rc, l_rc); + + PUTSCOM(i_target, address, data); + + // Lock the DPLL in via the override mode. Note: this DOES + // allow for continued CPM enablement + e_rc |= data.flushTo0(); + e_rc |= data.setBit(10); // dpll_freq_override_enable + E_RC_CHECK(e_rc, l_rc); + + address = EX_PMGP1_OR_0x100F0105 + (l_ex_number * 0x01000000); + PUTSCOM(i_target, address, data); + + // ****************************************************************** + // - Disable Pstate mode + // - disable Pstate requests + // ****************************************************************** + FAPI_INF("Disable Pstate mode and disable Pstate requests"); + + address = EX_PCBSPM_MODE_REG_0x100F0156 + + (l_ex_number * 0x01000000); + + GETSCOM(i_target, address, data ); + + e_rc |= data.clearBit(0); //Disable Pstate mode + e_rc |= data.clearBit(2); //Disable Pstate requests + E_RC_CHECK(e_rc, l_rc); + + PUTSCOM(i_target, address, data ); + + FAPI_INF("Disabled Pstate mode"); + + // ****************************************************************** + // OCC SPR Mode + // ****************************************************************** + // ****************************************************************** + // - set PCBS_PM_PMGP1_REG_1 + // [11] PM_SPR_OVERRIDE_EN = 1 + // ****************************************************************** + FAPI_INF("Force PM_SPR_OVERRIDE"); + + // Using Write OR to set bit11 + // Clear buffer + e_rc = data.flushTo0(); + e_rc |= data.setBit(11); // Force OCC SPR Mode = 1 + E_RC_CHECK(e_rc, l_rc); + + address = EX_PMGP1_OR_0x100F0105 + (l_ex_number * 0x01000000); + PUTSCOM(i_target, address, data ); + + FAPI_INF("Forced OCC SPR Mode"); + + // ****************************************************************** + // - Clear Power Management Idle Control bits that allow Pstate + // requensts to occur + // - Can occur as SPR override is set + // ****************************************************************** + FAPI_INF("Disabling Global Pstate Request bits "); + + address = EX_PCBS_Power_Management_Idle_Control_Reg_0x100F0158 + + (l_ex_number * 0x01000000); + GETSCOM(i_target, address, data ); + + e_rc |= data.clearBit(8); // Disable Nap Pstate Enable + e_rc |= data.clearBit(24); // Disable Sleep Pstate Enable + e_rc |= data.clearBit(40); // Disable Winkle Pstate Enable + E_RC_CHECK(e_rc, l_rc); + + PUTSCOM(i_target, address, data ); + + // Auto overrides + address = EX_PCBS_Power_Management_Control_Reg_0x100F0159 + + (l_ex_number * 0x01000000); + GETSCOM(i_target, address, data ); + + e_rc |= data.clearBit(16); // Disable Auto Override 0 + e_rc |= data.clearBit(17); // Disable Auto Override 1 + E_RC_CHECK(e_rc, l_rc); + + PUTSCOM(i_target, address, data ); + + FAPI_INF("Disabled Global Pstate Requests"); + + // ****************************************************************** + // - Reset Pmin and Pmax + // ****************************************************************** + FAPI_INF("Reset Pmin and Pmax"); + + // Clear data buffer + e_rc |= data.flushTo0(); + e_rc |= data.setByte(0, pcbs_val_init.PMIN_CLIP); //Pmin_clip = -128 + e_rc |= data.setByte(1, pcbs_val_init.PMAX_CLIP); //Pmax_clip = 127 + E_RC_CHECK(e_rc, l_rc); + + address = EX_PCBS_Power_Management_Bounds_Reg_0x100F015D + + (l_ex_number * 0x01000000); + PUTSCOM(i_target, address, data ); + + FAPI_DBG("Pmin/Pmax written to PCBS_Power_Management_Bounds_Reg : %016llX", + data.getDoubleWord(0)); + FAPI_INF("\t Pmin_clip => %d and Pmax_clip => %d ", + pcbs_val_init.PMIN_CLIP, + pcbs_val_init.PMAX_CLIP); + + // ****************************************************************** + // Disable RESCLK + // ****************************************************************** + FAPI_INF("Settings about RESCLK"); + /// \todo : Is there more to things than this. + // Using Write OR to just set bit22 + // Clear buffer + e_rc = data.flushTo0(); + e_rc = data.setBit(22); //disable RESCLK + E_RC_CHECK(e_rc, l_rc); + + address = EX_GP3_OR_0x100F0014 + (l_ex_number * 0x01000000); + PUTSCOM(i_target, address, data); + FAPI_INF ("Disabled RESCLK, set bit 22 of GP3_REG_0_RWXx1*0F0012 " ); - // - rc = fapiGetScom( i_target, EX_PCBS_UNDERVOLTING_REG_0x100F015B + (l_ex_number * 0x01000000) , data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_UNDERVOLTING_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - // debug: data.flushTo1(); - //if (VERBOSE) { - FAPI_DBG(" Pre write content of PCBS_UNDERVOLTING_REG_0x1*0F015B : %016llX", data.getDoubleWord(0)); - //} - /// \todo : Double check this bit settings - l_rc = data.setByte(2, pcbs_val_init.KUV); //Kuv = 0 - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - l_rc = data.shiftLeft(2); //Kuv is 6bit - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - l_rc = data.setByte(0, pcbs_val_init.PUV_MIN); //Puv_min = -128 - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - l_rc = data.setByte(1, pcbs_val_init.PUV_MAX); //Puv_max = -128 - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - rc = fapiPutScom(i_target, EX_PCBS_UNDERVOLTING_REG_0x100F015B + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(PCBS_UNDERVOLTING_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - - // if debug mode read back - //if (VERBOSE) { - FAPI_DBG("\t PUV_MIN => %d ", pcbs_val_init.PUV_MIN ); - FAPI_DBG("\t PUV_MAX => %d ", pcbs_val_init.PUV_MAX ); - FAPI_DBG("\t KUV => %d ", pcbs_val_init.KUV ); - - //rc = fapiGetScom(i_target, EX_PCBS_UNDERVOLTING_REG_0x100F015B + (l_ex_number * 0x01000000), data); if (l_rc) return rc; - //FAPI_DBG(" Post write content of PCBS_UNDERVOLTING_REG_0x1*0F015B : %016llX", data.getDoubleWord(0)); - //} - FAPI_INF ("Undervolting values reset done" ); - - /// \todo : Debug Register access problems PCBS_LPFT_Control_Register_Reg0 . Already fixed in TPC-LIB chiplevel 8053 - /// \todo : Uncomment the following lines - // - // rc = fapiGetScom( i_target, EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168 + (l_ex_number * 0x01000000) , data ); - // if (l_rc) { FAPI_ERR("fapiGetScom(PCBS_LPFT_Control_Register_Reg0) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + // ****************************************************************** + // Disable OCC Heartbeat + // ****************************************************************** + address = EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 + + (l_ex_number * 0x01000000); + GETSCOM(i_target, address, data); - // data.clearBit(20); //Local Pstate Frequency Target mechanism disabled + FAPI_DBG(" Pre write content of PCBS_OCC_HEARTBEAT_REG_0x1*0F0164 : %016llX", + data.getDoubleWord(0)); + + e_rc = data.clearBit(8); //OCC Heartbeat disable + E_RC_CHECK(e_rc, l_rc); + + PUTSCOM(i_target, address, data); + + FAPI_INF ("OCC Heartbeat disabled, cleared bit 8 of PCBS_OCC_HEARTBEAT_REG_0x1*0F0164" ); + + // ****************************************************************** + // IVRM Disable + // ****************************************************************** + // ****************************************************************** + // - disable ivrms + // - set bypass mode + // ****************************************************************** + // \todo DOES THIS WORK IF THE IVRMS ARE ACTIVE AND IN REGULATION???? + FAPI_INF("Disable IVRMs"); - // rc = fapiPutScom(i_target, EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168 + (l_ex_number * 0x01000000), data ); - // if (l_rc) { FAPI_ERR("fapiPutScom(PCBS_LPFT_Control_Register_Reg0) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + if (pcbs_val_init.ivrms_enabled) + { + address = EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 + + (l_ex_number * 0x01000000); + GETSCOM(i_target, address, data); + FAPI_DBG(" Pre write content of PCBS_iVRM_Control_Status_Reg_0x1*0F0154 : %016llX", + data.getDoubleWord(0)); - // if debug mode read back - // if (VERBOSE) { - // rc = fapiGetScom(i_target, EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; - // FAPI_DBG(" Content of EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168 : %016llX", data.getDoubleWord(0)); - // } - // FAPI_INF ("Local Pstate Frequency Target mechanism disabled" ); + e_rc = data.clearBit(0); // disable ivrms + e_rc |= data.clearBit(4); // ivrm_core_vdd_bypass_b + e_rc |= data.clearBit(6); // ivrm_core_vcs_bypass_b + e_rc |= data.clearBit(8); // ivrm_eco_vdd_bypass_b + e_rc |= data.clearBit(10); // ivrm_eco_vcs_bypass_b + E_RC_CHECK(e_rc, l_rc); + PUTSCOM(i_target, address, data); + // Write twice since ivrm_fsm_enable have to be 0 to enable the set the bypass modes + PUTSCOM(i_target, address, data); - // ****************************************************************** - // Issue reset to PCBS-PM - // ****************************************************************** - FAPI_DBG("**************************** *********"); - FAPI_INF("Reset PCBS-PM"); - FAPI_DBG("**************************** *********"); + FAPI_INF ("iVRMs disabled and in bypass-mode" ); + } - // - //rc = fapiGetScom( i_target,PMGP1_REG_0x100F00103 + (l_ex_number * 0x01000000) , data ); if (l_rc) return rc; - //if (l_rc) { FAPI_ERR("fapiGetScom(PMGP1_REG_0x100F00103) failed."); return rc; } - /// \todo : Double Check: Is that the right way to set and unset the reset or keep the reset longer and then unset it at the end ? - //if (VERBOSE) { - // rc = fapiGetScom(i_target, EX_PMGP1_REG_0_RWXx100F0103 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; - // FAPI_DBG(" Pre write content of PMGP1_REG_0_RWXx1*0F0103 : %016llX", data.getDoubleWord(0)); - //} - - l_rc = data.flushTo0(); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - l_rc = data.setBit(9); //endp_reset_pm_only = 1 - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WORx100F0105 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(PMGP1_REG_0_WORx1*0F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - /// \todo : Double check if RESET is effective - // if debug mode read back - //if (VERBOSE) { - // rc = fapiGetScom(i_target, EX_PMGP1_REG_0_RWXx100F0103 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; - // FAPI_DBG(" Post (set reset) write content of PMGP1_REG_0_RWXx1*0F0103 : %016llX", data.getDoubleWord(0)); - //} - FAPI_INF("Set reset to PCBS-PM"); - - l_rc = data.flushTo1(); - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - l_rc = data.clearBit(9); //endp_reset_pm_only = 0 - if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WANDx100F0104 + (l_ex_number * 0x01000000), data ); - if (rc) { FAPI_ERR("fapiGetScom(EX_PMGP1_REG_0_WANDx100F0104) failed. With rc = 0x%x", (uint32_t)l_rc); return rc; } - - // if debug mode read back - //if (VERBOSE) { - // rc = fapiGetScom(i_target, EX_PMGP1_REG_0_RWXx100F0103 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; - // FAPI_DBG(" Post (unset reset) content of EX_PMGP1_REG_0_RWXx100F0103 : %016llX", data.getDoubleWord(0)); - //} - FAPI_INF("Unset reset to PCBS-PM"); - - - - - - - } //ELSE IF functional and ATTR_CHIP_UNIT_POS - } else - { - // EX is not functional - FAPI_DBG("Core number = %d is not functional", c); - } //IF functional - }//ELSE IF ATTR_FUNCTIONAL - - } //END FOR + // ****************************************************************** + // Disable undervolting + // ****************************************************************** + address = EX_PCBS_UNDERVOLTING_REG_0x100F015B + + (l_ex_number * 0x01000000); + GETSCOM(i_target, address, data); + FAPI_DBG(" Pre write content of PCBS_UNDERVOLTING_REG_0x1*0F015B : %016llX", + data.getDoubleWord(0)); + + e_rc |= data.setByte(0, pcbs_val_init.PUV_MIN); //Puv_min = -128 + e_rc |= data.setByte(1, pcbs_val_init.PUV_MAX); //Puv_max = -128 + e_rc |= data.setByte(2, pcbs_val_init.KUV); //Kuv = 0 + E_RC_CHECK(e_rc, l_rc); + + PUTSCOM(i_target, address, data); + FAPI_DBG("\t PUV_MIN => %d ", pcbs_val_init.PUV_MIN ); + FAPI_DBG("\t PUV_MAX => %d ", pcbs_val_init.PUV_MAX ); + FAPI_DBG("\t KUV => %d ", pcbs_val_init.KUV ); + + FAPI_INF ("Undervolting values reset done" ); + + // ****************************************************************** + // Disable Local Pstate Frequency Target mechanism + // ****************************************************************** + address = EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168 + + (l_ex_number * 0x01000000); + GETSCOM(i_target, address, data); - + e_rc |= data.clearBit(20); + E_RC_CHECK(e_rc, l_rc); + PUTSCOM(i_target, address, data); - FAPI_INF(""); - FAPI_INF("Executing p8_pcbs_init ....\n"); + FAPI_INF ("Local Pstate Frequency Target mechanism disabled" ); + } // Chiplet loop + } while(0); + if (l_rc.ok()) + { + FAPI_INF("Reset complete ...."); + } - return rc; + return l_rc; } // end RESET +//------------------------------------------------------------------------------ +/** + * Set the PCBS-PM macro register back to the scan0 state for those that need + * a known state for OCC firmware + * + * @param[in] i_target Chip target + * @param[in] i_ex_number EX chiplet number used to create correct addresses + * + * @retval ECMD_SUCCESS + * @retval ERROR defined in xml + */ +fapi::ReturnCode +p8_pcbs_init_scan0(const Target &i_target, uint8_t i_ex_number) +{ + fapi::ReturnCode l_rc; + uint32_t e_rc; // ecmd returncode + ecmdDataBufferBase data(64); + uint64_t address; + uint64_t reset_doubleword; + uint32_t reset_word; + ///TODO RTC: 71328 - hack to indicate unused + bool __attribute__((unused)) error_flag = false; + + do + { + // ****************************************************************** + // initialize all pm_reg with scan-zero values upfront + // ***************************************************************** + FAPI_INF("Put selective PCBSLV_PM registers to the scan0 value that are touched by OCC firmware"); + + // Register NOT reset + // EX_PMGP0_REG_0x100F0100 not reset as this control EX fencing + // EX_PMGP1_REG_0_RWXx100F0103 not reset as idle configuration is done + // by p8_poreslw_init + // EX_PFVddCntlStat_REG_0x100F0106 not reset has this would disrupt + // VDD to operational chiplets. + // EX_PFVddCntlStat_REG_0x100F010E not reset has this would disrupt + // VCS to operational chiplets + // EX_FREQCNTL_0x100F0151not reset has this would disrupt the frequency + // of operational chiplets + // EX_DPLL_CPM_PARM_REG_0x100F0152 not reset has this has DPLL control + // bits that could/would disrupt operational chiplets + // EX_PCBSPM_MODE_REG_0x100F0156 not reset as this register has DPLL + // control bits could/would disrupt operational chiplets + // EX_PCBS_Power_Management_Control_Reg_0x100F0159 not reset as this + // as this register only applies if the OCC is in control of PState + // and, upon reset, the OCC FW is designed to recover from ANY + // PState. If PHYP is in control of PStates, this register must + // remain intact. + // EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 not reset as this is reset fully + // by register accesses + + //---- + address = EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165 + + (i_ex_number * 0x01000000); + reset_doubleword = EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165_scan0; + SETDWSCAN0(i_target, address, data, reset_doubleword ); + + //---- + address = EX_PMErrMask_REG_0x100F010A + + (i_ex_number * 0x01000000); + reset_word = EX_PMErrMask_REG_0x100F010A_scan0; + SETSCAN0(i_target, address, data, reset_word ); + + // OCC does not mess with the PFET delays so these are left in tact. + + // This can only be done IF the IVRM is previously disabled. + address = EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 + + (i_ex_number * 0x01000000); + reset_word = EX_PCBS_iVRM_Control_Status_Reg_0x100F0154_scan0; + SETSCAN0(i_target, address, data, reset_word ); + + //---- + address = EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155 + + (i_ex_number * 0x01000000); + reset_word = EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155_scan0; + SETSCAN0(i_target, address, data, reset_word ); + + //---- + address = EX_PCBS_PMC_VF_CTRL_REG_0x100F015A + + (i_ex_number * 0x01000000); + reset_word = EX_PCBS_PMC_VF_CTRL_REG_0x100F015A_scan0; + SETSCAN0(i_target, address, data, reset_word ); + + //---- + address = EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C + + (i_ex_number * 0x01000000); + reset_word = EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C_scan0; + SETSCAN0(i_target, address, data, reset_word ); + + //---- + address = EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E + + (i_ex_number * 0x01000000); + reset_word = EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E_scan0; + SETSCAN0(i_target, address, data, reset_word ); + + //---- + address = EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162 + + (i_ex_number * 0x01000000); + reset_word = EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162_scan0; + SETSCAN0(i_target, address, data, reset_word ); + + //---- + address = EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163 + + (i_ex_number * 0x01000000); + reset_word = EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163_scan0; + SETSCAN0(i_target, address, data, reset_word ); + + //---- + address = EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166 + + (i_ex_number * 0x01000000); + reset_word = EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166_scan0; + SETSCAN0(i_target, address, data, reset_word ); + + /// \todo Regcheck error check at latest model + // address = EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168 + // + (i_ex_number * 0x01000000); + // reset_word = EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168_scan0; + // SETSCAN0(i_target, address, data, reset_word ); + } while(0); + return l_rc; +} +} //end extern C +/* +*************** Do not edit this area *************** +This section is automatically updated by CVS when you check in this file. +Be sure to create CVS comments when you commit so that they can be included here. +$Log: p8_pcbs_init.C,v $ +Revision 1.15 2013/04/12 01:31:59 stillgs +Added DPLL replacement enablement and value setting per hardware PManIrr testing + +Revision 1.14 2013/04/01 04:18:13 stillgs + +Remove Psafe calculation as this caused Grub crash; format clean-up for RAS review readiness + +Revision 1.13 2013/03/15 09:14:27 pchatnah +fixing jeshuas error handling suggestion + +Revision 1.12 2013/03/13 12:51:51 pchatnah +fixing some debug codes + +Revision 1.11 2013/02/27 03:50:00 stillgs +Clean up for the reset process. Removed some old code for cleanliness. + +Revision 1.10 2013/01/25 12:43:05 pchatnah +commenting out flusing DPLL_LOCK_TIMER_REPLACEMENT_VALUE to 0 -} //end extern C +*/ diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.H index b60cddab1..807abeee7 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.H +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.H @@ -20,25 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_pcbs_init.H,v 1.2 2012/09/20 07:35:31 rmaier Exp $ -// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pcbs_init.H,v $ +// $Id: p8_pcbs_init.H,v 1.4 2013/04/12 01:32:01 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pcbs_init.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -47,32 +30,50 @@ // *! OWNER NAME: Ralf Maier Email: ralf.maier@de.ibm.com // *! // *! The purpose of this procedure is to establish the safe setting for PCBSLV -// *! o set psafe value +// *! o set psafe value // *! o set PMIN clip/Pmax clip -// *! o PMCR default values -// *! o PMICR default values +// *! o PMCR default values +// *! o PMICR default values // *! // *! include file for pcbs_init with constants, definitions, prototypes // *! //------------------------------------------------------------------------------ -// + +#ifndef _P8_PCBSINIT_H_ +#define _P8_PCBSINIT_H_ + +/// \todo : PSAFE, PUV_MIN, PUV_MAX - Attributes defined as uint8 but should be int8 +typedef struct { + uint8_t ivrms_enabled; // ATTR_IVRMS_ENABLED + uint8_t PSAFE; // ATTR_SAFE_PSTATE PSAFE + uint8_t PUV_MIN; // ATTR_PSTATE_UNDERVOLTING_MINIMUM + uint8_t PUV_MAX; // ATTR_PSTATE_UNDERVOLTING_MAXIMUM + uint32_t MAX_PSAFE_FSM_LOOPS; // max number of times PCBS-PMSR has been checked + uint32_t MAX_DELAY; // max number of Delay + uint32_t MAX_SIM_CYCLES; // max number of SimCycles (will be used when FSP is target) + char GLOBAL_ACTUAL_PSTATE; // Global Actual PSTATE + char MIN_PSTATE; // + char FNOM; // + char DPLL_FMIN; // + char DPLL_FMAX; // + char PMIN_CLIP; // + char PMAX_CLIP; // + char KUV; // +} struct_pcbs_val_init_type; // function pointer typedef definition for HWP call support typedef fapi::ReturnCode (*p8_pcbs_init_FP_t) (const fapi::Target&, uint32_t); - extern "C" { +/// \param[in] &i_target Chip target +/// \param[in] mode Mode 1: CONFIG-Mode +/// Mode 2: RESET-Mode +/// Mode 3: INIT-Mode - - /// \param[in] &i_target Chip target - /// \param[in] mode Mode 1: CONFIG-Mode - /// Mode 2: RESET-Mode - /// Mode 3: INIT-Mode - - fapi::ReturnCode p8_pcbs_init (const fapi::Target& i_target, uint32_t mode); - -} +fapi::ReturnCode p8_pcbs_init (const fapi::Target& i_target, uint32_t mode); +} // extern "C" +#endif // _P8_PCBSINIT_H_ diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_firinit.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_firinit.C index 6927d7f66..f27cd2ddb 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_firinit.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_firinit.C @@ -20,24 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_pm_firinit.C,v 1.3 2012/09/11 10:31:30 pchatnah Exp $ +// $Id: p8_pm_firinit.C,v 1.10 2013/04/02 12:48:19 pchatnah Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_firinit.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -89,13 +72,7 @@ #include "p8_pm_oha_firinit.H" #include "p8_pm_occ_firinit.H" - - - -// #ifdef FAPIECMD extern "C" { - // #endif - using namespace fapi; @@ -103,17 +80,14 @@ using namespace fapi; // Constant definitions // ---------------------------------------------------------------------- - // ---------------------------------------------------------------------- // Global variables // ---------------------------------------------------------------------- - // ---------------------------------------------------------------------- // Function prototypes // ---------------------------------------------------------------------- - // ---------------------------------------------------------------------- // Function definitions // ---------------------------------------------------------------------- @@ -124,88 +98,137 @@ fapi::ReturnCode p8_pm_firinitlist(Target &i_target); // ---------------------------------------------------------------------- fapi::ReturnCode -p8_pm_firinit(const fapi::Target &i_target ) +p8_pm_firinit(const fapi::Target &i_target , uint32_t mode) { - - fapi::ReturnCode l_rc; + fapi::ReturnCode rc; + ecmdDataBufferBase data(64); + // ecmdDataBufferBase mask(64); + uint32_t e_rc = 0; + uint64_t any_error = 0; - - - // ****************************************************************** - // PMC_FIRS - // ****************************************************************** + fapi::ReturnCode l_fapi_rc; + + do + { - FAPI_DBG(""); - FAPI_EXEC_HWP(l_rc, p8_pm_pmc_firinit , i_target ); - if (l_rc) - { - FAPI_ERR("ERROR: p8_pm_pmc_firinit detected failed result"); - return l_rc; - } - +// ************************************************************* + // CHECKING FOR FIRS BEFORE RESET and INIT +// ************************************************************* + + FAPI_DBG("checking FIRs of PBA PMC OCC ..."); + +// PMC FIR + e_rc = data.flushTo0(); if(e_rc){rc.setEcmdError(e_rc); return rc;} + rc = fapiGetScom(i_target, PMC_LFIR_0x01010840 , data ); + if (rc) { + FAPI_ERR("fapiGetScom(PMC_LFIR_0x01010840) failed."); return rc; + } + + any_error = data.getDoubleWord(0); + + if (any_error) + { + FAPI_ERR(" PMC_FIR has error(s) active. 0x%16llX ", data.getDoubleWord(0)); + //FAPI_SET_HWP_ERROR(rc, RC_PROCPM_FIR_ERROR); return rc; + //return rc ; + } + +// PBA FIR + e_rc = data.flushTo0(); if(e_rc){rc.setEcmdError(e_rc); return rc;} + rc = fapiGetScom(i_target, PBA_FIR_0x02010840 , data ); + if (rc) { + FAPI_ERR("fapiGetScom(PBA_FIR_0x02010840) failed."); return rc; + } + + any_error = data.getDoubleWord(0); + + if (any_error) + { + FAPI_ERR(" PBA_FIR_0x02010840 has error(s) active. 0x%16llX ", data.getDoubleWord(0)); + //FAPI_SET_HWP_ERROR(rc, RC_PROCPM_FIR_ERROR); return rc; + //return rc ; + } + + +// OCC FIR + e_rc = data.flushTo0(); if(e_rc){rc.setEcmdError(e_rc); return rc;} + rc = fapiGetScom(i_target, OCC_LFIR_0x01010800 , data ); + if (rc) { + FAPI_ERR("fapiGetScom(OCC_LFIR_0x01010800) failed."); return rc; + } + + any_error = data.getDoubleWord(0); + + if (any_error) + { + FAPI_ERR(" OCC_LFIR_0x01010800 has error(s) active. 0x%16llX ", data.getDoubleWord(0)); + //FAPI_SET_HWP_ERROR(rc, RC_PROCPM_FIR_ERROR); return rc; + //return rc ; + } - // ****************************************************************** - // PBA - // ****************************************************************** - - - FAPI_DBG(""); - FAPI_EXEC_HWP(l_rc, p8_pm_pba_firinit , i_target ); - if (l_rc) - { - FAPI_ERR("ERROR: p8_pm_pba_firinit detected failed result"); - return l_rc; - } - - // ****************************************************************** - // OHA - // ****************************************************************** - - - FAPI_DBG(""); - FAPI_EXEC_HWP(l_rc, p8_pm_oha_firinit , i_target ); - if (l_rc) - { - FAPI_ERR("ERROR: p8_pm_oha_firinit detected failed result"); - return l_rc; - } - - // ****************************************************************** - // PCBS - // ****************************************************************** - - - FAPI_DBG(""); - FAPI_EXEC_HWP(l_rc, p8_pm_pcbs_firinit , i_target ); - if (l_rc) - { - FAPI_ERR("ERROR: p8_pm_pcbs_firinit detected failed result"); - return l_rc; - } - - - // ****************************************************************** - // OCC - // ****************************************************************** - - - FAPI_DBG(""); - FAPI_EXEC_HWP(l_rc, p8_pm_occ_firinit , i_target ); - if (l_rc) - { - FAPI_ERR("ERROR: p8_pm_occ_firinit detected failed result"); - return l_rc; - } - + + // ****************************************************************** + // PMC_FIRS + // ****************************************************************** + + FAPI_EXEC_HWP(l_fapi_rc, p8_pm_pmc_firinit , i_target , mode ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_pmc_firinit detected failed result"); + break; + } + + // ****************************************************************** + // PBA + // ****************************************************************** + ; + FAPI_EXEC_HWP(l_fapi_rc, p8_pm_pba_firinit , i_target , mode ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_pba_firinit detected failed result"); + break; + } + + // ****************************************************************** + // OHA + // ****************************************************************** + + FAPI_EXEC_HWP(l_fapi_rc, p8_pm_oha_firinit , i_target , mode ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_oha_firinit detected failed result"); + break; + } + + // ****************************************************************** + // PCBS + // ****************************************************************** + + FAPI_EXEC_HWP(l_fapi_rc, p8_pm_pcbs_firinit , i_target , mode ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_pcbs_firinit detected failed result"); + break; + } + + // ****************************************************************** + // OCC + // ****************************************************************** + + FAPI_EXEC_HWP(l_fapi_rc, p8_pm_occ_firinit , i_target , mode ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_occ_firinit detected failed result"); + break; + } + + } while(0); - return l_rc; + return l_fapi_rc; -} - +} // Procedure - //#ifdef FAPIECMD } //end extern C -//#endif diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_firinit.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_firinit.H index 1a2790c63..a333cfd1b 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_firinit.H +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_firinit.H @@ -20,24 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_pm_firinit.H,v 1.5 2012/09/18 14:08:57 pchatnah Exp $ +// $Id: p8_pm_firinit.H,v 1.9 2013/04/01 04:27:47 stillgs Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_firinit.H,v $ //------------------------------------------------------------------------------ // *| @@ -62,7 +45,12 @@ // MACRO structure definitions //------------------------------------------------------------------------------ - #define SET_FIR_ACTION(b, x, y){ \ +#ifndef _P8_PM_FIRINIT_H_ +#define _P8_PM_FIRINIT_H_ + +#include "p8_pm.H" + +#define SET_FIR_ACTION(b, x, y){ \ if (x) { \ e_rc |= action_0.setBit(b); \ } \ @@ -79,10 +67,7 @@ }\ } - - - - #define SET_FIR_MASK(b,y){ \ +#define SET_FIR_MASK(b,y){ \ if (y) { \ e_rc |= mask.setBit(b); \ } \ @@ -92,16 +77,14 @@ } \ } - - #define SET_CHECK_STOP(b){SET_FIR_ACTION(b, 0, 0);} #define SET_RECOV_ATTN(b){SET_FIR_ACTION(b, 0, 1);} #define SET_RECOV_INTR(b){SET_FIR_ACTION(b, 1, 0);} #define SET_MALF_ALERT(b){SET_FIR_ACTION(b, 1, 1);} #define SET_FIR_MASKED(b){SET_FIR_MASK(b,1);} - -typedef fapi::ReturnCode (*p8_pm_firinit_FP_t) (const fapi::Target& ); +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*p8_pm_firinit_FP_t) (const fapi::Target& , uint32_t mode ); extern "C" { @@ -114,8 +97,16 @@ extern "C" { /// \calls p8_pm_occ_firinit +const uint32_t PCB_FIR_REGISTER_LENGTH = 43 ; +const uint32_t PMC_FIR_REGISTER_LENGTH = 49 ; +const uint32_t PBA_FIR_REGISTER_LENGTH = 46 ; +const uint32_t OHA_FIR_REGISTER_LENGTH = 6 ; +const uint32_t OCC_FIR_REGISTER_LENGTH = 64 ; + /// \ input chip_target -fapi::ReturnCode p8_pm_firinit(const fapi::Target& i_target ); +fapi::ReturnCode p8_pm_firinit(const fapi::Target& i_target , uint32_t mode); } // extern "C" + +#endif diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_init.C index 6cf80087d..a52c41106 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_init.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_init.C @@ -20,25 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_pm_init.C,v 1.8 2012/10/10 14:33:49 pchatnah Exp $ -// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_init.C,v $ +// $Id: p8_pm_init.C,v 1.18 2013/04/16 12:00:34 pchatnah Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_init.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -107,10 +90,7 @@ #include "p8_pm.H" #include "p8_pm_init.H" -//#ifdef FAPIECMD extern "C" { - //#endif - using namespace fapi; @@ -132,37 +112,30 @@ using namespace fapi; // ---------------------------------------------------------------------- // Function definitions // ---------------------------------------------------------------------- - fapi::ReturnCode p8_pm_list(const Target& i_target, uint32_t mode); + fapi::ReturnCode p8_pm_list(const Target& i_target, const Target& i_target2, uint32_t mode); // ---------------------------------------------------------------------- // p8_pm_init // ---------------------------------------------------------------------- fapi::ReturnCode -p8_pm_init(const fapi::Target &i_target, uint32_t mode) +p8_pm_init(const fapi::Target &i_target1 ,const fapi::Target &i_target2 , uint32_t mode) { fapi::ReturnCode l_fapi_rc; - - - // ****************************************************************** - + FAPI_INF("Executing p8_pm_init in mode %x ....\n", mode); /// ------------------------------- /// Configuration/Initialation if (mode == PM_CONFIG || mode == PM_INIT || mode == PM_RESET) - { - - l_fapi_rc = p8_pm_list(i_target, mode); - if (l_fapi_rc) - { - FAPI_ERR("ERROR: p8_pm_list detected failed "); - return l_fapi_rc; - } - - - + { + l_fapi_rc = p8_pm_list(i_target1, i_target2, mode); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_list detected failed "); + return l_fapi_rc; + } } /// ------------------------------- /// Unsupported Mode @@ -175,7 +148,6 @@ p8_pm_init(const fapi::Target &i_target, uint32_t mode) } - return l_fapi_rc; } @@ -185,34 +157,51 @@ p8_pm_init(const fapi::Target &i_target, uint32_t mode) // ---------------------------------------------------------------------- fapi::ReturnCode -p8_pm_list(const Target& i_target, uint32_t mode) +p8_pm_list(const Target& i_target, const Target& i_target2, uint32_t mode) { fapi::ReturnCode l_fapi_rc; + uint64_t SP_WKUP_REG_ADDRS; + uint8_t l_functional = 0; + uint8_t l_ex_number = 0; + ecmdDataBufferBase data(64); + + std::vector<fapi::Target> l_exChiplets; + // ****************************************************************** // PCBS_PM // ****************************************************************** - + + FAPI_INF("Executing: p8_pcbs_init.C in mode %x", mode); - FAPI_INF("Executing: p8_pcbs_init.C in mode %x", mode); - FAPI_EXEC_HWP(l_fapi_rc, p8_pcbs_init, i_target, mode); - if (l_fapi_rc) - { + if ( i_target.getType() != TARGET_TYPE_NONE ) + { + FAPI_EXEC_HWP(l_fapi_rc, p8_pcbs_init, i_target, mode); + if (l_fapi_rc) + { FAPI_ERR("ERROR: p8_pm_init detected failed PCBS_PM result"); return l_fapi_rc; - } - + } + } + if ( i_target2.getType() != TARGET_TYPE_NONE ) + { + FAPI_EXEC_HWP(l_fapi_rc, p8_pcbs_init, i_target2, mode); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed PCBS_PM result"); + return l_fapi_rc; + } + } // ****************************************************************** // PMC // ****************************************************************** - FAPI_INF("Executing: p8_pmc_init in mode %x", mode); - FAPI_EXEC_HWP(l_fapi_rc, p8_pmc_init, i_target, mode); + FAPI_EXEC_HWP(l_fapi_rc, p8_pmc_init, i_target, i_target2, mode); if (l_fapi_rc) { FAPI_ERR("ERROR: p8_pm_init detected failed PMC result"); @@ -224,41 +213,78 @@ p8_pm_list(const Target& i_target, uint32_t mode) // ****************************************************************** FAPI_INF("Executing: p8_poreslw_init in mode %x", mode); - - FAPI_EXEC_HWP(l_fapi_rc, p8_poreslw_init, i_target, mode); - if (l_fapi_rc) - { - FAPI_ERR("ERROR: p8_pm_init detected failed PORE SLW result"); - return l_fapi_rc; - } - + if ( i_target.getType() != TARGET_TYPE_NONE ) + { + FAPI_EXEC_HWP(l_fapi_rc, p8_poreslw_init, i_target, mode); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed PORE SLW result"); + return l_fapi_rc; + } + } + + if ( i_target2.getType() != TARGET_TYPE_NONE ) + { + FAPI_EXEC_HWP(l_fapi_rc, p8_poreslw_init, i_target2, mode); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed PORE SLW result"); + return l_fapi_rc; + } + } // ****************************************************************** // PORE General Purpose Engines // ****************************************************************** FAPI_INF("Executing: p8_poregpe_init in mode %x", mode); - FAPI_EXEC_HWP(l_fapi_rc, p8_poregpe_init, i_target, mode , GPEALL); - if (l_fapi_rc) - { - FAPI_ERR("ERROR: p8_pm_init detected failed PORE GPE result"); - return l_fapi_rc; - } + if ( i_target.getType() != TARGET_TYPE_NONE ) + { + FAPI_EXEC_HWP(l_fapi_rc, p8_poregpe_init, i_target, mode , GPEALL); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed PORE GPE result"); + return l_fapi_rc; + } + + } + + if ( i_target2.getType() != TARGET_TYPE_NONE ) + { + FAPI_EXEC_HWP(l_fapi_rc, p8_poregpe_init, i_target2, mode , GPEALL); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed PORE GPE result"); + return l_fapi_rc; + } + } // ****************************************************************** // OHA // ****************************************************************** FAPI_INF("Executing: p8_oha_init in mode %x", mode); - - FAPI_EXEC_HWP(l_fapi_rc, p8_oha_init, i_target, PM_CONFIG ); - if (l_fapi_rc) - { - FAPI_ERR("ERROR: p8_pm_init detected failed OHA result"); - return l_fapi_rc; - } - + if ( i_target.getType() != TARGET_TYPE_NONE ) + { + FAPI_EXEC_HWP(l_fapi_rc, p8_oha_init, i_target, mode); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed OHA result"); + return l_fapi_rc; + } + } + + if ( i_target2.getType() != TARGET_TYPE_NONE ) + { + FAPI_EXEC_HWP(l_fapi_rc, p8_oha_init, i_target2, mode); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed OHA result"); + return l_fapi_rc; + } + } + // ****************************************************************** // OCC-SRAM // ****************************************************************** @@ -266,81 +292,313 @@ p8_pm_list(const Target& i_target, uint32_t mode) FAPI_INF("Executing: p8_occ_sram_init in mode %x", mode); - FAPI_EXEC_HWP(l_fapi_rc, p8_occ_sram_init, i_target, mode ); - if (l_fapi_rc) - { - FAPI_ERR("ERROR: p8_pm_init detected failed OCC-SRAM result"); - return l_fapi_rc; - } + if ( i_target.getType() != TARGET_TYPE_NONE ) + { + FAPI_EXEC_HWP(l_fapi_rc, p8_occ_sram_init, i_target, mode ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed OCC-SRAM result"); + return l_fapi_rc; + } + } + + if ( i_target2.getType() != TARGET_TYPE_NONE ) + { + FAPI_EXEC_HWP(l_fapi_rc, p8_occ_sram_init, i_target2, mode ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed OCC-SRAM result"); + return l_fapi_rc; + } + } // ****************************************************************** // OCB // ****************************************************************** FAPI_INF("Executing: p8_ocb_init in mode %x", mode); + if ( i_target.getType() != TARGET_TYPE_NONE ) + { - FAPI_EXEC_HWP(l_fapi_rc, p8_ocb_init, i_target, mode,OCB_CHAN0,OCB_TYPE_NULL, 0x10000000, 1 , OCB_Q_OUFLOW_EN , OCB_Q_ITPTYPE_NOTFULL ); - if (l_fapi_rc) - { - FAPI_ERR("ERROR: p8_pm_init detected failed OCB result on channel 0"); - return l_fapi_rc; - } + FAPI_EXEC_HWP(l_fapi_rc, p8_ocb_init, i_target, mode,OCB_CHAN0,OCB_TYPE_NULL, 0x10000000, 1 , OCB_Q_OUFLOW_EN , OCB_Q_ITPTYPE_NOTFULL ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed OCB result on channel 0"); + return l_fapi_rc; + } - FAPI_EXEC_HWP(l_fapi_rc, p8_ocb_init, i_target, mode,OCB_CHAN1,OCB_TYPE_NULL, 0x10000000, 1 , OCB_Q_OUFLOW_EN , OCB_Q_ITPTYPE_NOTFULL ); - if (l_fapi_rc) - { - FAPI_ERR("ERROR: p8_pm_init detected failed OCB result on channel 1"); - return l_fapi_rc; - } + FAPI_EXEC_HWP(l_fapi_rc, p8_ocb_init, i_target, mode,OCB_CHAN1,OCB_TYPE_NULL, 0x10000000, 1 , OCB_Q_OUFLOW_EN , OCB_Q_ITPTYPE_NOTFULL ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed OCB result on channel 1"); + return l_fapi_rc; + } - FAPI_EXEC_HWP(l_fapi_rc, p8_ocb_init, i_target, mode,OCB_CHAN2,OCB_TYPE_NULL, 0x10000000, 1 , OCB_Q_OUFLOW_EN , OCB_Q_ITPTYPE_NOTFULL ); - if (l_fapi_rc) - { - FAPI_ERR("ERROR: p8_pm_init detected failed OCB result on channel 2"); - return l_fapi_rc; - } + FAPI_EXEC_HWP(l_fapi_rc, p8_ocb_init, i_target, mode,OCB_CHAN2,OCB_TYPE_NULL, 0x10000000, 1 , OCB_Q_OUFLOW_EN , OCB_Q_ITPTYPE_NOTFULL ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed OCB result on channel 2"); + return l_fapi_rc; + } - FAPI_EXEC_HWP(l_fapi_rc, p8_ocb_init, i_target, mode,OCB_CHAN3,OCB_TYPE_NULL, 0x10000000, 1 , OCB_Q_OUFLOW_EN , OCB_Q_ITPTYPE_NOTFULL ); - if (l_fapi_rc) - { - FAPI_ERR("ERROR: p8_pm_init detected failed OCB result on channel 0"); - return l_fapi_rc; - } + FAPI_EXEC_HWP(l_fapi_rc, p8_ocb_init, i_target, mode,OCB_CHAN3,OCB_TYPE_NULL, 0x10000000, 1 , OCB_Q_OUFLOW_EN , OCB_Q_ITPTYPE_NOTFULL ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed OCB result on channel 0"); + return l_fapi_rc; + } + + } + + if ( i_target2.getType() != TARGET_TYPE_NONE ) + { + + + FAPI_EXEC_HWP(l_fapi_rc, p8_ocb_init, i_target2, mode,OCB_CHAN0,OCB_TYPE_NULL, 0x10000000, 1 , OCB_Q_OUFLOW_EN , OCB_Q_ITPTYPE_NOTFULL ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed OCB result on channel 0"); + return l_fapi_rc; + } + + FAPI_EXEC_HWP(l_fapi_rc, p8_ocb_init, i_target2, mode,OCB_CHAN1,OCB_TYPE_NULL, 0x10000000, 1 , OCB_Q_OUFLOW_EN , OCB_Q_ITPTYPE_NOTFULL ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed OCB result on channel 1"); + return l_fapi_rc; + } + + FAPI_EXEC_HWP(l_fapi_rc, p8_ocb_init, i_target2, mode,OCB_CHAN2,OCB_TYPE_NULL, 0x10000000, 1 , OCB_Q_OUFLOW_EN , OCB_Q_ITPTYPE_NOTFULL ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed OCB result on channel 2"); + return l_fapi_rc; + } + + FAPI_EXEC_HWP(l_fapi_rc, p8_ocb_init, i_target2, mode,OCB_CHAN3,OCB_TYPE_NULL, 0x10000000, 1 , OCB_Q_OUFLOW_EN , OCB_Q_ITPTYPE_NOTFULL ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed OCB result on channel 0"); + return l_fapi_rc; + } + + } + // ****************************************************************** // PSS // ****************************************************************** + + FAPI_INF("Executing:p8_pss_init in mode %x", mode); + + if ( i_target.getType() != TARGET_TYPE_NONE ) + { + FAPI_EXEC_HWP(l_fapi_rc, p8_pss_init, i_target, mode ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed PSS result"); + return l_fapi_rc; + } + } - FAPI_INF("Executing:p8_pss_init in mode %x", mode); + if ( i_target2.getType() != TARGET_TYPE_NONE ) + { + FAPI_EXEC_HWP(l_fapi_rc, p8_pss_init, i_target2, mode ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed PSS result"); + return l_fapi_rc; + } + } + + // ****************************************************************** + // PBA + // ****************************************************************** - FAPI_EXEC_HWP(l_fapi_rc, p8_pss_init, i_target, mode ); - if (l_fapi_rc) - { - FAPI_ERR("ERROR: p8_pm_init detected failed PSS result"); - return l_fapi_rc; - } + FAPI_INF("Executing: p8_pba_init in mode %x", mode); + if ( i_target.getType() != TARGET_TYPE_NONE ) + { + FAPI_EXEC_HWP(l_fapi_rc, p8_pba_init, i_target, mode ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed PBA result"); + return l_fapi_rc; + } + } + + if ( i_target2.getType() != TARGET_TYPE_NONE ) + { + FAPI_EXEC_HWP(l_fapi_rc, p8_pba_init, i_target2, mode ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed PBA result"); + return l_fapi_rc; + } + } + + + + + + // loop over all the core chiplets + if (mode == PM_INIT) + { + // ****************************************************************** - // PBA + // FIRINIT // ****************************************************************** - FAPI_INF("Executing: p8_pba_init in mode %x", mode); - - FAPI_EXEC_HWP(l_fapi_rc, p8_pba_init, i_target, mode ); - if (l_fapi_rc) - { - FAPI_ERR("ERROR: p8_pm_init detected failed PBA result"); - return l_fapi_rc; - } + FAPI_INF("Executing:p8_pm_firinit in mode %x", mode); + + if ( i_target.getType() != TARGET_TYPE_NONE ) + { - return l_fapi_rc; + FAPI_EXEC_HWP(l_fapi_rc, p8_pm_firinit, i_target , mode ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_firinit detected failed result"); + return l_fapi_rc; + } + } + + if ( i_target2.getType() != TARGET_TYPE_NONE ) + { + + FAPI_EXEC_HWP(l_fapi_rc, p8_pm_firinit, i_target2 , mode ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_firinit detected failed result"); + return l_fapi_rc; + } + } + + + // ****************************************************************** + // CPU_SPECIAL_WAKEUP switch off + // ****************************************************************** + + + if ( i_target.getType() != TARGET_TYPE_NONE ) + { + l_fapi_rc = fapiGetChildChiplets ( i_target, + TARGET_TYPE_EX_CHIPLET, + l_exChiplets, + TARGET_STATE_PRESENT); + if (l_fapi_rc) + { + FAPI_ERR("Error from fapiGetChildChiplets!"); + return l_fapi_rc; + } + + FAPI_DBG("\tChiplet vector size => %u ", l_exChiplets.size()); + + // Iterate through the returned chiplets + for (uint8_t j=0; j < l_exChiplets.size(); j++) + { + + // Determine if it's functional + l_fapi_rc = FAPI_ATTR_GET( ATTR_FUNCTIONAL, + &l_exChiplets[j], + l_functional); + if (l_fapi_rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL error"); + break; + } + + if ( l_functional ) + { + // The ex is functional let's build the SCOM address + l_fapi_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[j], l_ex_number); + FAPI_DBG("Running special wakeup on ex chiplet %d ", l_ex_number); + + // Set special wakeup for EX + // Commented due to attribute errors + SP_WKUP_REG_ADDRS = PM_SPECIAL_WKUP_OCC_0x100F010C + (l_ex_number * 0x01000000) ; + l_fapi_rc=fapiGetScom(i_target, SP_WKUP_REG_ADDRS , data); if(l_fapi_rc) return l_fapi_rc; + FAPI_DBG(" Before clear of SPWKUP_REG PM_SPECIAL_WKUP_OCC_(0x%08llx) => =>0x%16llx", SP_WKUP_REG_ADDRS, data.getDoubleWord(0)); + + if (data.isBitSet(0)) + { + // FAPI_EXEC_HWP(l_fapi_rc, p8_cpu_special_wakeup, l_exChiplets[j], SPCWKUP_DISABLE , HOST); + l_fapi_rc = fapiSpecialWakeup(l_exChiplets[j], false); + if (l_fapi_rc) { FAPI_ERR("p8_cpu_special_wakeup: Failed to put CORE into special wakeup. With rc = 0x%x", (uint32_t)l_fapi_rc); return l_fapi_rc; } + + + } + } + } // chiplet loop + + } + ///////////////////////////////////////////// SLAVE TARGET ///////////////////////////////////////////////// + + + if ( i_target2.getType() != TARGET_TYPE_NONE ) + { + l_fapi_rc = fapiGetChildChiplets ( i_target2, + TARGET_TYPE_EX_CHIPLET, + l_exChiplets, + TARGET_STATE_PRESENT); + if (l_fapi_rc) + { + FAPI_ERR("Error from fapiGetChildChiplets!"); + return l_fapi_rc; + } + + FAPI_DBG("\tChiplet vector size => %u ", l_exChiplets.size()); + + // Iterate through the returned chiplets + for (uint8_t j=0; j < l_exChiplets.size(); j++) + { + + // Determine if it's functional + l_fapi_rc = FAPI_ATTR_GET( ATTR_FUNCTIONAL, + &l_exChiplets[j], + l_functional); + if (l_fapi_rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL error"); + break; + } + + if ( l_functional ) + { + // The ex is functional let's build the SCOM address + l_fapi_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[j], l_ex_number); + FAPI_DBG("Running special wakeup on ex chiplet %d ", l_ex_number); + + // Set special wakeup for EX + // Commented due to attribute errors + SP_WKUP_REG_ADDRS = PM_SPECIAL_WKUP_OCC_0x100F010C + (l_ex_number * 0x01000000) ; + l_fapi_rc=fapiGetScom(i_target2, SP_WKUP_REG_ADDRS , data); if(l_fapi_rc) return l_fapi_rc; + FAPI_DBG(" Before clear of SPWKUP_REG PM_SPECIAL_WKUP_OCC_(0x%08llx) => =>0x%16llx", SP_WKUP_REG_ADDRS, data.getDoubleWord(0)); + + if (data.isBitSet(0)) + { + // FAPI_EXEC_HWP(l_fapi_rc, p8_cpu_special_wakeup, l_exChiplets[j], SPCWKUP_DISABLE , HOST); + l_fapi_rc = fapiSpecialWakeup(l_exChiplets[j], false); + if (l_fapi_rc) { FAPI_ERR("p8_cpu_special_wakeup: Failed to put CORE into special wakeup. With rc = 0x%x", (uint32_t)l_fapi_rc); return l_fapi_rc; } + + + } + } + } // chiplet loop + } + + + + + + } + return l_fapi_rc; -} +} //#ifdef FAPIECMD diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_init.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_init.H index cfb954875..7301d71c9 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_init.H +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_init.H @@ -20,25 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_pm_init.H,v 1.4 2012/10/10 13:59:26 pchatnah Exp $ -// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_init.H,v $ +// $Id: p8_pm_init.H,v 1.7 2013/04/06 02:14:19 pchatnah Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_init.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -62,6 +45,8 @@ #include "p8_occ_sram_init.H" #include "p8_ocb_init.H" #include "p8_pss_init.H" +#include "p8_cpu_special_wakeup.H" +#include "p8_pm_firinit.H" /** * @brief Function pointer typedef. @@ -70,7 +55,7 @@ -typedef fapi::ReturnCode (*p8_pm_init_FP_t) (const fapi::Target&, uint32_t); +typedef fapi::ReturnCode (*p8_pm_init_FP_t) (const fapi::Target&, const fapi::Target&, uint32_t); extern "C" { @@ -91,7 +76,7 @@ extern "C" /// \param[in] mode PM_CONFIG, PM_INIT -fapi::ReturnCode p8_pm_init(const fapi::Target &i_target, uint32_t mode); +fapi::ReturnCode p8_pm_init(const fapi::Target &i_target1 , const fapi::Target &i_target2, uint32_t mode); } diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_occ_firinit.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_occ_firinit.C index 5d6c1bbe2..086492a92 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_occ_firinit.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_occ_firinit.C @@ -20,25 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_pm_occ_firinit.C,v 1.6 2012/10/04 03:41:45 jimyac Exp $ -// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_occ_firinit.C,v $ +// $Id: p8_pm_occ_firinit.C,v 1.12 2013/04/12 01:17:23 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_occ_firinit.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -61,7 +44,6 @@ // ---------------------------------------------------------------------- #include <fapi.H> #include "p8_scom_addresses.H" -#include "p8_pm_firinit.H" #include "p8_pm_occ_firinit.H" extern "C" { @@ -93,148 +75,199 @@ using namespace fapi; /// \retval FAPI_RC_SUCCESS /// \retval ERROR fapi::ReturnCode -p8_pm_occ_firinit(const fapi::Target& i_target) +p8_pm_occ_firinit(const fapi::Target& i_target , uint32_t mode) { - ReturnCode rc; - ecmdDataBufferBase action_0(64); - ecmdDataBufferBase action_1(64); - ecmdDataBufferBase mask(64); - uint32_t e_rc = 0; - - FAPI_INF("Executing p8_pm_occ_firinit ....\n"); - - // make action default be RECOV_ATTN - "01" - e_rc = action_0.flushTo0(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } - e_rc = action_1.flushTo1(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } - - // make mask default be unmasked - "0" - e_rc = mask.flushTo0() ; if (e_rc) { rc.setEcmdError(e_rc); return rc; } - - // ------------------------------------------------------------------------ - // set the action and mask for the OCC LFIR bits using the following macros - // ------------------------------------------------------------------------ - // Action0/1 Setting Macros - 4 possible settings - // SET_CHECK_STOP(b) - sets action0/1 to "00" for LFIR bit b - // SET_RECOV_ATTN(b) - sets action0/1 to "01" for LFIR bit b - // SET_RECOV_INTR(b) - sets action0/1 to "10" for LFIR bit b - // SET_MALF_ALERT(b) - sets action0/1 to "11" for LFIR bit b - // - // Mask Setting Macro - // SET_FIR_MASKED(b) - sets mask to '1' for LFIR bit b - // ------------------------------------------------------------------------ - - SET_MALF_ALERT(0); // 0 = occ_fw0 - SET_MALF_ALERT(1); // 1 = occ_fw1 - SET_MALF_ALERT(2); // 2 = occ_fw2 - SET_MALF_ALERT(3); // 3 = occ_fw3 - SET_MALF_ALERT(4); // 4 = pmc_pore_sw_malf - SET_MALF_ALERT(5); // 5 = pmc_occ_hb_malf - - SET_FIR_MASKED(6); // 6 = pore_gpe0_fatal_err - SET_FIR_MASKED(7); // 7 = pore_gpe1_fatal_err - SET_FIR_MASKED(8); // 8 = ocb_error - - SET_RECOV_ATTN(9); // 9 = srt_ue - SET_RECOV_ATTN(10); // 10 = srt_ce - SET_RECOV_ATTN(11); // 11 = srt_read_error - SET_RECOV_ATTN(12); // 12 = srt_write_error - SET_RECOV_ATTN(13); // 13 = srt_dataout_perr - SET_RECOV_ATTN(14); // 14 = srt_oci_write_data_parity - SET_RECOV_ATTN(15); // 15 = srt_oci_be_parity_err - SET_RECOV_ATTN(16); // 16 = srt_oci_addr_parity_err - - SET_FIR_MASKED(17); // 17 = pore_sw_error_err - SET_FIR_MASKED(18); // 18 = pore_gpe0_error_err - SET_FIR_MASKED(19); // 19 = pore_gpe1_error_err - SET_FIR_MASKED(20); // 20 = external_trap - SET_FIR_MASKED(21); // 21 = ppc405_core_reset - SET_FIR_MASKED(22); // 22 = ppc405_chip_reset - SET_FIR_MASKED(23); // 23 = ppc405_system_reset - SET_FIR_MASKED(24); // 24 = ppc405_dbgmsrwe - SET_FIR_MASKED(25); // 25 = ppc405_dbgstopack - - SET_RECOV_ATTN(26); // 26 = ocb_db_oci_timeout - SET_RECOV_ATTN(27); // 27 = ocb_db_oci_read_data_parity - SET_RECOV_ATTN(28); // 28 = ocb_db_oci_slave_error - SET_RECOV_ATTN(29); // 29 = ocb_pib_addr_parity_err - SET_RECOV_ATTN(30); // 30 = ocb_db_pib_data_parity_err - SET_RECOV_ATTN(31); // 31 = ocb_idc0_error - SET_RECOV_ATTN(32); // 32 = ocb_idc1_error - SET_RECOV_ATTN(33); // 33 = ocb_idc2_error - SET_RECOV_ATTN(34); // 34 = ocb_idc3_error - SET_RECOV_ATTN(35); // 35 = srt_fsm_err - SET_RECOV_ATTN(36); // 36 = jtagacc_err - - SET_FIR_MASKED(37); // 37 = spare_err_37 - - SET_RECOV_ATTN(38); // 38 = c405_ecc_ue - SET_RECOV_ATTN(39); // 39 = c405_ecc_ce - - SET_FIR_MASKED(40); // 40 = c405_oci_machinecheck - - SET_RECOV_ATTN(41); // 41 = sram_spare_direct_error0 - SET_RECOV_ATTN(42); // 42 = sram_spare_direct_error1 - SET_RECOV_ATTN(43); // 43 = sram_spare_direct_error2 - SET_RECOV_ATTN(44); // 44 = sram_spare_direct_error3 - SET_RECOV_ATTN(45); // 45 = slw_ocislv_err - SET_RECOV_ATTN(46); // 46 = gpe_ocislv_err - SET_RECOV_ATTN(47); // 47 = ocb_ocislv_err - SET_RECOV_ATTN(48); // 48 = c405icu_m_timeout - SET_RECOV_ATTN(49); // 49 = c405dcu_m_timeout - - SET_FIR_MASKED(50); // 50 = spare_fir - SET_FIR_MASKED(51); // 51 = spare_fir - SET_FIR_MASKED(52); // 52 = spare_fir - SET_FIR_MASKED(53); // 53 = spare_fir - SET_FIR_MASKED(54); // 54 = spare_fir - SET_FIR_MASKED(55); // 55 = spare_fir - SET_FIR_MASKED(56); // 56 = spare_fir - SET_FIR_MASKED(57); // 57 = spare_fir - SET_FIR_MASKED(58); // 58 = spare_fir - SET_FIR_MASKED(59); // 59 = spare_fir - SET_FIR_MASKED(60); // 60 = spare_fir - SET_FIR_MASKED(61); // 61 = spare_fir - - SET_RECOV_ATTN(62); // 62 = fir_parity_err_dup - SET_RECOV_ATTN(63); // 63 = fir_parity_err - - if (e_rc){ - rc.setEcmdError(e_rc); - return rc; - } - - FAPI_INF(" action_0 => %016llX ", action_0.getDoubleWord(0)); - FAPI_INF(" action_1 => %016llX ", action_1.getDoubleWord(0)); - FAPI_INF(" mask => %016llX ", mask.getDoubleWord(0)); - - // --------------- - // OCC_FIR_ACTION0 - // --------------- - rc = fapiPutScom(i_target, OCC_LFIR_ACT0_0x01010806, action_0 ); - if (!rc.ok()) { - FAPI_ERR("fapiPutScom(OCC_LFIR_ACT0_0x01010806) failed."); - return rc; - } - - // ---------------- - // OCC_FIR_ACTION1 - // ---------------- - rc = fapiPutScom(i_target, OCC_LFIR_ACT1_0x01010807, action_1 ); - if (!rc.ok()) { - FAPI_ERR("fapiPutScom(OCC_LFIR_ACT1_0x01010807) failed."); - return rc; - } - - // ------------ - // OCC_FIR_MASK - // ------------ - rc = fapiPutScom(i_target, OCC_LFIR_MASK_0x01010803, mask ); - if (!rc.ok()) { - FAPI_ERR("fapiPutScom(OCC_LFIR_MASK_0x01010803) failed."); - return rc; - } - - return rc ; + fapi::ReturnCode rc; + ecmdDataBufferBase fir(64); + ecmdDataBufferBase action_0(64); + ecmdDataBufferBase action_1(64); + ecmdDataBufferBase mask(64); + uint32_t e_rc = 0; + + FAPI_DBG("Executing p8_pm_occ_firinit ...."); + + do + { + if (mode == PM_RESET) + { + + e_rc = mask.flushTo0(); + e_rc |= mask.setBit(0,OCC_FIR_REGISTER_LENGTH); + if (e_rc) + { + rc.setEcmdError(e_rc); + break; + } + + // ------------ + // OCC_FIR_MASK + // ------------ + rc = fapiPutScom(i_target, OCC_LFIR_MASK_0x01010803, mask ); + if (!rc.ok()) + { + FAPI_ERR("fapiPutScom(OCC_LFIR_MASK_0x01010803) failed."); + break; + } + } + else + { + + // Clear the FIR + e_rc |= fir.flushTo0(); + + // make action default be RECOV_ATTN - "01" + e_rc |= action_0.flushTo0(); + e_rc |= action_1.flushTo1(); + + // make mask default be unmasked - "0" + e_rc |= mask.flushTo0() ; + if (e_rc) + { + rc.setEcmdError(e_rc); + break; + } + + // ------------------------------------------------------------------------ + // set the action and mask for the OCC LFIR bits using the following macros + // ------------------------------------------------------------------------ + // Action0/1 Setting Macros - 4 possible settings + // SET_CHECK_STOP(b) - sets action0/1 to "00" for LFIR bit b + // SET_RECOV_ATTN(b) - sets action0/1 to "01" for LFIR bit b + // SET_RECOV_INTR(b) - sets action0/1 to "10" for LFIR bit b + // SET_MALF_ALERT(b) - sets action0/1 to "11" for LFIR bit b + // + // Mask Setting Macro + // SET_FIR_MASKED(b) - sets mask to '1' for LFIR bit b + // ------------------------------------------------------------------------ + + SET_MALF_ALERT(0); // 0 = occ_fw0 + SET_MALF_ALERT(1); // 1 = occ_fw1 + SET_MALF_ALERT(2); // 2 = occ_fw2 + SET_MALF_ALERT(3); // 3 = occ_fw3 + SET_MALF_ALERT(4); // 4 = pmc_pore_sw_malf + SET_MALF_ALERT(5); // 5 = pmc_occ_hb_malf + + SET_FIR_MASKED(6); // 6 = pore_gpe0_fatal_err + SET_FIR_MASKED(7); // 7 = pore_gpe1_fatal_err + SET_FIR_MASKED(8); // 8 = ocb_error + + SET_RECOV_ATTN(9); // 9 = srt_ue + SET_RECOV_ATTN(10); // 10 = srt_ce + SET_RECOV_ATTN(11); // 11 = srt_read_error + SET_RECOV_ATTN(12); // 12 = srt_write_error + SET_RECOV_ATTN(13); // 13 = srt_dataout_perr + SET_RECOV_ATTN(14); // 14 = srt_oci_write_data_parity + SET_RECOV_ATTN(15); // 15 = srt_oci_be_parity_err + SET_RECOV_ATTN(16); // 16 = srt_oci_addr_parity_err + + SET_FIR_MASKED(17); // 17 = pore_sw_error_err + SET_FIR_MASKED(18); // 18 = pore_gpe0_error_err + SET_FIR_MASKED(19); // 19 = pore_gpe1_error_err + SET_FIR_MASKED(20); // 20 = external_trap + SET_FIR_MASKED(21); // 21 = ppc405_core_reset + SET_FIR_MASKED(22); // 22 = ppc405_chip_reset + SET_FIR_MASKED(23); // 23 = ppc405_system_reset + SET_FIR_MASKED(24); // 24 = ppc405_dbgmsrwe + SET_FIR_MASKED(25); // 25 = ppc405_dbgstopack + + SET_RECOV_ATTN(26); // 26 = ocb_db_oci_timeout + SET_RECOV_ATTN(27); // 27 = ocb_db_oci_read_data_parity + SET_RECOV_ATTN(28); // 28 = ocb_db_oci_slave_error + SET_RECOV_ATTN(29); // 29 = ocb_pib_addr_parity_err + SET_RECOV_ATTN(30); // 30 = ocb_db_pib_data_parity_err + SET_RECOV_ATTN(31); // 31 = ocb_idc0_error + SET_RECOV_ATTN(32); // 32 = ocb_idc1_error + SET_RECOV_ATTN(33); // 33 = ocb_idc2_error + SET_RECOV_ATTN(34); // 34 = ocb_idc3_error + SET_RECOV_ATTN(35); // 35 = srt_fsm_err + SET_RECOV_ATTN(36); // 36 = jtagacc_err + + SET_FIR_MASKED(37); // 37 = spare_err_37 + + SET_RECOV_ATTN(38); // 38 = c405_ecc_ue + SET_RECOV_ATTN(39); // 39 = c405_ecc_ce + + SET_FIR_MASKED(40); // 40 = c405_oci_machinecheck + + SET_RECOV_ATTN(41); // 41 = sram_spare_direct_error0 + SET_RECOV_ATTN(42); // 42 = sram_spare_direct_error1 + SET_RECOV_ATTN(43); // 43 = sram_spare_direct_error2 + SET_RECOV_ATTN(44); // 44 = sram_spare_direct_error3 + SET_RECOV_ATTN(45); // 45 = slw_ocislv_err + SET_RECOV_ATTN(46); // 46 = gpe_ocislv_err + SET_RECOV_ATTN(47); // 47 = ocb_ocislv_err + SET_RECOV_ATTN(48); // 48 = c405icu_m_timeout + SET_RECOV_ATTN(49); // 49 = c405dcu_m_timeout + + SET_FIR_MASKED(50); // 50 = spare_fir + SET_FIR_MASKED(51); // 51 = spare_fir + SET_FIR_MASKED(52); // 52 = spare_fir + SET_FIR_MASKED(53); // 53 = spare_fir + SET_FIR_MASKED(54); // 54 = spare_fir + SET_FIR_MASKED(55); // 55 = spare_fir + SET_FIR_MASKED(56); // 56 = spare_fir + SET_FIR_MASKED(57); // 57 = spare_fir + SET_FIR_MASKED(58); // 58 = spare_fir + SET_FIR_MASKED(59); // 59 = spare_fir + SET_FIR_MASKED(60); // 60 = spare_fir + SET_FIR_MASKED(61); // 61 = spare_fir + + SET_RECOV_ATTN(62); // 62 = fir_parity_err_dup + SET_RECOV_ATTN(63); // 63 = fir_parity_err + + if (e_rc) + { + rc.setEcmdError(e_rc); + break; + } + + // --------------- + // OCC_FIR - cleared + // --------------- + rc = fapiPutScom(i_target, OCC_LFIR_0x01010800, fir); + if (!rc.ok()) + { + FAPI_ERR("fapiPutScom(OCC_LFIR_0x01010800) failed."); + break; + } + + + FAPI_DBG(" action_0 => 0x%16llx ", action_0.getDoubleWord(0)); + FAPI_DBG(" action_1 => 0x%16llx ", action_1.getDoubleWord(0)); + FAPI_DBG(" mask => 0x%16llx ", mask.getDoubleWord(0)); + + // --------------- + // OCC_FIR_ACTION0 + // --------------- + rc = fapiPutScom(i_target, OCC_LFIR_ACT0_0x01010806, action_0 ); + if (!rc.ok()) + { + FAPI_ERR("fapiPutScom(OCC_LFIR_ACT0_0x01010806) failed."); + break; + } + + // ---------------- + // OCC_FIR_ACTION1 + // ---------------- + rc = fapiPutScom(i_target, OCC_LFIR_ACT1_0x01010807, action_1 ); + if (!rc.ok()) + { + FAPI_ERR("fapiPutScom(OCC_LFIR_ACT1_0x01010807) failed."); + break; + } + + // ------------ + // OCC_FIR_MASK + // ------------ + rc = fapiPutScom(i_target, OCC_LFIR_MASK_0x01010803, mask ); + if (!rc.ok()) + { + FAPI_ERR("fapiPutScom(OCC_LFIR_MASK_0x01010803) failed."); + break; + } + } + } while(0); + return rc ; } // end p8_pm_occ_firinit } //end extern C diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_occ_firinit.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_occ_firinit.H index 46ff64379..767b16c02 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_occ_firinit.H +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_occ_firinit.H @@ -20,25 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_pm_occ_firinit.H,v 1.3 2012/09/14 19:35:06 jimyac Exp $ -// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_occ_firinit.H,v $ +// $Id: p8_pm_occ_firinit.H,v 1.6 2013/04/01 04:27:49 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_occ_firinit.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 // *! All Rights Reserved -- Property of IBM @@ -54,10 +37,11 @@ #ifndef _P8_PM_OCC_FIRINIT_H_ #define _P8_PM_OCC_FIRINIT_H_ +#include "p8_pm_firinit.H" #include <fapi.H> // function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*p8_pm_occ_firinit_FP_t) (const fapi::Target&); +typedef fapi::ReturnCode (*p8_pm_occ_firinit_FP_t) (const fapi::Target& , uint32_t mode); extern "C" { //------------------------------------------------------------------------------ @@ -67,7 +51,7 @@ extern "C" { /// \param[in] i_target => Chip Target fapi::ReturnCode -p8_pm_occ_firinit(const fapi::Target& i_target); +p8_pm_occ_firinit(const fapi::Target& i_target , uint32_t mode); } // extern "C" diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_oha_firinit.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_oha_firinit.C index 7c98c1472..535f66922 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_oha_firinit.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_oha_firinit.C @@ -20,40 +20,27 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_pm_oha_firinit.C,v 1.4 2012/09/16 05:10:14 pchatnah Exp $ -// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_oha_firinit.C,v $ +// $Id: p8_pm_oha_firinit.C,v 1.11 2013/04/01 04:25:38 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_oha_firinit.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //------------------------------------------------------------------------------ -// *! OWNER NAME: Joe Procwriter Email: asmartpersion@xx.ibm.com +// *! OWNER NAME: Pradeep CN Email: pradeepcn@in.ibm.com // *! // *! General Description: Configures the FIR errors // *! // *! The purpose of this procedure is to ...... // *! // *! High-level procedure flow: -// *! o Do thing 1 -// *! o Do thing 2 -// *! o Do thing 3 +// *! o Set the particluar bits of databuffers action0 , action 1 and mask for the correspoding actions via MACROS +// *! o Write the action1 , actionn0 and mask registers of FIRs +// *! o +// *! o +// *! o +// *! o +// *! // *! o Check if all went well // *! o If so celebrate // *! o Else write logs, set bad return code @@ -68,10 +55,10 @@ // ---------------------------------------------------------------------- // Includes // ---------------------------------------------------------------------- + #include <fapi.H> #include "p8_scom_addresses.H" #include "p8_pm_oha_firinit.H" -#include "p8_pm_firinit.H" extern "C" { @@ -93,96 +80,145 @@ using namespace fapi; // ---------------------------------------------------------------------- - - - -// ---------------------------------------------------------------------- +//------------------------------------------------------------------------------ // Function prototypes -// ---------------------------------------------------------------------- - - - - -// ---------------------------------------------------------------------- -// Function definitions -// ---------------------------------------------------------------------- +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +// function: FAPI p8_pm_oha_firinit HWP entry point +// operates on chips passed in i_target argument to perform +// desired settings of FIRS of OHA macro +// parameters: i_target => chip target -// function: xxx -// parameters: none -// returns: ECMD_SUCCESS if something good happens, -// BAD_RETURN_CODE otherwise -ReturnCode -p8_pm_oha_firinit(const fapi::Target &i_target ) +// returns: FAPI_RC_SUCCESS if all specified operations complete successfully, +// else return code for failing operation +//------------------------------------------------------------------------------ +fapi::ReturnCode +p8_pm_oha_firinit(const fapi::Target &i_target , uint32_t mode ) { - ReturnCode rc; - // ecmdDataBufferBase action_0(64); -// ecmdDataBufferBase action_1(64); - ecmdDataBufferBase mask(64); - uint32_t e_rc = 0; - - std::vector<fapi::Target> l_chiplets; - std::vector<Target>::iterator itr; - - - // FAPI_INF(""); - FAPI_INF("Executing proc_pm_oha_firinit ....\n"); - - - -//#--OHA_ERROR_AND_ERROR_MASK_REG:0..1 WREG=0x0E OHA error and error mask register -//#-- tpc_oha1_mac_inst.error_mask 0..5 SCOM -//#-- 0..5 RW oha_error_mask Error mask for OHA/DPLL error reporting registers - - + fapi::ReturnCode rc; + //TODO RTC: 71328 unused fapi::TargetState l_state = TARGET_STATE_FUNCTIONAL; + ecmdDataBufferBase mask(64); + uint32_t e_rc = 0; + + std::vector<fapi::Target> l_chiplets; + std::vector<Target>::iterator itr; + + + enum OHA_FIRS + { + OHA21_PPT_TIMEOUT_ERR =0 , + NOT_CPM_BIT_SYNCED =1 , + AISS_HANG_CONDITION =2 , + TC_TC_THERM_TRIP0 =3 , + TC_TC_THERM_TRIP1 =4 , + PCB_ERR_TO_FIR =5 + }; - - - e_rc |= mask.flushTo0(); - - - SET_FIR_MASKED(0); // oha21_ppt_timeout_err - SET_FIR_MASKED(1); // NOT CPM_bit_synced - SET_FIR_MASKED(2); // aiss_hang_condition - SET_FIR_MASKED(3); // tc_tc_therm_trip0 - SET_FIR_MASKED(4); // tc_tc_therm_trip1 - SET_FIR_MASKED(5); // pcb_err_to_fir - - if (e_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)e_rc); rc.setEcmdError(e_rc); return rc; } + FAPI_INF("Executing proc_pm_oha_firinit ..."); - + do + { + + //#-- OHA_ERROR_AND_ERROR_MASK_REG: 0..1 WREG=0x0E OHA error and error mask register + //#-- tpc_oha1_mac_inst.error_mask 0..5 SCOM + //#-- 0..5 RW oha_error_mask Error mask for OHA/DPLL error reporting registers + + if (mode == PM_RESET) + { + rc = fapiGetChildChiplets ( i_target, + TARGET_TYPE_EX_CHIPLET, + l_chiplets, + TARGET_STATE_FUNCTIONAL); + if (rc) + { + FAPI_ERR("fapiGetChildChiplets failed."); + break; + } + + FAPI_DBG(" chiplet vector size => %u", l_chiplets.size()); + + e_rc = mask.flushTo0(); + e_rc |= mask.setBit(0,OHA_FIR_REGISTER_LENGTH); + if (e_rc) + { + rc.setEcmdError(e_rc); + break; + } + + for (itr = l_chiplets.begin(); itr != l_chiplets.end(); itr++) + { + rc = fapiPutScom((*itr), EX_OHA_ERROR_ERROR_MASK_REG_RWx1002000E, mask ); + if (rc) + { + FAPI_ERR("fapiPutScom(EX_OHA_ERROR_ERROR_MASK_REG_RWx1002000E) failed."); + break; + } + } + // Exit if error detected + if (!rc.ok()) + { + break; + } + } + else + { + e_rc = mask.flushTo0(); + + SET_FIR_MASKED(OHA21_PPT_TIMEOUT_ERR); // OHA21_PPT_TIMEOUT_ERR + SET_FIR_MASKED(NOT_CPM_BIT_SYNCED ); // NOT_CPM_BIT_SYNCED + SET_FIR_MASKED(AISS_HANG_CONDITION ); // AISS_HANG_CONDITION + SET_FIR_MASKED(TC_TC_THERM_TRIP0 ); // TC_TC_THERM_TRIP0 + SET_FIR_MASKED(TC_TC_THERM_TRIP1 ); // TC_TC_THERM_TRIP1 + SET_FIR_MASKED(PCB_ERR_TO_FIR ); // PCB_ERR_TO_FIR -// #--****************************************************************************** -// #-- Mask EX_OHA_ERROR_ERROR_MASK_REG_RWx1002000E -// #--****************************************************************************** - - rc = fapiGetChildChiplets (i_target, TARGET_TYPE_EX_CHIPLET, l_chiplets, TARGET_STATE_FUNCTIONAL); if (rc) return rc; - FAPI_DBG(" chiplet vector size => %u", l_chiplets.size()); - - for (itr = l_chiplets.begin(); itr != l_chiplets.end(); itr++){ - - + if (e_rc) + { + rc.setEcmdError(e_rc); + break; + } + + // #--*********************************************************** + // #-- Mask EX_OHA_ERROR_ERROR_MASK_REG_RWx1002000E + // #--*********************************************************** + + rc = fapiGetChildChiplets( i_target, + fapi::TARGET_TYPE_EX_CHIPLET, + l_chiplets, + TARGET_STATE_FUNCTIONAL); + if (rc) + { + FAPI_ERR("fapiGetChildChiplets failed."); + break; + } + + FAPI_DBG(" chiplet vector size => %u", l_chiplets.size()); + + for (itr = l_chiplets.begin(); itr != l_chiplets.end(); itr++) + { + + rc = fapiPutScom( (*itr), + EX_OHA_ERROR_ERROR_MASK_REG_RWx1002000E, + mask ); + if (rc) + { + FAPI_ERR("fapiPutScom(EX_OHA_ERROR_ERROR_MASK_REG_RWx1002000E) failed."); + break; + } + } // Chiplet loop + + // Exit if error detected + if (!rc.ok()) + { + break; + } + } // Mode + + } while(0); + + return rc; - rc = fapiPutScom((*itr), EX_OHA_ERROR_ERROR_MASK_REG_RWx1002000E, mask ); - if (rc) { - FAPI_ERR("fapiPutScom(EX_OHA_ERROR_ERROR_MASK_REG_RWx1002000E) failed."); return rc; - } - - FAPI_INF("Done in current chiplet ....\n"); - - } - - - - - - return rc ; - - } // Procedure - } //end extern C - - diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_oha_firinit.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_oha_firinit.H index 40d24b4f1..57bb5b90c 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_oha_firinit.H +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_oha_firinit.H @@ -20,25 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_pm_oha_firinit.H,v 1.2 2012/09/16 05:10:21 pchatnah Exp $ -// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_oha_firinit.H,v $ +// $Id: p8_pm_oha_firinit.H,v 1.5 2013/03/29 14:22:52 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_oha_firinit.H,v $ //------------------------------------------------------------------------------ // *| // *! (C) Copyright International Business Machines Corp. 2011 @@ -52,16 +35,33 @@ // *! BACKUP NAME : Pradeep CN Email: padeepcn@in.ibm.com // *! //------------------------------------------------------------------------------ +#include "p8_pm_firinit.H" + // function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*p8_pm_oha_firinit_FP_t) (const fapi::Target& ); +typedef fapi::ReturnCode (*p8_pm_oha_firinit_FP_t) (const fapi::Target& , uint32_t mode ); extern "C" { fapi::ReturnCode -p8_pm_oha_firinit(const fapi::Target& i_target ); - /// input CHIPTARGET +p8_pm_oha_firinit(const fapi::Target& i_target, uint32_t mode ); + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// function: FAPI p8_pm_oha_firinit HWP entry point +// operates on chips passed in i_target argument to perform +// desired settings of FIRS of OHA macro +// parameters: i_target => chip target + +// returns: FAPI_RC_SUCCESS if all specified operations complete successfully, +// else return code for failing operation +//------------------------------------------------------------------------------ + + } // extern "C" diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pba_firinit.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pba_firinit.C index 7a8578fef..40f5f63f1 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pba_firinit.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pba_firinit.C @@ -20,25 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_pm_pba_firinit.C,v 1.10 2012/10/05 08:44:02 pchatnah Exp $ -// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pba_firinit.C,v $ +// $Id: p8_pm_pba_firinit.C,v 1.15 2013/04/12 01:17:25 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pba_firinit.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -47,18 +30,18 @@ // *! OWNER NAME: Pradeep CN Email: pradeepcn@in.ibm.com // *! // *! General Description: -// *! +// *! // *! The purpose of this procedure is to ...... -// *! +// *! // *! High-level procedure flow: // *! o Set the particluar bits of databuffers action0 , action 1 and mask for the correspoding actions via MACROS // *! o Write the action1 , actionn0 and mask registers of FIRs -// *! o -// *! o -// *! o -// *! o +// *! o +// *! o +// *! o +// *! o // *! o Check if all went well -// *! o If so celebrate +// *! o If so celebrate // *! o Else write logs, set bad return code // *! // *! @@ -74,7 +57,6 @@ // ---------------------------------------------------------------------- #include <fapi.H> #include "p8_scom_addresses.H" -#include "p8_pm_firinit.H" #include "p8_pm_pba_firinit.H" extern "C" { @@ -98,8 +80,6 @@ using namespace fapi; // Macro definitions // ---------------------------------------------------------------------- - - // #define SET_CHECK_STOP(b){SET_FIR_ACTION(b, 0, 0);} // #define SET_RECOV_ATTN(b){SET_FIR_ACTION(b, 0, 1);} // #define SET_RECOV_INTR(b){SET_FIR_ACTION(b, 1, 0);} @@ -110,12 +90,8 @@ using namespace fapi; // Global variables // ---------------------------------------------------------------------- - - - - fapi::ReturnCode -p8_pm_pba_firinit(const fapi::Target& i_target ) +p8_pm_pba_firinit(const fapi::Target& i_target , uint32_t mode ) { //------------------------------------------------------------------------------ @@ -125,197 +101,209 @@ p8_pm_pba_firinit(const fapi::Target& i_target ) //------------------------------------------------------------------------------ // function: FAPI p8_pm_pba_firinit HWP entry point // operates on chips passed in i_target argument to perform -// desired settings of FIRS of PBA macro +// desired settings of FIRS of PBA macro // parameters: i_target => chip target // returns: FAPI_RC_SUCCESS if all specified operations complete successfully, // else return code for failing operation //------------------------------------------------------------------------------ - - - enum PBA_FIRS - { - - PBAFIR_OCI_APAR_ERR = 0 , - PBAFIR_PB_RDADRERR_FW =1 , - PBAFIR_PB_RDDATATO_FW =2 , - PBAFIR_PB_SUE_FW =3 , - PBAFIR_PB_UE_FW =4 , - PBAFIR_PB_CE_FW =5 , - PBAFIR_OCI_SLAVE_INIT =6 , - PBAFIR_OCI_WRPAR_ERR =7 , - PBAFIR_OCI_REREQTO =8 , - PBAFIR_PB_UNEXPCRESP =9 , - PBAFIR_PB_UNEXPDATA =10 , - PBAFIR_PB_PARITY_ERR =11 , - PBAFIR_PB_WRADRERR_FW =12 , - PBAFIR_PB_BADCRESP =13 , - PBAFIR_PB_ACKDEAD_FW_RD =14 , - PBAFIR_PB_CRESPTO =15 , - PBAFIR_BCUE_SETUP_ERR =16 , - PBAFIR_BCUE_PB_ACK_DEAD =17 , - PBAFIR_BCUE_PB_ADRERR =18 , - PBAFIR_BCUE_OCI_DATERR =19 , - PBAFIR_BCDE_SETUP_ERR =20 , - PBAFIR_BCDE_PB_ACK_DEAD =21 , - PBAFIR_BCDE_PB_ADRERR =22 , - PBAFIR_BCDE_RDDATATO_ERR =23 , - PBAFIR_BCDE_SUE_ERR =24 , - PBAFIR_BCDE_UE_ERR =25 , - PBAFIR_BCDE_CE =26 , - PBAFIR_BCDE_OCI_DATERR =27 , - PBAFIR_INTERNAL_ERR =28 , - PBAFIR_ILLEGAL_CACHE_OP =29 , - PBAFIR_OCI_BAD_REG_ADDR =30 , - PBAFIR_AXPUSH_WRERR =31 , - PBAFIR_AXRCV_DLO_ERR =32 , - PBAFIR_AXRCV_DLO_TO =33 , - PBAFIR_AXRCV_RSVDATA_TO =34 , - PBAFIR_AXFLOW_ERR =35 , - PBAFIR_AXSND_DHI_RTYTO =36 , - PBAFIR_AXSND_DLO_RTYTO =37 , - PBAFIR_AXSND_RSVTO =38 , - PBAFIR_AXSND_RSVERR =39 , - PBAFIR_PB_ACKDEAD_FW_WR =40 , - PBAFIR_RESERVED_41 =41 , - PBAFIR_RESERVED_42 =42 , - PBAFIR_RESERVED_43 =43 , - PBAFIR_FIR_PARITY_ERR2 =44 , - PBAFIR_FIR_PARITY_ERR =45 - - }; - - - - fapi::ReturnCode rc; + fapi::ReturnCode rc; + ecmdDataBufferBase fir(64); ecmdDataBufferBase action_0(64); ecmdDataBufferBase action_1(64); ecmdDataBufferBase mask(64); uint32_t e_rc = 0; - - - - FAPI_INF(""); - FAPI_INF("Executing p8_pm_pba_firinit ....\n"); - - e_rc = action_0.flushTo0(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } - e_rc = action_1.flushTo0(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } - e_rc = mask.flushTo0() ; if (e_rc) { rc.setEcmdError(e_rc); return rc; } - - SET_RECOV_ATTN (PBAFIR_OCI_APAR_ERR ) ; // 0 PBAFIR_OCI_APAR_ERR - SET_RECOV_ATTN (PBAFIR_PB_RDADRERR_FW ) ; // 1 PBAFIR_PB_RDADRERR_FW - SET_RECOV_ATTN (PBAFIR_PB_RDDATATO_FW ) ; // 2 PBAFIR_PB_RDDATATO_FW - SET_RECOV_ATTN (PBAFIR_PB_SUE_FW ) ; // 3 PBAFIR_PB_SUE_FW - SET_RECOV_ATTN (PBAFIR_PB_UE_FW ) ; // 4 PBAFIR_PB_UE_FW - SET_RECOV_ATTN (PBAFIR_PB_CE_FW ) ; // 5 PBAFIR_PB_CE_FW - SET_RECOV_ATTN (PBAFIR_OCI_SLAVE_INIT ) ; // 6 PBAFIR_OCI_SLAVE_INIT - SET_RECOV_ATTN (PBAFIR_OCI_WRPAR_ERR ) ; // 7 PBAFIR_OCI_WRPAR_ERR - SET_RECOV_ATTN (PBAFIR_OCI_REREQTO ) ; // 8 PBAFIR_OCI_REREQTO - SET_RECOV_ATTN (PBAFIR_PB_UNEXPCRESP ) ; // 9 PBAFIR_PB_UNEXPCRESP - SET_RECOV_ATTN (PBAFIR_PB_UNEXPDATA ) ; // 10 PBAFIR_PB_UNEXPDATA - SET_RECOV_ATTN (PBAFIR_PB_PARITY_ERR ) ; // 11 PBAFIR_PB_PARITY_ERR - SET_RECOV_ATTN (PBAFIR_PB_WRADRERR_FW ) ; // 12 PBAFIR_PB_WRADRERR_FW - SET_RECOV_ATTN (PBAFIR_PB_BADCRESP ) ; // 13 PBAFIR_PB_BADCRESP - SET_RECOV_ATTN (PBAFIR_PB_ACKDEAD_FW_RD ) ; // 14 PBAFIR_PB_ACKDEAD_FW_RD - SET_RECOV_ATTN (PBAFIR_PB_CRESPTO ) ; // 15 PBAFIR_PB_CRESPTO - SET_FIR_MASKED (PBAFIR_BCUE_SETUP_ERR ) ; // 16 PBAFIR_BCUE_SETUP_ERR - SET_FIR_MASKED (PBAFIR_BCUE_PB_ACK_DEAD ) ; // 17 PBAFIR_BCUE_PB_ACK_DEAD - SET_FIR_MASKED (PBAFIR_BCUE_PB_ADRERR ) ; // 18 PBAFIR_BCUE_PB_ADRERR - SET_FIR_MASKED (PBAFIR_BCUE_OCI_DATERR ) ; // 19 PBAFIR_BCUE_OCI_DATERR - SET_FIR_MASKED (PBAFIR_BCDE_SETUP_ERR ) ; // 20 PBAFIR_BCDE_SETUP_ERR - SET_FIR_MASKED (PBAFIR_BCDE_PB_ACK_DEAD ) ; // 21 PBAFIR_BCDE_PB_ACK_DEAD - SET_FIR_MASKED (PBAFIR_BCDE_PB_ADRERR ) ; // 22 PBAFIR_BCDE_PB_ADRERR - SET_FIR_MASKED (PBAFIR_BCDE_RDDATATO_ERR ) ; // 23 PBAFIR_BCDE_RDDATATO_ERR - SET_FIR_MASKED (PBAFIR_BCDE_SUE_ERR ) ; // 24 PBAFIR_BCDE_SUE_ERR - SET_FIR_MASKED (PBAFIR_BCDE_UE_ERR ) ; // 25 PBAFIR_BCDE_UE_ERR - SET_FIR_MASKED (PBAFIR_BCDE_CE ) ; // 26 PBAFIR_BCDE_CE - SET_FIR_MASKED (PBAFIR_BCDE_OCI_DATERR ) ; // 27 PBAFIR_BCDE_OCI_DATERR - SET_RECOV_ATTN (PBAFIR_INTERNAL_ERR ) ; // 28 PBAFIR_INTERNAL_ERR - SET_RECOV_ATTN (PBAFIR_ILLEGAL_CACHE_OP ) ; // 29 PBAFIR_ILLEGAL_CACHE_OP - SET_RECOV_ATTN (PBAFIR_OCI_BAD_REG_ADDR ) ; // 30 PBAFIR_OCI_BAD_REG_ADDR - SET_FIR_MASKED (PBAFIR_AXPUSH_WRERR ) ; // 31 PBAFIR_AXPUSH_WRERR - SET_FIR_MASKED (PBAFIR_AXRCV_DLO_ERR ) ; // 32 PBAFIR_AXRCV_DLO_ERR - SET_FIR_MASKED (PBAFIR_AXRCV_DLO_TO ) ; // 33 PBAFIR_AXRCV_DLO_TO - SET_FIR_MASKED (PBAFIR_AXRCV_RSVDATA_TO ) ; // 34 PBAFIR_AXRCV_RSVDATA_TO - SET_FIR_MASKED (PBAFIR_AXFLOW_ERR ) ; // 35 PBAFIR_AXFLOW_ERR - SET_FIR_MASKED (PBAFIR_AXSND_DHI_RTYTO ) ; // 36 PBAFIR_AXSND_DHI_RTYTO - SET_FIR_MASKED (PBAFIR_AXSND_DLO_RTYTO ) ; // 37 PBAFIR_AXSND_DLO_RTYTO - SET_FIR_MASKED (PBAFIR_AXSND_RSVTO ) ; // 38 PBAFIR_AXSND_RSVTO - SET_FIR_MASKED (PBAFIR_AXSND_RSVERR ) ; // 39 PBAFIR_AXSND_RSVERR - SET_RECOV_ATTN (PBAFIR_PB_ACKDEAD_FW_WR ) ; // 40 PBAFIR_PB_ACKDEAD_FW_WR - SET_FIR_MASKED (PBAFIR_RESERVED_41 ) ; // 41 PBAFIR_RESERVED_41 - SET_FIR_MASKED (PBAFIR_RESERVED_42 ) ; // 42 PBAFIR_RESERVED_42 - SET_FIR_MASKED (PBAFIR_RESERVED_43 ) ; // 43 PBAFIR_RESERVED_43 - SET_RECOV_ATTN (PBAFIR_FIR_PARITY_ERR2 ) ; // 44 PBAFIR_FIR_PARITY_ERR2 - SET_RECOV_ATTN (PBAFIR_FIR_PARITY_ERR ) ; // 45 PBAFIR_FIR_PARITY_ERR - - - if (e_rc) { rc.setEcmdError(e_rc); return rc; } - -// FAPI_INF(" action_0 => %s ", action_0.genHexRightStr(0,64).c_str()); -// FAPI_INF(" action_1 => %s ", action_1.genHexRightStr(0,64).c_str()); -// FAPI_INF(" mask => %s ", mask.genHexRightStr(0,64).c_str()); - - - //#--****************************************************************************** - //#-- PBA_FIR_ACTION0 - //#--****************************************************************************** - - rc = fapiPutScom(i_target, PBA_FIR_ACTION0_0x02010846, action_0 ); - if (rc) { - FAPI_ERR("fapiPutScom(PBA_FIR_ACTION0_0x02010846) failed."); return rc; - } - - //#--****************************************************************************** - //#-- PBA_FIR_ACTION1 - //#--****************************************************************************** - - rc = fapiPutScom(i_target, PBA_FIR_ACTION1_0x02010847, action_1 ); - if (rc) { - FAPI_ERR("fapiPutScom(PBA_FIR_ACTION1_0x02010847) failed."); return rc; - } - - - //--****************************************************************************** - //-- PBA_FIR_MASK (W0_OR_45) (WR_43) (WO_AND_44) - //--****************************************************************************** - rc = fapiPutScom(i_target, PBA_FIR_MASK_WR_0x02010843, mask ); - if (rc) { - FAPI_ERR("fapiPutScom(PBA_FIR_MASK_WR_0x02010843) failed."); return rc; - } - - - - - - - - - - - - return rc ; - - -} // Procedure - - -} //end extern C - - + enum PBA_FIRS + { + PBAFIR_OCI_APAR_ERR =0 , + PBAFIR_PB_RDADRERR_FW =1 , + PBAFIR_PB_RDDATATO_FW =2 , + PBAFIR_PB_SUE_FW =3 , + PBAFIR_PB_UE_FW =4 , + PBAFIR_PB_CE_FW =5 , + PBAFIR_OCI_SLAVE_INIT =6 , + PBAFIR_OCI_WRPAR_ERR =7 , + PBAFIR_OCI_REREQTO =8 , + PBAFIR_PB_UNEXPCRESP =9 , + PBAFIR_PB_UNEXPDATA =10 , + PBAFIR_PB_PARITY_ERR =11 , + PBAFIR_PB_WRADRERR_FW =12 , + PBAFIR_PB_BADCRESP =13 , + PBAFIR_PB_ACKDEAD_FW_RD =14 , + PBAFIR_PB_CRESPTO =15 , + PBAFIR_BCUE_SETUP_ERR =16 , + PBAFIR_BCUE_PB_ACK_DEAD =17 , + PBAFIR_BCUE_PB_ADRERR =18 , + PBAFIR_BCUE_OCI_DATERR =19 , + PBAFIR_BCDE_SETUP_ERR =20 , + PBAFIR_BCDE_PB_ACK_DEAD =21 , + PBAFIR_BCDE_PB_ADRERR =22 , + PBAFIR_BCDE_RDDATATO_ERR =23 , + PBAFIR_BCDE_SUE_ERR =24 , + PBAFIR_BCDE_UE_ERR =25 , + PBAFIR_BCDE_CE =26 , + PBAFIR_BCDE_OCI_DATERR =27 , + PBAFIR_INTERNAL_ERR =28 , + PBAFIR_ILLEGAL_CACHE_OP =29 , + PBAFIR_OCI_BAD_REG_ADDR =30 , + PBAFIR_AXPUSH_WRERR =31 , + PBAFIR_AXRCV_DLO_ERR =32 , + PBAFIR_AXRCV_DLO_TO =33 , + PBAFIR_AXRCV_RSVDATA_TO =34 , + PBAFIR_AXFLOW_ERR =35 , + PBAFIR_AXSND_DHI_RTYTO =36 , + PBAFIR_AXSND_DLO_RTYTO =37 , + PBAFIR_AXSND_RSVTO =38 , + PBAFIR_AXSND_RSVERR =39 , + PBAFIR_PB_ACKDEAD_FW_WR =40 , + PBAFIR_RESERVED_41 =41 , + PBAFIR_RESERVED_42 =42 , + PBAFIR_RESERVED_43 =43 , + PBAFIR_FIR_PARITY_ERR2 =44 , + PBAFIR_FIR_PARITY_ERR =45 + }; -// ---------------------------------------------------------------------- -// BACKUPS -// ---------------------------------------------------------------------- -// #define RECOV_INTR 1, 0 -// #define RECOV_ATTN 0, 1 -// #define MALF_ALERT 1, 1 + FAPI_DBG("Executing p8_pm_pba_firinit ...."); + do + { + if (mode == PM_RESET) + { + + e_rc = mask.flushTo0(); + e_rc |= mask.setBit(0, PBA_FIR_REGISTER_LENGTH); + if (e_rc) + { + rc.setEcmdError(e_rc); + break; + } + + //--****************************************************************************** + //-- PBA_FIR_MASK (W0_OR_45) (WR_43) (WO_AND_44) + //--****************************************************************************** + rc = fapiPutScom(i_target, PBA_FIR_MASK_WR_0x02010843, mask ); + if (rc) + { + FAPI_ERR("fapiPutScom(PBA_FIR_MASK_WR_0x02010843) failed."); + break; + } + } + else + { + e_rc |= fir.flushTo0(); + e_rc |= action_0.flushTo0(); + e_rc |= action_1.flushTo0(); + e_rc |= mask.flushTo0() ; + if (e_rc) + { + rc.setEcmdError(e_rc); + break; + } + + SET_RECOV_ATTN (PBAFIR_OCI_APAR_ERR ) ; // 0 PBAFIR_OCI_APAR_ERR + SET_RECOV_ATTN (PBAFIR_PB_RDADRERR_FW ) ; // 1 PBAFIR_PB_RDADRERR_FW + SET_RECOV_ATTN (PBAFIR_PB_RDDATATO_FW ) ; // 2 PBAFIR_PB_RDDATATO_FW + SET_RECOV_ATTN (PBAFIR_PB_SUE_FW ) ; // 3 PBAFIR_PB_SUE_FW + SET_RECOV_ATTN (PBAFIR_PB_UE_FW ) ; // 4 PBAFIR_PB_UE_FW + SET_RECOV_ATTN (PBAFIR_PB_CE_FW ) ; // 5 PBAFIR_PB_CE_FW + SET_RECOV_ATTN (PBAFIR_OCI_SLAVE_INIT ) ; // 6 PBAFIR_OCI_SLAVE_INIT + SET_RECOV_ATTN (PBAFIR_OCI_WRPAR_ERR ) ; // 7 PBAFIR_OCI_WRPAR_ERR + SET_RECOV_ATTN (PBAFIR_OCI_REREQTO ) ; // 8 PBAFIR_OCI_REREQTO + SET_RECOV_ATTN (PBAFIR_PB_UNEXPCRESP ) ; // 9 PBAFIR_PB_UNEXPCRESP + SET_RECOV_ATTN (PBAFIR_PB_UNEXPDATA ) ; // 10 PBAFIR_PB_UNEXPDATA + SET_RECOV_ATTN (PBAFIR_PB_PARITY_ERR ) ; // 11 PBAFIR_PB_PARITY_ERR + SET_RECOV_ATTN (PBAFIR_PB_WRADRERR_FW ) ; // 12 PBAFIR_PB_WRADRERR_FW + SET_RECOV_ATTN (PBAFIR_PB_BADCRESP ) ; // 13 PBAFIR_PB_BADCRESP + SET_RECOV_ATTN (PBAFIR_PB_ACKDEAD_FW_RD ) ; // 14 PBAFIR_PB_ACKDEAD_FW_RD + SET_RECOV_ATTN (PBAFIR_PB_CRESPTO ) ; // 15 PBAFIR_PB_CRESPTO + SET_FIR_MASKED (PBAFIR_BCUE_SETUP_ERR ) ; // 16 PBAFIR_BCUE_SETUP_ERR + SET_FIR_MASKED (PBAFIR_BCUE_PB_ACK_DEAD ) ; // 17 PBAFIR_BCUE_PB_ACK_DEAD + SET_FIR_MASKED (PBAFIR_BCUE_PB_ADRERR ) ; // 18 PBAFIR_BCUE_PB_ADRERR + SET_FIR_MASKED (PBAFIR_BCUE_OCI_DATERR ) ; // 19 PBAFIR_BCUE_OCI_DATERR + SET_FIR_MASKED (PBAFIR_BCDE_SETUP_ERR ) ; // 20 PBAFIR_BCDE_SETUP_ERR + SET_FIR_MASKED (PBAFIR_BCDE_PB_ACK_DEAD ) ; // 21 PBAFIR_BCDE_PB_ACK_DEAD + SET_FIR_MASKED (PBAFIR_BCDE_PB_ADRERR ) ; // 22 PBAFIR_BCDE_PB_ADRERR + SET_FIR_MASKED (PBAFIR_BCDE_RDDATATO_ERR ) ; // 23 PBAFIR_BCDE_RDDATATO_ERR + SET_FIR_MASKED (PBAFIR_BCDE_SUE_ERR ) ; // 24 PBAFIR_BCDE_SUE_ERR + SET_FIR_MASKED (PBAFIR_BCDE_UE_ERR ) ; // 25 PBAFIR_BCDE_UE_ERR + SET_FIR_MASKED (PBAFIR_BCDE_CE ) ; // 26 PBAFIR_BCDE_CE + SET_FIR_MASKED (PBAFIR_BCDE_OCI_DATERR ) ; // 27 PBAFIR_BCDE_OCI_DATERR + SET_RECOV_ATTN (PBAFIR_INTERNAL_ERR ) ; // 28 PBAFIR_INTERNAL_ERR + SET_RECOV_ATTN (PBAFIR_ILLEGAL_CACHE_OP ) ; // 29 PBAFIR_ILLEGAL_CACHE_OP + SET_RECOV_ATTN (PBAFIR_OCI_BAD_REG_ADDR ) ; // 30 PBAFIR_OCI_BAD_REG_ADDR + SET_FIR_MASKED (PBAFIR_AXPUSH_WRERR ) ; // 31 PBAFIR_AXPUSH_WRERR + SET_FIR_MASKED (PBAFIR_AXRCV_DLO_ERR ) ; // 32 PBAFIR_AXRCV_DLO_ERR + SET_FIR_MASKED (PBAFIR_AXRCV_DLO_TO ) ; // 33 PBAFIR_AXRCV_DLO_TO + SET_FIR_MASKED (PBAFIR_AXRCV_RSVDATA_TO ) ; // 34 PBAFIR_AXRCV_RSVDATA_TO + SET_FIR_MASKED (PBAFIR_AXFLOW_ERR ) ; // 35 PBAFIR_AXFLOW_ERR + SET_FIR_MASKED (PBAFIR_AXSND_DHI_RTYTO ) ; // 36 PBAFIR_AXSND_DHI_RTYTO + SET_FIR_MASKED (PBAFIR_AXSND_DLO_RTYTO ) ; // 37 PBAFIR_AXSND_DLO_RTYTO + SET_FIR_MASKED (PBAFIR_AXSND_RSVTO ) ; // 38 PBAFIR_AXSND_RSVTO + SET_FIR_MASKED (PBAFIR_AXSND_RSVERR ) ; // 39 PBAFIR_AXSND_RSVERR + SET_RECOV_ATTN (PBAFIR_PB_ACKDEAD_FW_WR ) ; // 40 PBAFIR_PB_ACKDEAD_FW_WR + SET_FIR_MASKED (PBAFIR_RESERVED_41 ) ; // 41 PBAFIR_RESERVED_41 + SET_FIR_MASKED (PBAFIR_RESERVED_42 ) ; // 42 PBAFIR_RESERVED_42 + SET_FIR_MASKED (PBAFIR_RESERVED_43 ) ; // 43 PBAFIR_RESERVED_43 + SET_RECOV_ATTN (PBAFIR_FIR_PARITY_ERR2 ) ; // 44 PBAFIR_FIR_PARITY_ERR2 + SET_RECOV_ATTN (PBAFIR_FIR_PARITY_ERR ) ; // 45 PBAFIR_FIR_PARITY_ERR + + if (e_rc) + { + rc.setEcmdError(e_rc); + break; + } + + // --------------- + // PBA_FIR - cleared + // --------------- + rc = fapiPutScom(i_target, PBA_FIR_0x02010840, fir); + if (!rc.ok()) + { + FAPI_ERR("fapiPutScom(PBA_FIR_0x02010840) failed."); + break; + } + + FAPI_DBG(" action_0 => 0x%16llx ", action_0.getDoubleWord(0)); + FAPI_DBG(" action_1 => 0x%16llx ", action_1.getDoubleWord(0)); + FAPI_DBG(" mask => 0x%16llx ", mask.getDoubleWord(0)); + + //#--****************************************************************************** + //#-- PBA_FIR_ACTION0 + //#--****************************************************************************** + + rc = fapiPutScom(i_target, PBA_FIR_ACTION0_0x02010846, action_0 ); + if (rc) + { + FAPI_ERR("fapiPutScom(PBA_FIR_ACTION0_0x02010846) failed."); + break; + } + + //#--****************************************************************************** + //#-- PBA_FIR_ACTION1 + //#--****************************************************************************** + + rc = fapiPutScom(i_target, PBA_FIR_ACTION1_0x02010847, action_1 ); + if (rc) + { + FAPI_ERR("fapiPutScom(PBA_FIR_ACTION1_0x02010847) failed."); + break; + } + + //--****************************************************************************** + //-- PBA_FIR_MASK (W0_OR_45) (WR_43) (WO_AND_44) + //--****************************************************************************** + rc = fapiPutScom(i_target, PBA_FIR_MASK_WR_0x02010843, mask ); + if (rc) + { + FAPI_ERR("fapiPutScom(PBA_FIR_MASK_WR_0x02010843) failed."); + break; + } + } // Mode + } while(0); + return rc; +} // Procedure -// SET_FIR_ACTION( 1 ,1 ,0) ; -// SET_FIR_ACTION( 2, 0, 1) ; -// SET_FIR_ACTION( 3, 1, 1) ; SET_FIR_MASK(3, 1) ; - +} //end extern C diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pba_firinit.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pba_firinit.H index 26af3d887..a376c7c8e 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pba_firinit.H +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pba_firinit.H @@ -20,25 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_pm_pba_firinit.H,v 1.3 2012/09/24 08:44:38 pchatnah Exp $ -// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pba_firinit.H,v $ +// $Id: p8_pm_pba_firinit.H,v 1.6 2013/04/01 04:27:50 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pba_firinit.H,v $ //------------------------------------------------------------------------------ // *| // *! (C) Copyright International Business Machines Corp. 2011 @@ -53,15 +36,13 @@ // *! //------------------------------------------------------------------------------ +#include "p8_pm_firinit.H" + // function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*p8_pm_pba_firinit_FP_t) (const fapi::Target& ); +typedef fapi::ReturnCode (*p8_pm_pba_firinit_FP_t) (const fapi::Target& , uint32_t mode); extern "C" { - -fapi::ReturnCode -p8_pm_pba_firinit(const fapi::Target& i_target ); - //------------------------------------------------------------------------------ // Function prototypes //------------------------------------------------------------------------------ @@ -75,6 +56,9 @@ p8_pm_pba_firinit(const fapi::Target& i_target ); // returns: FAPI_RC_SUCCESS if all specified operations complete successfully, // else return code for failing operation //------------------------------------------------------------------------------ +fapi::ReturnCode +p8_pm_pba_firinit(const fapi::Target& i_target, uint32_t mode ); + } // extern "C" diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pcbs_firinit.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pcbs_firinit.C index c141f7ee4..969fa15e7 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pcbs_firinit.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pcbs_firinit.C @@ -20,25 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_pm_pcbs_firinit.C,v 1.7 2012/10/16 13:43:50 pchatnah Exp $ -// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pcbs_firinit.C,v $ +// $Id: p8_pm_pcbs_firinit.C,v 1.10 2013/04/01 04:25:41 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pcbs_firinit.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -59,10 +42,10 @@ /// High-level procedure flow: /// /// get all functional child chiplets -/// +/// /// loop over all functional chiplets { /// calculate address -/// set the error mask in order to mask all errors +/// set the error mask in order to mask all errors /// /// } /// @@ -77,8 +60,6 @@ #include <fapi.H> #include "p8_scom_addresses.H" #include "p8_pm_pcbs_firinit.H" -#include "p8_pm_firinit.H" - extern "C" { @@ -88,9 +69,6 @@ using namespace fapi; // Constant definitions // ---------------------------------------------------------------------- - - - // ---------------------------------------------------------------------- // Macro definitions // ---------------------------------------------------------------------- @@ -102,167 +80,214 @@ using namespace fapi; // #define SET_MALF_ALERT(b){SET_FIR_ACTION(b, 1, 1);} // #define SET_FIR_MASKED(b){SET_FIR_MASK(b,1);} - // ---------------------------------------------------------------------- // Global variables // ---------------------------------------------------------------------- - - - - // ---------------------------------------------------------------------- // Function prototypes // ---------------------------------------------------------------------- - - - // ---------------------------------------------------------------------- // Function definitions // ---------------------------------------------------------------------- fapi::ReturnCode -p8_pm_pcbs_firinit(const fapi::Target &i_target ) +p8_pm_pcbs_firinit(const fapi::Target &i_target , uint32_t mode ) { + fapi::ReturnCode rc; ecmdDataBufferBase action_0(64); ecmdDataBufferBase action_1(64); ecmdDataBufferBase mask(64); - std::vector<fapi::Target> l_exChiplets; - fapi::TargetState l_state = TARGET_STATE_FUNCTIONAL; // TARGET_STATE_PRESENT or TARGET_STATE_FUNCTIONAL. It just depends on what you want to do. - + std::vector<fapi::Target> l_exChiplets; + fapi::TargetState l_state = TARGET_STATE_FUNCTIONAL; uint8_t l_functional = 0; uint8_t l_ex_number = 0; - uint32_t e_rc = 0; - - - FAPI_INF(""); - FAPI_INF("Executing proc_pm_pcbs_firinit ....\n"); - - - - - - SET_FIR_MASKED(PCBS_SLEEP_ENTRY_NOTIFY_PMC_HANG_ERR_MASK); - SET_FIR_MASKED(PCBS_SLEEP_ENTRY_NOTIFY_PMC_ASSIST_HANG_ERR_MASK); - SET_FIR_MASKED(PCBS_SLEEP_ENTRY_NOTIFY_PMC_ERR_MASK); - SET_FIR_MASKED(PCBS_SLEEP_EXIT_INVOKE_PORE_ERR_MASK); - SET_FIR_MASKED(PCBS_WINKLE_ENTRY_NOTIFY_PMC_ERR_MASK); - SET_FIR_MASKED(PCBS_WINKLE_ENTRY_SEND_INT_ASSIST_ERR_MASK); - SET_FIR_MASKED(PCBS_WINKLE_EXIT_NOTIFY_PMC_ERR_MASK); - SET_FIR_MASKED(PCBS_WAIT_DPLL_LOCK_ERR_MASK); - SET_FIR_MASKED(PCBS_SPARE8_ERR_MASK); - SET_FIR_MASKED(PCBS_WINKLE_EXIT_SEND_INT_ASSIST_ERR_MASK); - SET_FIR_MASKED(PCBS_WINKLE_EXIT_SEND_INT_POWUP_ASSIST_ERR_MASK); - SET_FIR_MASKED(PCBS_WRITE_FSM_GOTO_REG_IN_INVALID_STATE_ERR_MASK); - SET_FIR_MASKED(PCBS_WRITE_PMGP0_IN_INVALID_STATE_ERR_MASK); - SET_FIR_MASKED(PCBS_FREQ_OVERFLOW_IN_PSTATE_MODE_ERR_MASK); - SET_FIR_MASKED(PCBS_ECO_RS_BYPASS_CONFUSION_ERR_MASK); - SET_FIR_MASKED(PCBS_CORE_RS_BYPASS_CONFUSION_ERR_MASK); - SET_FIR_MASKED(PCBS_READ_LPST_IN_PSTATE_MODE_ERR_MASK); - SET_FIR_MASKED(PCBS_LPST_READ_CORR_ERR_MASK); - SET_FIR_MASKED(PCBS_LPST_READ_UNCORR_ERR_MASK); - SET_FIR_MASKED(PCBS_PFET_STRENGTH_OVERFLOW_ERR_MASK); - SET_FIR_MASKED(PCBS_VDS_LOOKUP_ERR_MASK); - SET_FIR_MASKED(PCBS_IDLE_INTERRUPT_TIMEOUT_ERR_MASK); - SET_FIR_MASKED(PCBS_PSTATE_INTERRUPT_TIMEOUT_ERR_MASK); - SET_FIR_MASKED(PCBS_GLOBAL_ACTUAL_SYNC_INTERRUPT_TIMEOUT_ERR_MASK); - SET_FIR_MASKED(PCBS_PMAX_SYNC_INTERRUPT_TIMEOUT_ERR_MASK); - SET_FIR_MASKED(PCBS_GLOBAL_ACTUAL_PSTATE_PROTOCOL_ERR_MASK); - SET_FIR_MASKED(PCBS_PMAX_PROTOCOL_ERR_MASK); - SET_FIR_MASKED(PCBS_IVRM_GROSS_OR_FINE_ERR_MASK); - SET_FIR_MASKED(PCBS_IVRM_RANGE_ERR_MASK); - SET_FIR_MASKED(PCBS_DPLL_CPM_FMIN_ERR_MASK); - SET_FIR_MASKED(PCBS_DPLL_DCO_FULL_ERR_MASK); - SET_FIR_MASKED(PCBS_DPLL_DCO_EMPTY_ERR_MASK); - SET_FIR_MASKED(PCBS_DPLL_INT_ERR_MASK); - SET_FIR_MASKED(PCBS_FMIN_AND_NOT_CPMBIT_ERR_MASK); - SET_FIR_MASKED(PCBS_DPLL_FASTER_THAN_FMAX_PLUS_DELTA1_ERR_MASK); - SET_FIR_MASKED(PCBS_DPLL_SLOWER_THAN_FMIN_MINUS_DELTA2_ERR_MASK); - SET_FIR_MASKED(PCBS_RESCLK_CSB_INSTR_VECTOR_CHG_IN_INVALID_STATE_ERR_MASK); - SET_FIR_MASKED(PCBS_RESLKC_BAND_BOUNDARY_CHG_IN_INVALID_STATE_ERR_MASK); - SET_FIR_MASKED(PCBS_OCC_HEARTBEAT_LOSS_ERR_MASK); - SET_FIR_MASKED(PCBS_SPARE39_ERR_MASK); - SET_FIR_MASKED(PCBS_SPARE40_ERR_MASK); - SET_FIR_MASKED(PCBS_SPARE41_ERR_MASK); - SET_FIR_MASKED(PCBS_SPARE42_ERR_MASK); - - - if(e_rc){rc.setEcmdError(e_rc); return rc;} - -// e_rc = mask.flushTo1(); -// if (e_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", e_rc); rc.setEcmdError(e_rc); return rc; } - - - - // #--****************************************************************************** - // #-- Mask EX_PMErrMask_REG_0x100F010A - // #--****************************************************************************** - - - - rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_EX_CHIPLET, l_exChiplets, l_state); if (rc) return rc; - FAPI_DBG(" chiplet vector size => %u", l_exChiplets.size()); - - - - for (uint8_t c=0; c< l_exChiplets.size(); c++) { - FAPI_DBG("********* ******************* *********"); - FAPI_DBG("\t Loop Variable %d ",c); - FAPI_DBG("********* ******************* *********"); - - rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_exChiplets[c], l_functional); - if (rc) - { - FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL with rc = 0x%x", (uint32_t)rc); - return rc; - } - else - { - if (l_functional) + FAPI_INF("Executing proc_pm_pcbs_firinit ..."); + do + { + if (mode == PM_RESET) { - // The ex is functional let's build the SCOM address - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[c], l_ex_number); - if (rc) - { - FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)rc); - return rc; - } - - else - { - - FAPI_DBG("Core number = %d", l_ex_number); - // Use the l_ex_number to build the SCOM address; - rc = fapiPutScom(i_target, EX_PMErrMask_REG_0x100F010A + (l_ex_number * 0x01000000), mask ); - if (rc) { - FAPI_ERR("fapiPutScom(EX_PMErrMask_REG_0x100F010A) failed."); return rc; + e_rc = mask.flushTo0(); + e_rc |= mask.setBit(0,PCB_FIR_REGISTER_LENGTH); + if (e_rc) + { + rc.setEcmdError(e_rc); + break; } - - FAPI_INF("Done with current core %d ....\n", l_ex_number); - - } + + // #--*********************************************************** + // #-- Mask EX_PMErrMask_REG_0x100F010A + // #--*********************************************************** + + + + rc = fapiGetChildChiplets( i_target, + fapi::TARGET_TYPE_EX_CHIPLET, + l_exChiplets, + l_state); + if (rc) return rc; + FAPI_DBG(" chiplet vector size => %u", l_exChiplets.size()); + + + + for (uint8_t c=0; c< l_exChiplets.size(); c++) + { + rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_exChiplets[c], l_functional); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL with rc = 0x%x", (uint32_t)rc); + break; + } + + if (l_functional) + { + // The ex is functional let's build the SCOM address + rc = FAPI_ATTR_GET( ATTR_CHIP_UNIT_POS, + &l_exChiplets[c], + l_ex_number); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)rc); + break; + } + + FAPI_DBG("Core number = %d", l_ex_number); + // Use the l_ex_number to build the SCOM address; + rc = fapiPutScom( i_target, + EX_PMErrMask_REG_0x100F010A + + (l_ex_number * 0x01000000), + mask ); + if (rc) + { + FAPI_ERR("fapiPutScom(EX_PMErrMask_REG_0x100F010A) failed."); + break; + } + } // Functional + } // Chiplet loop } - else + else { - // EX is not functional - FAPI_DBG("Core number = %d is not functional", c); - } - } - - } + SET_FIR_MASKED(PCBS_SLEEP_ENTRY_NOTIFY_PMC_HANG_ERR_MASK); + SET_FIR_MASKED(PCBS_SLEEP_ENTRY_NOTIFY_PMC_ASSIST_HANG_ERR_MASK); + SET_FIR_MASKED(PCBS_SLEEP_ENTRY_NOTIFY_PMC_ERR_MASK); + SET_FIR_MASKED(PCBS_SLEEP_EXIT_INVOKE_PORE_ERR_MASK); + SET_FIR_MASKED(PCBS_WINKLE_ENTRY_NOTIFY_PMC_ERR_MASK); + SET_FIR_MASKED(PCBS_WINKLE_ENTRY_SEND_INT_ASSIST_ERR_MASK); + SET_FIR_MASKED(PCBS_WINKLE_EXIT_NOTIFY_PMC_ERR_MASK); + SET_FIR_MASKED(PCBS_WAIT_DPLL_LOCK_ERR_MASK); + SET_FIR_MASKED(PCBS_SPARE8_ERR_MASK); + SET_FIR_MASKED(PCBS_WINKLE_EXIT_SEND_INT_ASSIST_ERR_MASK); + SET_FIR_MASKED(PCBS_WINKLE_EXIT_SEND_INT_POWUP_ASSIST_ERR_MASK); + SET_FIR_MASKED(PCBS_WRITE_FSM_GOTO_REG_IN_INVALID_STATE_ERR_MASK); + SET_FIR_MASKED(PCBS_WRITE_PMGP0_IN_INVALID_STATE_ERR_MASK); + SET_FIR_MASKED(PCBS_FREQ_OVERFLOW_IN_PSTATE_MODE_ERR_MASK); + SET_FIR_MASKED(PCBS_ECO_RS_BYPASS_CONFUSION_ERR_MASK); + SET_FIR_MASKED(PCBS_CORE_RS_BYPASS_CONFUSION_ERR_MASK); + SET_FIR_MASKED(PCBS_READ_LPST_IN_PSTATE_MODE_ERR_MASK); + SET_FIR_MASKED(PCBS_LPST_READ_CORR_ERR_MASK); + SET_FIR_MASKED(PCBS_LPST_READ_UNCORR_ERR_MASK); + SET_FIR_MASKED(PCBS_PFET_STRENGTH_OVERFLOW_ERR_MASK); + SET_FIR_MASKED(PCBS_VDS_LOOKUP_ERR_MASK); + SET_FIR_MASKED(PCBS_IDLE_INTERRUPT_TIMEOUT_ERR_MASK); + SET_FIR_MASKED(PCBS_PSTATE_INTERRUPT_TIMEOUT_ERR_MASK); + SET_FIR_MASKED(PCBS_GLOBAL_ACTUAL_SYNC_INTERRUPT_TIMEOUT_ERR_MASK); + SET_FIR_MASKED(PCBS_PMAX_SYNC_INTERRUPT_TIMEOUT_ERR_MASK); + SET_FIR_MASKED(PCBS_GLOBAL_ACTUAL_PSTATE_PROTOCOL_ERR_MASK); + SET_FIR_MASKED(PCBS_PMAX_PROTOCOL_ERR_MASK); + SET_FIR_MASKED(PCBS_IVRM_GROSS_OR_FINE_ERR_MASK); + SET_FIR_MASKED(PCBS_IVRM_RANGE_ERR_MASK); + SET_FIR_MASKED(PCBS_DPLL_CPM_FMIN_ERR_MASK); + SET_FIR_MASKED(PCBS_DPLL_DCO_FULL_ERR_MASK); + SET_FIR_MASKED(PCBS_DPLL_DCO_EMPTY_ERR_MASK); + SET_FIR_MASKED(PCBS_DPLL_INT_ERR_MASK); + SET_FIR_MASKED(PCBS_FMIN_AND_NOT_CPMBIT_ERR_MASK); + SET_FIR_MASKED(PCBS_DPLL_FASTER_THAN_FMAX_PLUS_DELTA1_ERR_MASK); + SET_FIR_MASKED(PCBS_DPLL_SLOWER_THAN_FMIN_MINUS_DELTA2_ERR_MASK); + SET_FIR_MASKED(PCBS_RESCLK_CSB_INSTR_VECTOR_CHG_IN_INVALID_STATE_ERR_MASK); + SET_FIR_MASKED(PCBS_RESLKC_BAND_BOUNDARY_CHG_IN_INVALID_STATE_ERR_MASK); + SET_FIR_MASKED(PCBS_OCC_HEARTBEAT_LOSS_ERR_MASK); + SET_FIR_MASKED(PCBS_SPARE39_ERR_MASK); + SET_FIR_MASKED(PCBS_SPARE40_ERR_MASK); + SET_FIR_MASKED(PCBS_SPARE41_ERR_MASK); + SET_FIR_MASKED(PCBS_SPARE42_ERR_MASK); + + + if (e_rc) + { + rc.setEcmdError(e_rc); + break; + } + + // #--************************************************************ + // #-- Mask EX_PMErrMask_REG_0x100F010A + // #--************************************************************ + + rc = fapiGetChildChiplets( i_target, + fapi::TARGET_TYPE_EX_CHIPLET, + l_exChiplets, + l_state); + if (rc) + { + FAPI_ERR("fapiGetChildChiplets failed."); + break; + } + + FAPI_DBG(" chiplet vector size => %u", l_exChiplets.size()); + + for (uint8_t c=0; c< l_exChiplets.size(); c++) + { + rc = FAPI_ATTR_GET( ATTR_FUNCTIONAL, + &l_exChiplets[c], + l_functional); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL with rc = 0x%x", (uint32_t)rc); + break; + } + + if (l_functional) + { + // The ex is functional let's build the SCOM address + rc = FAPI_ATTR_GET( ATTR_CHIP_UNIT_POS, + &l_exChiplets[c], + l_ex_number); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)rc); + break; + } + + FAPI_DBG("Core number = %d", l_ex_number); + // Use the l_ex_number to build the SCOM address; + rc = fapiPutScom( i_target, + EX_PMErrMask_REG_0x100F010A + + (l_ex_number * 0x01000000), + mask ); + if (rc) + { + FAPI_ERR("fapiPutScom(EX_PMErrMask_REG_0x100F010A) failed."); + break; + } + } // Functional + } // Chiplet loop + + // Exit if error detected + if (!rc.ok()) + { + break; + } + } // Mode - return rc ; - - -} // Procedure + } while(0); + return rc; -} //end extern C - +} // Procedure +} //end extern C diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pcbs_firinit.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pcbs_firinit.H index 51de0646c..853360a16 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pcbs_firinit.H +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pcbs_firinit.H @@ -20,25 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_pm_pcbs_firinit.H,v 1.2 2012/09/19 09:55:21 rmaier Exp $ -// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pcbs_firinit.H,v $ +// $Id: p8_pm_pcbs_firinit.H,v 1.4 2013/03/29 14:22:56 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pcbs_firinit.H,v $ //------------------------------------------------------------------------------ // *| // *! (C) Copyright International Business Machines Corp. 2011 @@ -54,9 +37,10 @@ //------------------------------------------------------------------------------ +#include "p8_pm_firinit.H" // function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*p8_pm_pcbs_firinit_FP_t) (const fapi::Target& ); +typedef fapi::ReturnCode (*p8_pm_pcbs_firinit_FP_t) (const fapi::Target& , uint32_t mode ); @@ -161,7 +145,7 @@ extern "C" { /// \param[in] &i_target Chip target -fapi::ReturnCode p8_pm_pcbs_firinit(const fapi::Target& i_target ); +fapi::ReturnCode p8_pm_pcbs_firinit(const fapi::Target& i_target , uint32_t mode ); } // extern "C" diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.C index bab789d0a..ab9c24044 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.C @@ -20,25 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_pm_pmc_firinit.C,v 1.7 2012/10/05 08:44:13 pchatnah Exp $ -// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pmc_firinit.C,v $ +// $Id: p8_pm_pmc_firinit.C,v 1.13 2013/04/12 01:17:27 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pmc_firinit.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -47,14 +30,14 @@ // *! OWNER NAME: Pradeep CN Email: pradeepcn@in.ibm.com // *! // *! General Description: Configures the FIR errors -// *! +// *! // *! The purpose of this procedure is to ...... -// *! +// *! // *! High-level procedure flow: // *! o Set the particluar bits of databuffers action0 , action 1 and mask for the correspoding actions via MACROS // *! o Write the action1 , actionn0 and mask registers of FIRs // *! o Check if all went well -// *! o If so celebrate +// *! o If so celebrate // *! o Else write logs, set bad return code // *! // *! Procedure Prereq: @@ -69,7 +52,6 @@ // ---------------------------------------------------------------------- #include <fapi.H> #include "p8_scom_addresses.H" -#include "p8_pm_firinit.H" #include "p8_pm_pmc_firinit.H" extern "C" { @@ -81,15 +63,7 @@ using namespace fapi; // ---------------------------------------------------------------------- - // \todo move these to p8_scom_addresses after testing - CONST_UINT64_T( PMC_FIR_ACTION1_0x01010847 , ULL(0x01010847)) ; - CONST_UINT64_T( PMC_FIR_ACTION0_0x01010846 , ULL(0x01010846)) ; - CONST_UINT64_T( PMC_FIR_MASK_WR_0x01010843 , ULL(0x01010843)) ; - CONST_UINT64_T( PMC_FIR_MASK_WR_AND_0x01010844 , ULL(0x01010844)) ; - CONST_UINT64_T( PMC_FIR_MASK_WR_OR_0x01010845 , ULL(0x01010845)) ; - - -// ---------------------------------------------------------------------- + // ---------------------------------------------------------------------- // Macro definitions // ---------------------------------------------------------------------- // ALL the below Macros are calling other macros SET_FIR_ACTION / SET_FIR_MASK . @@ -104,10 +78,6 @@ using namespace fapi; // Global variables // ---------------------------------------------------------------------- - - - - //------------------------------------------------------------------------------ // Function prototypes //------------------------------------------------------------------------------ @@ -115,7 +85,7 @@ using namespace fapi; //------------------------------------------------------------------------------ // function: FAPI p8_pm_pmc_firinit HWP entry point // operates on chips passed in i_target argument to perform -// desired settings of FIRS of PMC macro +// desired settings of FIRS of PMC macro // parameters: i_target => chip target // returns: FAPI_RC_SUCCESS if all specified operations complete successfully, @@ -123,181 +93,191 @@ using namespace fapi; //------------------------------------------------------------------------------ fapi::ReturnCode -p8_pm_pmc_firinit(const fapi::Target& i_target ) +p8_pm_pmc_firinit(const fapi::Target& i_target , uint32_t mode ) { - fapi::ReturnCode rc; + fapi::ReturnCode rc; + ecmdDataBufferBase fir(64); ecmdDataBufferBase action_0(64); ecmdDataBufferBase action_1(64); ecmdDataBufferBase mask(64); uint32_t e_rc = 0; - - enum PMC_FIRS - { - - PSTATE_OCI_MASTER_RDERR = 0 , - PSTATE_OCI_MASTER_RDDATA_PARITY_ERR =1 , - PSTATE_GPST_CHECKBYTE_ERR =2 , - PSTATE_GACK_TO_ERR =3 , - PSTATE_PIB_MASTER_NONOFFLINE_ERR =4 , - PSTATE_PIB_MASTER_OFFLINE_ERR =5 , - PSTATE_OCI_MASTER_TO_ERR =6 , - PSTATE_INTERCHIP_UE_ERR =7 , - PSTATE_INTERCHIP_ERRORFRAME_ERR =8 , - PSTATE_MS_FSM_ERR =9 , - MS_COMP_PARITY_ERR =10 , - IDLE_PORESW_FATAL_ERR =11 , - IDLE_PORESW_STATUS_RC_ERR =12 , - IDLE_PORESW_STATUS_VALUE_ERR =13 , - IDLE_PORESW_WRITE_WHILE_INACTIVE_ERR =14 , - IDLE_PORESW_TIMEOUT_ERR =15 , - IDLE_OCI_MASTER_WRITE_TIMEOUT_ERR =16 , - IDLE_INTERNAL_ERR =17 , - INT_COMP_PARITY_ERR =18 , - PMC_OCC_HEARTBEAT_TIMEOUT =19 , - SPIVID_CRC_ERROR0 =20 , - SPIVID_CRC_ERROR1 =21 , - SPIVID_CRC_ERROR2 =22 , - SPIVID_RETRY_TIMEOUT =23 , - SPIVID_FSM_ERR =24 , - SPIVID_MAJORITY_DETECTED_A_MINORITY =25 , - O2S_CRC_ERROR0 =26 , - O2S_CRC_ERROR1 =27 , - O2S_CRC_ERROR2 =28 , - O2S_RETRY_TIMEOUT =29 , - O2S_WRITE_WHILE_BRIDGE_BUSY_ERR =30 , - O2S_FSM_ERR =31 , - O2S_MAJORITY_DETECTED_A_MINORITY =32 , - O2P_WRITE_WHILE_BRIDGE_BUSY_ERR =33 , - O2P_FSM_ERR =34 , - OCI_SLAVE_ERR =35 , - IF_COMP_PARITY_ERR =36 , - FIR_PARITY_ERR_DUP =47 , - FIR_PARITY_ERR =48 - - - }; - - - - - - - FAPI_INF(""); - FAPI_INF("Executing p8_pm_pmc_firinit ....\n"); - - e_rc = action_0.flushTo0(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } - e_rc = action_1.flushTo0(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } - e_rc = mask.flushTo0() ; if (e_rc) { rc.setEcmdError(e_rc); return rc; } - - - - - - SET_RECOV_INTR(PSTATE_OCI_MASTER_RDERR ) ; // pstate_oci_master_rderr - SET_RECOV_INTR(PSTATE_OCI_MASTER_RDDATA_PARITY_ERR ); // pstate_oci_master_rddata_parity_err - SET_RECOV_INTR(PSTATE_GPST_CHECKBYTE_ERR ); // pstate_gpst_checkbyte_err - SET_RECOV_INTR(PSTATE_GACK_TO_ERR ); // pstate_gack_to_err - SET_RECOV_INTR(PSTATE_PIB_MASTER_NONOFFLINE_ERR ); // pstate_pib_master_nonoffline_err - SET_RECOV_INTR(PSTATE_PIB_MASTER_OFFLINE_ERR ); // pstate_pib_master_offline_err - SET_RECOV_INTR(PSTATE_OCI_MASTER_TO_ERR ); // pstate_oci_master_to_err - SET_RECOV_INTR(PSTATE_INTERCHIP_UE_ERR ); // pstate_interchip_ue_err - SET_RECOV_INTR(PSTATE_INTERCHIP_ERRORFRAME_ERR ); // pstate_interchip_errorframe_err - SET_RECOV_INTR(PSTATE_MS_FSM_ERR ); // pstate_ms_fsm_err - SET_MALF_ALERT(MS_COMP_PARITY_ERR ); // ms_comp_parity_err - SET_MALF_ALERT(IDLE_PORESW_FATAL_ERR ); // idle_poresw_fatal_err - SET_MALF_ALERT(IDLE_PORESW_STATUS_RC_ERR ); // idle_poresw_status_rc_err - SET_MALF_ALERT(IDLE_PORESW_STATUS_VALUE_ERR ); // idle_poresw_status_value_err - SET_MALF_ALERT(IDLE_PORESW_WRITE_WHILE_INACTIVE_ERR ); // idle_poresw_write_while_inactive_err - SET_MALF_ALERT(IDLE_PORESW_TIMEOUT_ERR ); // idle_poresw_timeout_err - SET_FIR_MASKED(IDLE_OCI_MASTER_WRITE_TIMEOUT_ERR ); // idle_oci_master_write_timeout_err - SET_MALF_ALERT(IDLE_INTERNAL_ERR ); // idle_internal_err - SET_MALF_ALERT(INT_COMP_PARITY_ERR ); // int_comp_parity_err - SET_MALF_ALERT(PMC_OCC_HEARTBEAT_TIMEOUT ); // pmc_occ_heartbeat_timeout - SET_FIR_MASKED(SPIVID_CRC_ERROR0 ); // spivid_crc_error0 - SET_FIR_MASKED(SPIVID_CRC_ERROR1 ); // spivid_crc_error1 - SET_FIR_MASKED(SPIVID_CRC_ERROR2 ); // spivid_crc_error2 - SET_FIR_MASKED(SPIVID_RETRY_TIMEOUT ); // spivid_retry_timeout - SET_FIR_MASKED(SPIVID_FSM_ERR ); // spivid_fsm_err - SET_FIR_MASKED(SPIVID_MAJORITY_DETECTED_A_MINORITY ); // spivid_majority_detected_a_minority - SET_FIR_MASKED(O2S_CRC_ERROR0 ); // o2s_crc_error0 - SET_FIR_MASKED(O2S_CRC_ERROR1 ); // o2s_crc_error1 - SET_FIR_MASKED(O2S_CRC_ERROR2 ); // o2s_crc_error2 - SET_FIR_MASKED(O2S_RETRY_TIMEOUT ); // o2s_retry_timeout - SET_FIR_MASKED(O2S_WRITE_WHILE_BRIDGE_BUSY_ERR ); // o2s_write_while_bridge_busy_err - SET_FIR_MASKED(O2S_FSM_ERR ); // o2s_fsm_err - SET_FIR_MASKED(O2S_MAJORITY_DETECTED_A_MINORITY ); // o2s_majority_detected_a_minority - SET_FIR_MASKED(O2P_WRITE_WHILE_BRIDGE_BUSY_ERR ); // o2p_write_while_bridge_busy_err - SET_FIR_MASKED(O2P_FSM_ERR ); // o2p_fsm_err - SET_FIR_MASKED(OCI_SLAVE_ERR ); // oci_slave_err - SET_MALF_ALERT(IF_COMP_PARITY_ERR ); // if_comp_parity_err // 37:46 spare_fir - SET_RECOV_ATTN(FIR_PARITY_ERR_DUP ); // fir_parity_err_dup - SET_RECOV_ATTN(FIR_PARITY_ERR ); // fir_parity_err - - if(e_rc){rc.setEcmdError(e_rc); return rc;} - - FAPI_INF(" action_0 => 0x%16llx ", action_0.getDoubleWord(0)); - FAPI_INF(" action_1 => 0x%16llx ", action_1.getDoubleWord(0)); - FAPI_INF(" mask => 0x%16llx ", mask.getDoubleWord(0)); - - - //#--****************************************************************************** - //#-- PMC_FIR_ACTION0 - //#--****************************************************************************** - - rc = fapiPutScom(i_target, PMC_FIR_ACTION0_0x01010846, action_0 ); - if (rc) { - FAPI_ERR("fapiPutScom(PMC_FIR_ACTION0_0x01010846) failed."); return rc; - } - - //#--****************************************************************************** - //#-- PMC_FIR_ACTION1 - //#--****************************************************************************** - - rc = fapiPutScom(i_target, PMC_FIR_ACTION1_0x01010847, action_1 ); - if (rc) { - FAPI_ERR("fapiPutScom(PMC_FIR_ACTION1_0x01010847) failed."); return rc; - } - - - //--****************************************************************************** - //-- PMC_FIR_MASK (W0_OR_45) (WR_43) (WO_AND_44) - //--****************************************************************************** - rc = fapiPutScom(i_target, PMC_FIR_MASK_WR_0x01010843, mask ); - if (rc) { - FAPI_ERR("fapiPutScom(PMC_FIR_MASK_WR_0x01010843) failed."); return rc; - } - - - - - - - - - + enum PMC_FIRS + { + PSTATE_OCI_MASTER_RDERR =0 , + PSTATE_OCI_MASTER_RDDATA_PARITY_ERR =1 , + PSTATE_GPST_CHECKBYTE_ERR =2 , + PSTATE_GACK_TO_ERR =3 , + PSTATE_PIB_MASTER_NONOFFLINE_ERR =4 , + PSTATE_PIB_MASTER_OFFLINE_ERR =5 , + PSTATE_OCI_MASTER_TO_ERR =6 , + PSTATE_INTERCHIP_UE_ERR =7 , + PSTATE_INTERCHIP_ERRORFRAME_ERR =8 , + PSTATE_MS_FSM_ERR =9 , + MS_COMP_PARITY_ERR =10 , + IDLE_PORESW_FATAL_ERR =11 , + IDLE_PORESW_STATUS_RC_ERR =12 , + IDLE_PORESW_STATUS_VALUE_ERR =13 , + IDLE_PORESW_WRITE_WHILE_INACTIVE_ERR =14 , + IDLE_PORESW_TIMEOUT_ERR =15 , + IDLE_OCI_MASTER_WRITE_TIMEOUT_ERR =16 , + IDLE_INTERNAL_ERR =17 , + INT_COMP_PARITY_ERR =18 , + PMC_OCC_HEARTBEAT_TIMEOUT =19 , + SPIVID_CRC_ERROR0 =20 , + SPIVID_CRC_ERROR1 =21 , + SPIVID_CRC_ERROR2 =22 , + SPIVID_RETRY_TIMEOUT =23 , + SPIVID_FSM_ERR =24 , + SPIVID_MAJORITY_DETECTED_A_MINORITY =25 , + O2S_CRC_ERROR0 =26 , + O2S_CRC_ERROR1 =27 , + O2S_CRC_ERROR2 =28 , + O2S_RETRY_TIMEOUT =29 , + O2S_WRITE_WHILE_BRIDGE_BUSY_ERR =30 , + O2S_FSM_ERR =31 , + O2S_MAJORITY_DETECTED_A_MINORITY =32 , + O2P_WRITE_WHILE_BRIDGE_BUSY_ERR =33 , + O2P_FSM_ERR =34 , + OCI_SLAVE_ERR =35 , + IF_COMP_PARITY_ERR =36 , + FIR_PARITY_ERR_DUP =47 , + FIR_PARITY_ERR =48 + }; + + FAPI_DBG("Executing p8_pm_pmc_firinit ..."); + do + { + if (mode == PM_RESET) + { + e_rc = mask.flushTo0(); + e_rc |= mask.setBit(0,PMC_FIR_REGISTER_LENGTH); + if (e_rc) + { + rc.setEcmdError(e_rc); + break; + } + + //--****************************************************************************** + //-- PMC_FIR_MASK (W0_OR_45) (WR_43) (WO_AND_44) + //--****************************************************************************** + rc = fapiPutScom(i_target, PMC_LFIR_MASK_0x01010843, mask ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_LFIR_MASK_0x01010843) failed."); + break; + } + } + else + { + e_rc |= fir.flushTo0(); + e_rc |= action_0.flushTo0(); + e_rc |= action_1.flushTo0(); + e_rc |= mask.flushTo0() ; + if (e_rc) + { + rc.setEcmdError(e_rc); + break; + } + + SET_RECOV_INTR(PSTATE_OCI_MASTER_RDERR ); // pstate_oci_master_rderr + SET_RECOV_INTR(PSTATE_OCI_MASTER_RDDATA_PARITY_ERR ); // pstate_oci_master_rddata_parity_err + SET_RECOV_INTR(PSTATE_GPST_CHECKBYTE_ERR ); // pstate_gpst_checkbyte_err + SET_RECOV_INTR(PSTATE_GACK_TO_ERR ); // pstate_gack_to_err + SET_RECOV_INTR(PSTATE_PIB_MASTER_NONOFFLINE_ERR ); // pstate_pib_master_nonoffline_err + SET_RECOV_INTR(PSTATE_PIB_MASTER_OFFLINE_ERR ); // pstate_pib_master_offline_err + SET_RECOV_INTR(PSTATE_OCI_MASTER_TO_ERR ); // pstate_oci_master_to_err + SET_RECOV_INTR(PSTATE_INTERCHIP_UE_ERR ); // pstate_interchip_ue_err + SET_RECOV_INTR(PSTATE_INTERCHIP_ERRORFRAME_ERR ); // pstate_interchip_errorframe_err + SET_RECOV_INTR(PSTATE_MS_FSM_ERR ); // pstate_ms_fsm_err + SET_MALF_ALERT(MS_COMP_PARITY_ERR ); // ms_comp_parity_err + SET_MALF_ALERT(IDLE_PORESW_FATAL_ERR ); // idle_poresw_fatal_err + SET_MALF_ALERT(IDLE_PORESW_STATUS_RC_ERR ); // idle_poresw_status_rc_err + SET_MALF_ALERT(IDLE_PORESW_STATUS_VALUE_ERR ); // idle_poresw_status_value_err + SET_MALF_ALERT(IDLE_PORESW_WRITE_WHILE_INACTIVE_ERR ); // idle_poresw_write_while_inactive_err + SET_MALF_ALERT(IDLE_PORESW_TIMEOUT_ERR ); // idle_poresw_timeout_err + SET_FIR_MASKED(IDLE_OCI_MASTER_WRITE_TIMEOUT_ERR ); // idle_oci_master_write_timeout_err + SET_MALF_ALERT(IDLE_INTERNAL_ERR ); // idle_internal_err + SET_MALF_ALERT(INT_COMP_PARITY_ERR ); // int_comp_parity_err + SET_FIR_MASKED(PMC_OCC_HEARTBEAT_TIMEOUT ); // pmc_occ_heartbeat_timeout + SET_FIR_MASKED(SPIVID_CRC_ERROR0 ); // spivid_crc_error0 + SET_FIR_MASKED(SPIVID_CRC_ERROR1 ); // spivid_crc_error1 + SET_FIR_MASKED(SPIVID_CRC_ERROR2 ); // spivid_crc_error2 + SET_FIR_MASKED(SPIVID_RETRY_TIMEOUT ); // spivid_retry_timeout + SET_FIR_MASKED(SPIVID_FSM_ERR ); // spivid_fsm_err + SET_FIR_MASKED(SPIVID_MAJORITY_DETECTED_A_MINORITY ); // spivid_majority_detected_a_minority + SET_FIR_MASKED(O2S_CRC_ERROR0 ); // o2s_crc_error0 + SET_FIR_MASKED(O2S_CRC_ERROR1 ); // o2s_crc_error1 + SET_FIR_MASKED(O2S_CRC_ERROR2 ); // o2s_crc_error2 + SET_FIR_MASKED(O2S_RETRY_TIMEOUT ); // o2s_retry_timeout + SET_FIR_MASKED(O2S_WRITE_WHILE_BRIDGE_BUSY_ERR ); // o2s_write_while_bridge_busy_err + SET_FIR_MASKED(O2S_FSM_ERR ); // o2s_fsm_err + SET_FIR_MASKED(O2S_MAJORITY_DETECTED_A_MINORITY ); // o2s_majority_detected_a_minority + SET_FIR_MASKED(O2P_WRITE_WHILE_BRIDGE_BUSY_ERR ); // o2p_write_while_bridge_busy_err + SET_FIR_MASKED(O2P_FSM_ERR ); // o2p_fsm_err + SET_FIR_MASKED(OCI_SLAVE_ERR ); // oci_slave_err + SET_MALF_ALERT(IF_COMP_PARITY_ERR ); // if_comp_parity_err 37:46 spare_fir + SET_RECOV_ATTN(FIR_PARITY_ERR_DUP ); // fir_parity_err_dup + SET_RECOV_ATTN(FIR_PARITY_ERR ); // fir_parity_err + + if (e_rc) + { + rc.setEcmdError(e_rc); + break; + } + + FAPI_DBG(" action_0 => 0x%16llx ", action_0.getDoubleWord(0)); + FAPI_DBG(" action_1 => 0x%16llx ", action_1.getDoubleWord(0)); + FAPI_DBG(" mask => 0x%16llx ", mask.getDoubleWord(0)); + + //#--****************************************************************************** + //#-- PMC_FIR - clear + //#--****************************************************************************** + + rc = fapiPutScom(i_target, PMC_LFIR_0x01010840, fir); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_LFIR_0x01010840) failed."); + break; + } + + //#--****************************************************************************** + //#-- PMC_FIR_ACTION0 + //#--****************************************************************************** + + rc = fapiPutScom(i_target, PMC_LFIR_ACT0_0x01010846, action_0 ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_LFIR_ACT0_0x01010846) failed."); + break; + } + + //#--****************************************************************************** + //#-- PMC_FIR_ACTION1 + //#--****************************************************************************** + + rc = fapiPutScom(i_target, PMC_LFIR_ACT1_0x01010847, action_1 ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_LFIR_ACT1_0x01010847) failed."); + break; + } + + //--****************************************************************************** + //-- PMC_FIR_MASK (W0_OR_45) (WR_43) (WO_AND_44) + //--****************************************************************************** + rc = fapiPutScom(i_target, PMC_LFIR_MASK_0x01010843, mask ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_LFIR_MASK_0x01010843) failed."); + break; + } + } + } while(0); return rc ; - - + } // Procedure } //end extern C - - - - -// ---------------------------------------------------------------------- -// BACKUPS -// ---------------------------------------------------------------------- - -// #define RECOV_INTR 1, 0 -// #define RECOV_ATTN 0, 1 -// #define MALF_ALERT 1, 1 - - -// SET_FIR_ACTION( 1 ,1 ,0) ; -// SET_FIR_ACTION( 2, 0, 1) ; -// SET_FIR_ACTION( 3, 1, 1) ; SET_FIR_MASK(3, 1) ; - diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.H index 15032293b..20990621d 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.H +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.H @@ -20,25 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_pm_pmc_firinit.H,v 1.2 2012/09/24 08:50:36 pchatnah Exp $ -// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pmc_firinit.H,v $ +// $Id: p8_pm_pmc_firinit.H,v 1.5 2013/04/01 04:27:51 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pmc_firinit.H,v $ //------------------------------------------------------------------------------ // *| // *! (C) Copyright International Business Machines Corp. 2011 @@ -58,16 +41,13 @@ //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ - +#include "p8_pm_firinit.H" // function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*p8_pm_pmc_firinit_FP_t) (const fapi::Target& ); +typedef fapi::ReturnCode (*p8_pm_pmc_firinit_FP_t) (const fapi::Target& , uint32_t mode ); extern "C" { - -fapi::ReturnCode -p8_pm_pmc_firinit(const fapi::Target& i_target ); //------------------------------------------------------------------------------ // function: FAPI p8_pm_pmc_firinit HWP entry point // operates on chips passed in i_target argument to perform @@ -77,6 +57,8 @@ p8_pm_pmc_firinit(const fapi::Target& i_target ); // returns: FAPI_RC_SUCCESS if all specified operations complete successfully, // else return code for failing operation //------------------------------------------------------------------------------ +fapi::ReturnCode +p8_pm_pmc_firinit(const fapi::Target& i_target, uint32_t mode ); } // extern "C" diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C index 129080c85..300986800 100755..100644 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C @@ -20,25 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_pmc_init.C,v 1.6 2012/10/04 10:24:27 pchatnah Exp $ -// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pmc_init.C,v $ +// $Id: p8_pmc_init.C,v 1.30 2013/04/30 11:20:22 pchatnah Exp $ +// $Source: /archive/shadow/ekb/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pmc_init.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -67,1255 +50,2420 @@ // ---------------------------------------------------------------------- // Includes // ---------------------------------------------------------------------- - #include "p8_pm.H" #include "p8_pmc_init.H" -//---------------------------------------------------------------------- -// eCMD Includes -//---------------------------------------------------------------------- -// #include <ecmdClientCapi.H> -// #include <ecmdUtils.H> -// #include <ecmdSharedUtils.H> -// #include <iostream> -// #include <fapiUtil.H> -//#include <sim_utils.inc> -//#include "myscoms.H" // Remove eventually - - -// ---------------------------------------------------------------------- -// Includes -// ---------------------------------------------------------------------- -#include <fapi.H> -#include <ecmdDataBufferBase.H> +#define INTERCHIP_HALT_POLL_COUNT 256 +#define VOLTAGE_CHANGE_POLL_COUNT 100 +#define O2S_POLL_COUNT 256 +#define O2P_POLL_COUNT 8 +#define PSTATE_HALT_POLL_COUNT 256 +#define PORE_REQ_POLL_COUNT 256 -//#ifdef FAPIECMD extern "C" { - // #endif - - using namespace fapi; -//TODO RTC: 68461 - Refresh procedures to remove multiple definitions -//RTC 68461 CONST_UINT64_T( OCB_OCI_OIMR1_0x0006a014 , ULL(0x0006a014) ); -//RTC 68461 CONST_UINT64_T( OCB_OCI_OIMR0_0x0006a004 , ULL(0x0006a004) ); - //NST_UINT64_T( PMC_MODE_REG_0x00062000 , ULL(0x00062000) ); -//RTC 68461 CONST_UINT64_T( PMC_INTCHP_COMMAND_REG_0x00062014 , ULL(0x00062014) ); -//RTC 68461 CONST_UINT64_T( PMC_INTCHP_STATUS_REG_0x00062013 , ULL(0x00062013) ); - //CONST_UINT64_T( PMC_INTCHP_COMMAND_REG_0x00062014 , ULL(0x00062014) ); - - // ---------------------------------------------------------------------- // Function prototypes // ---------------------------------------------------------------------- - -// fapi::ReturnCode -// pmc_create_spivid_settings(const Target& l_pTarget) -// { -// fapi::ReturnCode rc; - - - - - -// return rc ; -// } - -//------------------------------------------------------------------------- - /// Locally computed variables to put into the feature attributes -//------------------------------------------------------------------------- - +// ---------------------------------------------------------------------- +/** + * pmc_config_spivid_settings + * + * @param[in] i_target Chip target + * + * @retval ECMD_SUCCESS + * @retval ERROR defined in xml + */ fapi::ReturnCode pmc_config_spivid_settings(const Target& l_pTarget) { fapi::ReturnCode rc; - uint32_t attr_pm_spivid_clock_divider; - uint32_t attr_pm_spivid_frequency = 10; - uint32_t attr_proc_nest_frequency = 2400; - - FAPI_INF("entering the config function"); - - rc = FAPI_ATTR_GET(ATTR_FREQ_PB, NULL, attr_proc_nest_frequency); if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_FREQUENCY, NULL, attr_pm_spivid_frequency); if (rc) return rc; - + // SPIVID Defaults + const uint32_t default_spivid_frequency = 1; // MHz + // Units: nanoseconds; Value 10 microseconds + const uint32_t default_spivid_interframe_delay_write_status = 10000; + // Units: nanoseconds; Value 1 microsecond + const uint32_t default_spivid_inter_retry_delay = 1000; - // calculation of clock divider - attr_pm_spivid_clock_divider = (attr_proc_nest_frequency/(attr_pm_spivid_frequency*8)-1 ); + uint32_t attr_pm_spivid_frequency = 1; + uint32_t attr_proc_nest_frequency = 2000; - rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CLOCK_DIVIDER, &l_pTarget, attr_pm_spivid_clock_divider); if (rc) return rc; + uint32_t attr_pm_spivid_clock_divider; + uint32_t attr_pm_spivid_interframe_delay_write_status; + uint32_t attr_pm_spivid_interframe_delay_write_status_value; + uint32_t attr_pm_spivid_inter_retry_delay_value; + uint32_t attr_pm_spivid_inter_retry_delay; + + + do + { + FAPI_INF("Entering the config function"); + + //---------------------------------------------------------- + GETATTR( ATTR_FREQ_PB, + "ATTR_FREQ_PB", + NULL, + attr_proc_nest_frequency); + + //---------------------------------------------------------- + GETATTR_DEFAULT( ATTR_PM_SPIVID_FREQUENCY, + "ATTR_PM_SPIVID_FREQUENCY", + NULL, + attr_pm_spivid_frequency, + default_spivid_frequency); + + // calculation of clock divider + attr_pm_spivid_clock_divider = (attr_proc_nest_frequency / + (attr_pm_spivid_frequency*8)-1 ); + + + SETATTR( ATTR_PM_SPIVID_CLOCK_DIVIDER, + "ATTR_PM_SPIVID_CLOCK_DIVIDER", + &l_pTarget, + attr_pm_spivid_clock_divider); + + //---------------------------------------------------------- + // Delay between command and status frames of a SPIVID WRITE operation + // (binary in nanoseconds) + + GETATTR_DEFAULT( ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS, + "ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS", + &l_pTarget, + attr_pm_spivid_interframe_delay_write_status, + default_spivid_interframe_delay_write_status); + + // Delay is computed as: (value * ~100ns_hang_pulse) + // +0/-~100ns_hang_pulse time + // Thus, value = delay / 100 + attr_pm_spivid_interframe_delay_write_status_value = + attr_pm_spivid_interframe_delay_write_status / 100; + + SETATTR( ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, + "ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE", + &l_pTarget, + attr_pm_spivid_interframe_delay_write_status_value); + + //---------------------------------------------------------- + + // Delay between SPIVID reture attempts when WRITE command status + // indicates an error (binary in nanoseconds) + + GETATTR_DEFAULT( ATTR_PM_SPIVID_INTER_RETRY_DELAY, + "ATTR_PM_SPIVID_INTER_RETRY_DELAY", + &l_pTarget, + attr_pm_spivid_inter_retry_delay, + default_spivid_inter_retry_delay); + + FAPI_DBG (" attr_pm_spivid_inter_retry_delay value in config function = 0x%x", + attr_pm_spivid_inter_retry_delay ); + + // Delay is computed as: (value * ~100ns_hang_pulse) + // +0/-~100ns_hang_pulse time + // Thus, value = delay / 100 + attr_pm_spivid_inter_retry_delay_value = + attr_pm_spivid_inter_retry_delay / 100; + + SETATTR( ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, + "ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE", + &l_pTarget, + attr_pm_spivid_inter_retry_delay_value); + + FAPI_INF("Exiting the config function"); + + } while(0); - FAPI_INF("exiting the config function"); return rc ; } - +// ---------------------------------------------------------------------- +/** + * pmc_reset_function + * + * @param[in] i_target1 Primary Chip target: Murano - chip0; Venice - chip + * @param[in] i_target2 Secondary Chip target: Murano - chip1; Venice - NULL + * + * @retval ECMD_SUCCESS + * @retval ERROR defined in xml + */ fapi::ReturnCode -pmc_reset_function(const Target& i_target) +pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2 ) { - fapi::ReturnCode rc; - ecmdDataBufferBase data(64); - // ecmdDataBufferBase mask(64); - uint32_t e_rc = 0; - uint32_t count = 0 ; - bool is_stopped ; - bool is_spivid_stopped ; - bool is_not_ongoing ; - bool enable_pstate_voltage_changes ; - bool fw_pstate_mode = false; ////TODO RTC: 68461 - refresh procedures, and to init variable. - bool is_pstate_error_stopped ; - bool is_intchp_error_stopped; - bool is_MasterPMC; - bool __attribute__((unused)) enable_fw_pstate_mode; // HACK - - -//////////////////////////////////////////////////////////////////////////// -// 1. cRQ_TD_IntMaskRQ: Mask OCC interrupts in OIMR1 -// PMC_PSTATE_REQUEST, PMC_PROTOCOL_ONGOING, PMC_VOLTAGE_CHANGE_ONGOING, -// PMC_INTERCHIP_MSG_SEND_ONGOING, PMC_IDLE_ENTER, PMC_IDLE_EXIT, PMC_SYNC -//////////////////////////////////////////////////////////////////////////// - - FAPI_INF("Performing STEP 1"); - - e_rc = data.flushTo0(); if(e_rc){rc.setEcmdError(e_rc); return rc;} - - rc = fapiGetScom(i_target, OCB_OCI_OIMR1_0x0006a014 , data ); - if (rc) { - FAPI_ERR("fapiGetScom(OCB_OCI_OIMR1_0x0006a014) failed."); return rc; - } - - - e_rc = data.setBit(12); if(e_rc){rc.setEcmdError(e_rc); return rc; } - e_rc = data.setBit(13); if(e_rc){rc.setEcmdError(e_rc); return rc; } - e_rc = data.setBit(14); if(e_rc){rc.setEcmdError(e_rc); return rc; } - e_rc = data.setBit(15); if(e_rc){rc.setEcmdError(e_rc); return rc; } - e_rc = data.setBit(18); if(e_rc){rc.setEcmdError(e_rc); return rc; } - e_rc = data.setBit(20); if(e_rc){rc.setEcmdError(e_rc); return rc; } - e_rc = data.setBit(22); if(e_rc){rc.setEcmdError(e_rc); return rc; } - - - - rc = fapiPutScom(i_target, OCB_OCI_OIMR1_0x0006a014 , data ); - if (rc) { - FAPI_ERR("fapiPutScom(OCB_OCI_OIMR1_0x0006a014) failed."); return rc; - } - -//////////////////////////////////////////////////////////////////////////// -// 2. cRQ_TD_IntMaskER: Mask OCC interrupts in OIMR0 -// PMC_ERROR, PMC_MALF_ALERT, PMC_INTERCHIP_MSG_RECVD -//////////////////////////////////////////////////////////////////////////// - - - - FAPI_INF("Performing STEP 2"); - rc = fapiGetScom(i_target, OCB_OCI_OIMR0_0x0006a004 , data ); - if (rc) { - FAPI_ERR("fapiGetScom(OCB_OCI_OIMR0_0x0006a004) failed."); return rc; - } - - - e_rc = data.setBit(9); if(e_rc){rc.setEcmdError(e_rc); return rc; } - e_rc = data.setBit(13); if(e_rc){rc.setEcmdError(e_rc); return rc; } - e_rc = data.setBit(21); if(e_rc){rc.setEcmdError(e_rc); return rc; } - - - - rc = fapiPutScom(i_target, OCB_OCI_OIMR0_0x0006a004 , data ); - if (rc) { - FAPI_ERR("fapiPutScom(OCB_OCI_OIMR0_0x0006a004) failed."); return rc; - } - - -//////////////////////////////////////////////////////////////////////////// -// 3. cRQ_TD_DisableMPS: Write PMC_MODE_REG to halt things Which register bits should be written with what to make this below halts ? -// halt_pstate_master_fsm<-1 <-1 indicates to write the bit with the value 1 -// halt_idle_state_master_fsm<-1 <-1 indicates to write the bit with the value 1 -// Note: Other bits are left as setup so the configuration remains as things halt, and new -// requests are queued (just now processed now). -//////////////////////////////////////////////////////////////////////////// - - FAPI_INF("Performing STEP 3"); - rc = fapiGetScom(i_target, PMC_MODE_REG_0x00062000 , data ); - if (rc) { - FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); return rc; - } - - - e_rc = data.setBit(05); if(e_rc){rc.setEcmdError(e_rc); return rc; } - e_rc = data.setBit(14); if(e_rc){rc.setEcmdError(e_rc); return rc; } - - - - rc = fapiPutScom(i_target, PMC_MODE_REG_0x00062000 , data ); - if (rc) { - FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); return rc; - } - - is_MasterPMC = data.isBitSet(6) & data.isBitSet(7) ; - enable_pstate_voltage_changes = data.isBitSet(6) ; - enable_fw_pstate_mode = data.isBitSet(2) ; - - - - - - -//////////////////////////////////////////////////////////////////////////// -// 4. if enable_interchip_interface==1 -// cRQ_TD_HaltInterchip_On: Write PMC_INTCHP_COMMAND_REG.interchip_halt_msg_fsm<-1 Should we write the command register here ? That's why I specified the command register, PMC_INTCHP_COMMAND_REG. -// cRQ_TD_HaltInterchip_Wait1: Read PMC_STATUS_REG -// cRQ_TD_HaltInterchip_Wait2: Read PMC_INTCHP_STATUS_REG -// is_pstate_error_stopped = pstate_processing_is_suspended || gpsa_bdcst_error || gpsa_vchg_error || gpsa_timeout_error || pstate_interchip_error -// is_intchp_error_stopped = interchip_ecc_ue_err || interchip_fsm_err || (is_MasterPMC && interchip_slave_error_code != 0) is_MasterPMC where is this bit ? -// is_stopped = (interchip_ga_ongoing == 0) || is_pstate_error_stopped || is_intchp_error_stopped -// If !is_stopped Then -->cRQ_TD_HaltInterchip_Wait1 (Wait limit is parm TD_Interchip_HaltWait_max=260) -// cRQ_TD_HaltInterchipIf: PMC_MODE_REG.interchip_halt_if<-1 interchip_halt_if where is this bit ? PMC_MODE_REG bit 15 as documented. - - -//////////////////////////////////////////////////////////////////////////// - - - FAPI_INF("Performing STEP 4"); - if (data.isBitSet(6)) - - { - - rc = fapiGetScom(i_target, PMC_INTCHP_COMMAND_REG_0x00062014 , data ); - if (rc) { - FAPI_ERR("fapiGetScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); return rc; - } - - e_rc = data.setBit(01); if(e_rc){rc.setEcmdError(e_rc); return rc; } - - - rc = fapiPutScom(i_target, PMC_INTCHP_COMMAND_REG_0x00062014 , data ); - if (rc) { - FAPI_ERR("fapiPutScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); return rc; - } - - - - - - - for (count = 0 , is_stopped = 0 ; count <= 256 && is_stopped == 0; count++) - { -// cRQ_TD_HaltInterchip_Wait1: Read PMC_STATUS_REG -// is_pstate_error_stopped = pstate_processing_is_suspended || gpsa_bdcst_error || gpsa_vchg_error || gpsa_timeout_error || pstate_interchip_error - - rc = fapiGetScom(i_target, PMC_STATUS_REG_0x00062009 , data ); - if (rc) { - FAPI_ERR("fapiGetScom(PMC_STATUS_REG_0x00062009) failed."); return rc; - } - - - is_pstate_error_stopped = data.isBitSet(0) | data.isBitSet(1) | data.isBitSet(5)| data.isBitSet(6) | data.isBitSet(11) ; - - -// cRQ_TD_HaltInterchip_Wait2: Read PMC_INTCHP_STATUS_REG -// is_intchp_error_stopped = interchip_ecc_ue_err || interchip_fsm_err || (is_MasterPMC && interchip_slave_error_code != 0) is_MasterPMC where is this bit ? - - rc = fapiGetScom(i_target, PMC_INTCHP_STATUS_REG_0x00062013 , data ); - if (rc) { - FAPI_ERR("fapiGetScom(PMC_INTCHP_STATUS_REG_0x00062013) failed."); return rc; - } - is_intchp_error_stopped = data.isBitSet(1) | data.isBitSet(7) | (~( data.isBitClear(16,4) && is_MasterPMC)) ; - -// is_stopped = (interchip_ga_ongoing == 0) || is_pstate_error_stopped || is_intchp_error_stopped ; - is_stopped = data.isBitClear(0) || is_pstate_error_stopped || is_intchp_error_stopped; - - -// If !is_stopped Then -->cRQ_TD_HaltInterchip_Wait1 (Wait limit is parm TD_Interchip_HaltWait_max=260) - - - } // end_for - if (count > 256) - { - FAPI_ERR("Timed out in polling interchip ongoing ... "); - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); - return rc; - - } - - -// cRQ_TD_HaltInterchipIf: PMC_MODE_REG.interchip_halt_if<-1 interchip_halt_if where is this bit ? PMC_MODE_REG bit 15 as documented. - rc = fapiGetScom(i_target, PMC_MODE_REG_0x00062000 , data ); - if (rc) { - FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); return rc; - } - - e_rc = data.setBit(15); if(e_rc){rc.setEcmdError(e_rc); return rc; } - - rc = fapiPutScom(i_target, PMC_MODE_REG_0x00062000 , data ); - if (rc) { - FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); return rc; - } - - - - - } // end if - - - - -//////////////////////////////////////////////////////////////////////////// -// 5. if enable_pstate_voltage_changes==1 -// cRQ_TD_HaltSpivid: PMC_SPIV_COMMAND_REG.spivid_halt_fsm<-1 -// cRQ_TD_Spivid_HaltWait: Read PMC_SPIV_STATUS_REG -// is_spivid_error = spivid_retry_timeout || spivid_fsm_err -// if spivid_ongoing && !is_spivid_error Then -->cRQ_TD_Spivid_HaltWait (Wait limit is parm TD_Spivid_HaltWait_max=100) -// else -->cRQ_TD_MPS_HaltWait -//////////////////////////////////////////////////////////////////////////// - - FAPI_INF("Performing STEP 5"); - - if (enable_pstate_voltage_changes==1) - { -// cRQ_TD_HaltSpivid: PMC_SPIV_COMMAND_REG.spivid_halt_fsm<-1 - rc = fapiGetScom(i_target, PMC_SPIV_COMMAND_REG_0x00062047 , data ); - if (rc) { - FAPI_ERR("fapiGetScom(PMC_SPIV_COMMAND_REG_0x00062047) failed."); return rc; - } - - e_rc = data.setBit(15); if(e_rc){rc.setEcmdError(e_rc); return rc; } - - rc = fapiPutScom(i_target, PMC_SPIV_COMMAND_REG_0x00062047 , data ); - if (rc) { - FAPI_ERR("fapiPutScom(PMC_SPIV_COMMAND_REG_0x00062047) failed."); return rc; - } - - - -// cRQ_TD_Spivid_HaltWait: Read PMC_SPIV_STATUS_REG - -// if spivid_ongoing && !is_spivid_error Then -->cRQ_TD_Spivid_HaltWait (Wait limit is parm TD_Spivid_HaltWait_max=100) - - for (count = 0 , is_spivid_stopped=0; count <= 100 && is_spivid_stopped==0 ; count++) - { - - rc = fapiGetScom(i_target, PMC_SPIV_STATUS_REG_0x00062046 , data ); - if (rc) { - FAPI_ERR("fapiGetScom(PMC_SPIV_STATUS_REG_0x00062046) failed."); return rc; + fapi::ReturnCode rc; + ecmdDataBufferBase data(64); + // ecmdDataBufferBase mask(64); + uint32_t e_rc = 0; + uint32_t count = 0 ; + bool is_stopped ; + bool is_spivid_stopped ; + bool is_not_ongoing ; + + // bool fw_pstate_mode ; + bool is_pstate_error_stopped ; + bool is_intchp_error_stopped; + bool master_enable_pstate_voltage_changes ; + bool master_is_MasterPMC; + bool master_enable_fw_pstate_mode; + bool master_is_enable_interchip_interface; + + + //TODO RTC: 71328 - explicit default - could be uninitialized on line 1084 + bool slave_enable_pstate_voltage_changes = false; + bool slave_is_MasterPMC; + //TODO RTC: 71328 - explicit default - could be uninitialized on line 1075 + bool slave_enable_fw_pstate_mode = false; + //TODO RTC: 71328 - explicit default - could be uninitialized on line 1374 + bool slave_is_enable_interchip_interface = false; + + + fapi::Target master_target; + fapi::Target slave_target; + uint8_t attr_pm_spivid_port_enable1 = 0; +// uint8_t attr_pm_spivid_port_enable2 = 0; + uint8_t attr_dcm_installed_1 = 0; + uint8_t attr_dcm_installed_2 = 0; + uint64_t any_error = 0; + + do + { + // Check for validity of passed parms + bool dcm = false; + + FAPI_INF("Performing STEP 1"); + rc = FAPI_ATTR_GET(ATTR_PROC_DCM_INSTALLED, &i_target1, attr_dcm_installed_1); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_DCM_INSTALLED with rc = 0x%x", (uint32_t)rc); + break; + } + + FAPI_INF (" ATTR_DCM_INSTALLED value in reset function = 0x%x", attr_dcm_installed_1 ); + + if (attr_dcm_installed_1 == 0) + { + + // target2 should be NULL + // if not NULL, exit with config error + if (i_target2.getType() != TARGET_TYPE_NONE ) + { + FAPI_ERR ("config error : target2 is not null for target1 dcm not installed case"); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_DCM_INSTALL_ERROR); + break; + } + } + else + { + // GSS: test removed as this can be the case for a deconfigured DCM + // if target2 is NULL, exit with config error + // if target2 dcm attr not 1, exit with config error + //if (i_target2.getType() == TARGET_TYPE_NONE ) + //{ + // FAPI_ERR ("config error : target2 is null for target1 dcm installed case"); + // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_DCM_INSTALL_ERROR); + // break; + //} + + if (i_target2.getType() != TARGET_TYPE_NONE ) + { rc = FAPI_ATTR_GET(ATTR_PROC_DCM_INSTALLED, &i_target2, attr_dcm_installed_2); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_DCM_INSTALLED with rc = 0x%x", (uint32_t)rc); + break; + } + FAPI_INF (" ATTR_DCM_INSTALLED value in reset function = 0x%x", attr_dcm_installed_2 ); + + if (attr_dcm_installed_2 != 1) + { + FAPI_ERR ("config error: DCM_INSTALLED target2 does not match target1"); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_DCM_INSTALL_ERROR); + break; + } + + dcm = true; } - is_spivid_stopped = data.isBitClear(0) | data.isBitSet(1) | data.isBitSet(2) | data.isBitSet(3) | data.isBitSet(4) ; - - } // end for - - - - if (count > 100) - { - FAPI_ERR("Timed out in polling spiv ongoing ... "); - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); - return rc; - - } - - } // end if - - -//////////////////////////////////////////////////////////////////////////// -// 6. cRQ_TD_MPS_HaltWait: Read PMC_STATUS_REG -// -// if (fw_pstate_mode) -// is_not_ongoing = (enable_pstate_voltage_changes==0 || volt_chg_ongoing==0) && (brd_cst_ongoing == 0) -// else -// is_not_ongoing = (enable_pstate_voltage_changes==0 || gpsa_chg_ongoing==0) - -// is_pstate_error = (pstate_interchip_error || pstate_processing_is_suspended || gpsa_bdcst_error || gpsa_vchg_error || gpsa_timeout_error) -// is_stopped = is_not_ongoing || is_pstate_error - -// if (!is_stopped) then -->cRQ_TD_MPS_HaltWait (Wait limit) - -//////////////////////////////////////////////////////////////////////////// - - FAPI_INF("Performing STEP "); - - - for (count = 0 , is_stopped = 0 ; count <= 256 && is_stopped == 0 ; count++) - { - - rc = fapiGetScom(i_target, PMC_STATUS_REG_0x00062009 , data ); - if (rc) { - FAPI_ERR("fapiGetScom(PMC_STATUS_REG_0x00062009) failed."); return rc; - } - - - if (fw_pstate_mode) - { - - is_not_ongoing = (enable_pstate_voltage_changes==0 || data.isBitClear(8)) && data.isBitClear(9); - - } - else - { - is_not_ongoing = (enable_pstate_voltage_changes==0 || data.isBitClear(7)); - } - - is_stopped = (data.isBitSet(11) | data.isBitSet(12) | data.isBitSet(1) | data.isBitSet(5) | data.isBitSet(6)) | is_not_ongoing ; - - } // end for - - if (count > 100) - { - FAPI_ERR("Timed out in polling voltage change ongoing ... "); - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); - return rc; - - } - return rc; + } + + //////////////////////////////////////////////////////////////////////////// + // 1) Determine master chip and slave chip. By reading the SPIVID_EN attribute + // If SPIVID_EN is != 0 then that target is master + // If SPIVID_EN is == 0 then that target is slave + // If both SPIVID_EN are != 0 then its an error + //////////////////////////////////////////////////////////////////////////// + + + FAPI_INF("Performing STEP 1"); + rc = FAPI_ATTR_GET( ATTR_PM_SPIVID_PORT_ENABLE, + &i_target1, + attr_pm_spivid_port_enable1); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_PORT_ENABLE with rc = 0x%x", (uint32_t)rc); + break; + } + FAPI_INF (" value read from the attribute attr_pm_spivid_port_enable in reset function = 0x%x", + attr_pm_spivid_port_enable1); + + // \todo Removing until as the secondary port enable attrributes are irrelevant + /* + if (dcm) + { + rc = FAPI_ATTR_GET( ATTR_PM_SPIVID_PORT_ENABLE, + &i_target2, + attr_pm_spivid_port_enable2); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_PORT_ENABLE with rc = 0x%x", (uint32_t)rc); + break; + } + FAPI_INF (" value read from the attribute attr_pm_spivid_port_enable in reset function = 0x%x", + attr_pm_spivid_port_enable2); + } + + + if (attr_pm_spivid_port_enable2 != 0 && attr_pm_spivid_port_enable1 != 0 ) + { + FAPI_ERR("Both targets have SPIVIDs enabled: check the configuration setup."); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_TARGET_ERROR); + break; + } + else if (attr_pm_spivid_port_enable2 == 0 && attr_pm_spivid_port_enable1 == 0 ) + { + FAPI_ERR("Neither target has SPIVID enabled: check the configuration setup."); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_TARGET_ERROR); + break; + } + else + { + + if (attr_pm_spivid_port_enable2 != 0 ) + { + master_target = i_target2; + slave_target = i_target1; + } + */ + if (attr_pm_spivid_port_enable1 != 0 ) + { + master_target = i_target1; + slave_target = i_target2; + } + else + { + FAPI_ERR("Master target does not have SPIVID ports enabled: check the configuration setup."); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_TARGET_ERROR); + break; + } + //} + + + + //////////////////////////////////////////////////////////////////////////// + // 2.0 cRQ_TD_IntMaskRQ: Mask OCC interrupts in OIMR1 + // PMC_PSTATE_REQUEST, PMC_PROTOCOL_ONGOING, PMC_VOLTAGE_CHANGE_ONGOING, + // PMC_INTERCHIP_MSG_SEND_ONGOING, PMC_IDLE_ENTER, PMC_IDLE_EXIT, PMC_SYNC + // 12 + // 13 + // 14 + // 15 + // 18 + // 20 + // 22 of OCB_OCI_OIMR1_0x0006a014 + // + // 2.1 cRQ_TD_IntMaskER: Mask OCC interrupts in OIMR0 + // PMC_ERROR, PMC_MALF_ALERT, PMC_INTERCHIP_MSG_RECVD + // 9 + // 13 + // 21 of OCB_OCI_OIMR0_0x0006a004 + //////////////////////////////////////////////////////////////////////////// + + // ****************************************************** + // Master + // ****************************************************** + + FAPI_INF("Performing STEP 2.00"); + + // CHECKING PMC_FIRS + + e_rc = data.flushTo0(); + if (e_rc) + { + rc.setEcmdError(e_rc); + break; + } + rc = fapiGetScom(master_target, PMC_LFIR_0x01010840 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_LFIR_0x01010840) failed."); + break; + } + + any_error = data.getDoubleWord(0); + + if (any_error) + { + FAPI_DBG(" PMC_FIR has error(s) active. Continuing though 0x%16llX ", data.getDoubleWord(0)); + //FAPI_SET_HWP_ERROR(rc, RC_PROCPM_FIR_ERROR); break; + //return rc ; + } + + + e_rc = data.flushTo0(); + if (e_rc) + { + rc.setEcmdError(e_rc); + break; + } + + rc = fapiGetScom(master_target, OCB_OCI_OIMR1_0x0006a014 , data ); + if (rc) { + FAPI_ERR("fapiGetScom(OCB_OCI_OIMR1_0x0006a014) failed."); break; + } + + + e_rc = data.setBit(12); + e_rc |= data.setBit(13); + e_rc |= data.setBit(14); + e_rc |= data.setBit(15); + e_rc |= data.setBit(18); + e_rc |= data.setBit(20); + e_rc |= data.setBit(22); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up OCB_OCI_OIMR1_0x0006a014 on Master"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(master_target, OCB_OCI_OIMR1_0x0006a014 , data ); + if (rc) { + FAPI_ERR("fapiPutScom(OCB_OCI_OIMR1_0x0006a014) failed."); break; + } + + rc = fapiGetScom(master_target, OCB_OCI_OIMR0_0x0006a004 , data ); + if (rc) { + FAPI_ERR("fapiGetScom(OCB_OCI_OIMR0_0x0006a004) failed."); break; + } + + + e_rc = data.setBit(9); + e_rc |= data.setBit(13); + e_rc |= data.setBit(21); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up OCB_OCI_OIMR0_0x0006a004 on Master"); + rc.setEcmdError(e_rc); + break; + } + + + + rc = fapiPutScom(master_target, OCB_OCI_OIMR0_0x0006a004 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(OCB_OCI_OIMR0_0x0006a004) failed."); + break; + } + + // ****************************************************** + // Slave + // ****************************************************** + + if (dcm) + { + + FAPI_INF("Performing STEP 2.01"); + + // CHECKING PMC_FIRS + + e_rc = data.flushTo0(); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error flushing buffer"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiGetScom(slave_target, PMC_LFIR_0x01010840 , data ); + if (rc) { + FAPI_ERR("fapiGetScom(PMC_LFIR_0x01010840) failed."); + break; + } + + any_error = data.getDoubleWord(0); + + if (any_error) + { + FAPI_ERR(" PMC_FIR has error(s) active. 0x%16llX ", data.getDoubleWord(0)); + //FAPI_SET_HWP_ERROR(rc, RC_PROCPM_FIR_ERROR); break; + //return rc ; + } + + e_rc = data.flushTo0(); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error flushing buffer"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiGetScom(slave_target, OCB_OCI_OIMR1_0x0006a014 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(OCB_OCI_OIMR1_0x0006a014) failed."); break; + } + + e_rc = data.setBit(12); + e_rc |= data.setBit(13); + e_rc |= data.setBit(14); + e_rc |= data.setBit(15); + e_rc |= data.setBit(18); + e_rc |= data.setBit(20); + e_rc |= data.setBit(22); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up OIMR1"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(slave_target, OCB_OCI_OIMR1_0x0006a014 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(OCB_OCI_OIMR1_0x0006a014) failed."); + break; + } + + rc = fapiGetScom(slave_target, OCB_OCI_OIMR0_0x0006a004 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(OCB_OCI_OIMR0_0x0006a004) failed."); + break; + } + + e_rc = data.setBit(9); + e_rc |= data.setBit(13); + e_rc |= data.setBit(21); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up OIMR0"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(slave_target, OCB_OCI_OIMR0_0x0006a004 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(OCB_OCI_OIMR0_0x0006a004) failed."); break; + } + } + + + //////////////////////////////////////////////////////////////////////////// + // Issue halt to Pstate Master FSM on master_chiptarget + // Issue halt to Pstate Master FSM on slave_chiptarget + // + // 3. cRQ_TD_DisableMPS: Write PMC_MODE_REG to halt things + // halt_pstate_master_fsm<-1 <-1 indicates to write the bit with the value 1 + // halt_idle_state_master_fsm<-1 <-1 indicates to write the bit with the value 1 + // Note: Other bits are left as setup so the configuration remains as things halt, and new + // requests are queued (just now processed now). + //////////////////////////////////////////////////////////////////////////// + + + // ****************************************************** + // Master + // ****************************************************** + FAPI_INF("Performing STEP 3.00"); + + rc = fapiGetScom(master_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + e_rc = data.setBit(05); + e_rc |= data.setBit(14); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_MODE_REG_0x00062000 on Master during reset"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(master_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + master_is_MasterPMC = data.isBitSet(6) & data.isBitSet(7) ; + master_enable_pstate_voltage_changes = data.isBitSet(3) ; + master_enable_fw_pstate_mode = data.isBitSet(2) ; + master_is_enable_interchip_interface = data.isBitSet(6) ; + + + // ****************************************************** + // Slave + // ****************************************************** + + if (dcm) + { + FAPI_INF("Performing STEP 3.01"); + rc = fapiGetScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + + e_rc = data.setBit(05); + e_rc |= data.setBit(14); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_MODE_REG_0x00062000 on Slave during reset"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + slave_is_MasterPMC = data.isBitSet(6) & data.isBitSet(7) ; + slave_enable_pstate_voltage_changes = data.isBitSet(3) ; + slave_enable_fw_pstate_mode = data.isBitSet(2) ; + slave_is_enable_interchip_interface = data.isBitSet(6) ; + + + // Check with Greg about return + // TODO : if ATTR_DCM_INSTALLED = 1 chip level attribute + if (master_is_MasterPMC == 0) + { + FAPI_ERR(" MasterPMC bit of Master PMC is not set"); + + } + + if (slave_is_MasterPMC == 1) + { + FAPI_ERR(" MasterPMC bit of Slave PMC is set"); + } + + + //TODO RTC: 71328 - make priorities explicit with paranthesis + if ((master_is_enable_interchip_interface ==1) & (slave_is_enable_interchip_interface == 0)) + { + FAPI_ERR (" Configuration Error : Master is enabled with interchip interface but slave is not "); + + } + + //TODO RTC: 71328 - make priorities explicit with paranthesis + if ( (master_enable_fw_pstate_mode == 1) & (slave_enable_fw_pstate_mode == 0)) + { + FAPI_ERR (" Configuration Error : Master is enabled with FW pstate mode but slave is not "); + + } + } + + + + //////////////////////////////////////////////////////////////////////////// + // Issue halt to interchip FSM on master_chiptarget + // Poll for interchip interface to stop on master_chiptarget + // If poll not complete, flag "reset_suspicious" and save the poll point; continue + + // Issue halt to interchip FSM on slave_chiptarget + // Poll for interchip interface to stop on slave_chiptarget + // If poll not complete, flag "reset_suspicious" and save the poll point; continue + + // Poll for Pstate Master FSM being stopped on slave_chiptarget + // If poll not complete, flag "reset_suspicious" and save the poll point; continue + // Poll for Pstate Master FSM being stopped on slave_chiptarget + // If poll not complete, flag "reset_suspicious" and save the poll point; continue + // + // 4. if enable_interchip_interface==1 + // cRQ_TD_HaltInterchip_On: Write PMC_INTCHP_COMMAND_REG.interchip_halt_msg_fsm<-1 Should we write the command register here ? That's why I specified the command register, PMC_INTCHP_COMMAND_REG. + // cRQ_TD_HaltInterchip_Wait1: Read PMC_STATUS_REG + // cRQ_TD_HaltInterchip_Wait2: Read PMC_INTCHP_STATUS_REG + // is_pstate_error_stopped = pstate_processing_is_suspended || gpsa_bdcst_error || gpsa_vchg_error || gpsa_timeout_error || pstate_interchip_error + // is_intchp_error_stopped = interchip_ecc_ue_err || interchip_fsm_err || (is_MasterPMC && interchip_slave_error_code != 0) is_MasterPMC where is this bit ? + // is_stopped = (interchip_ga_ongoing == 0) || is_pstate_error_stopped || is_intchp_error_stopped + // If !is_stopped Then -->cRQ_TD_HaltInterchip_Wait1 (Wait limit is parm TD_Interchip_HaltWait_max=260) + // cRQ_TD_HaltInterchipIf: PMC_MODE_REG.interchip_halt_if<-1 interchip_halt_if where is this bit ? PMC_MODE_REG bit 15 as documented. + + + //////////////////////////////////////////////////////////////////////////// + + // ****************************************************** + // Master + // ****************************************************** + if (dcm) + { + FAPI_INF("Performing STEP 4.00"); + if (master_is_enable_interchip_interface == 1) + { + + rc = fapiGetScom(master_target, PMC_INTCHP_COMMAND_REG_0x00062014 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); + break; + } + + e_rc = data.setBit(01); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_INTCHP_COMMAND_REG_0x00062014 on Master during reset"); + rc.setEcmdError(e_rc); + break; + } + + + rc = fapiPutScom(master_target, PMC_INTCHP_COMMAND_REG_0x00062014 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); + break; + } + + // Poll for interchip interface to stop + for (count = 0 , is_stopped = 0 ; count <= INTERCHIP_HALT_POLL_COUNT && is_stopped == 0; count++) + { + // Interchip_Wait1: Read PMC_STATUS_REG + // is_pstate_error_stopped = pstate_processing_is_suspended || + // gpsa_bdcst_error || + // gpsa_vchg_error || + // gpsa_timeout_error || + // pstate_interchip_error + + rc = fapiGetScom(master_target, PMC_STATUS_REG_0x00062009 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_STATUS_REG_0x00062009) failed."); + break; + } + + is_pstate_error_stopped = data.isBitSet(0) | + data.isBitSet(1) | + data.isBitSet(5) | + data.isBitSet(6) | + data.isBitSet(11); + + // Interchip_Wait2: Read PMC_INTCHP_STATUS_REG + // is_intchp_error_stopped = interchip_ecc_ue_err || + // interchip_fsm_err || + // (is_MasterPMC && interchip_slave_error_code != 0) is_MasterPMC + rc = fapiGetScom(master_target, PMC_INTCHP_STATUS_REG_0x00062013 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_INTCHP_STATUS_REG_0x00062013) failed."); + break; + } + is_intchp_error_stopped = data.isBitSet(1) | + data.isBitSet(7) | + (~( data.isBitClear(16,4) && master_is_MasterPMC)) ; + + // is_stopped = (interchip_ga_ongoing == 0) || + // is_pstate_error_stopped || + // is_intchp_error_stopped ; + is_stopped = data.isBitClear(0) || is_pstate_error_stopped || is_intchp_error_stopped; + FAPI_DBG("polling interchip ongoing : ... "); + + // If !is_stopped Then -->Interchip_Wait1 (Wait limit is parm TD_Interchip_HaltWait_max=260) + + } // end_for + // Error check + if (!rc.ok()) + { + break; + } + + if (count > INTERCHIP_HALT_POLL_COUNT) + { + FAPI_ERR("Timed out in polling interchip ongoing : Reset_suspicious ... "); + // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); + // break; + } + + // InterchipIf: PMC_MODE_REG.interchip_halt_if<-1 interchip_halt_if + + rc = fapiGetScom(master_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + e_rc = data.setBit(15); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_MODE_REG_0x00062000 on Master during reset"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(master_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) { + FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); break; + } + + } // end if + + // ****************************************************** + // Slave + // ****************************************************** + + + FAPI_INF("Performing STEP 4.01"); + + if (slave_is_enable_interchip_interface ==1) + { + + rc = fapiGetScom(slave_target, PMC_INTCHP_COMMAND_REG_0x00062014 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); + break; + } + + e_rc = data.setBit(01); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_INTCHP_COMMAND_REG_0x00062014 on Slave during reset"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(slave_target, PMC_INTCHP_COMMAND_REG_0x00062014 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); + break; + } + + // Poll for interchip interface to stop + for (count = 0 , is_stopped = 0 ; count <= INTERCHIP_HALT_POLL_COUNT && is_stopped == 0; count++) + { + // Interchip_Wait1: Read PMC_STATUS_REG + // is_pstate_error_stopped = pstate_processing_is_suspended || + // gpsa_bdcst_error || + // gpsa_vchg_error || + // gpsa_timeout_error || + // pstate_interchip_error + + rc = fapiGetScom(slave_target, PMC_STATUS_REG_0x00062009 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_STATUS_REG_0x00062009) failed."); + break; + } + + is_pstate_error_stopped = data.isBitSet(0) | + data.isBitSet(1) | + data.isBitSet(5) | + data.isBitSet(6) | + data.isBitSet(11) ; + + + // Interchip_Wait2: Read PMC_INTCHP_STATUS_REG + // is_intchp_error_stopped = interchip_ecc_ue_err || + // interchip_fsm_err || + // (is_MasterPMC && interchip_slave_error_code != 0) is_MasterPMC + + rc = fapiGetScom(slave_target, PMC_INTCHP_STATUS_REG_0x00062013 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_INTCHP_STATUS_REG_0x00062013) failed."); + break; + } + is_intchp_error_stopped = data.isBitSet(1) | + data.isBitSet(7) | + (~( data.isBitClear(16,4) && slave_is_MasterPMC)); + + // is_stopped = (interchip_ga_ongoing == 0) || + // is_pstate_error_stopped || + // is_intchp_error_stopped ; + is_stopped = data.isBitClear(0) || + is_pstate_error_stopped || + is_intchp_error_stopped; + FAPI_DBG("polling interchip ongoing : ... "); + + } // end_for + + // Error check + if (!rc.ok()) + { + break; + } + + // Timeout check + if (count > INTERCHIP_HALT_POLL_COUNT) + { + FAPI_ERR("Timed out in polling interchip ongoing : Reset_suspicious ... "); + // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); + // break; + } + + + // InterchipIf: PMC_MODE_REG.interchip_halt_if<-1 interchip_halt_if + rc = fapiGetScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + e_rc = data.setBit(15); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_MODE_REG_0x00062000 on Slave during reset"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + } // end if + } // end dcm + + //////////////////////////////////////////////////////////////////////////// + // If voltage changes are enable, issue halt to SPIVID controller on FSM on master_chiptarget + // Poll for SPIVID FSM to halt on master_chiptarget + // If poll not complete, flag "reset_suspicious" and save the poll point; continue + // + // 5. if enable_pstate_voltage_changes==1 + // HaltSpivid: PMC_SPIV_COMMAND_REG.spivid_halt_fsm<-1 + // Spivid_HaltWait: Read PMC_SPIV_STATUS_REG + // is_spivid_error = spivid_retry_timeout || spivid_fsm_err + // if spivid_ongoing && !is_spivid_error Then -->Spivid_HaltWait (Wait limit is parm TD_Spivid_HaltWait_max=100) + // else -->MPS_HaltWait + //////////////////////////////////////////////////////////////////////////// + + FAPI_INF("Performing STEP 5.00"); + + if (master_enable_pstate_voltage_changes==1) + { + // HaltSpivid: PMC_SPIV_COMMAND_REG.spivid_halt_fsm<-1 + rc = fapiGetScom(master_target, PMC_SPIV_COMMAND_REG_0x00062047 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_SPIV_COMMAND_REG_0x00062047) failed."); + break; + } + + e_rc = data.setBit(0); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_SPIV_COMMAND_REG_0x00062047 on Master during reset"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(master_target, PMC_SPIV_COMMAND_REG_0x00062047 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_SPIV_COMMAND_REG_0x00062047) failed."); + break; + } + + // Spivid_HaltWait: Read PMC_SPIV_STATUS_REG + for (count = 0 , is_spivid_stopped=0; count <= VOLTAGE_CHANGE_POLL_COUNT && is_spivid_stopped==0 ; count++) + { + rc = fapiGetScom(master_target, PMC_SPIV_STATUS_REG_0x00062046 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_SPIV_STATUS_REG_0x00062046) failed."); + break; + } + is_spivid_stopped = data.isBitClear(0) | + data.isBitSet(1) | + data.isBitSet(2) | + data.isBitSet(3) | + data.isBitSet(4) ; + FAPI_DBG("Polling spivid ongoing on Masster ... "); + } // end for + + // Error check + if (!rc.ok()) + { + break; + } + + // Timeout check + if (count > VOLTAGE_CHANGE_POLL_COUNT) + { + FAPI_ERR("Timed out in polling spiv ongoing : Reset_suspicious ... "); + // \todo + // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); + // break; + } + } // end if + + + //////////////////////////////////////////////////////////////////////////// + // Poll for Pstate Master FSM being stopped on master_chiptarget + // If poll not complete, flag "reset_suspicious" and save the poll point; continue + // Poll for Pstate Master FSM being stopped on slave_chiptarget + // If poll not complete, flag "reset_suspicious" and save the poll point; continue + // + // 6. MPS_HaltWait: Read PMC_STATUS_REG + // + // if (fw_pstate_mode) + // is_not_ongoing = (enable_pstate_voltage_changes==0 || volt_chg_ongoing==0) && (brd_cst_ongoing == 0) + // else + // is_not_ongoing = (enable_pstate_voltage_changes==0 || gpsa_chg_ongoing==0) + // + // is_pstate_error = (pstate_interchip_error || pstate_processing_is_suspended || gpsa_bdcst_error || gpsa_vchg_error || gpsa_timeout_error) + // is_stopped = is_not_ongoing || is_pstate_error + // + // if (!is_stopped) then -->MPS_HaltWait (Wait limit) + //////////////////////////////////////////////////////////////////////////// + + FAPI_INF("Performing STEP 6.00 "); + + + // ****************************************************** + // Master + // ****************************************************** + for (count = 0, is_stopped = 0; count <= PSTATE_HALT_POLL_COUNT && is_stopped == 0 ; count++) + { + rc = fapiGetScom(master_target, PMC_STATUS_REG_0x00062009 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_STATUS_REG_0x00062009) failed."); + break; + } + + + if (master_enable_fw_pstate_mode) + { + is_not_ongoing = (master_enable_pstate_voltage_changes == 0 || + data.isBitClear(8) ) && + data.isBitClear(9); + } + else + { + is_not_ongoing = (master_enable_pstate_voltage_changes==0 || + data.isBitClear(7) ); + } + + is_stopped = ( data.isBitSet(11) | + data.isBitSet(12) | + data.isBitSet(1) | + data.isBitSet(5) | + data.isBitSet(6)) | + is_not_ongoing ; + FAPI_DBG("Polling voltage change ongoing on Master ... "); + } // end for + + if (count > PSTATE_HALT_POLL_COUNT ) + { + FAPI_ERR("Timed out in polling voltage change ongoing : Reset_suspicious ... "); + // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); + // break; + } + + // ****************************************************** + // Slave + // ****************************************************** + if (dcm) + { + FAPI_INF("Performing STEP 6.01 "); + + for (count = 0 , is_stopped = 0 ; count <= PSTATE_HALT_POLL_COUNT && is_stopped == 0 ; count++) + { + + rc = fapiGetScom(slave_target, PMC_STATUS_REG_0x00062009 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_STATUS_REG_0x00062009) failed."); + break; + } + + if (slave_enable_fw_pstate_mode) + { + is_not_ongoing = ( slave_enable_pstate_voltage_changes == 0 || + data.isBitClear(8) ) && + data.isBitClear(9); + } + else + { + is_not_ongoing = ( slave_enable_pstate_voltage_changes == 0 || + data.isBitClear(7) ); + } + + is_stopped = ( data.isBitSet(11) | + data.isBitSet(12) | + data.isBitSet(1) | + data.isBitSet(5) | + data.isBitSet(6)) | + is_not_ongoing ; + FAPI_DBG("polling voltage change ongoing on Slave ..."); + } // end for + + // Error check + if (!rc.ok()) + { + break; + } + + // Timeout check + if (count > PSTATE_HALT_POLL_COUNT ) + { + FAPI_ERR("Timed out in polling voltage change ongoing : Reset_suspicious ... "); + // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); + // break; + } + } // dcm + + + /////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Poll for O2P bridge being complete on master_chiptarget + // As the OCC (PPC405) has been halt prior to entry of this procedure, + // this poll will be immediate if there are no PIB related errors present + // Poll for O2P bridge being complete on slave_chiptarget + // As the OCC (PPC405) has been halt prior to entry of this procedure, + // this poll will be immediate if there are no PIB related errors present + // + // Poll for O2S bridge being complete on master_chiptarget + // As the OCC (PPC405) has been halt prior to entry of this procedure, + // this poll will be immediate if there are no SPIVID related errors present + // + // 7. Wait + // - If an O2P or O2S Op is pending and did not hit an error + // - Queisce after traffic generation or last FW GA_Step + // The O2P and O2S bridges are treated separately. The firmware should handle these + // recognizing they are still busy, hit an error, or hit a firmware timeout. The + // firmware can then choose a halt sequence for them. + // O2S: Write PMC_O2S_COMMAND_REG.o2s_halt_retries<-1 + // Read PMC_O2S_STATUS_REG + // Wait for o2s_ongoing==0 or error (o2s_retry_timeout | o2s_write_while_bridge_busy_err | o2s_fsm_err) + // O2P: No halt command in PMC - wait for PIB timeout. + // Read PMC_O2P_CTRL_STATUS_REG + // Wait for o2p_ongoing==0 or error (o2p_write_while_bridge_busy_err | o2p_fsm_err | o2p_abort | o2p_parity_error) + /////////////////////////////////////////////////////////////////////////////////////////////////////////// + + // ****************************************************** + // Master + // ****************************************************** + + FAPI_INF("Performing STEP 7.00 "); + rc = fapiGetScom(master_target, PMC_O2S_COMMAND_REG_0x00062057 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_O2S_COMMAND_REG__0x00062057) failed."); + break; + } + + e_rc = data.setBit(00); if(e_rc){rc.setEcmdError(e_rc); break; } + + rc = fapiPutScom(master_target, PMC_O2S_COMMAND_REG_0x00062057 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_O2S_COMMAND_REG__0x00062057) failed."); + break; + } + + // Poll for O2S to be stopped + for (count = 0 , is_stopped = 0 ; count <= O2S_POLL_COUNT && is_stopped == 0 ; count++) + { + rc = fapiGetScom(master_target, PMC_O2S_STATUS_REG_0x00062056 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_O2S_STATUS_REG__0x00062056) failed."); + break; + } + + is_stopped = ( data.isBitClear(0) | + data.isBitSet(4) | + data.isBitSet(5) | + data.isBitSet(7)); + FAPI_DBG("Polling O2S ongoing . : .. "); + } + + // Error check + if (!rc.ok()) + { + break; + } + + // Timeout check + if (count > O2S_POLL_COUNT) + { + FAPI_ERR("Timed out in polling O2S ongoing . : Reset_suspicious .. "); + // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); + // break; + } + + // Poll for O2P to be stopped + for (count = 0 , is_stopped = 0 ; count <= O2P_POLL_COUNT && is_stopped == 0 ; count++) + { + rc = fapiGetScom(master_target, PMC_O2P_CTRL_STATUS_REG_0x00062061 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_O2P_STATUS_REG__0x00062061) failed."); + break; + } + + is_stopped = ( data.isBitClear(0) | + data.isBitSet(4) | + data.isBitSet(5) | + data.isBitSet(6) | + data.isBitSet(7)); + FAPI_DBG("Polling O2P ongoing . : .. "); + } + + // Error check + if (!rc.ok()) + { + break; + } + + // Timeout check + if (count > O2P_POLL_COUNT) + { + FAPI_ERR("Timed out in polling O2P ongoing . : Reset_suspicious .. "); + // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); + // break; + } + + // ****************************************************** + // Slave + // ****************************************************** + + if (dcm) + { + FAPI_INF("Performing STEP 7.01 "); + + for (count = 0 , is_stopped = 0 ; count <= O2P_POLL_COUNT && is_stopped == 0 ; count++) + { + rc = fapiGetScom(slave_target, PMC_O2P_CTRL_STATUS_REG_0x00062061 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_O2P_STATUS_REG__0x00062061) failed."); + break; + } + + is_stopped = ( data.isBitClear(0) | + data.isBitSet(4) | + data.isBitSet(5) | + data.isBitSet(6) | + data.isBitSet(7)); + FAPI_DBG("Polling O2P ongoing . : .. "); + } + + // Error check + if (!rc.ok()) + { + break; + } + + // Timeout check + if (count > O2P_POLL_COUNT) + { + FAPI_ERR("Timed out in polling O2P ongoing . : Reset_suspicious .. "); + // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); + // break; + } + } // dcm + + + /////////////////////////////////////////////////////////////////////////////////////////////////////////// + //GREG: Check with Greg whether this is needed for both master and slave? + // 8) Poll for Idle FSM being quiesced (timeout: 500ms to cover the case of having all 4 types of Deep Idle + // transitions in flight) + // Note: Previously issued special wake-ups could have triggered PORE activity through the Idle FSM (and + // the related pending queues). if poll timeout, mark the error point + // + // Note on Idle/PORE-SLW state (prior to reset) + // Given that special wake-up occurred before this point, any errors that resulted from that special wake-up + // (eg PORE-SLW fatal or timeout indicated in PMC LFIR) will have fired a malfunction alert to PHYP whereby + // the execution of p8_poreslw_recovery.C will have taken place. + /////////////////////////////////////////////////////////////////////////////////////////////////////////// + + FAPI_INF("Performing STEP 8.00 "); + for (count = 0 , is_stopped = 0 ; count <= PORE_REQ_POLL_COUNT && is_stopped == 0 ; count++) + { + rc = fapiGetScom(master_target, PMC_PORE_REQ_REG0_0x0006208E , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_O2P_STATUS_REG__0x00062061) failed."); + break; + } + + is_stopped = (data.isBitClear(20)) ; + FAPI_DBG("Polling pore_busy bit ..."); + } + + // Error check + if (!rc.ok()) + { + break; + } + + // Timeout check + if (count > PORE_REQ_POLL_COUNT) + { + FAPI_ERR("Timed out in polling pore_busy bit . : Reset_suspicious .. "); + // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); + // break; + } + + /////////////////////////////////////////////////////////////////////////////// + // GREG: + // Issue interchip interface reset (if enabled) on master_chiptarget + // PMC_INTCHP_COMMAND_REG.reset (0) = 1 + // PMC_INTCHP_COMMAND_REG.reset (0) = 0 + // Issue interchip interface reset (if enabled) on slave_chiptarget + // PMC_INTCHP_COMMAND_REG.reset (0) = 1 + // PMC_INTCHP_COMMAND_REG.reset (0) = 0 + + // SCOTT: + // 9. if enable_interchip_interface==1 and parm InterchipResetIf_AfterHalt + // InterchipResetIf_On: PMC_INTCHP_COMMAND_REG.interchip_reset_if<-1 + // InterchipResetIf_Off: PMC_INTCHP_COMMAND_REG.interchip_reset_if<-0 + /////////////////////////////////////////////////////////////////////////////// + + // ****************************************************** + // Master + // ****************************************************** + + + FAPI_INF("Performing STEP 9.00 "); + + if ( master_is_enable_interchip_interface == 1) + { + + rc = fapiGetScom(master_target, PMC_INTCHP_COMMAND_REG_0x00062014 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); + break; + } + + e_rc = data.setBit(0); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_INTCHP_COMMAND_REG_0x00062014 on Master reset"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(master_target, PMC_INTCHP_COMMAND_REG_0x00062014 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); + break; + } + + e_rc = data.clearBit(0); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error clearing up PMC_INTCHP_COMMAND_REG_0x00062014 on Master reset"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(master_target, PMC_INTCHP_COMMAND_REG_0x00062014 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); + break; + } + } + + // ****************************************************** + // Slave + // ****************************************************** + + if (dcm) + { + FAPI_INF("Performing STEP 9.01 "); + + if ( slave_is_enable_interchip_interface == 1) + { + + rc = fapiGetScom(slave_target, PMC_INTCHP_COMMAND_REG_0x00062014 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); + break; + } + + e_rc = data.setBit(0); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_INTCHP_COMMAND_REG_0x00062014 on Slave reset"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(slave_target, PMC_INTCHP_COMMAND_REG_0x00062014 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); + break; + } + + e_rc = data.clearBit(0); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error clearing up PMC_INTCHP_COMMAND_REG_0x00062014 on Slave reset"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(slave_target, PMC_INTCHP_COMMAND_REG_0x00062014 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); + break; + } + } + } + + /////////////////////////////////////////////////////////////////////////////////////////////////////////// + // Issue reset to the PMC + // Note: this action will wipe out the Idle Pending queue so that requests for idle transitions (entry and exit) will be lost which means that PHYP notification needs to happen. + // Write PMC_MODE_REG.pmc_reset_all_voltage_registers = 1. + // Clearing LFIRs will have been done by PRD + // Note: this will remove CONFIG settings + // This puts the PMC into firmware mode which halts any future Global Actual operations + /////////////////////////////////////////////////////////////////////////////////////////////////////////// + + // ****************************************************** + // Master + // ****************************************************** + // RESET_ALL_PMC_REGISTERS + rc = fapiGetScom(master_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + e_rc = data.setBit(12); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_INTCHP_COMMAND_REG_0x00062014 on Master reset"); + rc.setEcmdError(e_rc); + break; + } + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); + break; + } + + rc = fapiPutScom(master_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + // ****************************************************** + // Slave + // ****************************************************** + if (dcm) + { + + rc = fapiGetScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + e_rc = data.setBit(12); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_MODE_REG_0x00062000 on Slave reset"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + // \todo remove in deference to init path + // Restored only for slave + // SAFE_MODE_WITHOUT_SPIVID + rc = fapiGetScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + e_rc = data.setBit(13); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error for PMC_MODE_REG_0x00062000 on Slave reset"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiPutScom(slave_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + } + } while(0); + + return rc; } -// ---------------------------------------------------------------------- -// Function definitions -// ---------------------------------------------------------------------- - -// function: p8_pmc_init -// parameters: target , mode = (PM_INIT , PM_CONFIG, PM_RESET) -// returns: ECMD_SUCCESS if something good happens, -// BAD_RETURN_CODE otherwise -fapi::ReturnCode -p8_pmc_init(const Target& i_target, uint32_t mode) +// ---------------------------------------------------------------------- +/** + * pmc_init_function + * + * @param[in] i_target1 Primary Chip target: Murano - chip0; Venice - chip + + * @retval ECMD_SUCCESS + * @retval ERROR defined in xml + */ +fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 ) { - fapi::ReturnCode rc; - ecmdDataBufferBase data(64); - ecmdDataBufferBase mask(64); - uint32_t e_rc = 0; - - FAPI_INF(""); - FAPI_INF("Executing p8_pmc_init ...."); - - - // ------------------------------------------------ - // CONFIG mode - // ------------------------------------------------ - if (mode == PM_CONFIG) - { - - FAPI_INF("PMC configuration..."); rc=pmc_config_spivid_settings(i_target); - - } - - // ------------------------------------------------ - // INIT mode - // ------------------------------------------------ - - else if (mode == PM_INIT) { - - uint8_t attr_pm_spivid_frame_size; - uint8_t attr_pm_spivid_in_delay_frame1; - uint8_t attr_pm_spivid_in_delay_frame2; - uint8_t attr_pm_spivid_clock_polarity; - uint8_t attr_pm_spivid_clock_phase; - uint32_t attr_pm_spivid_clock_divider; - uint8_t attr_pm_spivid_port_enable = 7; - // uint32_t attr_pm_spivid_interframe_delay_write_status; - uint32_t attr_pm_spivid_interframe_delay_write_status_value; -// uint32_t attr_pm_spivid_inter_retry_delay_value; -// uint32_t attr_pm_spivid_inter_retry_delay; - uint8_t attr_pm_spivid_crc_gen_enable; - uint8_t attr_pm_spivid_crc_check_enable; - uint8_t attr_pm_spivid_majority_vote_enable; - uint8_t attr_pm_spivid_max_retries; - uint8_t attr_pm_spivid_crc_polynomial_enables; - - - - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_FRAME_SIZE, &i_target, attr_pm_spivid_frame_size); - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_FRAME_SIZE with rc = 0x%x", (uint32_t)rc); return rc; } - else { FAPI_INF (" value read from the attribute attr_pm_spivid_frame_size = 0x%x", attr_pm_spivid_frame_size );} - - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_IN_DELAY_FRAME1, &i_target, attr_pm_spivid_in_delay_frame1); - - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_IN_DELAY_FRAME1 with rc = 0x%x", (uint32_t)rc); return rc; } - else { FAPI_INF (" value read from the attribute attr_pm_spivid_in_delay_frame1 = 0x%x", attr_pm_spivid_in_delay_frame1);} - - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_IN_DELAY_FRAME2, &i_target, attr_pm_spivid_in_delay_frame2); - - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_IN_DELAY_FRAME2 with rc = 0x%x", (uint32_t)rc); return rc; } - else { FAPI_INF (" value read from the attribute attr_pm_spivid_in_delay_frame2 = 0x%x", attr_pm_spivid_in_delay_frame2);} - - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_POLARITY, &i_target, attr_pm_spivid_clock_polarity); - - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CLOCK_POLARITY with rc = 0x%x", (uint32_t)rc); return rc; } - else { FAPI_INF (" value read from the attribute attr_pm_spivid_clock_polarity = 0x%x", attr_pm_spivid_clock_polarity);} - - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_PHASE, &i_target, attr_pm_spivid_clock_phase); - - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CLOCK_PHASE with rc = 0x%x", (uint32_t)rc); return rc; } - else { FAPI_INF (" value read from the attribute attr_pm_spivid_clock_phase = 0x%x", attr_pm_spivid_clock_phase);} - - //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS, &i_target, attr_pm_spivid_interframe_delay_write_status); - -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS with rc = 0x%x", (uint32_t)rc); return rc; } -// else { FAPI_INF (" value read from the attribute attr_pm_spivid_interframe_delay_write_status = 0x%x", attr_pm_spivid_interframe_delay_write_status);} - - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, &i_target, attr_pm_spivid_interframe_delay_write_status_value); - - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } - else { FAPI_INF (" value read from the attribute attr_pm_spivid_interframe_delay_write_status_value = 0x%x", attr_pm_spivid_interframe_delay_write_status_value);} - - //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, &i_target, attr_pm_spivid_inter_retry_delay_value); - -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } -// else { FAPI_INF (" value read from the attribute attr_pm_spivid_inter_retry_delay_value = 0x%x", attr_pm_spivid_inter_retry_delay_value);} - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_RETRY_DELAY, &i_target, attr_pm_spivid_inter_retry_delay); - -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTER_RETRY_DELAY with rc = 0x%x", (uint32_t)rc); return rc; } -// else { FAPI_INF (" value read from the attribute attr_pm_spivid_inter_retry_delay = 0x%x", attr_pm_spivid_inter_retry_delay);} - - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_GEN_ENABLE, &i_target, attr_pm_spivid_crc_gen_enable); - - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CRC_GEN_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } - else { FAPI_INF (" value read from the attribute attr_pm_spivid_crc_gen_enable = 0x%x", attr_pm_spivid_crc_gen_enable);} - - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_CHECK_ENABLE, &i_target, attr_pm_spivid_crc_check_enable); - - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CRC_CHECK_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } - else { FAPI_INF (" value read from the attribute attr_pm_spivid_crc_check_enable = 0x%x", attr_pm_spivid_crc_check_enable);} - - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE, &i_target, attr_pm_spivid_majority_vote_enable); - - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } - else { FAPI_INF (" value read from the attribute attr_pm_spivid_majority_vote_enable = 0x%x", attr_pm_spivid_majority_vote_enable);} - - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_MAX_RETRIES, &i_target, attr_pm_spivid_max_retries); - - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_MAX_RETRIES with rc = 0x%x", (uint32_t)rc); return rc; } - else { FAPI_INF (" value read from the attribute attr_pm_spivid_max_retries = 0x%x", attr_pm_spivid_max_retries);} - - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES, &i_target, attr_pm_spivid_crc_polynomial_enables); - - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES with rc = 0x%x", (uint32_t)rc); return rc; } - else { FAPI_INF (" value read from the attribute attr_pm_spivid_crc_polynomial_enables = 0x%x", attr_pm_spivid_crc_polynomial_enables);} - - - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_DIVIDER, &i_target, attr_pm_spivid_clock_divider); - - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CLOCK_DIVIDER with rc = 0x%x", (uint32_t)rc); return rc; } - else { FAPI_INF (" value read from the attribute attr_pm_spivid_clock_divider = 0x%x", attr_pm_spivid_clock_divider);} - - - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_PORT_ENABLE, &i_target, attr_pm_spivid_port_enable); - - if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_PORT_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } - else { FAPI_INF (" value read from the attribute attr_pm_spivid_port_enable = 0x%x", attr_pm_spivid_port_enable);} - - - //---------------------------------------------------------- - - - - - - - - - - - - // rc=pmc_create_spivid_settings(i_target); above lines replaced this functions - - FAPI_INF("PMC initialization..."); - - uint8_t o2s_frame_size = attr_pm_spivid_frame_size; - uint8_t o2s_in_delay1 = attr_pm_spivid_in_delay_frame1; - uint8_t o2s_in_delay2 = attr_pm_spivid_in_delay_frame2; - uint8_t o2s_clk_pol = attr_pm_spivid_clock_polarity; - uint8_t o2s_clk_pha = attr_pm_spivid_clock_phase; - uint8_t o2s_port_enable = attr_pm_spivid_port_enable; - uint32_t o2s_inter_frame_delay = attr_pm_spivid_interframe_delay_write_status_value; - uint8_t o2s_crc_gen_en = attr_pm_spivid_crc_gen_enable; - uint8_t o2s_crc_check_en = attr_pm_spivid_crc_check_enable; - uint8_t o2s_majority_vote_en = attr_pm_spivid_majority_vote_enable; - uint8_t o2s_max_retries = attr_pm_spivid_max_retries; - uint8_t o2s_crc_polynomial_enables = attr_pm_spivid_crc_polynomial_enables; - uint16_t o2s_clk_divider = attr_pm_spivid_clock_divider; - //spivid_freq = attr_pm_spivid_frequency; - uint8_t o2s_in_count2 = 0 ; - uint8_t o2s_out_count2 = 0 ; - uint8_t o2s_bridge_enable = 0x1 ; - uint8_t o2s_nr_of_frames = 1 ; //(uint8_t) args.front(); args.pop_front(); // for pmc o2s operations it is usually 1 - uint8_t o2s_in_count1 = 0 ; - uint8_t o2s_out_count1 = 32 ; - uint32_t dummy = 0 ; - - - uint8_t one=1; - - - - - - // Here to bypass feature attribute passing until these as moved into proc.pm.pmc.scom.initfile - -// o2s_frame_size = 0x10 ; -// o2s_clk_pol = 0; -// o2s_clk_pha = 0; -// o2s_clk_divider= 0x1D; -// o2s_inter_frame_delay = 0x0; -// nest_freq = 600; -// spivid_freq = 10; -// o2s_in_count1=0; -// o2s_out_count1=0; -// o2s_in_delay1=0; -// o2s_in_count2=0; -// o2s_out_count2=0; -// o2s_in_delay2=0; -// o2s_wdata = 0x11223344; - - - - // ****************************************************************** - // - set PMC_o2s_CTRL_REG0A (24b) - // ****************************************************************** - - rc = fapiGetScom(i_target, PMC_O2S_CTRL_REG0A_0x00062050, data ); - if (rc) { - FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG0A) failed."); return rc; - } - - e_rc = data.insertFromRight( o2s_frame_size ,0,6); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.insertFromRight( o2s_in_count1 ,6,6); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.insertFromRight( o2s_out_count1 ,12,6); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.insertFromRight( o2s_in_delay1 ,18,6); if(e_rc){rc.setEcmdError(e_rc); return rc;} - - - - // FAPI_INF(" -----------------------------------------------------"); - FAPI_INF(" PMC O2S CTRL_REG_0A Configuration "); - // FAPI_INF(" -----------------------------------------------------"); - e_rc = data.extractToRight(&dummy,0,6); - FAPI_INF(" frame size => %x ", dummy); - e_rc |= data.extractToRight(&dummy,6,6); - FAPI_INF(" o2s_out_count1 => %x ", dummy); - e_rc |= data.extractToRight(&dummy,12,6); - FAPI_INF(" o2s_in_delay1 => %x ", dummy); - e_rc |= data.extractToRight(&dummy,18,6); - FAPI_INF(" o2s_in_count1 => %x ", dummy); - FAPI_INF(" " ); - FAPI_INF(" " ); - // FAPI_INF(" -----------------------------------------------------"); - - if(e_rc){rc.setEcmdError(e_rc); return rc;} - rc = fapiPutScom(i_target, PMC_O2S_CTRL_REG0A_0x00062050, data ); - if (rc) { - FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG0A_0x00062050) failed."); return rc; - } - - - // ****************************************************************** - // - set PMC_O2S_CTRL_REG0B (24b) - // ****************************************************************** - - rc = fapiGetScom(i_target, PMC_O2S_CTRL_REG0B_0x00062051, data ); - if (rc) { - FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG0B) failed."); return rc; - } - - e_rc = data.insertFromRight(o2s_out_count2,00,6); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.insertFromRight(o2s_in_delay2 ,06,6); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.insertFromRight(o2s_in_count2 ,12,6); if(e_rc){rc.setEcmdError(e_rc); return rc;} - - // FAPI_INF(" -----------------------------------------------------"); - FAPI_INF(" PMC O2S CTRL_REG_0B Configuration "); - // FAPI_INF(" -----------------------------------------------------"); - FAPI_INF(" o2s_out_count2 => %d ", o2s_out_count2); - FAPI_INF(" o2s_in_delay2 => %d ", o2s_in_delay2 ); - FAPI_INF(" o2s_in_count2 => %d ", o2s_in_count2 ); - FAPI_INF(" " ); - FAPI_INF(" " ); - // FAPI_INF(" -----------------------------------------------------"); - - rc = fapiPutScom(i_target, PMC_O2S_CTRL_REG0B_0x00062051, data ); - if (rc) { - FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG0B_0x00062051) failed."); return rc; - } - - // ****************************************************************** - // - set PMC_O2S_CTRL_REG1 - // ****************************************************************** - - rc = fapiGetScom(i_target, PMC_O2S_CTRL_REG1_0x00062052, data ); - if (rc) { - FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG1) failed."); return rc; - } - - o2s_nr_of_frames--; - e_rc = data.insertFromRight( o2s_bridge_enable ,0,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.insertFromRight( o2s_clk_pol ,2,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.insertFromRight( o2s_clk_pha ,3,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.insertFromRight( o2s_clk_divider,4,10); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.insertFromRight( o2s_nr_of_frames ,17,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.insertFromRight( o2s_port_enable ,18,3); if(e_rc){rc.setEcmdError(e_rc); return rc;} - o2s_nr_of_frames++; - - - // FAPI_INF(" -----------------------------------------------------"); - FAPI_INF(" PMC O2S CTRL_REG_1 Configuration "); - // FAPI_INF(" -----------------------------------------------------"); - FAPI_INF(" o2s_bridge_enable => %d ", o2s_bridge_enable ); - FAPI_INF(" o2s_clk_pol => %d ", o2s_clk_pol ); - FAPI_INF(" o2s_clk_pha => %d ", o2s_clk_pha ); - FAPI_INF(" o2s_clk_divider => %d ", o2s_clk_divider); - FAPI_INF(" o2s_nr_of_frames => %d ", o2s_nr_of_frames); - FAPI_INF(" o2s_port_enable => %d ", o2s_port_enable); - FAPI_INF(" " ); - FAPI_INF(" " ); - // FAPI_INF(" -----------------------------------------------------"); - - rc = fapiPutScom(i_target, PMC_O2S_CTRL_REG1_0x00062052, data ); - if (rc) { - FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG1_0x00062052) failed."); return rc; - } - - - // ****************************************************************** - // - set PMC_O2S_CTRL_REG2 - // ****************************************************************** - - - rc = fapiGetScom(i_target, PMC_O2S_CTRL_REG2_0x00062053, data ); - if (rc) { - FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG2) failed."); return rc; - } - - e_rc = data.insertFromRight( o2s_inter_frame_delay ,0,17); if(e_rc){rc.setEcmdError(e_rc); return rc;} - - // FAPI_INF(" -----------------------------------------------------"); - FAPI_INF(" PMC O2S CTRL_REG_2 Configuration "); - // FAPI_INF(" -----------------------------------------------------"); - FAPI_INF(" o2s_inter_frame_delay => %d ", o2s_inter_frame_delay ); - FAPI_INF(" " ); - FAPI_INF(" " ); - // FAPI_INF(" -----------------------------------------------------"); - - - - rc = fapiPutScom(i_target, PMC_O2S_CTRL_REG2_0x00062053, data ); - if (rc) { - FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG2_0x00062053) failed."); return rc; - } - - // ****************************************************************** - // - set PMC_O2S_CTRL_REG4 - // ****************************************************************** - - rc = fapiGetScom(i_target, PMC_O2S_CTRL_REG4_0x00062055, data ); - if (rc) { - FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG4) failed."); return rc; - } - - e_rc = data.insertFromRight( o2s_crc_gen_en ,0,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.insertFromRight( o2s_crc_check_en ,1,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.insertFromRight( o2s_majority_vote_en ,2,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.insertFromRight( o2s_max_retries ,3,5); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.insertFromRight( o2s_crc_polynomial_enables,8,8); if(e_rc){rc.setEcmdError(e_rc); return rc;} - - // FAPI_INF(" -----------------------------------------------------"); - FAPI_INF(" PMC O2S CTRL_REG_4 Configuration "); - // FAPI_INF(" -----------------------------------------------------"); - FAPI_INF(" o2s_crc_gen_en => %d ", o2s_crc_gen_en ); - FAPI_INF(" o2s_crc_check_en => %d ", o2s_crc_check_en ); - FAPI_INF(" o2s_majority_vote_en => %d ", o2s_majority_vote_en ); - FAPI_INF(" o2s_max_retries => %d ", o2s_max_retries ); - FAPI_INF(" o2s_crc_polynomial_enab => %d ", o2s_crc_polynomial_enables ); - FAPI_INF(" " ); - FAPI_INF(" " ); - // FAPI_INF(" -----------------------------------------------------"); - - - rc = fapiPutScom(i_target, PMC_O2S_CTRL_REG4_0x00062055, data ); - if (rc) { - FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG4_0x00062055) failed."); return rc; - } - -// ****************************************************************** -// Program crc polynomials -// ****************************************************************** - - rc = fapiGetScom(i_target, PMC_SPIV_CTRL_REG4_0x00062045, data ); - if (rc) { - FAPI_ERR("fapiGetScom(PMC_SPIV_CTRL_REG4) failed."); return rc; - } - - - e_rc = data.insertFromRight( o2s_crc_gen_en ,0,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.insertFromRight( o2s_crc_check_en ,1,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.insertFromRight( o2s_majority_vote_en ,2,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.insertFromRight( o2s_max_retries ,3,5); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.insertFromRight( o2s_crc_polynomial_enables,8,8); if(e_rc){rc.setEcmdError(e_rc); return rc;} - - // FAPI_INF(" -----------------------------------------------------"); - FAPI_INF(" PMC O2S CTRL_REG_3Configuration "); - // FAPI_INF(" -----------------------------------------------------"); - FAPI_INF(" spiv_crc_gen_en => %d ", o2s_crc_gen_en ); - FAPI_INF(" spiv_crc_check_en => %d ", o2s_crc_check_en ); - FAPI_INF(" spiv_majority_vote_en => %d ", o2s_majority_vote_en ); - FAPI_INF(" spiv_max_retries => %d ", o2s_max_retries ); - FAPI_INF(" spiv_crc_polynomial_enab => %d ", o2s_crc_polynomial_enables ); - FAPI_INF(" " ); - FAPI_INF(" " ); - // FAPI_INF(" -----------------------------------------------------"); - - - rc = fapiPutScom(i_target, PMC_SPIV_CTRL_REG4_0x00062045, data ); - if (rc) { - FAPI_ERR("fapiPutScom(PMC_SPIV_CTRL_REG4_0x00062045) failed."); return rc; - } - - - // ****************************************************************** - // - write PMC_O2S_command_reg to clear any latent errors - // ****************************************************************** - e_rc = data.flushTo0(); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.insertFromRight(one ,0,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} // halt retries - e_rc = data.insertFromRight(one ,1,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} // reset sticky errors - // FAPI_INF(" -----------------------------------------------------"); - FAPI_INF(" clearing errors "); - // FAPI_INF(" -----------------------------------------------------"); - - rc = fapiPutScom(i_target, PMC_O2S_COMMAND_REG_0x00062057, data ); - if (rc) { - FAPI_ERR("fapiPutScom(PMC_O2S_COMMAND_REG_0x00062057) failed."); return rc; - } - - e_rc = data.flushTo0(); if(e_rc){rc.setEcmdError(e_rc); return rc;} - - rc = fapiPutScom(i_target, PMC_O2S_COMMAND_REG_0x00062057, data ); - if (rc) { - FAPI_ERR("fapiPutScom(PMC_O2S_COMMAND_REG_0x00062057) failed."); return rc; - } - FAPI_INF ("I m done with the init " ); - - } - - /// ------------------------------- - /// Reset: perform reset of PMC - else if (mode == PM_RESET) - { - - FAPI_INF("PMC reset..."); - - // Reset PMC. However, the bit used means the entire PMC must be reconfigured! - - e_rc = data.flushTo0(); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.setBit(12); if(e_rc){rc.setEcmdError(e_rc); return rc; } // RESET_ALL_PMC_REGISTERS - - rc=fapiPutScom(i_target, PMC_MODE_REG_0x00062000 , data); if(rc) return rc; - // This function is not yet verified - rc=pmc_reset_function(i_target); - - - } + fapi::ReturnCode rc; + uint32_t e_rc; + ecmdDataBufferBase data(64); + uint8_t attr_pm_spivid_frame_size; + uint8_t attr_pm_spivid_in_delay_frame1; + uint8_t attr_pm_spivid_in_delay_frame2; + uint8_t attr_pm_spivid_clock_polarity; + uint8_t attr_pm_spivid_clock_phase; + uint32_t attr_pm_spivid_clock_divider; + uint8_t attr_pm_spivid_port_enable = 7; + uint32_t attr_pm_spivid_interframe_delay_write_status_value; + uint32_t attr_pm_spivid_inter_retry_delay_value; + uint8_t attr_pm_spivid_crc_gen_enable; + uint8_t attr_pm_spivid_crc_check_enable; + uint8_t attr_pm_spivid_majority_vote_enable; + uint8_t attr_pm_spivid_max_retries; + uint8_t attr_pm_spivid_crc_polynomial_enables; + + + const uint8_t default_spivid_frame_size = 32; + const uint8_t default_spivid_in_delay_frame1 = 0; + const uint8_t default_spivid_in_delay_frame2 = 0; + const uint8_t default_spivid_clock_polarity = 0; + const uint8_t default_spivid_clock_phase = 0; + const uint32_t default_spivid_port_enable = 0x0; + const uint8_t default_spivid_crc_gen_enable = 1; + const uint8_t default_spivid_crc_check_enable = 0; + const uint8_t default_spivid_majority_vote_enable = 1; + const uint8_t default_spivid_max_retries = 5; + const uint8_t default_spivid_crc_polynomial_enables = 0xD5; + + uint32_t var_100ns_div_value = 0; + uint32_t proc_nest_frequency = 2400; + uint32_t attr_pm_interchip_frequency = 10; + uint32_t interchip_clock_divider = 0 ; + + do + { + + rc = FAPI_ATTR_GET(ATTR_FREQ_PB, NULL, proc_nest_frequency); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_FREQ_PB with rc = 0x%x", (uint32_t)rc); + break; + } + + // var_100ns_div_value = (( attr_proc_pss_init_nest_frequency * 1000000 * 100) /4000000000); + var_100ns_div_value = (( proc_nest_frequency ) /40); + interchip_clock_divider = ( proc_nest_frequency /(attr_pm_interchip_frequency*8)-1 ); + + //---------------------------------------------------------- + GETATTR_DEFAULT( ATTR_PM_SPIVID_FRAME_SIZE, + "ATTR_PM_SPIVID_FRAME_SIZE", + &i_target1, + attr_pm_spivid_frame_size, + default_spivid_frame_size ); + + //---------------------------------------------------------- + GETATTR_DEFAULT( ATTR_PM_SPIVID_IN_DELAY_FRAME1, + "ATTR_PM_SPIVID_IN_DELAY_FRAME1", + &i_target1, + attr_pm_spivid_in_delay_frame1, + default_spivid_in_delay_frame1 ); + + //---------------------------------------------------------- + GETATTR_DEFAULT( ATTR_PM_SPIVID_IN_DELAY_FRAME1, + "ATTR_PM_SPIVID_IN_DELAY_FRAME1", + &i_target1, + attr_pm_spivid_in_delay_frame2, + default_spivid_in_delay_frame2 ); + + //---------------------------------------------------------- + GETATTR_DEFAULT( ATTR_PM_SPIVID_CLOCK_POLARITY, + "ATTR_PM_SPIVID_CLOCK_POLARITY", + &i_target1, + attr_pm_spivid_clock_polarity, + default_spivid_clock_polarity ); + + //---------------------------------------------------------- + GETATTR_DEFAULT( ATTR_PM_SPIVID_CLOCK_PHASE, + "ATTR_PM_SPIVID_CLOCK_PHASE", + &i_target1, + attr_pm_spivid_clock_phase, + default_spivid_clock_phase ); + + //---------------------------------------------------------- + GETATTR_DEFAULT( ATTR_PM_SPIVID_CRC_GEN_ENABLE, + "ATTR_PM_SPIVID_CRC_GEN_ENABLE", + &i_target1, + attr_pm_spivid_crc_gen_enable, + default_spivid_crc_gen_enable ); + + //---------------------------------------------------------- + GETATTR_DEFAULT( ATTR_PM_SPIVID_CRC_CHECK_ENABLE, + "ATTR_PM_SPIVID_CRC_CHECK_ENABLE", + &i_target1, + attr_pm_spivid_crc_check_enable, + default_spivid_crc_check_enable ); + + //---------------------------------------------------------- + GETATTR_DEFAULT( ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE, + "ATTR_PM_SPIVID_CRC_CHECK_ENABLE", + &i_target1, + attr_pm_spivid_majority_vote_enable, + default_spivid_majority_vote_enable ); + + //---------------------------------------------------------- + GETATTR_DEFAULT( ATTR_PM_SPIVID_MAX_RETRIES, + "ATTR_PM_SPIVID_MAX_RETRIES", + &i_target1, + attr_pm_spivid_max_retries, + default_spivid_max_retries ); + + //---------------------------------------------------------- + GETATTR_DEFAULT( ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES, + "ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES", + &i_target1, + attr_pm_spivid_crc_polynomial_enables, + default_spivid_crc_polynomial_enables ); + + //---------------------------------------------------------- + GETATTR_DEFAULT( ATTR_PM_SPIVID_PORT_ENABLE, + "ATTR_PM_SPIVID_PORT_ENABLE", + &i_target1, + attr_pm_spivid_port_enable, + default_spivid_port_enable ); + + //---------------------------------------------------------- + GETATTR( ATTR_PM_SPIVID_CLOCK_DIVIDER, + "ATTR_PM_SPIVID_CLOCK_DIVIDER", + &i_target1, + attr_pm_spivid_clock_divider); + + //---------------------------------------------------------- + GETATTR( ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, + "ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE", + &i_target1, + attr_pm_spivid_interframe_delay_write_status_value); + + //---------------------------------------------------------- + GETATTR( ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, + "ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE", + &i_target1, + attr_pm_spivid_inter_retry_delay_value); + + FAPI_INF("PMC initialization..."); + + uint8_t o2s_frame_size = attr_pm_spivid_frame_size; + uint8_t o2s_in_delay1 = attr_pm_spivid_in_delay_frame1; + uint8_t o2s_in_delay2 = attr_pm_spivid_in_delay_frame2; + uint8_t o2s_clk_pol = attr_pm_spivid_clock_polarity; + uint8_t o2s_clk_pha = attr_pm_spivid_clock_phase; + uint8_t o2s_port_enable = attr_pm_spivid_port_enable; + uint32_t o2s_inter_frame_delay = attr_pm_spivid_interframe_delay_write_status_value; + uint8_t o2s_crc_gen_en = attr_pm_spivid_crc_gen_enable; + uint8_t o2s_crc_check_en = attr_pm_spivid_crc_check_enable; + uint8_t o2s_majority_vote_en = attr_pm_spivid_majority_vote_enable; + uint8_t o2s_max_retries = attr_pm_spivid_max_retries; + uint8_t o2s_crc_polynomial_enables = attr_pm_spivid_crc_polynomial_enables; + uint16_t o2s_clk_divider = attr_pm_spivid_clock_divider; + //spivid_freq = attr_pm_spivid_frequency; + uint8_t o2s_in_count2 = o2s_frame_size ; + uint8_t o2s_out_count2 = o2s_frame_size ; + uint8_t o2s_bridge_enable = 0x1 ; + uint8_t o2s_nr_of_frames = 2 ; + uint8_t o2s_in_count1 = o2s_frame_size ; + uint8_t o2s_out_count1 = o2s_frame_size ; + uint8_t hangpulse_predivider = 1; + uint8_t gpsa_timeout_value = 100; + uint8_t one=1; + uint8_t zero=0; + uint8_t dcm=0; + uint8_t is_master=0; + uint8_t is_slave=1; + + uint8_t is_simulation = 0; + uint8_t attr_dcm_installed_1 = 0; + uint64_t any_error = 0; + + rc = FAPI_ATTR_GET( ATTR_IS_SIMULATION, NULL, is_simulation); + if (rc) + { + FAPI_ERR("Failed to get attribute: ATTR_IS_SIMULATION."); + break ; + } + + if (is_simulation) + { + // Simulation value + gpsa_timeout_value = 100; + } + else + { + // Hardware + gpsa_timeout_value = 255; + } + + // Here to bypass feature attribute passing until these as moved into proc.pm.pmc.scom.initfile + o2s_bridge_enable = 0x1 ; + + e_rc = data.flushTo0(); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error flushing buffer"); + rc.setEcmdError(e_rc); + break; + } + + rc = fapiGetScom(i_target1, PMC_LFIR_0x01010840 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_LFIR_0x01010840) failed."); + break; + } + + any_error = data.getDoubleWord(0); + + if (any_error) + { + FAPI_ERR(" PMC_FIR has error(s) active. 0x%16llX ", data.getDoubleWord(0)); + //FAPI_SET_HWP_ERROR(rc, RC_PROCPM_FIR_ERROR); break; + //return rc ; + } + + // ****************************************************************** + // - set PMC_o2s_CTRL_REG0A (24b) + // ****************************************************************** + + rc = fapiGetScom(i_target1, PMC_O2S_CTRL_REG0A_0x00062050, data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG0A) failed."); + break; + } + + e_rc = data.insertFromRight(o2s_frame_size , 0,6); + e_rc |= data.insertFromRight(o2s_out_count1 , 6,6); + e_rc |= data.insertFromRight(o2s_in_delay1 ,12,6); + e_rc |= data.insertFromRight(o2s_in_count1 ,18,6); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_O2S_CTRL_REG0A on Master init"); + rc.setEcmdError(e_rc); + break; + } + + FAPI_INF(" PMC_O2S_CTRL_REG0A / PMC_SPIV_CTRL_REG0A Configuration"); + FAPI_INF(" frame size => %d ", o2s_frame_size); + FAPI_INF(" o2s_out_count1 => %d ", o2s_out_count1); + FAPI_INF(" o2s_in_delay1 => %d ", o2s_in_delay1); + FAPI_INF(" o2s_in_count1 => %d ", o2s_in_count1); + + rc = fapiPutScom(i_target1, PMC_O2S_CTRL_REG0A_0x00062050, data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG0A_0x00062050) failed."); + break; + } + + rc = fapiPutScom(i_target1, PMC_SPIV_CTRL_REG0A_0x00062040, data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_SPIV_CTRL_REG0A_0x00062040) failed."); + break; + } + + // ****************************************************************** + // - set PMC_O2S_CTRL_REG0B (24b) + // ****************************************************************** + + rc = fapiGetScom(i_target1, PMC_O2S_CTRL_REG0B_0x00062051, data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG0B) failed."); + break; + } + + e_rc = data.insertFromRight(o2s_out_count2,00,6); + e_rc |= data.insertFromRight(o2s_in_delay2 ,06,6); + e_rc |= data.insertFromRight(o2s_in_count2 ,12,6); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_O2S_CTRL_REG0B_0x00062051 on Master init"); + rc.setEcmdError(e_rc); + break; + } + + FAPI_INF(" PMC_O2S_CTRL_REG0B_ / PMC_SPIV_CTRL_REG0B Configuration"); + FAPI_INF(" o2s_out_count2 => %d ", o2s_out_count2); + FAPI_INF(" o2s_in_delay2 => %d ", o2s_in_delay2 ); + FAPI_INF(" o2s_in_count2 => %d ", o2s_in_count2 ); + + rc = fapiPutScom(i_target1, PMC_O2S_CTRL_REG0B_0x00062051, data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG0B_0x00062051) failed."); + break; + } + + rc = fapiPutScom(i_target1, PMC_SPIV_CTRL_REG0B_0x00062041, data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_SPIV_CTRL_REG0B_0x00062041) failed."); + break; + } + + // ****************************************************************** + // - set PMC_O2S_CTRL_REG1 + // ****************************************************************** + + rc = fapiGetScom(i_target1, PMC_O2S_CTRL_REG1_0x00062052, data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG1) failed."); + break; + } + + o2s_nr_of_frames--; + e_rc = data.insertFromRight(o2s_bridge_enable ,0 ,1); + e_rc |= data.insertFromRight(o2s_clk_pol ,2 ,1); + e_rc |= data.insertFromRight(o2s_clk_pha ,3 ,1); + e_rc |= data.insertFromRight(o2s_clk_divider ,4 ,10); + e_rc |= data.insertFromRight(o2s_nr_of_frames ,17,1); + e_rc |= data.insertFromRight(o2s_port_enable ,18,3); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_O2S_CTRL_REG1 on Master init"); + rc.setEcmdError(e_rc); + break; + } + + o2s_nr_of_frames++ ; + FAPI_INF(" PMC_O2S_CTRL_REG1 / PMC_SPIV_CTRL_REG1 "); + FAPI_INF(" o2s_bridge_enable => %d ", o2s_bridge_enable ); + FAPI_INF(" o2s_clk_pol => %d ", o2s_clk_pol ); + FAPI_INF(" o2s_clk_pha => %d ", o2s_clk_pha ); + FAPI_INF(" o2s_clk_divider => 0x%x", o2s_clk_divider); + FAPI_INF(" o2s_nr_of_frames => %d ", o2s_nr_of_frames); + FAPI_INF(" o2s_port_enable => %d ", o2s_port_enable); + + + rc = fapiPutScom(i_target1, PMC_O2S_CTRL_REG1_0x00062052, data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG1_0x00062052) failed."); + break; + } + + rc = fapiPutScom(i_target1, PMC_SPIV_CTRL_REG1_0x00062042, data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_SPIV_CTRL_REG1_0x00062042) failed."); + break; + } + + // ****************************************************************** + // - set PMC_O2S_CTRL_REG2 + // ****************************************************************** + + rc = fapiGetScom(i_target1, PMC_O2S_CTRL_REG2_0x00062053, data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG2) failed."); + break; + } + + e_rc = data.insertFromRight( o2s_inter_frame_delay ,0,17); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_O2S_CTRL_REG2 on Master init"); + rc.setEcmdError(e_rc); + break; + } + + FAPI_INF(" PMC_O2S_CTRL_REG2_ / PMC_SPIV_CTRL_REG2Configuration"); + FAPI_INF(" o2s_inter_frame_delay => %d ", o2s_inter_frame_delay ); + + rc = fapiPutScom(i_target1, PMC_O2S_CTRL_REG2_0x00062053, data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG2_0x00062053) failed."); + break; + } + + rc = fapiPutScom(i_target1, PMC_SPIV_CTRL_REG2_0x00062043, data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_SPIV_CTRL_REG2_0x00062043) failed."); + break; + } + + // ****************************************************************** + // - set PMC_SPIV_CTRL_REG3 + // ****************************************************************** + + rc = fapiGetScom(i_target1, PMC_SPIV_CTRL_REG3_0x00062044, data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_SPIV_CTRL_REG3) failed."); + break; + } + + e_rc = data.insertFromRight( attr_pm_spivid_inter_retry_delay_value ,0,17); + e_rc |= data.insertFromRight( var_100ns_div_value , 17 , 6); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_SPIV_CTRL_REG3 on Master init"); + rc.setEcmdError(e_rc); + break; + } + + FAPI_INF(" PMC_SPIV_CTRL_REG3 Configuration "); + FAPI_INF(" spivid_inter_retry_delay_value => %d ", attr_pm_spivid_inter_retry_delay_value ); + FAPI_INF(" 100ns_div_value => %d ", var_100ns_div_value); + + rc = fapiPutScom(i_target1, PMC_SPIV_CTRL_REG3_0x00062044, data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_SPIV_CTRL_REG3_0x00062044) failed."); + break; + } + + // ****************************************************************** + // - set PMC_O2S_CTRL_REG4 + // ****************************************************************** + + rc = fapiGetScom(i_target1, PMC_O2S_CTRL_REG4_0x00062055, data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG4) failed."); + break; + } + + e_rc = data.insertFromRight( o2s_crc_gen_en ,0,1); + e_rc |= data.insertFromRight( o2s_crc_check_en ,1,1); + e_rc |= data.insertFromRight( o2s_majority_vote_en ,2,1); + e_rc |= data.insertFromRight( o2s_max_retries ,3,5); + e_rc |= data.insertFromRight( o2s_crc_polynomial_enables,8,8); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_O2S_CTRL_REG on Master init"); + rc.setEcmdError(e_rc); + break; + } + + FAPI_INF(" PMC_O2S_CTRL_REG4 Configuration"); + FAPI_INF(" o2s_crc_gen_en => %d ", o2s_crc_gen_en ); + FAPI_INF(" o2s_crc_check_en => %d ", o2s_crc_check_en ); + FAPI_INF(" o2s_majority_vote_en => %d ", o2s_majority_vote_en ); + FAPI_INF(" o2s_max_retries => %d ", o2s_max_retries ); + FAPI_INF(" o2s_crc_polynomial_enab => 0x%x ", o2s_crc_polynomial_enables ); + + + rc = fapiPutScom(i_target1, PMC_O2S_CTRL_REG4_0x00062055, data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG4_0x00062055) failed."); + break; + } + + // ****************************************************************** + // Program crc polynomials + // ****************************************************************** + + rc = fapiGetScom(i_target1, PMC_SPIV_CTRL_REG4_0x00062045, data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_SPIV_CTRL_REG4) failed."); + break; + } + + e_rc = data.insertFromRight( o2s_crc_gen_en ,0,1); + e_rc |= data.insertFromRight( o2s_crc_check_en ,1,1); + e_rc |= data.insertFromRight( o2s_majority_vote_en ,2,1); + e_rc |= data.insertFromRight( o2s_max_retries ,3,5); + e_rc |= data.insertFromRight( o2s_crc_polynomial_enables,8,8); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_SPIV_CTRL_REG4 on Master init"); + rc.setEcmdError(e_rc); + break; + } + + FAPI_INF(" PMC_SPIV_CTRL_REG4 Configuration"); + FAPI_INF(" spiv_crc_gen_en => %d ", o2s_crc_gen_en ); + FAPI_INF(" spiv_crc_check_en => %d ", o2s_crc_check_en ); + FAPI_INF(" spiv_majority_vote_en => %d ", o2s_majority_vote_en ); + FAPI_INF(" spiv_max_retries => %d ", o2s_max_retries ); + FAPI_INF(" spiv_crc_polynomial_enab => 0x%x ", o2s_crc_polynomial_enables ); + + rc = fapiPutScom(i_target1, PMC_SPIV_CTRL_REG4_0x00062045, data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_SPIV_CTRL_REG4_0x00062045) failed."); + break; + } + + // ****************************************************************** + // - write PMC_PARAMETER_REG0 + // ****************************************************************** + rc = fapiGetScom(i_target1, PMC_PARAMETER_REG0_0x00062005, data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_PARAMETER_REG0_0x00062005) failed."); + break; + } + + e_rc = data.insertFromRight(hangpulse_predivider ,15,6); + e_rc |= data.insertFromRight(gpsa_timeout_value ,21,8); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_PARAMETER_REG0_0x00062005 on Master init"); + rc.setEcmdError(e_rc); + break; + } + + FAPI_INF(" PMC_PARAMETER_REG0 Configuration"); + FAPI_INF(" hangpulse_predivider => 0x%x ", hangpulse_predivider); + FAPI_INF(" gpsa_timeout_value => 0x%x ", gpsa_timeout_value ); + + rc = fapiPutScom(i_target1, PMC_PARAMETER_REG0_0x00062005, data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_PARAMETER_REG0_0x00062005) failed."); + break; + } + + // ****************************************************************** + // - write PMC_MODE_REG + // ****************************************************************** + rc = fapiGetScom(i_target1, PMC_MODE_REG_0x00062000, data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + e_rc = data.insertFromRight(zero , 0 ,1); //HW_PSTATE_MODE + e_rc |= data.insertFromRight(zero , 1 ,1); //FW_PSTATE_AUCTION_MODE + e_rc |= data.insertFromRight(one , 2 ,1); //FW_PSTATE_MODE + e_rc |= data.insertFromRight(zero , 13 ,1); //SAFE_MODE_WITHOUT_SPIVID + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_SPIV_CTRL_REG4 on Master init"); + rc.setEcmdError(e_rc); + break; + } + + FAPI_INF(" PMC_MODE_REG Configuration"); + FAPI_INF(" SAFE_MODE_WITHOUT_SPIVID => %d ", zero); + + rc = fapiPutScom(i_target1, PMC_MODE_REG_0x00062000, data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + // ************************************************************* + // REGISTER WRITES FOR DCMS + // ************************************************************* + + rc = FAPI_ATTR_GET(ATTR_PROC_DCM_INSTALLED, &i_target1, attr_dcm_installed_1); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_DCM_INSTALLED with rc = 0x%x", (uint32_t)rc); + break; + } + FAPI_INF (" value read from the attribute ATTR_DCM_INSTALLED in init function = 0x%x", attr_dcm_installed_1 ); + + if (attr_dcm_installed_1 == 1) + { + dcm = 1; + + rc = fapiGetScom(i_target1, DEVICE_ID_REG_0x000F000F, data ); + if (rc) + { + FAPI_ERR("fapiGetScom(DEVICE_ID_REG_0x000F000F) failed."); + break; + } + + is_master = data.isBitClear(39) ; + is_slave = not is_master ; + } + else + { + dcm = 0 ; + } + + if (dcm == 1) + { + if (is_master) + { + FAPI_INF ("**** Setting up DCM Master ****"); + } + else + { + FAPI_INF ("**** Setting up DCM Slave ****"); + } + // **************************************************************** + // - write PMC_MODE_REG + // **************************************************************** + rc = fapiGetScom(i_target1, PMC_MODE_REG_0x00062000, data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + + e_rc = data.insertFromRight( one , 6 ,1); //ENABLE_INTERCHIP_INTERFACE + e_rc |= data.insertFromRight( is_master, 7 ,1); //INTERCHIP_MODE + e_rc |= data.insertFromRight( is_master, 8 ,1); //ENABLE_INTERCHIP_PSTATE_IN_HAPS + e_rc |= data.insertFromRight( is_slave ,13 ,1); //SAFEMODE_WITHOUT_SPIVID + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_MODE_REG_0x00062000 on Master DCM init"); + rc.setEcmdError(e_rc); + break; + } + + FAPI_INF(" PMC_MODE_REG Configuration"); + FAPI_DBG(" ENABLE_INTERCHIP_INTERFACE => %d ", one ); + FAPI_DBG(" INTERCHIP_MODE => %d ", is_master ); + FAPI_DBG(" ENABLE_INTERCHIP_PSTATE_IN_HAPS => %d ", is_master ); + FAPI_DBG(" SAFE_MODE_WITHOUT_SPIVID => %d ", is_slave ); + + rc = fapiPutScom(i_target1, PMC_MODE_REG_0x00062000, data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); + break; + } + FAPI_DBG(" before exiting pmc_init PMC_MODE_REG_0x00062000 =>0x%16llx", data.getDoubleWord(0)); + + // ****************************************************************** + // - set PMC_O2S_CTRL_REG1 + // ****************************************************************** + + rc = fapiGetScom(i_target1, PMC_O2S_CTRL_REG1_0x00062052, data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG1) failed."); + break; + } + + // Force the port enables on the slave or else the SPIVID on the slave + // chip will hang + if (is_slave) + { + o2s_port_enable = 4 ; + e_rc = data.insertFromRight(o2s_port_enable ,18,3); + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up forced slave port enable on Slave DCM init"); + rc.setEcmdError(e_rc); + break; + } + FAPI_INF("Forcing port enable on slave to avoid SPIVID controller hang"); + FAPI_INF(" PMC O2S CTRL_REG_1 / PMC_SPIV_CTRL_REG1 Configuration"); + FAPI_INF(" spiv/o2s_port_enable => %d ", o2s_port_enable ); + } + + // \todo this should be looked at for removal to avoid future problems + rc = fapiPutScom(i_target1, PMC_O2S_CTRL_REG1_0x00062052, data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG1_0x00062052) failed."); + break; + } + + rc = fapiPutScom(i_target1, PMC_SPIV_CTRL_REG1_0x00062042, data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_SPIV_CTRL_REG1_0x00062042) failed."); + break; + } + + // ****************************************************************** + // - write PMC_INTCHP_CTRL_REG1 + // ****************************************************************** + rc = fapiGetScom(i_target1, PMC_INTCHP_CTRL_REG1_0x00062010, data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_INTCHP_CTRL_REG1_0x00062010) failed."); + break; + } + + e_rc = data.insertFromRight(one , 0 ,1); //INTERCHIP_GA_FSM_ENABLE + e_rc |= data.insertFromRight(zero, 7 ,1); //INTERCHIP_CPHA + e_rc |= data.insertFromRight( interchip_clock_divider, 4 ,10); //INTERCHIP_CLOCK_DIVIDER + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_INTCHP_CTRL_REG1_0x00062010 on Master DCM init"); + rc.setEcmdError(e_rc); + break; + } + + FAPI_INF(" PMC_INTCHP_CTRL_REG1 Configuration "); + FAPI_DBG(" INTERCHIP_GA_FSM_ENABLE => %d ", one ); + FAPI_DBG(" INTERCHIP_CPHA => %d ", zero ); + FAPI_DBG(" INTERCHIP_CLOCK_DIVIDER => 0x%x ", interchip_clock_divider ); + + rc = fapiPutScom(i_target1, PMC_INTCHP_CTRL_REG1_0x00062010, data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_INTCHP_CTRL_REG1_0x00062010) failed."); + break; + } + FAPI_DBG(" before exiting pmc_init PMC_INTCHP_CTRL_REG1_0x00062010 =>0x%16llx", data.getDoubleWord(0)); + + // ****************************************************************** + // - write PMC_INTCHP_CTRL_REG4 + // ****************************************************************** + rc = fapiGetScom(i_target1, PMC_INTCHP_CTRL_REG4_0x00062012, data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_INTCHP_CTRL_REG4_0x00062012) failed."); + break; + } + e_rc = data.insertFromRight(one , 0 ,1); //INTERCHIP_ECC_GEN_EN + e_rc |= data.insertFromRight(one , 1 ,1); //INTERCHIP_ECC_CHECK_EN + e_rc |= data.insertFromRight(one , 2 ,1); //INTERCHIP_MSG_RCV_OVERFLOW_CHECK_EN + e_rc |= data.insertFromRight(one , 3 ,1); //INTERCHIP_ECC_UE_BLOCK_EN + if (e_rc) + { + FAPI_ERR("ecmdDataBufferBase error setting up PMC_INTCHP_CTRL_REG1_0x00062010 on Master DCM init"); + rc.setEcmdError(e_rc); + break; + } + + FAPI_INF(" PMC_INTCHP_CTRL_REG4 Configuration "); + FAPI_DBG(" INTERCHIP_ECC_GEN_EN => %d ", one ); + FAPI_DBG(" INTERCHIP_ECC_CHECK_EN => %d ", one ); + FAPI_DBG(" INTERCHIP_MSG_RCV_OVERFLOW_CHECK_EN => %d ", one ); + FAPI_DBG(" INTERCHIP_ECC_UE_BLOCK_EN => %d ", one ); + + rc = fapiPutScom(i_target1, PMC_INTCHP_CTRL_REG4_0x00062012, data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_INTCHP_CTRL_REG4_0x00062012) failed."); + break; + } + FAPI_DBG(" before exiting pmc_init PMC_INTCHP_CTRL_REG4_0x00062012 =>0x%16llx", data.getDoubleWord(0)); + } // dcm + + } while(0); - /// ------------------------------- - /// Unsupported Mode - else { - FAPI_ERR("Unknown mode passed to p8_pmc_init. Mode %x ", mode); - uint32_t & MODE = mode; - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMC_CODE_BAD_MODE); - } - return rc; + FAPI_INF ("Done with the init"); + FAPI_INF ("Done with the init"); + return rc; } - - //#ifdef FAPIECMD -} //end extern C -// #endif - - - - - - - - - - - -// BackUPS - // ---------------------------------------------------------------------- -// Constant definitions -// ---------------------------------------------------------------------- - - - -// PIB Space Addresses - - -/* - CONST_UINT64_T( PMC_SPIV_CTRL_REG0B_0x00072041 , ULL(0x00072041) ); - CONST_UINT64_T( PMC_SPIV_CTRL_REG1_0x00072042 , ULL(0x00072042) ); - CONST_UINT64_T( PMC_SPIV_CTRL_REG2_0x00072043 , ULL(0x00072043) ); - CONST_UINT64_T( PMC_SPIV_CTRL_REG3_0x00072044 , ULL(0x00072044) ); - CONST_UINT64_T( PMC_SPIV_CTRL_REG4_0x00072045 , ULL(0x00072045) ); - CONST_UINT64_T( PMC_SPIV_STATUS_REG_0x00072046 , ULL(0x00072046) ); - CONST_UINT64_T( PMC_SPIV_COMMAND_REG_0x00072047 , ULL(0x00072047) ); - - - CONST_UINT64_T( PMC_O2S_CTRL_REG0A_0x00062050 , ULL(0x00062050) ); - CONST_UINT64_T( PMC_O2S_CTRL_REG0B_0x00062051 ,ULL(0x00062051) ); - CONST_UINT64_T( PMC_O2S_CTRL_REG1_0x00062052 ,ULL(0x00062052) ); - CONST_UINT64_T( PMC_O2S_CTRL_REG2_0x00062053 ,ULL(0x00062053) ); - CONST_UINT64_T( PMC_O2S_CTRL_REG4_0x00062055 ,ULL(0x00062055) ); - CONST_UINT64_T( PMC_O2S_STATUS_REG_0x00062056 ,ULL(0x00062056) ); - CONST_UINT64_T( PMC_O2S_COMMAND_REG_0x00062057 ,ULL(0x00062057) ); - CONST_UINT64_T( PMC_O2S_WDATA_REG_0x00062058 ,ULL(0x00062058) ); - CONST_UINT64_T( PMC_O2S_RDATA_REG_0x00062059 ,ULL(0x00062059) ); - -// OCI Space Addresses -CONST_UINT32_T( OCI_PMC_MODE_REG_0x40010000 , ULL(0x40010000) ); -*/ - -// ---------------------------------------------------------------------- -// Global variables -// ---------------------------------------------------------------------- - -// std::string PROCEDURE = "p8_pmc_init"; // procedure name - //std::string REVISION = "$Revision: 1.6 $"; // procedure CVS revision - -//ReturnCode BAD_RETURN_CODE = 0x12000001; // procedure return code on fail, not used by ECMD -//uint32_t SIM_CYCLE_POLL_DELAY = 200000; // simulation cycle delay between status register polls -//bool VERBOSE = true; // enable verbose mode debug comments -//uint32_t MAX_POLL_ATTEMPTS = 5; // maximum number of status poll attempts to make before giving up - - - - // Global Variables - /// From generated pm_attributes_plat.H - -/* - uint8_t attr_pm_pstate_stepsize; - uint8_t attr_pm_external_vrm_stepdelay_range; - uint8_t attr_pm_external_vrm_stepdelay_value; - uint8_t attr_pm_pmc_hangpulse_divider; - uint8_t attr_pm_pvsafe_pstate; - uint8_t attr_pm_pstate_undervolting_minimum; - uint8_t attr_pm_pstate_undervolting_maximum; -*/ - - - /// From generated pm_attributes_plat.H - - - - - - - - +/** + * p8_pmc_init + * + * @param[in] i_target1 Primary Chip target: Murano - chip0; Venice - chip + * @param[in] i_target2 Secondary Chip target: Murano - chip1; Venice - NULL + * @param[in] mode (PM_INIT , PM_CONFIG, PM_RESET) + * + * @retval ECMD_SUCCESS + * @retval ERROR defined in xml + */ +fapi::ReturnCode +p8_pmc_init(const fapi::Target& i_target1, const fapi::Target& i_target2, uint32_t mode) +{ + fapi::ReturnCode rc; + + do + { + + // ------------------------------------------------ + // CONFIG mode + // ------------------------------------------------ + if (mode == PM_CONFIG) + { + rc = pmc_config_spivid_settings(i_target1); + if (rc) + { + FAPI_ERR("Error from pmc_config_spivid_settings for target1"); + break; + } + + if ( i_target2.getType() != TARGET_TYPE_NONE ) + { + rc = pmc_config_spivid_settings(i_target2); + if (rc) + { + FAPI_ERR("Error from pmc_config_spivid_settings for target2"); + break; + } + } + } + + // ------------------------------------------------ + // INIT mode + // ------------------------------------------------ + else if (mode == PM_INIT) + { + FAPI_INF("Executing p8_pmc_init for Target %s ...", i_target1.toEcmdString()); + rc = pmc_init_function(i_target1); + // FAPI_INF("Reacged here"); + if (rc) + { + FAPI_ERR("Error from pmc_init_function for target1"); + break; + } + + + + if ( i_target2.getType() != TARGET_TYPE_NONE ) + { + FAPI_INF("Executing p8_pmc_init for target %s ...", i_target2.toEcmdString()); + rc = pmc_init_function(i_target2); + if (rc) + { + FAPI_ERR("Error from pmc_init_function for target2"); + break; + } + } + + + } + + /// ------------------------------- + /// Reset: perform reset of PMC + /// ------------------------------- + else if (mode == PM_RESET) + { + rc = pmc_reset_function(i_target1 , i_target2); + if (rc) + { + FAPI_ERR("Error from pmc_reset_function"); + break; + } + } + + /// ------------------------------- + /// Unsupported Mode + /// ------------------------------- + else + { + FAPI_ERR("Unknown mode passed to p8_pmc_init. Mode %x ", mode); + uint32_t & MODE = mode; + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMC_CODE_BAD_MODE); + } + + } while(0); + // FAPI_INF("im here "); + return rc; + +} // end p8_pmc_init + +} //end extern C /* - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_FRAME_SIZE, l_pTarget, attr_pm_spivid_frame_size); if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_IN_DELAY_FRAME1, l_pTarget, attr_pm_spivid_in_delay_frame1); if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_IN_DELAY_FRAME2, l_pTarget, attr_pm_spivid_in_delay_frame2); if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_FRAME_DELAY, l_pTarget, attr_pm_spivid_inter_frame_delay); if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_FRAME_DELAY_WRITE_STATUS, l_pTarget, attr_pm_spivid_inter_frame_delay_write_status); if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_RETRY_DELAY, l_pTarget, attr_pm_spivid_inter_retry_delay); if (rc) return rc; -*/ - - - // Here to test feature attribute passing util these as moved into proc.pm.pmc.scom.initfile - /* - rc = FAPI_ATTR_GET(ATTR_SPIVID_CLOCK_POLARITY, NULL, o2s_clk_pol); if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_SPIVID_CLOCK_PHASE, NULL, o2s_clk_pha); if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_SPIVID_PORT_ENABLE, NULL, o2s_port_enable); if (rc) return rc; - rc = FAPI_ATTR_GET(SPIVID_INTER_FRAME_DELAY_WRITE_STATUS, NULL, o2s_inter_frame_delay); if (rc) return rc; - - - // rc = FAPI_ATTR_GET(SPIVID_INTER_RETRY_DELAY, NULL, l_uint64_1); if (rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_SPIVID_CRC_GEN_ENABLE, NULL, o2s_crc_gen_en); if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_SPIVID_CRC_CHECK_ENABLE, NULL, o2s_crc_check_en); if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_SPIVID_MAJORITY_VOTE_ENABLE, NULL, o2s_majority_vote_en); if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_SPIVID_MAX_RETRIES, NULL, o2s_max_retries); if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_SPIVID_CRC_POLYNOMIAL_ENABLES, NULL, o2s_crc_polynomial_enables); if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_SPIVID_IN_DELAY_FRAME1, NULL, o2s_in_delay1); if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_SPIVID_IN_DELAY_FRAME2, NULL, o2s_in_delay2); if (rc) return rc; - */ - - - - -// uint8_t attr_pm_spivid_frame_size_set = 32; -// uint8_t attr_pm_spivid_in_delay_frame1_set = 0; -// uint8_t attr_pm_spivid_in_delay_frame2_set = 0 ; -// uint8_t attr_pm_spivid_clock_polarity_set = 0; -// uint8_t attr_pm_spivid_clock_phase_set = 0 ; -// // uint32_t attr_pm_spivid_clock_divider_set = 0x1D ; -// // uint8_t attr_pm_spivid_port_enable_set = 3 ; -// uint32_t attr_pm_spivid_interframe_delay_write_status_set = 0 ; -// uint32_t attr_pm_spivid_interframe_delay_write_status_value_set = 12; -// uint32_t attr_pm_spivid_inter_retry_delay_value_set = 20 ; -// uint32_t attr_pm_spivid_inter_retry_delay_set = 1; -// uint8_t attr_pm_spivid_crc_gen_enable_set = 1 ; -// uint8_t attr_pm_spivid_crc_check_enable_set = 1 ; -// uint8_t attr_pm_spivid_majority_vote_enable_set = 1; -// uint8_t attr_pm_spivid_max_retries_set = 5 ; -// uint8_t attr_pm_spivid_crc_polynomial_enables_set = 0xD5; -// // uint32_t attr_pm_spivid_frequency_set = 20; -// // uint32_t attr_p8_nest_frequency_set = 3000; - - - - - -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_FRAME_SIZE, &l_pTarget, attr_pm_spivid_frame_size_set); -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_FRAME_SIZE with rc = 0x%x", (uint32_t)rc); return rc; } - - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_IN_DELAY_FRAME1, &l_pTarget, attr_pm_spivid_in_delay_frame1_set); -// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_IN_DELAY_FRAME1 with rc = 0x%x", (uint32_t)rc); return rc; } - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_IN_DELAY_FRAME2, &l_pTarget, attr_pm_spivid_in_delay_frame2_set); -// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_IN_DELAY_FRAME2 with rc = 0x%x", (uint32_t)rc); return rc; } - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CLOCK_POLARITY, &l_pTarget, attr_pm_spivid_clock_polarity_set); -// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_CLOCK_POLARITY with rc = 0x%x", (uint32_t)rc); return rc; } - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CLOCK_PHASE, &l_pTarget, attr_pm_spivid_clock_phase_set); -// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_CLOCK_PHASE with rc = 0x%x", (uint32_t)rc); return rc; } - - - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS, &l_pTarget, attr_pm_spivid_interframe_delay_write_status_set); -// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS with rc = 0x%x", (uint32_t)rc); return rc; } - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, &l_pTarget, attr_pm_spivid_interframe_delay_write_status_value_set); -// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, &l_pTarget, attr_pm_spivid_inter_retry_delay_value_set); -// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_INTER_RETRY_DELAY, &l_pTarget, attr_pm_spivid_inter_retry_delay_set); -// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_INTER_RETRY_DELAY with rc = 0x%x", (uint32_t)rc); return rc; } - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CRC_GEN_ENABLE, &l_pTarget, attr_pm_spivid_crc_gen_enable_set); -// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_CRC_GEN_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CRC_CHECK_ENABLE, &l_pTarget, attr_pm_spivid_crc_check_enable_set); -// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_CRC_CHECK_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE, &l_pTarget, attr_pm_spivid_majority_vote_enable_set); -// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_MAX_RETRIES, &l_pTarget, attr_pm_spivid_max_retries_set); -// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_MAX_RETRIES with rc = 0x%x", (uint32_t)rc); return rc; } - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES, &l_pTarget, attr_pm_spivid_crc_polynomial_enables_set); -// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES with rc = 0x%x", (uint32_t)rc); return rc; } - - -// // rc = FAPI_ATTR_SET(ATTR_FREQ_PB, &l_pTarget, attr_p8_nest_frequency_set); if (rc) return rc; -// // rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_FREQUENCY, &l_pTarget, attr_pm_spivid_frequency_set); if (rc) return rc; - - -// //---------------------------------------------------------- -// // rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CLOCK_DIVIDER, &l_pTarget, attr_pm_spivid_clock_divider_set); -// // if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_CLOCK_DIVIDER with rc = 0x%x", (uint32_t)rc); return rc; } +*************** Do not edit this area *************** +This section is automatically updated by CVS when you check in this file. +Be sure to create CVS comments when you commit so that they can be included here. +$Log: p8_pmc_init.C,v $ +Revision 1.30 2013/04/30 11:20:22 pchatnah +fixing memory fault issue for scm -// //---------------------------------------------------------- -// // rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_PORT_ENABLE, &l_pTarget, attr_pm_spivid_port_enable_set); -// // if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_PORT_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } +Revision 1.29 2013/04/17 13:11:28 pchatnah +fixing some more SCM issues +Revision 1.28 2013/04/16 12:00:26 pchatnah +fixing Daniels failures on hardware +Revision 1.27 2013/04/12 01:25:02 stillgs +Update for DCM initialization and reset function per hardware testing +Revision 1.25 2013/04/06 02:14:03 pchatnah + restructuring +Revision 1.24 2013/04/04 12:43:49 pchatnah +fixing sm_without_spivid +Revision 1.23 2013/04/02 14:17:55 pchatnah +fixing spivid_enable for slave +Revision 1.22 2013/04/01 04:11:54 stillgs +Output formating changes only to remove extraneous log content +Revision 1.21 2013/03/28 14:42:02 pchatnah +adding FIR check +Revision 1.20 2013/03/28 14:29:04 pchatnah +adding FIR check - /// //---------------------------------------------------------- - /// rc = FAPI_ATTR_SET(ATTR_PM_PSTATE_STEPSIZE, &l_pTarget, attr_pm_pstate_stepsize_set); - /// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_PSTATE_STEPSIZE with rc = 0x%x", (uint32_t)rc); break; } +Revision 1.19 2013/03/15 12:25:57 pchatnah +fixing no_of_ports - /// //---------------------------------------------------------- - /// rc = FAPI_ATTR_SET(ATTR_PM_EXTERNAL_VRM_STEPDELAY_RANGE, &l_pTarget, attr_pm_external_vrm_stepdelay_range_set); - /// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_EXTERNAL_VRM_STEPDELAY_RANGE with rc = 0x%x", (uint32_t)rc); break; } +Revision 1.18 2013/03/04 16:15:35 pchatnah +fising more issues for prep_for_reset - /// //---------------------------------------------------------- - /// rc = FAPI_ATTR_SET(ATTR_PM_EXTERNAL_VRM_STEPDELAY_VALUE, &l_pTarget, attr_pm_external_vrm_stepdelay_value_set); - /// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_EXTERNAL_VRM_STEPDELAY_VALUE with rc = 0x%x", (uint32_t)rc); break; } +Revision 1.17 2013/02/25 19:27:01 pchatnah +fising compilation issues - /// //---------------------------------------------------------- - /// rc = FAPI_ATTR_SET(ATTR_PM_PMC_HANGPULSE_DIVIDER, &l_pTarget, attr_pm_pmc_hangpulse_divider_set); - /// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_PMC_HANGPULSE_DIVIDER with rc = 0x%x", (uint32_t)rc); break; } +Revision 1.16 2013/02/21 08:58:37 pchatnah +fixing 100ns calculation - /// //---------------------------------------------------------- - /// rc = FAPI_ATTR_SET(ATTR_PM_PVSAFE_PSTATE, &l_pTarget, attr_pm_pvsafe_pstate_set); - /// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_PVSAFE_PSTATE with rc = 0x%x", (uint32_t)rc); break; } +Revision 1.15 2013/02/11 15:44:16 pchatnah +fixing pstate - /// //---------------------------------------------------------- - /// rc = FAPI_ATTR_SET(ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM, &l_pTarget, attr_pm_pstate_undervolting_minimum_set); - /// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM with rc = 0x%x", (uint32_t)rc); break; } +Revision 1.14 2013/02/07 18:44:49 pchatnah +adding PM_LFIR reset also into it - /// //---------------------------------------------------------- - /// rc = FAPI_ATTR_SET(ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM, &l_pTarget, attr_pm_pstate_undervolting_maximum_set); - /// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM with rc = 0x%x", (uint32_t)rc); break; } +Revision 1.13 2013/01/24 11:58:12 pchatnah +adding log inside the file - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_OCC_HEARTBEAT_TIME, &l_pTarget, attr_pm_occ_heartbeat_time_set); -// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_OCC_HEARTBEAT_TIME with rc = 0x%x", (uint32_t)rc); break; } - -// ------------------------------------------------------------------------------------------------------------------------------------------------ - -// Enable the get functions - - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_FRAME_SIZE, &l_pTarget, attr_pm_spivid_frame_size); -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_FRAME_SIZE with rc = 0x%x", (uint32_t)rc); return rc; } -// else { FAPI_INF (" value read from the attribute attr_pm_spivid_frame_size = 0x%x", attr_pm_spivid_frame_size );} - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_IN_DELAY_FRAME1, &l_pTarget, attr_pm_spivid_in_delay_frame1); - -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_IN_DELAY_FRAME1 with rc = 0x%x", (uint32_t)rc); return rc; } -// else { FAPI_INF (" value read from the attribute attr_pm_spivid_in_delay_frame1 = 0x%x", attr_pm_spivid_in_delay_frame1);} - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_IN_DELAY_FRAME2, &l_pTarget, attr_pm_spivid_in_delay_frame2); - -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_IN_DELAY_FRAME2 with rc = 0x%x", (uint32_t)rc); return rc; } -// else { FAPI_INF (" value read from the attribute attr_pm_spivid_in_delay_frame2 = 0x%x", attr_pm_spivid_in_delay_frame2);} - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_POLARITY, &l_pTarget, attr_pm_spivid_clock_polarity); - -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CLOCK_POLARITY with rc = 0x%x", (uint32_t)rc); return rc; } -// else { FAPI_INF (" value read from the attribute attr_pm_spivid_clock_polarity = 0x%x", attr_pm_spivid_clock_polarity);} - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_PHASE, &l_pTarget, attr_pm_spivid_clock_phase); - -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CLOCK_PHASE with rc = 0x%x", (uint32_t)rc); return rc; } -// else { FAPI_INF (" value read from the attribute attr_pm_spivid_clock_phase = 0x%x", attr_pm_spivid_clock_phase);} - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS, &l_pTarget, attr_pm_spivid_interframe_delay_write_status); - -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS with rc = 0x%x", (uint32_t)rc); return rc; } -// else { FAPI_INF (" value read from the attribute attr_pm_spivid_interframe_delay_write_status = 0x%x", attr_pm_spivid_interframe_delay_write_status);} - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, &l_pTarget, attr_pm_spivid_interframe_delay_write_status_value); - -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } -// else { FAPI_INF (" value read from the attribute attr_pm_spivid_interframe_delay_write_status_value = 0x%x", attr_pm_spivid_interframe_delay_write_status_value);} - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, &l_pTarget, attr_pm_spivid_inter_retry_delay_value); - -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } -// else { FAPI_INF (" value read from the attribute attr_pm_spivid_inter_retry_delay_value = 0x%x", attr_pm_spivid_inter_retry_delay_value);} - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_RETRY_DELAY, &l_pTarget, attr_pm_spivid_inter_retry_delay); - -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTER_RETRY_DELAY with rc = 0x%x", (uint32_t)rc); return rc; } -// else { FAPI_INF (" value read from the attribute attr_pm_spivid_inter_retry_delay = 0x%x", attr_pm_spivid_inter_retry_delay);} - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_GEN_ENABLE, &l_pTarget, attr_pm_spivid_crc_gen_enable); - -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CRC_GEN_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } -// else { FAPI_INF (" value read from the attribute attr_pm_spivid_crc_gen_enable = 0x%x", attr_pm_spivid_crc_gen_enable);} - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_CHECK_ENABLE, &l_pTarget, attr_pm_spivid_crc_check_enable); - -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CRC_CHECK_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } -// else { FAPI_INF (" value read from the attribute attr_pm_spivid_crc_check_enable = 0x%x", attr_pm_spivid_crc_check_enable);} - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE, &l_pTarget, attr_pm_spivid_majority_vote_enable); - -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } -// else { FAPI_INF (" value read from the attribute attr_pm_spivid_majority_vote_enable = 0x%x", attr_pm_spivid_majority_vote_enable);} - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_MAX_RETRIES, &l_pTarget, attr_pm_spivid_max_retries); - -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_MAX_RETRIES with rc = 0x%x", (uint32_t)rc); return rc; } -// else { FAPI_INF (" value read from the attribute attr_pm_spivid_max_retries = 0x%x", attr_pm_spivid_max_retries);} - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES, &l_pTarget, attr_pm_spivid_crc_polynomial_enables); - -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES with rc = 0x%x", (uint32_t)rc); return rc; } -// else { FAPI_INF (" value read from the attribute attr_pm_spivid_crc_polynomial_enables = 0x%x", attr_pm_spivid_crc_polynomial_enables);} - - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_DIVIDER, &l_pTarget, attr_pm_spivid_clock_divider); - -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CLOCK_DIVIDER with rc = 0x%x", (uint32_t)rc); return rc; } -// else { FAPI_INF (" value read from the attribute attr_pm_spivid_clock_divider = 0x%x", attr_pm_spivid_clock_divider);} - - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_PORT_ENABLE, &l_pTarget, attr_pm_spivid_port_enable); - -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_PORT_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } -// else { FAPI_INF (" value read from the attribute attr_pm_spivid_port_enable = 0x%x", attr_pm_spivid_port_enable);} - - -// //---------------------------------------------------------- - - - - - - - //-------------------------------------------------------------------- - //- >>> SCOM.INITFILE elements - //-------------------------------------------------------------------- +*/ diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.H index 20a1b14dc..724030484 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.H +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.H @@ -20,23 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ +// $Id: p8_pmc_init.H,v 1.7 2013/04/12 01:25:04 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pmc_init.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -44,32 +29,30 @@ //------------------------------------------------------------------------------ // *! OWNER NAME: Greg Stilll Email: stillgs@us.ibm.com // *! + // *! General Description: // *! This procedure is intializes / resets / configures the O2S access bridge // *! Target : Processor chip //------------------------------------------------------------------------------ // -/// \param[in] i_target Chip target +/// \param[in] i_target1 Primary chip target of the module +/// \param[in] i_target2 Secondary chip target (applicable to DCMs) /// \param[in] mode // function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*p8_pmc_init_FP_t) (const fapi::Target&, uint32_t mode); +typedef fapi::ReturnCode (*p8_pmc_init_FP_t) ( const fapi::Target& , + const fapi::Target&, + uint32_t mode); extern "C" { -// enum p8_PM_FLOW_MODE { -// PM_CONFIG = 0x1, -// PM_RESET = 0x2, -// PM_INIT = 0x3, -// PM_SETUP = 0x4, -// PM_SETUP_PIB = 0x5, -// PM_SETUP_ALL = 0x6 -// }; - -fapi::ReturnCode p8_pmc_init(const fapi::Target& i_target, uint32_t mode); +fapi::ReturnCode +p8_pmc_init(const fapi::Target& i_target1, + const fapi::Target& i_target2, + uint32_t mode); } diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_poregpe_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_poregpe_init.C index c072347ee..b83468c9a 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_poregpe_init.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_poregpe_init.C @@ -20,25 +20,8 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_poregpe_init.C,v 1.2 2012/10/10 20:23:05 stillgs Exp $ -// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_poregpe_init.C,v $ +// $Id: p8_poregpe_init.C,v 1.3 2013/04/01 04:11:56 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_poregpe_init.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -118,13 +101,13 @@ p8_poregpe_init(const Target& i_target, uint32_t mode, uint32_t engine) do { - FAPI_INF("Executing p8_poregpe_init in mode %x for engine %x....\n", + FAPI_INF("Executing p8_poregpe_init in mode %x for engine %x....", mode, engine); if (!(engine == GPE0 || engine == GPE1 || engine == GPEALL) ) { - FAPI_ERR("Unknown engine passed to p8_poregpe_init. Engine %x ....\n", + FAPI_ERR("Unknown engine passed to p8_poregpe_init. Engine %x ....", engine); FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_GPE_BAD_ENGINE); break; @@ -135,8 +118,8 @@ p8_poregpe_init(const Target& i_target, uint32_t mode, uint32_t engine) /// Feature Attributes that are applied during Initalization if (mode == PM_CONFIG) { - FAPI_INF("PORE-GPE configuration...\n"); - FAPI_INF("---> None is defined...done by OCC firmware\n"); + FAPI_INF("PORE-GPE configuration..."); + FAPI_INF("---> None is defined...done by OCC firmware"); } /// ------------------------------- @@ -144,8 +127,8 @@ p8_poregpe_init(const Target& i_target, uint32_t mode, uint32_t engine) /// the GPEs using necessary Platform or Feature attributes. else if (mode == PM_INIT) { - FAPI_INF("PORE-GPE initialization...\n"); - FAPI_INF("---> None is defined...done by OCC firmware\n"); + FAPI_INF("PORE-GPE initialization..."); + FAPI_INF("---> None is defined...done by OCC firmware"); } /// ------------------------------- @@ -171,7 +154,7 @@ p8_poregpe_init(const Target& i_target, uint32_t mode, uint32_t engine) else { - FAPI_ERR("Unknown mode passed to p8_poregpe_init. Mode %x ....\n", mode); + FAPI_ERR("Unknown mode passed to p8_poregpe_init. Mode %x ....", mode); FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_GPE_CODE_BAD_MODE); } } while(0); @@ -199,7 +182,7 @@ poregpe_reset(const Target& i_target, const uint32_t engine) - FAPI_INF("PORE-GPE reset...Engine: %x\n", engine); + FAPI_INF("PORE-GPE reset...Engine: %x", engine); do { @@ -302,7 +285,7 @@ poregpe_reset(const Target& i_target, const uint32_t engine) if(!wait_state_detected) { - FAPI_ERR("GPE%x reset failed \n", engine); + FAPI_ERR("GPE%x reset failed ", engine); FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_GPE0_RESET_TIMEOUT); } diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pss_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pss_init.C index 14d76fe38..991242c5d 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pss_init.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pss_init.C @@ -20,24 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ -// $Id: p8_pss_init.C,v 1.2 2012/08/24 10:18:50 pchatnah Exp $ +// $Id: p8_pss_init.C,v 1.4 2013/04/05 12:25:34 pchatnah Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pss_init.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -175,7 +158,7 @@ pss_config_spi_settings(const Target& l_pTarget) rc = FAPI_ATTR_GET(ATTR_FREQ_PB, NULL , attr_proc_pss_init_nest_frequency); if (rc) return rc; - //TODO RTC: 68461 - refresh procedures - hacked target in the line below to be NULL + ///TODO RTC: 71328 - hack to use system target rc = FAPI_ATTR_GET(ATTR_PM_SPIPSS_FREQUENCY, NULL,attr_pm_pss_init_spipss_frequency); if (rc) return rc ; @@ -208,7 +191,7 @@ p8_pss_init(Target &i_target, uint32_t mode) uint8_t attr_pm_apss_chip_select=1 ; uint8_t attr_pm_spipss_frame_size ; // uint8_t attr_pm_spipss_out_count ; - // uint8_t attr_pm_spipss_in_delay ; + uint8_t attr_pm_spipss_in_delay ; // uint8_t attr_pm_spipss_in_count ; uint8_t attr_pm_spipss_clock_polarity ; uint8_t attr_pm_spipss_clock_phase ; @@ -260,10 +243,10 @@ p8_pss_init(Target &i_target, uint32_t mode) else { FAPI_INF (" value read from the attribute attr_pm_spipss_frame_size = 0x%x", attr_pm_spipss_frame_size );} //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIPSS_IN_DELAY, &i_target, attr_pm_spipss_in_delay); + rc = FAPI_ATTR_GET(ATTR_PM_SPIPSS_IN_DELAY, &i_target, attr_pm_spipss_in_delay); -// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIPSS_IN_DELAY with rc = 0x%x", (uint32_t)rc); return rc; } -// else { FAPI_INF (" value read from the attribute attr_pm_spipss_in_delay_frame1 = 0x%x", attr_pm_spipss_in_delay);} + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIPSS_IN_DELAY with rc = 0x%x", (uint32_t)rc); return rc; } + else { FAPI_INF (" value read from the attribute attr_pm_spipss_in_delay_frame1 = 0x%x", attr_pm_spipss_in_delay);} //---------------------------------------------------------- rc = FAPI_ATTR_GET(ATTR_PM_SPIPSS_CLOCK_POLARITY, &i_target, attr_pm_spipss_clock_polarity); @@ -304,7 +287,7 @@ p8_pss_init(Target &i_target, uint32_t mode) else { FAPI_INF (" value read from the attribute attr_pm_spipss_clock_divider = 0x%x", attr_pm_spipss_clock_divider);} - + rc = FAPI_ATTR_GET(ATTR_FREQ_PB, NULL, attr_proc_pss_init_nest_frequency); if (rc) return rc; @@ -348,16 +331,17 @@ p8_pss_init(Target &i_target, uint32_t mode) uint8_t hwctrl_frame_size = attr_pm_spipss_frame_size ; // uint8_t hwctrl_out_count = attr_pm_spipss_out_count ; -// uint8_t hwctrl_in_delay = attr_pm_spipss_in_delay ; + uint8_t hwctrl_in_delay = attr_pm_spipss_in_delay ; // uint8_t hwctrl_in_count = attr_pm_spipss_in_count ; uint8_t hwctrl_clk_pol = attr_pm_spipss_clock_polarity ; uint8_t hwctrl_clk_pha = attr_pm_spipss_clock_phase ; uint32_t hwctrl_clk_divider = attr_pm_spipss_clock_divider ; uint32_t hwctrl_inter_frame_delay = attr_pm_spipss_inter_frame_delay ; uint8_t hwctrl_device = attr_pm_apss_chip_select; - uint8_t nest_freq = attr_proc_pss_init_nest_frequency ; - uint32_t spipss_100ns_div_value ; - spipss_100ns_div_value = 4 / ( attr_proc_pss_init_nest_frequency*1000000) * (100 /1000000000); + uint32_t nest_freq = attr_proc_pss_init_nest_frequency ; + uint32_t spipss_100ns_div_value ; + spipss_100ns_div_value = (( attr_proc_pss_init_nest_frequency ) /40); + // spipss_100ns_div_value = (( attr_proc_pss_init_nest_frequency * 1000000 * 100) /4000000000); @@ -382,6 +366,7 @@ p8_pss_init(Target &i_target, uint32_t mode) // data.flushTo0(); // data.setWord(1, 0x41000100); e_rc=data.insertFromRight(hwctrl_frame_size,0,6); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc=data.insertFromRight(hwctrl_in_delay,12,6); if (e_rc) { rc.setEcmdError(e_rc); return rc; } // FAPI_INF(" -----------------------------------------------------"); FAPI_INF(" SPIPSS ADC CTRL_REG_0 Configuration "); @@ -417,7 +402,7 @@ p8_pss_init(Target &i_target, uint32_t mode) // modify_data here - uint8_t hwctrl_fsm_enable = 0x0 ; + uint8_t hwctrl_fsm_enable = 0x1 ; uint8_t hwctrl_nr_of_frames = 0x10 ; @@ -542,7 +527,7 @@ p8_pss_init(Target &i_target, uint32_t mode) uint32_t p2s_inter_frame_delay = 0x0; // uint8_t p2s_in_count1; // uint8_t p2s_out_count1; -// uint8_t p2s_in_delay1; + uint8_t p2s_in_delay; // uint8_t p2s_in_count2; // uint8_t p2s_out_count2; // uint8_t p2s_in_delay2; @@ -580,7 +565,7 @@ p8_pss_init(Target &i_target, uint32_t mode) p2s_frame_size = attr_pm_spipss_frame_size ; // p2s_out_count = attr_pm_spipss_out_count ; - // p2s_in_delay = attr_pm_spipss_in_delay ; + p2s_in_delay = attr_pm_spipss_in_delay ; // p2s_in_count = attr_pm_spipss_in_count ; p2s_clk_pol = attr_pm_spipss_clock_polarity ; p2s_clk_pha = attr_pm_spipss_clock_phase ; @@ -607,12 +592,13 @@ p8_pss_init(Target &i_target, uint32_t mode) // e_rc=data.flushTo0(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } // e_rc=data.setWord(1, 0x41000100); if (e_rc) { rc.setEcmdError(e_rc); return rc; } e_rc=data.insertFromRight(p2s_frame_size,0,6); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc=data.insertFromRight(p2s_in_delay,12,6); if (e_rc) { rc.setEcmdError(e_rc); return rc; } // FAPI_INF(" -----------------------------------------------------"); FAPI_INF(" SPIPSS P2S CTRL_REG_0 Configuration "); // FAPI_INF(" -----------------------------------------------------"); FAPI_INF(" frame size => %d ", p2s_frame_size); - FAPI_INF(" " ); + FAPI_INF(" p2s_in_delay => %d ", p2s_in_delay ); FAPI_INF(" " ); // FAPI_INF(" -----------------------------------------------------"); @@ -642,7 +628,7 @@ p8_pss_init(Target &i_target, uint32_t mode) // modify_data here - uint8_t p2s_fsm_enable = 0x0 ; + uint8_t p2s_fsm_enable = 0x1 ; uint8_t p2s_nr_of_frames = 0x10 ; // e_rc=data.flushTo0(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } @@ -757,8 +743,8 @@ p8_pss_init(Target &i_target, uint32_t mode) // FAPI_INF(" -----------------------------------------------------"); FAPI_INF(" SPIPSS_100NS_REG is set the value "); // FAPI_INF(" -----------------------------------------------------"); - FAPI_INF(" spipss_100ns_div_value => %d ", spipss_100ns_div_value ); - FAPI_INF(" " ); + FAPI_INF(" spipss_100ns_div_value_hi => %d ", spipss_100ns_div_value ); + FAPI_INF(" nest_freq => %d ", nest_freq ); FAPI_INF(" " ); // FAPI_INF(" -----------------------------------------------------"); diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pss_init.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pss_init.H index 9e5394804..b4c37bad1 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pss_init.H +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pss_init.H @@ -20,29 +20,14 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -/* begin_generated_IBM_copyright_prolog */ -/* */ -/* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ -/* --------------------------------------------------------------- */ -/* IBM Confidential */ -/* */ -/* Licensed Internal Code Source Materials */ -/* */ -/* (C)Copyright IBM Corp. 2014, 2014 */ -/* */ -/* The Source code for this program is not published or otherwise */ -/* divested of its trade secrets, irrespective of what has been */ -/* deposited with the U.S. Copyright Office. */ -/* -------------------------------------------------------------- */ -/* */ -/* end_generated_IBM_copyright_prolog */ +// $Id: p8_pss_init.H,v 1.4 2012/11/27 18:11:55 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pss_init.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //------------------------------------------------------------------------------ -// *! OWNER NAME: Greg Stilll Email: stillgs@us.ibm.com +// *! OWNER NAME: Greg Still Email: stillgs@us.ibm.com // *! // *! General Description: Calls the function p8_pss_init.C // *! Initializes the PSS macro , resets it and configures the required @@ -57,11 +42,8 @@ // function pointer typedef definition for HWP call support typedef fapi::ReturnCode (*p8_pss_init_FP_t) (const fapi::Target&, uint32_t); - extern "C" { fapi::ReturnCode p8_pss_init(const fapi::Target& i_target, uint32_t mode); } - - |