SW289468: INITPROC: FSP&Hostboot - Changes for Naples

CMVC-Coreq: 947204
CQ:SW289468
Change-Id: I5d139ba3a6b003d05e8841e27f2414859010ea4a
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/14867
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/14910
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

5 files changed, 188 insertions, 77 deletions

diff --git a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C
index a86dc56db..f6c033582 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -1011,6 +1011,9 @@ errlHndl_t computeProcPcieConfigAttrs(
         i_pProcChipTarget ?
             i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>() : 0);
 
+    // TODO:
+    // RTC 109249: Update comments for 40 lanes in Naples 
+
     // Currently there are two IOP config tables, one for procs with 24 usable
     // PCIE lanes and one for proces with 32 usable PCIE lanes.  In general, the
     // code accumulates the current configuration of the IOPs from the MRW and
@@ -1270,37 +1273,41 @@ errlHndl_t computeProcPcieConfigAttrs(
         }
 
         // Pick the appropriate IOP configuration table
-        if(   i_pProcChipTarget->getAttr<TARGETING::ATTR_IOP_LANES_PER_PROC>()
+        if(   i_pProcChipTarget->getAttr<TARGETING::ATTR_PROC_PCIE_NUM_LANES>()
            == IOP_LANES_PER_PROC_32X)
         {
             pLaneConfigTableBegin = x32_laneConfigTable;
             pLaneConfigTableEnd = x32_end;
         }
         else if(   i_pProcChipTarget->getAttr<
-                       TARGETING::ATTR_IOP_LANES_PER_PROC>()
+                       TARGETING::ATTR_PROC_PCIE_NUM_LANES>()
                 == IOP_LANES_PER_PROC_24X)
         {
             pLaneConfigTableBegin = x24_laneConfigTable;
             pLaneConfigTableEnd = x24_end;
         }
+
+        // TODO:
+        // RTC 109249: Support Naples with 40 lanes
+
         else
         {
             TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
                 ERR_MRK "computeProcPcieConfigAttrs> "
-                "Code bug! Unsupported ATTR_IOP_LANES_PER_PROC attribute for "
+                "Code bug! Unsupported ATTR_PROC_PCIE_NUM_LANES attribute for "
                 "processor with HUID of 0x%08X.  Expected 24 or 32, but read "
                 "value of %d.",
                 i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>(),
                 i_pProcChipTarget->getAttr<
-                    TARGETING::ATTR_IOP_LANES_PER_PROC>());
+                    TARGETING::ATTR_PROC_PCIE_NUM_LANES>());
 
             /*@
              * @errortype
              * @moduleid         ISTEP_COMPUTE_PCIE_CONFIG_ATTRS
              * @reasoncode       ISTEP_INVALID_ATTR_VALUE
              * @userdata1[0:31]  Target's HUID
-             * @userdata2[32:63] ATTR_IOP_LANES_PER_PROC attribute value
-             * @devdesc          Illegal ATTR_IOP_LANES_PER_PROC attribute read
+             * @userdata2[32:63] ATTR_PROC_PCIE_NUM_LANES attribute value
+             * @devdesc          Illegal ATTR_PROC_PCIE_NUM_LANES attribute read
              *                   from a processor chip target.
              * @custdesc         A problem isolated to firmware or firmware
              *                   customization occurred during the IPL of the
@@ -1313,7 +1320,7 @@ errlHndl_t computeProcPcieConfigAttrs(
                 TWO_UINT32_TO_UINT64(
                     i_pProcChipTarget->getAttr<TARGETING::ATTR_HUID>(),
                     i_pProcChipTarget->getAttr<
-                        TARGETING::ATTR_IOP_LANES_PER_PROC>()),
+                        TARGETING::ATTR_PROC_PCIE_NUM_LANES>()),
                 0,
                 true);
             ERRORLOG::ErrlUserDetailsTarget(i_pProcChipTarget).addToLog(pError);
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C
index d49b010f6..b0b1cd34e 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_chiplet_scominit.C,v 1.24 2014/10/17 16:41:10 jmcgill Exp $
+// $Id: proc_chiplet_scominit.C,v 1.26 2014/11/20 18:00:37 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_chiplet_scominit.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -71,6 +71,7 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target)
     fapi::Target master_mcs;
     uint8_t enable_xbus_resonant_clocking = 0x0;
     uint8_t i2c_slave_address = 0x0;
+    uint8_t dual_capp_present = 0x0;
 
     ecmdDataBufferBase data(64);
     ecmdDataBufferBase cfam_data(32);
@@ -249,6 +250,30 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target)
                     break;
                 }
 
+                // get dual CAPP presence attribute
+                FAPI_DBG("proc_chiplet_scominit: Querying dual CAPP feature attribute");
+                rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_DUAL_CAPP_PRESENT,
+                                   &i_target,
+                                   dual_capp_present);
+                if (!rc.ok())
+                {
+                    FAPI_ERR("proc_chiplet_scominit: Error querying ATTR_CHIP_EC_FEATURE_DUAL_CAPP_PRESENT");
+                    break;
+                }
+                
+                if (dual_capp_present != 0)
+                {
+                    rc = fapiPutScom(i_target,
+                                     CAPP1_APC_MASTER_LCO_TARGET_0x020131A1,
+                                     data);
+                    if (!rc.ok())
+                    {
+                        FAPI_ERR("proc_chiplet_scominit: fapiPutScom error (CAPP1_APC_MASTER_LCO_TARGET_0x020131A1) on %s",
+                                 i_target.toEcmdString());
+                        break;
+                    }
+                }
+
                 // execute AS SCOM initfile
                 FAPI_INF("proc_chiplet_scominit: Executing %s on %s",
                          PROC_CHIPLET_SCOMINIT_AS_IF, i_target.toEcmdString());
@@ -346,7 +371,6 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target)
                 break;
             }
 
-
             if (enable_xbus_resonant_clocking)
             {
                 FAPI_DBG("proc_chiplet_scominit: Enabling XBUS resonant clocking");
@@ -414,7 +438,6 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target)
                 break;
             }
 
-
             // determine set of functional MCS chiplets
             rc = fapiGetChildChiplets(i_target,
                                       fapi::TARGET_TYPE_MCS_CHIPLET,
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C
index f2a8183d8..ee4080bbf 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_pcie_scominit.C,v 1.10 2014/08/05 15:15:13 kahnevan Exp $
+// $Id: proc_pcie_scominit.C,v 1.11 2014/11/18 17:38:50 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_scominit.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -54,7 +54,9 @@ extern "C" {
 //             set master IOP lane configuration and IOP swap bits via PCIe GP4
 //             set PHB iovalids via PCIe GP0
 //             remove IOP logic from reset via PCIe GP4
-// parameters: i_target => processor chip target
+// parameters: i_target  => processor chip target
+//             i_num_iop => number of IOP units
+//             i_num_phb => number of PHB units
 // returns: FAPI_RC_SUCCESS if all actions are successful,
 //          RC_PROC_PCIE_SCOMINIT_IOP_CONFIG_ATTR_ERR if invalid IOP lane
 //            configuration attribute value is presented,
@@ -63,7 +65,9 @@ extern "C" {
 //          else error
 //------------------------------------------------------------------------------
 fapi::ReturnCode proc_pcie_scominit_iop_init(
-    const fapi::Target & i_target)
+    const fapi::Target & i_target,
+    uint8_t i_num_iop,
+    uint8_t i_num_phb)
 {
     fapi::ReturnCode rc;
     uint32_t rc_ecmd = 0;
@@ -118,7 +122,7 @@ fapi::ReturnCode proc_pcie_scominit_iop_init(
             FAPI_ERR("proc_pcie_scominit_iop_init: Error from FAPI_ATTR_GET (ATTR_PROC_PCIE_IOP_SWAP)");
             break;
         }
-        for (size_t i = 0; (i < PROC_PCIE_SCOMINIT_NUM_IOP) && rc.ok(); i++)
+        for (size_t i = 0; (i < i_num_iop) && rc.ok(); i++)
         {
             FAPI_DBG("proc_pcie_scominit_iop_init: ATTR_PROC_PCIE_IOP_SWAP[%zd]= %02X",
                      i, iop_swap[i]);
@@ -145,7 +149,7 @@ fapi::ReturnCode proc_pcie_scominit_iop_init(
             (PCIE_GP4_IOP_LANE_CFG_END_BIT-
              PCIE_GP4_IOP_LANE_CFG_START_BIT+1));
 
-        for (size_t i = 0; (i < PROC_PCIE_SCOMINIT_NUM_IOP) && !rc_ecmd; i++)
+        for (size_t i = 0; (i < i_num_iop) && !rc_ecmd; i++)
         {
             rc_ecmd |= gp4_data.insertFromRight(
                 iop_swap[i],
@@ -191,14 +195,14 @@ fapi::ReturnCode proc_pcie_scominit_iop_init(
             break;
         }
 
-        for (size_t i = 0; (i < PROC_PCIE_SCOMINIT_NUM_PHB); i++)
+        for (size_t i = 0; (i < i_num_phb); i++)
         {
             phb_active[i] = ((phb_active_mask >> (7-i)) & 0x1)?(true):(false);
             refclock_active[i] = ((refclock_active_mask >> (7-i)) & 0x1)?(true):(false);
         }
 
         // set PCIe GP0 mask for PHB iovalid/refclock enable
-        for (size_t i = 0; (i < PROC_PCIE_SCOMINIT_NUM_PHB) && !rc_ecmd; i++)
+        for (size_t i = 0; (i < i_num_phb) && !rc_ecmd; i++)
         {
             rc_ecmd |= gp0_data.writeBit(
                 PCIE_GP0_PHB_IOVALID_BIT[i],
@@ -226,7 +230,7 @@ fapi::ReturnCode proc_pcie_scominit_iop_init(
 
         // set PCIe GP4 mask for IOP reset
         rc_ecmd |= gp4_data.flushTo0();
-        for (size_t i = 0; (i < PROC_PCIE_SCOMINIT_NUM_IOP) && !rc_ecmd; i++)
+        for (size_t i = 0; (i < i_num_iop) && !rc_ecmd; i++)
         {
             rc_ecmd |= gp4_data.setBit(
                 PCIE_GP4_IOP_RESET_BIT[i]);
@@ -319,12 +323,14 @@ fapi::ReturnCode proc_pcie_scominit_iop_config(
 //------------------------------------------------------------------------------
 // function: mark IOP programming complete (executed after all IOP
 //           customization is complete)
-// parameters: i_target => processor chip target
+// parameters: i_target  => processor chip target
+//             i_num_iop => number of IOP units
 // returns: FAPI_RC_SUCCESS if program complete is successful for all IOPs,
 //          else error
 //------------------------------------------------------------------------------
 fapi::ReturnCode proc_pcie_scominit_iop_complete(
-    const fapi::Target & i_target)
+    const fapi::Target & i_target,
+    uint8_t i_num_iop)
 {
     fapi::ReturnCode rc;
     uint32_t rc_ecmd = 0;
@@ -347,7 +353,7 @@ fapi::ReturnCode proc_pcie_scominit_iop_complete(
         }
 
         // set IOP program complete
-        for (size_t i = 0; i < PROC_PCIE_SCOMINIT_NUM_IOP; i++)
+        for (size_t i = 0; i < i_num_iop; i++)
         {
             rc = fapiPutScomUnderMask(i_target,
                                       PROC_PCIE_SCOMINIT_PLL_GLOBAL_CONTROL2[i],
@@ -366,7 +372,7 @@ fapi::ReturnCode proc_pcie_scominit_iop_complete(
         }
 
         // configure IOP FIR
-        for (size_t i = 0; i < PROC_PCIE_SCOMINIT_NUM_IOP; i++)
+        for (size_t i = 0; i < i_num_iop; i++)
         {
             rc_ecmd |= data.flushTo0();
             if (rc_ecmd)
@@ -438,6 +444,8 @@ fapi::ReturnCode proc_pcie_scominit(
 {
     fapi::ReturnCode rc;
     uint8_t pcie_enabled;
+    uint8_t num_phb;
+    uint8_t num_iop;
 
     // mark HWP entry
     FAPI_INF("proc_pcie_scominit: Start");
@@ -463,11 +471,30 @@ fapi::ReturnCode proc_pcie_scominit(
             break;
         }
 
-        // initialize/configure/finalize IOP programming (only if partial good
+        // initialize/configure/finalize PHB & IOP programming (only if partial good
         // attribute is set)
         if (pcie_enabled == fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE)
         {
-            rc = proc_pcie_scominit_iop_init(i_target);
+            // determine PHB/IOP configuration
+            rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_NUM_PHB,
+                               &i_target,
+                               num_phb);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_pcie_scominit: Error from FAPI_ATTR_GET (ATTR_PROC_PCIE_NUM_PHB)");
+                break;
+            }
+
+            rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_NUM_IOP,
+                               &i_target,
+                               num_iop);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_pcie_scominit: Error from FAPI_ATTR_GET (ATTR_PROC_PCIE_NUM_IOP)");
+                break;
+            }
+
+            rc = proc_pcie_scominit_iop_init(i_target, num_iop, num_phb);
             if (!rc.ok())
             {
                 FAPI_ERR("proc_pcie_scominit: Error from proc_pcie_scominit_iop_init");
@@ -481,7 +508,7 @@ fapi::ReturnCode proc_pcie_scominit(
                 break;
             }
 
-            rc = proc_pcie_scominit_iop_complete(i_target);
+            rc = proc_pcie_scominit_iop_complete(i_target, num_iop);
             if (!rc.ok())
             {
                 FAPI_ERR("proc_pcie_scominit: Error from proc_pcie_scominit_iop_complete");
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H
index f7d2f13c5..59797ffa1 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_pcie_scominit.H,v 1.6 2013/10/28 03:57:13 jmcgill Exp $
+// $Id: proc_pcie_scominit.H,v 1.7 2014/11/18 17:38:50 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_scominit.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -61,41 +61,46 @@
 const char * const PROC_PCIE_SCOMINIT_PHASE1_IF = "p8.pe.phase1.scom.if";
 
 // PCIe physical constants
-const uint8_t PROC_PCIE_SCOMINIT_NUM_IOP = 2;
-const uint8_t PROC_PCIE_SCOMINIT_NUM_PHB = 3;
+const uint8_t PROC_PCIE_SCOMINIT_NUM_IOP = 3;
+const uint8_t PROC_PCIE_SCOMINIT_NUM_PHB = 4;
 
 // PCIe GP0 register field/bit definitions
 const uint32_t PCIE_GP0_PHB_IOVALID_BIT[PROC_PCIE_SCOMINIT_NUM_PHB] =
 {
     48,
     49,
-    50
+    50,
+    51
 };
 
 const uint32_t PCIE_GP0_PHB_REFCLOCK_DRIVE_EN_BIT[PROC_PCIE_SCOMINIT_NUM_PHB] =
 {
     52,
     53,
-    54
+    54,
+    55
 };
 
 // PCIe GP4 register field/bit definitions
 const uint32_t PCIE_GP4_IOP_RESET_BIT[PROC_PCIE_SCOMINIT_NUM_IOP] =
 {
     37,
-    38
+    38,
+    39
 };
 const uint32_t PCIE_GP4_IOP_LANE_CFG_START_BIT = 41;
 const uint32_t PCIE_GP4_IOP_LANE_CFG_END_BIT = 44;
 const uint32_t PCIE_GP4_IOP_SWAP_START_BIT[PROC_PCIE_SCOMINIT_NUM_IOP] =
 {
     47,
-    53
+    53,
+    50
 };
 const uint32_t PCIE_GP4_IOP_SWAP_END_BIT[PROC_PCIE_SCOMINIT_NUM_IOP] =
 {
     49,
-    55
+    55,
+    52
 };
 
 // Murano/Venice support lane configurations bewtween 0x0 & 0xC,
@@ -108,7 +113,8 @@ const uint8_t PCIE_GP4_IOP_SWAP_MAX = 0x7;
 const uint64_t PROC_PCIE_SCOMINIT_PLL_GLOBAL_CONTROL2[PROC_PCIE_SCOMINIT_NUM_IOP] =
 {
     PCIE_IOP0_PLL_GLOBAL_CONTROL2_0x8000080A0901143F,
-    PCIE_IOP1_PLL_GLOBAL_CONTROL2_0x8000080A0901187F
+    PCIE_IOP1_PLL_GLOBAL_CONTROL2_0x8000080A0901187F,
+    PCIE_IOP2_PLL_GLOBAL_CONTROL2_0x8000080A09011C7F
 };
 const uint32_t PLL_GLOBAL_CONTROL2_PROG_COMPLETE_BIT = 50;
 
@@ -116,19 +122,22 @@ const uint32_t PLL_GLOBAL_CONTROL2_PROG_COMPLETE_BIT = 50;
 const uint32_t PROC_PCIE_SCOMINIT_PLL_FIR[PROC_PCIE_SCOMINIT_NUM_IOP] =
 {
     PCIE_IOP0_PLL_FIR_0x09011400,
-    PCIE_IOP1_PLL_FIR_0x09011840
+    PCIE_IOP1_PLL_FIR_0x09011840,
+    PCIE_IOP2_PLL_FIR_0x09011C40
 };
 
 const uint32_t PROC_PCIE_SCOMINIT_PLL_FIR_WOF[PROC_PCIE_SCOMINIT_NUM_IOP] =
 {
     PCIE_IOP0_PLL_FIR_WOF_0x09011408,
-    PCIE_IOP1_PLL_FIR_WOF_0x09011848
+    PCIE_IOP1_PLL_FIR_WOF_0x09011848,
+    PCIE_IOP2_PLL_FIR_WOF_0x09011C48
 };
 
 const uint32_t PROC_PCIE_SCOMINIT_PLL_FIR_MASK[PROC_PCIE_SCOMINIT_NUM_IOP] =
 {
     PCIE_IOP0_PLL_FIR_MASK_0x09011403,
-    PCIE_IOP1_PLL_FIR_MASK_0x09011843
+    PCIE_IOP1_PLL_FIR_MASK_0x09011843,
+    PCIE_IOP2_PLL_FIR_MASK_0x09011C43
 };
 
 const uint64_t PCIE_PLL_FIR_MASK_VAL = 0x0080000000000000ULL;
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml
index d4582c7d4..7efcf7449 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml
@@ -5,7 +5,9 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- COPYRIGHT International Business Machines Corp. 2012,2014              -->
+<!-- Contributors Listed Below - COPYRIGHT 2012,2015                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
 <!--                                                                        -->
 <!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
 <!-- you may not use this file except in compliance with the License.       -->
@@ -20,11 +22,54 @@
 <!-- permissions and limitations under the License.                         -->
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
-<!-- $Id: proc_pcie_scominit_attributes.xml,v 1.6 2013/12/09 21:52:08 jmcgill Exp $ -->
+<!-- $Id: proc_pcie_scominit_attributes.xml,v 1.7 2014/11/18 17:46:06 jmcgill Exp $ -->
 <!-- proc_pcie_scominit_attributes.xml -->
 <attributes>
   <!-- ********************************************************************* -->
   <attribute>
+    <id>ATTR_PROC_PCIE_NUM_PHB</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      creator: platform
+        Number of PCIe PHB units present on target
+        Murano/Venice: 3
+        Naples: 4
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_PCIE_NUM_IOP</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      creator: platform
+        Number of PCIe IOP units present on target
+        Murano/Venice: 2
+        Naples: 3
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_PCIE_NUM_LANES</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      creator: platform
+        Number of PCIe I/O lanes supported by target
+        Murano: 24
+        Venice: 32
+        Naples: 40
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
     <id>ATTR_PROC_PCIE_IOP_CONFIG</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>PCIE IOP lane configuration
@@ -46,10 +91,10 @@
       consumer: proc_pcie_scominit
       firmware notes:
         Encoded PCIE IOP swap configuration
-        Array index: IOP number (0:1)
+        Array index: IOP number (0:2)
     </description>
     <valueType>uint8</valueType>
-    <array>2</array>
+    <array>3</array>
     <platInit/>
     <persistRuntime/>
   </attribute>
@@ -62,7 +107,7 @@
       consumer: proc_pcie_scominit
       firmware notes:
         Bit mask defining set of active/valid PHBs
-        bit0=PHB0, bit1=PHB1, bit2=PHB2
+        bit0=PHB0, bit1=PHB1, bit2=PHB2, bit3=PHB3
     </description>
     <valueType>uint8</valueType>
     <platInit/>
@@ -77,7 +122,7 @@
       consumer: proc_pcie_scominit
       firmware notes:
         Bit mask defining state of refclock drive enables
-        bit0=PCI0, bit1=PCI1, bit2=PCI2
+        bit0=PCI0, bit1=PCI1, bit2=PCI2, bit3=PCI3
     </description>
     <valueType>uint8</valueType>
     <platInit/>
@@ -93,10 +138,10 @@
       firmware notes:
         PCIe Gen3 PLL Control Register 0.
         ATUNE/CPISEL.
-        Array index: IOP number(0:1)
+        Array index: IOP number(0:2)
     </description>
     <valueType>uint32</valueType>
-    <array>2</array>
+    <array>3</array>
     <platInit/>
   </attribute>
   <!-- ********************************************************************* -->
@@ -109,10 +154,10 @@
       notes:
         PCIe Gen2/Gen1 PLL Control Register 0.
         ATUNE/CPISEL.
-        Array index: IOP number (0:1)
+        Array index: IOP number (0:2)
     </description>
     <valueType>uint32</valueType>
-    <array>2</array>
+    <array>3</array>
     <platInit/>
   </attribute>
   <!-- ********************************************************************* -->
@@ -125,10 +170,10 @@
       notes:
         PCIe PLL Global Control Register 0.
         REFISRC/REFISINK.
-        Array index: IOP number (0:1)
+        Array index: IOP number (0:2)
     </description>
     <valueType>uint32</valueType>
-    <array>2</array>
+    <array>3</array>
     <platInit/>
   </attribute>
   <!-- ********************************************************************* -->
@@ -141,10 +186,10 @@
       notes:
         PCIe PLL Global Control Register 1.
 	ENBGDOCPSRC/ENBGDOCAMP/REFVREG.
-        Array index: IOP number (0:1)
+        Array index: IOP number (0:2)
     </description>
     <valueType>uint32</valueType>
-    <array>2</array>
+    <array>3</array>
     <platInit/>
   </attribute>
   <!-- ********************************************************************* -->
@@ -158,10 +203,10 @@
         PCIe PCS Control Register 0.
         BITLOCKTIME/ADDDREMDELTA_810_B/STARTUPDELTA_810_B/ADDDREMDELTA_810_A/
         STARTUPDELTA_A/RXREJECTHANDLING/EQCOMLETERESPONSE.
-        Array index: IOP number (0:1)
+        Array index: IOP number (0:2)
     </description>
     <valueType>uint32</valueType>
-    <array>2</array>
+    <array>3</array>
     <platInit/>
   </attribute>
   <!-- ********************************************************************* -->
@@ -175,10 +220,10 @@
         PCIe PCS Control Register 1.
 	RXSIGDETSETTING/ADDDREMDELTA_128130_B/STARTUPDELTA_128130_B/
         ADDDREMDELTA_128130_A/STARTUPDELTA_128130_A.
-        Array index: IOP number (0:1)
+        Array index: IOP number (0:2)
     </description>
     <valueType>uint32</valueType>
-    <array>2</array>
+    <array>3</array>
     <platInit/>
   </attribute>
   <!-- ********************************************************************* -->
@@ -191,11 +236,11 @@
       notes:
         PCIe TX FIFO Offset Register.
 	G3OFFSET/G2OFFSET/G1OFFSET.
-        First array index: IOP number (0:1)
+        First array index: IOP number (0:2)
         Second array index: Lane number (0:15)
     </description>
     <valueType>uint32</valueType>
-    <array>2,16</array>
+    <array>3 16</array>
     <platInit/>
   </attribute>
   <!-- ********************************************************************* -->
@@ -208,11 +253,11 @@
       notes:
         PCIe TX Receiver Detect Control Register.
         VREFSEL/RCVRDETCNT/DETDRVC/PH1WAIT.
-        First array index: IOP number (0:1)
+        First array index: IOP number (0:2)
         Second array index: Lane number (0:15)
     </description>
     <valueType>uint32</valueType>
-    <array>2,16</array>
+    <array>3 16</array>
     <platInit/>
   </attribute>
   <!-- ********************************************************************* -->
@@ -225,11 +270,11 @@
       notes:
         PCIe TX Bandwidth Loss Coefficient Register.
         GEN3BWCOEFF/GEN2BWCOEFF/GEN1BWCOEFF.
-        First array index: IOP number (0:1)
+        First array index: IOP number (0:2)
         Second array index: Lane number (0:15)
     </description>
     <valueType>uint32</valueType>
-    <array>2,16</array>
+    <array>3 16</array>
     <platInit/>
   </attribute>
   <!-- ********************************************************************* -->
@@ -242,11 +287,11 @@
       notes:
         PCIe RX VGA Control Register 2.
         GAIN2/GAIN1.
-        First array index: IOP number (0:1)
+        First array index: IOP number (0:2)
         Second array index: Lane number (0:15)
     </description>
     <valueType>uint32</valueType>
-    <array>2,16</array>
+    <array>3 16</array>
     <platInit/>
   </attribute>
   <!-- ********************************************************************* -->
@@ -259,11 +304,11 @@
       notes:
         PCIe RX Receiver Peaking Value Register.
 	PEAK1/PEAK2/PEAK3.
-        First array index: IOP number (0:1)
+        First array index: IOP number (0:2)
         Second array index: Lane number (0:15)
     </description>
     <valueType>uint32</valueType>
-    <array>2,16</array>
+    <array>3 16</array>
     <platInit/>
   </attribute>
   <!-- ********************************************************************* -->
@@ -276,11 +321,11 @@
       notes:
         PCIe RX Signal Detect Level Register.
         SDLVL3/SDLVL2/SDLVL1.
-        First array index: IOP number (0:1)
+        First array index: IOP number (0:2)
         Second array index: Lane number (0:15)
     </description>
     <valueType>uint32</valueType>
-    <array>2,16</array>
+    <array>3 16</array>
     <platInit/>
   </attribute>
   <!-- ********************************************************************* -->
@@ -292,11 +337,11 @@
       consumer: proc_pcie_scominit
       notes:
         PCIe TX FFE (Gen1)
-        First array index: IOP number (0:1)
+        First array index: IOP number (0:2)
         Second array index: Lane number (0:15)
     </description>
     <valueType>uint32</valueType>
-    <array>2,16</array>
+    <array>3 16</array>
     <platInit/>
   </attribute>
   <!-- ********************************************************************* -->
@@ -308,11 +353,11 @@
       consumer: proc_pcie_scominit
       notes:
         PCIe TX FFE (Gen2)
-        First array index: IOP number (0:1)
+        First array index: IOP number (0:2)
         Second array index: Lane number (0:15)
     </description>
     <valueType>uint32</valueType>
-    <array>2,16</array>
+    <array>3 16</array>
     <platInit/>
   </attribute>
   <!-- ********************************************************************* -->
@@ -325,10 +370,10 @@
       notes:
         PCIe ZCAL Control Register.
         CMPEVALDLY.
-        Array index: IOP number (0:1)
+        Array index: IOP number (0:2)
     </description>
     <valueType>uint32</valueType>
-    <array>2</array>
+    <array>3</array>
     <platInit/>
   </attribute>
   <!-- ********************************************************************* -->