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author | Thi Tran <thi@us.ibm.com> | 2014-08-27 12:33:41 -0500 |
---|---|---|
committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-09-02 10:23:10 -0500 |
commit | 68a0676a2788e98aec11c549f0a1d232fea00277 (patch) | |
tree | 78c1ce4a7c5eba5ca0068aa2eeb4431a5862bb8b /src/usr/hwpf/hwp/nest_chiplets | |
parent | 294bd883533b79bd79b83e1c6554ffa866afe381 (diff) | |
download | talos-hostboot-68a0676a2788e98aec11c549f0a1d232fea00277.tar.gz talos-hostboot-68a0676a2788e98aec11c549f0a1d232fea00277.zip |
SW273877: Memory:Brazos: Clock error BC58E504 reported with 1434 Firmware, Fabri
Change-Id: Ia08213789d1c66f287cf258e08a4dd3c29a4589d
CQ:SW273877
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/13038
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/13040
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp/nest_chiplets')
-rw-r--r-- | src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C | 17 | ||||
-rw-r--r-- | src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H | 12 |
2 files changed, 15 insertions, 14 deletions
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C index d5bda7b7f..004ed3b44 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_a_x_pci_dmi_pll_setup.C,v 1.15 2014/04/02 14:02:33 jmcgill Exp $ +// $Id: proc_a_x_pci_dmi_pll_setup.C,v 1.16 2014/08/27 14:53:40 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_setup.C,v $ //------------------------------------------------------------------------------ // *| @@ -327,18 +327,6 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_setup_unmask_lock(const fapi::Target & i_t break; } -// TODO: Temporary workaround for SW274072 and SW273877 in order to release 820 driver. -// HW team is investigating. Also, refer to SW255565 for more info. -// -// rc = proc_a_x_pci_dmi_pll_setup_unmask_lock( -// i_target, -// PCIE_CHIPLET_0x09000000); -// if (!rc.ok()) -// { -// FAPI_ERR("Error from proc_a_x_pci_dmi_pll_setup_unmask_lock"); -// break; -// } - FAPI_INF("Done setting up PCIE PLL. "); } // end PCIE PLL @@ -357,6 +345,9 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_setup_unmask_lock(const fapi::Target & i_t This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: proc_a_x_pci_dmi_pll_setup.C,v $ +Revision 1.16 2014/08/27 14:53:40 jmcgill +shift PCI PLL unlock reporting from istep 7 -> 14 (SW273877) + Revision 1.15 2014/04/02 14:02:33 jmcgill respect function input parameters/partial good in unlock error clear/unmask logic (SW252901) diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H index c40bd52f1..ce3df4d2e 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_a_x_pci_dmi_pll_setup.H,v 1.7 2014/04/02 14:02:33 jmcgill Exp $ +// $Id: proc_a_x_pci_dmi_pll_setup.H,v 1.8 2014/08/27 14:53:48 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_setup.H,v $ //------------------------------------------------------------------------------ // *| @@ -62,6 +62,16 @@ typedef fapi::ReturnCode (*proc_a_x_pci_dmi_pll_setup_FP_t)(const fapi::Target & extern "C" { +/* + * @brief Clear and unmask chiplet PLL lock indication + * @param[in] i_target Reference to target + * @param[in] i_chiplet_base_scom_addr Aligned base address of chiplet SCOM + * address space + * @return ReturnCode + */ + fapi::ReturnCode proc_a_x_pci_dmi_pll_setup_unmask_lock(const fapi::Target & i_target, + const uint32_t i_chiplet_base_scom_addr); + /** * @brief Initialize and lock A/X/PCI/DMI PLLs * |