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author | Thi Tran <thi@us.ibm.com> | 2014-07-09 15:25:46 -0500 |
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committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-07-24 15:29:58 -0500 |
commit | 37513ea0bc79f720873cfbd8effd86f2b438928b (patch) | |
tree | a2b3432ac210963d64f6ee4eda49b9634a542e2f /src/usr/hwpf/hwp/nest_chiplets | |
parent | a8ec2507ef714ad8510daa176b62c2e1a83a81b0 (diff) | |
download | talos-hostboot-37513ea0bc79f720873cfbd8effd86f2b438928b.tar.gz talos-hostboot-37513ea0bc79f720873cfbd8effd86f2b438928b.zip |
Reinstate PCIE PLL unmask in proc_a_x_pci_dmi_pll_setup (Brazos only)
Change-Id: I64b2277878d0459c50f12ede1a037270db4a4120
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/#/c/12064/
Tested-by: Jenkins Server
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/12064
Diffstat (limited to 'src/usr/hwpf/hwp/nest_chiplets')
-rw-r--r-- | src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C index 822d2907e..adda180bc 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C @@ -327,15 +327,14 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_setup_unmask_lock(const fapi::Target & i_t break; } -//TODO: Temporarily undo this unmask for Brazos until Joe McGill fixes SW255565 -// rc = proc_a_x_pci_dmi_pll_setup_unmask_lock( -// i_target, -// PCIE_CHIPLET_0x09000000); -// if (!rc.ok()) -// { -// FAPI_ERR("Error from proc_a_x_pci_dmi_pll_setup_unmask_lock"); -// break; -// } + rc = proc_a_x_pci_dmi_pll_setup_unmask_lock( + i_target, + PCIE_CHIPLET_0x09000000); + if (!rc.ok()) + { + FAPI_ERR("Error from proc_a_x_pci_dmi_pll_setup_unmask_lock"); + break; + } FAPI_INF("Done setting up PCIE PLL. "); |