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| author | Richard J. Knight <rjknight@us.ibm.com> | 2013-09-13 10:44:58 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-09-18 15:46:40 -0500 |
| commit | 252d16ee2f6246933f6422eef48546e6b7c48d25 (patch) | |
| tree | 4e8fce83b84d441540a8bf2e38f4b733557c5138 /src/usr/hwpf/hwp/nest_chiplets | |
| parent | e884dd55d9411dff27c22088911e2075b5e60bef (diff) | |
| download | talos-hostboot-252d16ee2f6246933f6422eef48546e6b7c48d25.tar.gz talos-hostboot-252d16ee2f6246933f6422eef48546e6b7c48d25.zip | |
INITPROC: Hostboot - Low Priority HW Init Procedures
cleaning up some old defects, these files did not
get included with the original code drops for
SW206490 and SW201169.
Change-Id: I321e4640729ff1abdd5e44aaf3112f46fa82d2d5
CQ:SW206490
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/6237
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp/nest_chiplets')
| -rw-r--r-- | src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C | 26 |
1 files changed, 19 insertions, 7 deletions
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C index a13da8498..db63cd585 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_a_x_pci_dmi_pll_initf.C,v 1.13 2013/04/18 17:33:35 jmcgill Exp $ +// $Id: proc_a_x_pci_dmi_pll_initf.C,v 1.14 2013/04/29 16:38:51 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_initf.C,v $ //------------------------------------------------------------------------------ // *| @@ -62,6 +62,15 @@ const uint32_t PCI_BNDY_PLL_RING_ADDR = 0x09030088; const uint32_t DMI_PLL_VCO_WORKAROUND_THRESHOLD_FREQ = 4800; +const uint32_t PB_BNDY_DMIPLL_RING_CCALLOAD_OFFSET = 580; +const uint32_t PB_BNDY_DMIPLL_RING_CCALFMIN_OFFSET = 581; + +const uint32_t AB_BNDY_PLL_RING_CCALLOAD_OFFSET = 278; +const uint32_t AB_BNDY_PLL_RING_CCALFMIN_OFFSET = 279; + +const uint32_t PCI_BNDY_PLL_RING_CCALLOAD_OFFSET = 0x0; +const uint32_t PCI_BNDY_PLL_RING_CCALFMIN_OFFSET = 0x0; + //------------------------------------------------------------------------------ // Function definition @@ -227,8 +236,8 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_initf(const fapi::Target & i_target, AB_BNDY_PLL_RING_ADDR, ring_data, a_lctank_pll_vco_workaround, - 278, - 279); + AB_BNDY_PLL_RING_CCALLOAD_OFFSET, + AB_BNDY_PLL_RING_CCALFMIN_OFFSET); if (rc) { FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_pll"); @@ -316,8 +325,8 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_initf(const fapi::Target & i_target, PB_BNDY_DMIPLL_RING_ADDR, ring_data, dmi_lctank_pll_vco_workaround, - 580, - 581); + PB_BNDY_DMIPLL_RING_CCALLOAD_OFFSET, + PB_BNDY_DMIPLL_RING_CCALFMIN_OFFSET); if (rc) { FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_pll"); @@ -397,8 +406,8 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_initf(const fapi::Target & i_target, PCI_BNDY_PLL_RING_ADDR, ring_data, false, - 0x0, - 0x0); + PCI_BNDY_PLL_RING_CCALLOAD_OFFSET, + PCI_BNDY_PLL_RING_CCALFMIN_OFFSET); if (rc) { FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_pll"); @@ -425,6 +434,9 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_initf(const fapi::Target & i_target, This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: proc_a_x_pci_dmi_pll_initf.C,v $ +Revision 1.14 2013/04/29 16:38:51 jmcgill +add constants for Murano DD1 ccalload/ccalfmin ring offsets used in workaround + Revision 1.13 2013/04/18 17:33:35 jmcgill qualify workaround for DMI bus based on frequency |
