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authorRichard J. Knight <rjknight@us.ibm.com>2015-07-28 17:22:00 -0500
committerA. Patrick Williams III <iawillia@us.ibm.com>2015-08-26 07:28:19 -0500
commit102ee037ba001da14eaa754766130558c1e8a0e0 (patch)
tree440c47ab3556061b8a6eb6dc40d4233a29b434be /src/usr/hwpf/hwp/nest_chiplets
parentf7d5f8b567302b7f2d1c3540af268dcde8e99016 (diff)
downloadtalos-hostboot-102ee037ba001da14eaa754766130558c1e8a0e0.tar.gz
talos-hostboot-102ee037ba001da14eaa754766130558c1e8a0e0.zip
SW315524 : System terminates when ipled with guard records on PSI links
Change-Id: I53e4ae0a3b0d3be3a780dc1d59179dc80a2b55ad CQ:SW315524 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19454 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: WILLIAM G. HOFFA <wghoffa@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp/nest_chiplets')
-rw-r--r--src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C131
1 files changed, 111 insertions, 20 deletions
diff --git a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C
index f6c033582..14b44310a 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C
@@ -23,9 +23,9 @@
/* */
/* IBM_PROLOG_END_TAG */
/**
- @file nest_chiplets.C
+ @file nest_chiplets.C
*
- * Support file for IStep: nest_chiplets
+ * Support file for IStep: nest_chiplets
* Nest Chiplets
*
* HWP_IGNORE_VERSION_CHECK
@@ -63,7 +63,7 @@
// -- prototype includes --
// Add any customized routines that you don't want overwritten into
-// "start_clocks_on_nest_chiplets_custom.C" and include
+// "start_clocks_on_nest_chiplets_custom.C" and include
// the prototypes here.
// #include "nest_chiplets_custom.H"
#include "nest_chiplets.H"
@@ -119,6 +119,11 @@ void* call_proc_a_x_pci_dmi_pll_initf( void *io_pArgs )
TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"call_proc_a_x_pci_dmi_pll_initf entry" );
+ fapi::ReturnCode rc;
+
+ uint8_t abus_enable_attr = ENUM_ATTR_PROC_A_ENABLE_DISABLE;
+ uint8_t xbus_enable_attr = ENUM_ATTR_PROC_X_ENABLE_DISABLE;
+
TARGETING::TargetHandleList l_procTargetList;
getAllChips(l_procTargetList, TYPE_PROC);
@@ -139,19 +144,38 @@ void* call_proc_a_x_pci_dmi_pll_initf( void *io_pArgs )
bool l_startAbusPll = false;
bool l_startPCIEPll = false;
bool l_startDMIPll = false;
-
- TARGETING::TargetHandleList l_xbus;
- getChildChiplets( l_xbus, l_proc_target, TYPE_XBUS );
- if (l_xbus.size() > 0)
+
+
+ rc = FAPI_ATTR_GET(ATTR_PROC_X_ENABLE,
+ &l_fapi_proc_target,
+ xbus_enable_attr);
+
+ if (!rc.ok())
{
- l_startXbusPll = true;
+ FAPI_ERR("Error querying ATTR_PROC_X_ENABLE");
+ l_err = fapi::fapiRcToErrl(rc);
+ break;
}
- TARGETING::TargetHandleList l_abus;
- getChildChiplets( l_abus, l_proc_target, TYPE_ABUS );
- if (l_abus.size() > 0)
+ if( xbus_enable_attr == fapi::ENUM_ATTR_PROC_X_ENABLE_ENABLE )
{
- l_startAbusPll = true;
+ l_startXbusPll = true;
+ }
+
+ rc = FAPI_ATTR_GET(ATTR_PROC_A_ENABLE,
+ &l_fapi_proc_target,
+ abus_enable_attr);
+
+ if (!rc.ok())
+ {
+ FAPI_ERR("Error querying ATTR_PROC_A_ENABLE");
+ l_err = fapi::fapiRcToErrl(rc);
+ break;
+ }
+
+ if( abus_enable_attr == fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE )
+ {
+ l_startAbusPll = true;
}
TARGETING::TargetHandleList l_pci;
@@ -170,11 +194,11 @@ void* call_proc_a_x_pci_dmi_pll_initf( void *io_pArgs )
// call proc_a_x_pci_dmi_pll_initf
FAPI_INVOKE_HWP(l_err, proc_a_x_pci_dmi_pll_initf,
- l_fapi_proc_target,
- l_startXbusPll, // xbus
- l_startAbusPll, // abus
- l_startPCIEPll, // pcie
- l_startDMIPll); // dmi
+ l_fapi_proc_target,
+ l_startXbusPll, // xbus
+ l_startAbusPll, // abus
+ l_startPCIEPll, // pcie
+ l_startDMIPll); // dmi
if (l_err)
{
@@ -199,6 +223,16 @@ void* call_proc_a_x_pci_dmi_pll_initf( void *io_pArgs )
}
}
+ if (l_err)
+ {
+ // Create IStep error log and cross reference to error that occurred
+ l_StepError.addErrorDetails( l_err );
+
+ // Commit Error
+ errlCommit( l_err, HWPF_COMP_ID );
+ }
+
+
TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"call_proc_a_x_pci_dmi_pll_initf exit" );
return l_StepError.getErrorHandle();
@@ -493,6 +527,53 @@ void* call_proc_startclock_chiplets( void *io_pArgs )
break;
}
+ uint8_t abus_enable_attr = ENUM_ATTR_PROC_A_ENABLE_DISABLE;
+ uint8_t xbus_enable_attr = ENUM_ATTR_PROC_X_ENABLE_DISABLE;
+
+ fapi::ReturnCode rc;
+ bool l_startXbusPll = false;
+ bool l_startAbusPll = false;
+ bool l_startPCIEPll = false;
+
+ rc = FAPI_ATTR_GET(ATTR_PROC_X_ENABLE,
+ &l_fapi_proc_target,
+ xbus_enable_attr);
+
+ if (!rc.ok())
+ {
+ FAPI_ERR("Error querying ATTR_PROC_X_ENABLE");
+ l_err = fapi::fapiRcToErrl(rc);
+ break;
+ }
+
+ if( xbus_enable_attr == fapi::ENUM_ATTR_PROC_X_ENABLE_ENABLE )
+ {
+ l_startXbusPll = true;
+ }
+
+ rc = FAPI_ATTR_GET(ATTR_PROC_A_ENABLE,
+ &l_fapi_proc_target,
+ abus_enable_attr);
+
+ if (!rc.ok())
+ {
+ FAPI_ERR("Error querying ATTR_PROC_A_ENABLE");
+ l_err = fapi::fapiRcToErrl(rc);
+ break;
+ }
+
+ if( abus_enable_attr == fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE )
+ {
+ l_startAbusPll = true;
+ }
+
+ TARGETING::TargetHandleList l_pci;
+ getChildChiplets( l_pci, l_proc_target, TYPE_PCI );
+ if (l_pci.size() > 0)
+ {
+ l_startPCIEPll = true;
+ }
+
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"Running proc_startclock_chiplets HWP on "
@@ -501,9 +582,9 @@ void* call_proc_startclock_chiplets( void *io_pArgs )
// call the HWP with each fapi::Target
FAPI_INVOKE_HWP(l_err, proc_start_clocks_chiplets,
l_fapi_proc_target,
- true, // xbus
- true, // abus
- true); // pcie
+ l_startXbusPll, // xbus
+ l_startAbusPll, // abus
+ l_startPCIEPll); // pcie
if (l_err)
{
TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
@@ -528,6 +609,16 @@ void* call_proc_startclock_chiplets( void *io_pArgs )
}
}
+ if (l_err)
+ {
+ // Create IStep error log and cross reference to error that occurred
+ l_StepError.addErrorDetails( l_err );
+
+ // Commit Error
+ errlCommit( l_err, HWPF_COMP_ID );
+ }
+
+
TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"call_proc_startclock_chiplets exit" );
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