diff options
author | Thi Tran <thi@us.ibm.com> | 2014-03-28 15:40:19 -0500 |
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committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-03-31 11:54:08 -0500 |
commit | 08b2a7d1c64a65cba7146f16180d42d6f9198700 (patch) | |
tree | 4ea3701dcd373b6f354984f033817cd2d804f2b0 /src/usr/hwpf/hwp/nest_chiplets | |
parent | 1888906cc09f32acd9ce9a50c071935c98a9acfd (diff) | |
download | talos-hostboot-08b2a7d1c64a65cba7146f16180d42d6f9198700.tar.gz talos-hostboot-08b2a7d1c64a65cba7146f16180d42d6f9198700.zip |
INITPROC: Hostboot SW252901 Additional changes needed to fix MBSFIR[3]
Change-Id: Ifaa3df03c16267ea72c8f1f9915e55e707fbb04b
CQ:SW252901
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9994
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp/nest_chiplets')
-rw-r--r-- | src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C | 246 | ||||
-rw-r--r-- | src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H | 19 |
2 files changed, 261 insertions, 4 deletions
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C index f292520e6..30259e9a3 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_a_x_pci_dmi_pll_setup.C,v 1.12 2014/01/07 14:43:34 mfred Exp $ +// $Id: proc_a_x_pci_dmi_pll_setup.C,v 1.14 2014/03/28 15:25:39 bgeukes Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_setup.C,v $ //------------------------------------------------------------------------------ // *| @@ -73,10 +73,13 @@ extern "C" { // data buffer to hold register values ecmdDataBufferBase gp_data(64); + ecmdDataBufferBase scom_data(64); + // return codes + uint32_t rc_ecmd = 0; fapi::ReturnCode rc; - + // locals uint8_t pcie_enable_attr; uint8_t abus_enable_attr; @@ -209,6 +212,239 @@ extern "C" + /// Perform PLL lock error clean up and Error unmasking + + // Pervasive Chiplet + rc = fapiGetScom(i_target,PERV_PLL_LOCK_ERROR_INDICATION_0x010F001F,scom_data); + + if(rc) + { + FAPI_ERR("Error reading PCB Slave PLL Lock Indication"); + break; + } + + rc_ecmd |= scom_data.setBit(25); // set bit to clear previous lock errors + rc_ecmd |= scom_data.setBit(26); // set bit to clear previous lock errors + rc_ecmd |= scom_data.setBit(27); // set bit to clear previous lock errors + rc_ecmd |= scom_data.setBit(28); // set bit to clear previous lock errors + + if (rc_ecmd) + { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + + FAPI_INF("Clearing PCB Slave Lock Indication Bit 25,26,27,28"); + rc = fapiPutScom(i_target,PERV_PLL_LOCK_ERROR_INDICATION_0x010F001F,scom_data); + + if(rc) + { + FAPI_ERR("Error writing Perv PCB Slave Lock Inidication Register"); + break; + } + + // Nest Chiplet + rc = fapiGetScom(i_target,NEST_PLL_LOCK_ERROR_INDICATION_0x020F001F,scom_data); + + if(rc) + { + FAPI_ERR("Error reading Nest PCB Slave PLL Lock Indication"); + break; + } + + rc_ecmd |= scom_data.setBit(25); // set bit to clear previous lock errors + rc_ecmd |= scom_data.setBit(26); // set bit to clear previous lock errors + rc_ecmd |= scom_data.setBit(27); // set bit to clear previous lock errors + rc_ecmd |= scom_data.setBit(28); // set bit to clear previous lock errors + + if (rc_ecmd) + { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + FAPI_INF("Clearing PCB Slave Lock Indication Bit 25,26,27,28"); + rc = fapiPutScom(i_target,NEST_PLL_LOCK_ERROR_INDICATION_0x020F001F,scom_data); + + if(rc) + { + FAPI_ERR("Error writing Perv PCB Slave Lock Inidication Register"); + break; + } + + // ABUS Chiplet + rc = fapiGetScom(i_target,ABUS_PLL_LOCK_ERROR_INDICATION_0x080F001F,scom_data); + + if(rc) + { + FAPI_ERR("Error reading ABUS PCB Slave PLL Lock Indication"); + break; + } + + rc_ecmd |= scom_data.setBit(25); // set bit to clear previous lock errors + rc_ecmd |= scom_data.setBit(26); // set bit to clear previous lock errors + rc_ecmd |= scom_data.setBit(27); // set bit to clear previous lock errors + rc_ecmd |= scom_data.setBit(28); // set bit to clear previous lock errors + + if (rc_ecmd) + { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + FAPI_INF("Clearing ABUS PCB Slave Lock Indication Bit 25,26,27,28"); + rc = fapiPutScom(i_target,ABUS_PLL_LOCK_ERROR_INDICATION_0x080F001F,scom_data); + + if(rc) + { + FAPI_ERR("Error writing ABUS PCB Slave Lock Inidication Register"); + break; + } + + // PCI Chiplet + rc = fapiGetScom(i_target,PCI_PLL_LOCK_ERROR_INDICATION_0x090F001F,scom_data); + + if(rc) + { + FAPI_ERR("Error reading PCI PCB Slave PLL Lock Indication"); + break; + } + + rc_ecmd |= scom_data.setBit(25); // set bit to clear previous lock errors + rc_ecmd |= scom_data.setBit(26); // set bit to clear previous lock errors + rc_ecmd |= scom_data.setBit(27); // set bit to clear previous lock errors + rc_ecmd |= scom_data.setBit(28); // set bit to clear previous lock errors + + if (rc_ecmd) + { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + FAPI_INF("Clearing PCI PCB Slave Lock Indication Bit 25,26,27,28"); + rc = fapiPutScom(i_target,PCI_PLL_LOCK_ERROR_INDICATION_0x090F001F,scom_data); + + if(rc) + { + FAPI_ERR("Error writing PCI PCB Slave Lock Inidication Register"); + break; + } + + //// Unmasking Lock Indication + // Pervasive Chiplet + rc = fapiGetScom(i_target,PERV_PLL_LOCK_MASK_0x010F001E,scom_data); + + if(rc) + { + FAPI_ERR("Error reading PCB Slave PLL Lock Mask"); + break; + } + + rc_ecmd |= scom_data.clearBit(12); // set bit to clear PLL Lock Mask + + if (rc_ecmd) + { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + FAPI_INF("Clearing PCB Slave Lock Mask Bit 12"); + rc = fapiPutScom(i_target,PERV_PLL_LOCK_MASK_0x010F001E,scom_data); + + if(rc) + { + FAPI_ERR("Error writing Perv PCB Slave Lock Mask"); + break; + } + + // Nest Chiplet + rc = fapiGetScom(i_target,NEST_PLL_LOCK_MASK_0x020F001E,scom_data); + + if(rc) + { + FAPI_ERR("Error reading PCB Slave PLL Lock Mask"); + break; + } + + rc_ecmd |= scom_data.clearBit(12); // set bit to clear PLL Lock Mask + + if (rc_ecmd) + { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + FAPI_INF("Clearing Nest PCB Slave Lock Mask Bit 12"); + rc = fapiPutScom(i_target,NEST_PLL_LOCK_MASK_0x020F001E,scom_data); + + if(rc) + { + FAPI_ERR("Error writing Nest PCB Slave Lock Mask"); + break; + } + + // ABUS Chiplet + rc = fapiGetScom(i_target,ABUS_PLL_LOCK_MASK_0x080F001E,scom_data); + + if(rc) + { + FAPI_ERR("Error reading ABUS PCB Slave PLL Lock Mask"); + break; + } + + rc_ecmd |= scom_data.clearBit(12); // set bit to clear PLL Lock Mask + + if (rc_ecmd) + { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + FAPI_INF("Clearing ABUS PCB Slave Lock Mask Bit 12"); + rc = fapiPutScom(i_target,ABUS_PLL_LOCK_MASK_0x080F001E,scom_data); + + if(rc) + { + FAPI_ERR("Error writing ABUS PCB Slave Lock Mask"); + break; + } + + // PCI Chiplet + rc = fapiGetScom(i_target,PCI_PLL_LOCK_MASK_0x090F001E,scom_data); + + if(rc) + { + FAPI_ERR("Error reading PCB Slave PLL Lock Mask"); + break; + } + + rc_ecmd |= scom_data.clearBit(12); // set bit to clear PLL Lock Mask + + if (rc_ecmd) + { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + FAPI_INF("Clearing PCI PCB Slave Lock Mask Bit 12"); + rc = fapiPutScom(i_target,PCI_PLL_LOCK_MASK_0x090F001E,scom_data); + + if(rc) + { + FAPI_ERR("Error writing PCI PCB Slave Lock Mask"); + break; + } + + } while (0); // end do // mark function exit @@ -223,6 +459,12 @@ extern "C" This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: proc_a_x_pci_dmi_pll_setup.C,v $ +Revision 1.14 2014/03/28 15:25:39 bgeukes +updates for SW252901 after RAS review + +Revision 1.13 2014/03/27 17:58:08 bgeukes +fix for the scominit updates + Revision 1.12 2014/01/07 14:43:34 mfred Checking in updates from Andrea Ma: Include statements fixed and one fapi dbg statement changed. diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H index 4e43cdd99..465d81221 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_a_x_pci_dmi_pll_setup.H,v 1.5 2013/04/17 22:38:44 jmcgill Exp $ +// $Id: proc_a_x_pci_dmi_pll_setup.H,v 1.6 2014/03/27 17:58:11 bgeukes Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_setup.H,v $ //------------------------------------------------------------------------------ // *| @@ -44,6 +44,21 @@ #include <fapi.H> +//----- +// Constant Definitions +// + +CONST_UINT64_T( PERV_PLL_LOCK_ERROR_INDICATION_0x010F001F , ULL(0x010F001F) ); +CONST_UINT64_T( NEST_PLL_LOCK_ERROR_INDICATION_0x020F001F , ULL(0x020F001F) ); +CONST_UINT64_T( ABUS_PLL_LOCK_ERROR_INDICATION_0x080F001F , ULL(0x080F001F) ); +CONST_UINT64_T( PCI_PLL_LOCK_ERROR_INDICATION_0x090F001F , ULL(0x090F001F) ); + +CONST_UINT64_T( PERV_PLL_LOCK_MASK_0x010F001E , ULL(0x010F001E) ); +CONST_UINT64_T( NEST_PLL_LOCK_MASK_0x020F001E , ULL(0x020F001E) ); +CONST_UINT64_T( ABUS_PLL_LOCK_MASK_0x080F001E , ULL(0x080F001E) ); +CONST_UINT64_T( PCI_PLL_LOCK_MASK_0x090F001E , ULL(0x090F001E) ); + + //------------------------------------------------------------------------------ // Structure definitions //------------------------------------------------------------------------------ |