INITPROC: Hostboot - SW228141 PLL Rescan for DCCAL

Change-Id: Ic4b2f3b5dda2abe151923ac70103e298a47d4169
CMVC-Prereq:903906
CQ:SW228141
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/6849
Tested-by: Jenkins Server
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

4 files changed, 126 insertions, 35 deletions

diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C
index db63cd585..00fbedacf 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_a_x_pci_dmi_pll_initf.C,v 1.14 2013/04/29 16:38:51 jmcgill Exp $
+// $Id: proc_a_x_pci_dmi_pll_initf.C,v 1.15 2013/09/30 16:09:56 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_initf.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -53,26 +53,6 @@ using namespace fapi;
 
 
 //------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-const uint32_t PB_BNDY_DMIPLL_RING_ADDR = 0x02030088;
-const uint32_t AB_BNDY_PLL_RING_ADDR    = 0x08030088;
-const uint32_t PCI_BNDY_PLL_RING_ADDR   = 0x09030088;
-
-const uint32_t DMI_PLL_VCO_WORKAROUND_THRESHOLD_FREQ = 4800;
-
-const uint32_t PB_BNDY_DMIPLL_RING_CCALLOAD_OFFSET = 580;
-const uint32_t PB_BNDY_DMIPLL_RING_CCALFMIN_OFFSET = 581;
-
-const uint32_t AB_BNDY_PLL_RING_CCALLOAD_OFFSET = 278;
-const uint32_t AB_BNDY_PLL_RING_CCALFMIN_OFFSET = 279;
-
-const uint32_t PCI_BNDY_PLL_RING_CCALLOAD_OFFSET = 0x0;
-const uint32_t PCI_BNDY_PLL_RING_CCALFMIN_OFFSET = 0x0;
-
-
-//------------------------------------------------------------------------------
 // Function definition
 //------------------------------------------------------------------------------
 
@@ -237,7 +217,8 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_initf(const fapi::Target & i_target,
                     ring_data,
                     a_lctank_pll_vco_workaround,
                     AB_BNDY_PLL_RING_CCALLOAD_OFFSET,
-                    AB_BNDY_PLL_RING_CCALFMIN_OFFSET);
+                    AB_BNDY_PLL_RING_CCALFMIN_OFFSET,
+                    false);
             if (rc)
             {
                 FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_pll");
@@ -326,7 +307,8 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_initf(const fapi::Target & i_target,
                     ring_data,
                     dmi_lctank_pll_vco_workaround,
                     PB_BNDY_DMIPLL_RING_CCALLOAD_OFFSET,
-                    PB_BNDY_DMIPLL_RING_CCALFMIN_OFFSET);
+                    PB_BNDY_DMIPLL_RING_CCALFMIN_OFFSET,
+                    true);
             if (rc)
             {
                 FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_pll");
@@ -407,7 +389,8 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_initf(const fapi::Target & i_target,
                     ring_data,
                     false,
                     PCI_BNDY_PLL_RING_CCALLOAD_OFFSET,
-                    PCI_BNDY_PLL_RING_CCALFMIN_OFFSET);
+                    PCI_BNDY_PLL_RING_CCALFMIN_OFFSET,
+                    false);
             if (rc)
             {
                 FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_pll");
@@ -434,6 +417,9 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_initf(const fapi::Target & i_target,
 This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 $Log: proc_a_x_pci_dmi_pll_initf.C,v $
+Revision 1.15  2013/09/30 16:09:56  jmcgill
+fix HW268965
+
 Revision 1.14  2013/04/29 16:38:51  jmcgill
 add constants for Murano DD1 ccalload/ccalfmin ring offsets used in workaround
 
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.H b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.H
index 5efeb3d1e..925d060e3 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.H
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_a_x_pci_dmi_pll_initf.H,v 1.3 2013/04/17 22:38:40 jmcgill Exp $
+// $Id: proc_a_x_pci_dmi_pll_initf.H,v 1.4 2013/09/30 16:09:57 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_initf.H,v $
 //------------------------------------------------------------------------------
 // *|
@@ -44,9 +44,6 @@
 
 #include <fapi.H>
 
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
 
 //------------------------------------------------------------------------------
 // Structure definitions
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C
index a5944b2cd..af09b1947 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_a_x_pci_dmi_pll_utils.C,v 1.3 2013/08/20 02:05:06 jmcgill Exp $
+// $Id: proc_a_x_pci_dmi_pll_utils.C,v 1.4 2013/09/30 16:09:57 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_utils.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -55,6 +55,9 @@ const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_MAX_LOCK_POLLS = 50;
 const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_POLL_DELAY_HW = 2000000;
 const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_POLL_DELAY_SIM = 1;
 
+// Pervasive LFIR Register field/bit definitions
+const uint8_t PERV_LFIR_SCAN_COLLISION_BIT = 3;
+
 // OPCG/Clock Region Register values
 const uint64_t OPCG_REG0_FOR_SETPULSE  = 0x818C000000000000ull;
 const uint64_t OPCG_REG2_FOR_SETPULSE  = 0x0000000000002000ull;
@@ -89,6 +92,8 @@ extern "C"
 //             i_pll_ring_addr          => PLL ring address
 //             i_pll_ring_data          => data buffer containing full PLL ring
 //                                         content
+//             i_mask_scan_collision    => mask scan collision bit in chiplet
+//                                         pervasive LFIR
 // returns: FAPI_RC_SUCCESS if operation was successful, else error
 //------------------------------------------------------------------------------
 
@@ -96,7 +101,8 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_scan_bndy(
     const fapi::Target& i_target,
     const uint32_t i_chiplet_base_scom_addr,
     const uint32_t i_pll_ring_addr,
-    ecmdDataBufferBase& i_pll_ring_data)
+    ecmdDataBufferBase& i_pll_ring_data,
+    const bool i_mask_scan_collision)
 {
     // data buffer to hold SCOM data
     ecmdDataBufferBase data(64);
@@ -111,6 +117,28 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_scan_bndy(
     do
     {
         //-------------------------------------------
+        //  Mask Pervasive LFIR
+        //------------------------------------------
+
+        if (i_mask_scan_collision)
+        {
+            FAPI_DBG("Masking Pervasive LFIR scan collision bit ...");
+            rc_ecmd |= data.setBit(PERV_LFIR_SCAN_COLLISION_BIT);
+            if (rc_ecmd)
+            {
+                FAPI_ERR("Error 0x%x setting up ecmd data buffer to set Pervasive LFIR Mask Register.", rc_ecmd);
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+            rc = fapiPutScom(i_target, i_chiplet_base_scom_addr | GENERIC_PERV_LFIR_MASK_OR_0x0004000F, data);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error writing Pervasive LFIR Mask OR Register.");
+                break;
+            }
+        }
+
+        //-------------------------------------------
         //  Set the OPCG to generate the setpulse
         //------------------------------------------
 
@@ -220,6 +248,37 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_scan_bndy(
             break;
         }
 
+
+        //-------------------------------------------
+        //  Clear & Unmask Pervasive LFIR
+        //------------------------------------------
+
+        if (i_mask_scan_collision)
+        {
+            FAPI_DBG("Clearing Pervasive LFIR scan collision bit ...");
+            rc_ecmd |= data.flushTo1();
+            rc_ecmd |= data.clearBit(PERV_LFIR_SCAN_COLLISION_BIT);
+            if (rc_ecmd)
+            {
+                FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear Pervasive LFIR Register.", rc_ecmd);
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+            rc = fapiPutScom(i_target, i_chiplet_base_scom_addr | GENERIC_PERV_LFIR_AND_0x0004000B, data);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error writing Pervasive LFIR AND Register.");
+                break;
+            }
+
+            FAPI_DBG("Unmasking Pervasive LFIR scan collision bit ...");
+            rc = fapiPutScom(i_target, i_chiplet_base_scom_addr | GENERIC_PERV_LFIR_MASK_AND_0x0004000E, data);
+            if (!rc.ok())
+            {
+                FAPI_ERR("Error writing Pervasive LFIR Mask And Register.");
+                break;
+            }
+        }
     } while(0);
 
 
@@ -257,7 +316,8 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_scan_pll(
     ecmdDataBufferBase& i_pll_ring_data,
     const bool i_lctank_pll_vco_workaround,
     const uint32_t i_ccalload_ring_offset,
-    const uint32_t i_ccalfmin_ring_offset)
+    const uint32_t i_ccalfmin_ring_offset,
+    const bool i_mask_scan_collision)
 {
     // return codes
     uint32_t rc_ecmd = 0;
@@ -287,7 +347,8 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_scan_pll(
                 i_target,
                 i_chiplet_base_scom_addr,
                 i_pll_ring_addr,
-                i_pll_ring_data);
+                i_pll_ring_data,
+                i_mask_scan_collision);
         if (!rc.ok())
         {
             FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy (scan = %d)", scan_count);
@@ -322,7 +383,8 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_scan_pll(
                     i_target,
                     i_chiplet_base_scom_addr,
                     i_pll_ring_addr,
-                    i_pll_ring_data);
+                    i_pll_ring_data,
+                    i_mask_scan_collision);
             if (!rc.ok())
             {
                 FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy (scan = %d)", scan_count);
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.H b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.H
index 9d0f5a8a8..4a0c8e0a1 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.H
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_a_x_pci_dmi_pll_utils.H,v 1.1 2013/04/17 22:36:34 jmcgill Exp $
+// $Id: proc_a_x_pci_dmi_pll_utils.H,v 1.2 2013/09/30 16:09:57 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_utils.H,v $
 //------------------------------------------------------------------------------
 // *|
@@ -46,6 +46,27 @@
 
 
 //------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+
+const uint32_t TP_BNDY_PLL_RING_ADDR    = 0x00030088;
+const uint32_t PB_BNDY_DMIPLL_RING_ADDR = 0x02030088;
+const uint32_t AB_BNDY_PLL_RING_ADDR    = 0x08030088;
+const uint32_t PCI_BNDY_PLL_RING_ADDR   = 0x09030088;
+
+const uint32_t DMI_PLL_VCO_WORKAROUND_THRESHOLD_FREQ = 4800;
+
+const uint32_t PB_BNDY_DMIPLL_RING_CCALLOAD_OFFSET = 580;
+const uint32_t PB_BNDY_DMIPLL_RING_CCALFMIN_OFFSET = 581;
+
+const uint32_t AB_BNDY_PLL_RING_CCALLOAD_OFFSET = 278;
+const uint32_t AB_BNDY_PLL_RING_CCALFMIN_OFFSET = 279;
+
+const uint32_t PCI_BNDY_PLL_RING_CCALLOAD_OFFSET = 0x0;
+const uint32_t PCI_BNDY_PLL_RING_CCALFMIN_OFFSET = 0x0;
+
+
+//------------------------------------------------------------------------------
 // Function prototypes
 //------------------------------------------------------------------------------
 
@@ -55,6 +76,28 @@ extern "C"
 
 //------------------------------------------------------------------------------
 // function:
+//      Scan PLL boundary ring with setpulse
+//
+// parameters: i_target                 => chip target
+//             i_chiplet_base_scom_addr => aligned base address of chiplet SCOM
+//                                         address space
+//             i_pll_ring_addr          => PLL ring address
+//             i_pll_ring_data          => data buffer containing full PLL ring
+//                                         content
+//             i_mask_scan_collision    => mask scan collision bit in chiplet
+//                                         pervasive LFIR
+// returns: FAPI_RC_SUCCESS if operation was successful, else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_a_x_pci_dmi_pll_scan_bndy(
+    const fapi::Target& i_target,
+    const uint32_t i_chiplet_base_scom_addr,
+    const uint32_t i_pll_ring_addr,
+    ecmdDataBufferBase& i_pll_ring_data,
+    const bool i_mask_scan_collision);
+
+
+//------------------------------------------------------------------------------
+// function:
 //      Scan PLL ring to establish runtime state
 //
 // parameters: i_target                    => chip target
@@ -71,6 +114,8 @@ extern "C"
 //             i_ccalfmin_ring_offset      => ring offset for ccalfmin PLL control
 //                                            bit (used only if workaround
 //                                            is true)
+//             i_mask_scan_collision       => mask scan collision bit in chiplet
+//                                            pervasive LFIR
 // returns: FAPI_RC_SUCCESS if operation was successful, else error
 //------------------------------------------------------------------------------
 fapi::ReturnCode proc_a_x_pci_dmi_pll_scan_pll(
@@ -80,7 +125,8 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_scan_pll(
     ecmdDataBufferBase& i_pll_ring_data,
     const bool i_lctank_pll_vco_workaround,
     const uint32_t i_ccalload_ring_offset,
-    const uint32_t i_ccalfmin_ring_offset);
+    const uint32_t i_ccalfmin_ring_offset,
+    const bool i_mask_scan_collision);
 
 
 //------------------------------------------------------------------------------