Changes for Brazos 2z/3z Support

This commit has the hostboot changes for Brazos 2z/3z support along with
some attributes that Hostboot and HWSV share.  It also contains memory
XML and HWP changes from SW305517 and SW305518.

Change-Id: I71896dfac6946624bed3e216fe7823bd73e8e6bc
RTC: 125037
CQ:SW305518
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19306
Reviewed-by: PRACHI GUPTA <pragupta@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Michael D. Pardeik <pardeik@us.ibm.com>
Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com>
Tested-by: Michael Baiocchi <baiocchi@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19375
Tested-by: Jenkins Server
Tested-by: Jenkins OP Build CI
Reviewed-by: WILLIAM G. HOFFA <wghoffa@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Tested-by: Jenkins OP HW
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

6 files changed, 318 insertions, 30 deletions

diff --git a/src/usr/hwpf/hwp/mc_config/mc_config.C b/src/usr/hwpf/hwp/mc_config/mc_config.C
index 1d1ea9780..b2bc2f165 100644
--- a/src/usr/hwpf/hwp/mc_config/mc_config.C
+++ b/src/usr/hwpf/hwp/mc_config/mc_config.C
@@ -89,6 +89,230 @@ using   namespace   ERRORLOG;
 using   namespace   TARGETING;
 using   namespace   fapi;
 
+
+//
+//  Helper function to set _EFF_CONFIG attributes for HWPs
+//
+void set_eff_config_attrs_helper( const EFF_CONFIG_ATTRIBUTES_BASE i_base,
+                                  bool & o_post_dram_inits_found)
+{
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+               "set_eff_config_attrs_helper: setting _EFF_CONFIG attributes "
+               "enter: i_base=%d", i_base);
+
+    o_post_dram_inits_found = false;
+
+    // Local Variables ('pdi_' means 'post dram init')
+    uint32_t pdi_ddr3_vddr_slope=0;
+    uint32_t pdi_ddr3_vddr_intercept=0;
+    uint32_t pdi_ddr3_vddr_max_limit=0;
+    uint32_t pdi_ddr4_vddr_slope=0;
+    uint32_t pdi_ddr4_vddr_intercept=0;
+    uint32_t pdi_ddr4_vddr_max_limit=0;
+    uint32_t pdi_vpp_slope=0;
+    uint32_t pdi_vpp_intercept=0;
+
+    uint32_t eff_conf_ddr3_vddr_slope=0;
+    uint32_t eff_conf_ddr3_vddr_intercept=0;
+    uint32_t eff_conf_ddr3_vddr_max_limit=0;
+    uint32_t eff_conf_ddr4_vddr_slope=0;
+    uint32_t eff_conf_ddr4_vddr_intercept=0;
+    uint32_t eff_conf_ddr4_vddr_max_limit=0;
+    uint32_t eff_conf_vpp_slope=0;
+    uint32_t eff_conf_vpp_intercept=0;
+
+    // Check input base
+    assert( ( i_base == DEFAULT ) || (i_base == POST_DRAM_INIT ),
+            "set_eff_config_attrs_helper: Invalid i_base passed in: %d",
+            i_base);
+
+    // Get Node Target
+    TARGETING::Target* sysTgt = NULL;
+    TARGETING::targetService().getTopLevelTarget(sysTgt);
+    assert(sysTgt != NULL,"System target was NULL.");
+
+    TARGETING::TargetHandleList l_nodeList;
+
+    TARGETING::PredicateCTM isaNode(TARGETING::CLASS_ENC,
+                                    TARGETING::TYPE_NODE);
+
+    TARGETING::targetService().getAssociated(
+                                   l_nodeList,
+                                   sysTgt,
+                                   TARGETING::TargetService::CHILD,
+                                   TARGETING::TargetService::IMMEDIATE,
+                                   &isaNode);
+
+    // Node list should only have 1 tgt
+    assert ( l_nodeList.size() == 1,
+             "System target returned multiple or zero nodes ");
+    TARGETING::Target* nodeTgt=l_nodeList[0];
+
+
+
+    // Look for POST_DRAM_INIT Attributes if requested
+    if ( i_base == POST_DRAM_INIT )
+    {
+        // POST_DRAM_INIT DDR3 VDDR
+        pdi_ddr3_vddr_slope =
+                 nodeTgt->getAttr<
+                 TARGETING::ATTR_MSS_VOLT_DDR3_VDDR_SLOPE_POST_DRAM_INIT>();
+
+        pdi_ddr3_vddr_intercept =
+                 nodeTgt->getAttr<
+                 TARGETING::ATTR_MSS_VOLT_DDR3_VDDR_INTERCEPT_POST_DRAM_INIT>();
+
+        pdi_ddr3_vddr_max_limit =
+                 nodeTgt->getAttr<
+                 TARGETING::ATTR_MRW_DDR3_VDDR_MAX_LIMIT_POST_DRAM_INIT>();
+
+        // POST_DRAM_INIT DDR4 VDDR
+        pdi_ddr4_vddr_slope =
+                 nodeTgt->getAttr<
+                 TARGETING::ATTR_MSS_VOLT_DDR4_VDDR_SLOPE_POST_DRAM_INIT>();
+
+        pdi_ddr4_vddr_intercept =
+                 nodeTgt->getAttr<
+                 TARGETING::ATTR_MSS_VOLT_DDR4_VDDR_INTERCEPT_POST_DRAM_INIT>();
+
+        pdi_ddr4_vddr_max_limit =
+                 nodeTgt->getAttr<
+                 TARGETING::ATTR_MRW_DDR4_VDDR_MAX_LIMIT_POST_DRAM_INIT>();
+
+
+        // POST_DRAM_INIT VPP
+        pdi_vpp_slope =
+                 nodeTgt->getAttr<
+                 TARGETING::ATTR_MSS_VOLT_VPP_SLOPE_POST_DRAM_INIT>();
+
+        pdi_vpp_intercept =
+                 nodeTgt->getAttr<
+                 TARGETING::ATTR_MSS_VOLT_VPP_INTERCEPT_POST_DRAM_INIT>();
+    }
+    o_post_dram_inits_found = ( pdi_ddr3_vddr_slope || pdi_ddr3_vddr_intercept ||
+                                pdi_ddr3_vddr_max_limit ||
+                                pdi_ddr4_vddr_slope || pdi_ddr4_vddr_intercept ||
+                                pdi_ddr4_vddr_max_limit ||
+                                pdi_vpp_slope || pdi_vpp_intercept )
+                              ? true : false;
+
+    // -----------------------------------
+    // EFF CONFIG: DDR3 VDDR
+    if ( o_post_dram_inits_found == false )
+    {
+        // Use default system values
+        eff_conf_ddr3_vddr_slope =
+                 sysTgt->getAttr<TARGETING::ATTR_MSS_VOLT_DDR3_VDDR_SLOPE>();
+
+        eff_conf_ddr3_vddr_intercept =
+                 sysTgt->getAttr<
+                         TARGETING::ATTR_MSS_VOLT_DDR3_VDDR_INTERCEPT>();
+
+        eff_conf_ddr3_vddr_max_limit =
+                 sysTgt->getAttr<
+                    TARGETING::ATTR_MRW_DDR3_VDDR_MAX_LIMIT>();
+    }
+    else
+    {
+        // Use POST_DRAM INIT values
+        eff_conf_ddr3_vddr_slope     = pdi_ddr3_vddr_slope;
+        eff_conf_ddr3_vddr_intercept = pdi_ddr3_vddr_intercept;
+        eff_conf_ddr3_vddr_max_limit = pdi_ddr3_vddr_max_limit;
+    }
+
+    nodeTgt->setAttr<TARGETING::ATTR_MSS_VOLT_DDR3_VDDR_SLOPE_EFF_CONFIG>\
+             (eff_conf_ddr3_vddr_slope);
+
+    nodeTgt->setAttr<TARGETING::ATTR_MSS_VOLT_DDR3_VDDR_INTERCEPT_EFF_CONFIG>\
+             (eff_conf_ddr3_vddr_intercept);
+
+    nodeTgt->setAttr<TARGETING::ATTR_MRW_DDR3_VDDR_MAX_LIMIT_EFF_CONFIG>\
+             (eff_conf_ddr3_vddr_max_limit);
+
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,"set_eff_config_attrs_helper: "
+               "DDR3 _EFF_CONFIG(%d, %d): slope=%d, intercept=%d, max_limit=%d",
+               i_base, o_post_dram_inits_found,
+               eff_conf_ddr3_vddr_slope,
+               eff_conf_ddr3_vddr_intercept,
+               eff_conf_ddr3_vddr_max_limit);
+
+
+    // -----------------------------------
+    // EFF CONFIG: DDR4 VDDR
+    if ( o_post_dram_inits_found == false )
+    {
+        // Use default system value
+        eff_conf_ddr4_vddr_slope =
+                 sysTgt->getAttr<TARGETING::ATTR_MSS_VOLT_DDR4_VDDR_SLOPE>();
+
+        eff_conf_ddr4_vddr_intercept =
+                 sysTgt->getAttr<
+                         TARGETING::ATTR_MSS_VOLT_DDR4_VDDR_INTERCEPT>();
+
+        eff_conf_ddr4_vddr_max_limit =
+                 sysTgt->getAttr<
+                    TARGETING::ATTR_MRW_DDR4_VDDR_MAX_LIMIT>();
+    }
+    else
+    {
+        // Use POST_DRAM INIT value
+        eff_conf_ddr4_vddr_slope     = pdi_ddr4_vddr_slope;
+        eff_conf_ddr4_vddr_intercept = pdi_ddr4_vddr_intercept;
+        eff_conf_ddr4_vddr_max_limit = pdi_ddr4_vddr_max_limit;
+    }
+    nodeTgt->setAttr<TARGETING::ATTR_MSS_VOLT_DDR4_VDDR_SLOPE_EFF_CONFIG>\
+             (eff_conf_ddr4_vddr_slope);
+
+    nodeTgt->setAttr<TARGETING::ATTR_MSS_VOLT_DDR4_VDDR_INTERCEPT_EFF_CONFIG>\
+             (eff_conf_ddr4_vddr_intercept);
+
+    nodeTgt->setAttr<TARGETING::ATTR_MRW_DDR4_VDDR_MAX_LIMIT_EFF_CONFIG>\
+             (eff_conf_ddr4_vddr_max_limit);
+
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,"set_eff_config_attrs_helper: "
+               "DDR4 _EFF_CONFIG(%d, %d): slope=%d, intercept=%d, max_limit=%d",
+               i_base, o_post_dram_inits_found,
+               eff_conf_ddr4_vddr_slope,
+               eff_conf_ddr4_vddr_intercept,
+               eff_conf_ddr4_vddr_max_limit);
+
+    // -----------------------------------
+    // EFF CONFIG: VPP
+    if ( o_post_dram_inits_found == false )
+    {
+        // Use default system value
+        eff_conf_vpp_slope =
+                 sysTgt->getAttr<TARGETING::ATTR_MSS_VOLT_VPP_SLOPE>();
+
+        eff_conf_vpp_intercept =
+                 sysTgt->getAttr<
+                         TARGETING::ATTR_MSS_VOLT_VPP_INTERCEPT>();
+    }
+    else
+    {
+        // Use POST_DRAM INIT value
+        eff_conf_vpp_slope     = pdi_vpp_slope;
+        eff_conf_vpp_intercept = pdi_vpp_intercept;
+    }
+    nodeTgt->setAttr<TARGETING::ATTR_MSS_VOLT_VPP_SLOPE_EFF_CONFIG>\
+             (eff_conf_vpp_slope);
+
+    nodeTgt->setAttr<TARGETING::ATTR_MSS_VOLT_VPP_INTERCEPT_EFF_CONFIG>\
+             (eff_conf_vpp_intercept);
+
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,"set_eff_config_attrs_helper: "
+               "VPP _EFF_CONFIG(%d, %d): slope=%d, intercept=%d",
+               i_base, o_post_dram_inits_found,
+               eff_conf_vpp_slope,
+               eff_conf_vpp_intercept);
+
+
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+               "set_eff_config_attrs_helper: setting _EFF_CONFIG "
+               "attributes exit");
+
+}
+
 //
 //  Wrapper function to call host_collect_dimm_spd
 //
@@ -528,6 +752,10 @@ void* call_mss_volt( void *io_pArgs )
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_volt entry" );
 
+    // Check that VPP, DDR3 VDDR, and DDR4 VDDR _EFF_CONFIG attributes are set
+    bool unused = false;
+    set_eff_config_attrs_helper(DEFAULT, unused);
+
     TARGETING::TargetHandleList l_membufTargetList;
     getAllChips(l_membufTargetList, TYPE_MEMBUF);
 
diff --git a/src/usr/hwpf/hwp/mc_config/mc_config.H b/src/usr/hwpf/hwp/mc_config/mc_config.H
index 12b25b36c..8e53cdbd1 100644
--- a/src/usr/hwpf/hwp/mc_config/mc_config.H
+++ b/src/usr/hwpf/hwp/mc_config/mc_config.H
@@ -5,7 +5,9 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
 /*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
@@ -180,6 +182,32 @@ void*    call_mss_eff_config( void * io_pArgs );
 void*    call_mss_attr_update( void *io_pArgs );
 
 
+/**
+ *  @brief Enum specifying what attributes should be used to set the
+ *         memory _EFF_CONFIG attributes
+ *
+ */
+enum EFF_CONFIG_ATTRIBUTES_BASE
+{
+    DEFAULT         = 0x00, ///< Use System Defaults
+    POST_DRAM_INIT  = 0x01, ///< Use POST_DRAM_INIT attributes if non-zero
+};
+
+
+/**
+ * @brief  Helper function to set memory _EFF_CONFIG attributes for HWPs
+ *
+ *  param[in]  i_base - Determines base of EFF_CONFIG attributes values
+ *
+ *  param[out] o_post_dram_inits_found - if i_base==POST_DRAM_INIT and
+ *                                          POST_DRAM_INIT attributes were
+ *                                          found return TRUE;
+ *                                       else, return FALSE
+ */
+void set_eff_config_attrs_helper( const EFF_CONFIG_ATTRIBUTES_BASE i_base,
+                                  bool & o_post_dram_inits_found);
+
+
 };   // end namespace
 
 #endif
diff --git a/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vcs_offset.C b/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vcs_offset.C
index daeb4bcc0..5fd0ed7d4 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vcs_offset.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vcs_offset.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_volt_vcs_offset.C,v 1.7 2014/06/19 16:06:11 dcadiga Exp $
+// $Id: mss_volt_vcs_offset.C,v 1.8 2015/07/22 14:15:46 sglancy Exp $
 /* File mss_volt_vcs_offset.C created by Stephen Glancy on Tue 20 May 2014. */
 
 //------------------------------------------------------------------------------
@@ -45,6 +45,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:   | Comment:
 //---------|----------|----------|-----------------------------------------------
+//  1.8    | sglancy  | 03/24/15 | Updated for 2Z/3Z ATTR update
 //  1.7    | sglancy  | 06/19/14 | Includes update to force the VCS to be 100 mV higher than the VDD
 //  1.6    | sglancy  | 06/18/14 | Updated errors
 //  1.5    | sglancy  | 06/09/14 | Updated debug statements
@@ -90,12 +91,14 @@ fapi::ReturnCode mss_volt_vcs_offset(std::vector<fapi::Target> & i_targets)
     }
     
     //computes vcs value
-    //gets the necessary attributes and checks for errors
-    l_rc = FAPI_ATTR_GET(ATTR_MSS_VCS_SLOPE_ACTIVE,NULL,slope_active); 
+    //gets the necessary attributes and checks for errors - attributes should be the same accross each node
+    //attributes are stored at the centaur level, only the first centaur in the vector is grabbed
+    // this code should only be called with 1 or more centaur's configured, so this is a valid assumption to make
+    l_rc = FAPI_ATTR_GET(ATTR_MSS_VCS_SLOPE_ACTIVE,&i_targets[0],slope_active);
     if(l_rc) return l_rc;
-    l_rc = FAPI_ATTR_GET(ATTR_MSS_VCS_SLOPE_INACTIVE,NULL,slope_inactive); 
+    l_rc = FAPI_ATTR_GET(ATTR_MSS_VCS_SLOPE_INACTIVE,&i_targets[0],slope_inactive);
     if(l_rc) return l_rc;
-    l_rc = FAPI_ATTR_GET(ATTR_MSS_VCS_SLOPE_INTERCEPT,NULL,intercept); 
+    l_rc = FAPI_ATTR_GET(ATTR_MSS_VCS_SLOPE_INTERCEPT,&i_targets[0],intercept);
     if(l_rc) return l_rc;
 
     //checks to make sure that none of the values are zeros.  If any of the values are 0's then 0 * any other value = 0
diff --git a/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vdd_offset.C b/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vdd_offset.C
index 3fa305d0c..950ebd6fb 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vdd_offset.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vdd_offset.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_volt_vdd_offset.C,v 1.6 2014/06/18 20:34:34 dcadiga Exp $
+// $Id: mss_volt_vdd_offset.C,v 1.7 2015/07/22 14:15:53 sglancy Exp $
 /* File mss_volt_vdd_offset.C created by Stephen Glancy on Tue 20 May 2014. */
 
 //------------------------------------------------------------------------------
@@ -45,6 +45,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:   | Comment:
 //---------|----------|----------|-----------------------------------------------
+//  1.7    | sglancy  | 03/24/15 | Updated for 2Z/3Z ATTR update
 //  1.6    | sglancy  | 06/18/14 | Updated error flags
 //  1.5    | sglancy  | 06/09/14 | Updated debug statements
 //  1.4    | sglancy  | 06/04/14 | Updated to include output attribute
@@ -89,12 +90,14 @@ fapi::ReturnCode mss_volt_vdd_offset(std::vector<fapi::Target> & i_targets)
     }
 
     //computes vdd value
-    //gets the necessary attributes and checks for errors
-    l_rc = FAPI_ATTR_GET(ATTR_MSS_VDD_SLOPE_ACTIVE,NULL,slope_active); 
+    //gets the necessary attributes and checks for errors - attributes should be the same accross each node
+    //attributes are stored at the centaur level, only the first centaur in the vector is grabbed
+    // this code should only be called with 1 or more centaur's configured, so this is a valid assumption to make
+    l_rc = FAPI_ATTR_GET(ATTR_MSS_VDD_SLOPE_ACTIVE,&i_targets[0],slope_active);
     if(l_rc) return l_rc;
-    l_rc = FAPI_ATTR_GET(ATTR_MSS_VDD_SLOPE_INACTIVE,NULL,slope_inactive); 
+    l_rc = FAPI_ATTR_GET(ATTR_MSS_VDD_SLOPE_INACTIVE,&i_targets[0],slope_inactive);
     if(l_rc) return l_rc;
-    l_rc = FAPI_ATTR_GET(ATTR_MSS_VDD_SLOPE_INTERCEPT,NULL,intercept); 
+    l_rc = FAPI_ATTR_GET(ATTR_MSS_VDD_SLOPE_INTERCEPT,&i_targets[0],intercept);
     if(l_rc) return l_rc;
     
     //checks to make sure that none of the values are zeros.  If any of the values are 0's then 0 * any other value = 0
diff --git a/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vddr_offset.C b/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vddr_offset.C
index 15540644c..120a0212b 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vddr_offset.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vddr_offset.C
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_volt_vddr_offset.C,v 1.24 2015/01/21 18:13:30 sglancy Exp $
+// $Id: mss_volt_vddr_offset.C,v 1.25 2015/07/22 14:16:02 sglancy Exp $
 /* File mss_volt_vddr_offset.C created by Stephen Glancy on Tue 20 May 2014. */
 
 //------------------------------------------------------------------------------
@@ -45,6 +45,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:   | Comment:
 //---------|----------|----------|-----------------------------------------------
+//  1.25   | sglancy  | 07/22/15 | Updates for 2z/3z and DDR4
 //  1.24   | sglancy  | 01/21/15 | Updated for addition of ATTR_CENTAUR_EC_DISABLE_VDDR_DYNAMIC_VID
 //  1.23   | sglancy  | 11/20/14 | Updated for rounding
 //  1.22   | sglancy  | 11/20/14 | Fixed compile issue
@@ -235,20 +236,20 @@ fapi::ReturnCode mss_volt_vddr_offset(std::vector<fapi::Target> & i_targets)
     
     //gets the attributes and computes var_power_on based upon whether the DRAM type is DDR3 or DDR4
     if(dram_gen == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) {
-       l_rc = FAPI_ATTR_GET(ATTR_MSS_DDR3_VDDR_SLOPE,NULL,volt_slope); 
+       l_rc = FAPI_ATTR_GET(ATTR_MSS_DDR3_VDDR_SLOPE,&i_targets[0],volt_slope);
        if(l_rc) return l_rc;
-       l_rc = FAPI_ATTR_GET(ATTR_MSS_DDR3_VDDR_INTERCEPT,NULL,volt_intercept); 
+       l_rc = FAPI_ATTR_GET(ATTR_MSS_DDR3_VDDR_INTERCEPT,&i_targets[0],volt_intercept);
        if(l_rc) return l_rc;
-       l_rc = FAPI_ATTR_GET(ATTR_MRW_DDR3_VDDR_MAX_LIMIT,NULL,vddr_max_limit_mv); 
+       l_rc = FAPI_ATTR_GET(ATTR_MRW_DDR3_VDDR_MAX_LIMIT,&i_targets[0],vddr_max_limit_mv);
        if(l_rc) return l_rc;
     }
     //ddr4
     else {
-       l_rc = FAPI_ATTR_GET(ATTR_MSS_DDR4_VDDR_SLOPE,NULL,volt_slope); 
+       l_rc = FAPI_ATTR_GET(ATTR_MSS_DDR4_VDDR_SLOPE,&i_targets[0],volt_slope);
        if(l_rc) return l_rc;
-       l_rc = FAPI_ATTR_GET(ATTR_MSS_DDR4_VDDR_INTERCEPT,NULL,volt_intercept); 
+       l_rc = FAPI_ATTR_GET(ATTR_MSS_DDR4_VDDR_INTERCEPT,&i_targets[0],volt_intercept);
        if(l_rc) return l_rc;
-       l_rc = FAPI_ATTR_GET(ATTR_MRW_DDR4_VDDR_MAX_LIMIT,NULL,vddr_max_limit_mv); 
+       l_rc = FAPI_ATTR_GET(ATTR_MRW_DDR4_VDDR_MAX_LIMIT,&i_targets[0],vddr_max_limit_mv);
        if(l_rc) return l_rc;
     }
     
diff --git a/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vpp_offset.C b/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vpp_offset.C
index 26ef2938e..b8740823b 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vpp_offset.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt_vpp_offset.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_volt_vpp_offset.C,v 1.18 2014/09/12 15:37:51 sglancy Exp $
+// $Id: mss_volt_vpp_offset.C,v 1.20 2015/07/22 14:15:06 sglancy Exp $
 /* File mss_volt_vpp_offset.C created by Stephen Glancy on Tue 20 May 2014. */
 
 //------------------------------------------------------------------------------
@@ -45,6 +45,8 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:   | Comment:
 //---------|----------|----------|-----------------------------------------------
+//  1.20   | sglancy  | 07/22/15 | DDR4 updates allowing both DDR3 and DDR4 DIMMs on the same VPP plane
+//  1.19   | sglancy  | 04/21/15 | Added support for mixed voltage plane configurations.  still checks for mixed centaur bugs
 //  1.18   | sglancy  | 09/12/14 | Removed references to EFF attributes
 //  1.17   | sglancy  | 09/12/14 | Fixed bugs
 //  1.16   | sglancy  | 09/11/14 | Fixed bugs
@@ -90,13 +92,16 @@ fapi::ReturnCode mss_volt_vpp_offset(std::vector<fapi::Target> & i_targets)
     uint32_t vpp_slope, vpp_intercept;
     uint8_t dram_width, enable, dram_gen;
     uint8_t cur_dram_gen, is_functional; 
+    bool dram_gen_found_mc = false;
     bool dram_gen_found = false;
+    bool dram_gen_ddr4 = false;
     uint8_t num_spares[2][2][4];
     uint8_t rank_config, num_non_functional;
     num_non_functional = 0;
     std::vector<fapi::Target>  l_mbaChiplets;
     std::vector<fapi::Target>  l_dimm_targets;
-    
+    std::vector<uint8_t> dram_gen_vector; //used to ID whether an MC needs to be used in the VPP offset calculations
+
     //checks to make sure that all of the DRAM generation attributes are the same, if not error out
     for(uint32_t i = 0; i < i_targets.size();i++) {
        //gets the functional attribute to check for an active centaur
@@ -108,7 +113,9 @@ fapi::ReturnCode mss_volt_vpp_offset(std::vector<fapi::Target> & i_targets)
        if(is_functional != fapi::ENUM_ATTR_FUNCTIONAL_FUNCTIONAL) {
           num_non_functional++;
        }
-       
+
+       dram_gen_found_mc = false;
+
        //loops through all MBA chiplets to compare the DRAM technology generation attribute
        l_mbaChiplets.clear();
        l_rc=fapiGetChildChiplets(i_targets[i], fapi::TARGET_TYPE_MBA_CHIPLET, l_mbaChiplets, fapi::TARGET_STATE_PRESENT);
@@ -147,12 +154,13 @@ fapi::ReturnCode mss_volt_vpp_offset(std::vector<fapi::Target> & i_targets)
 	     }
 	     //if this is the first DIMM that has a valid DRAM Technology level, then set the level and continue
 	     //otherwise throw an error and exit
-	     if(!dram_gen_found) {
+	     if(!dram_gen_found_mc) {
 	        dram_gen = cur_dram_gen;
 		dram_gen_found = true;
+		dram_gen_found_mc = true;
 	     } //end if
 	     else {
-	        //values are not equal -> set the fapi RC and exit out
+	        //values are not equal for one given centaur -> set the fapi RC and exit out
     	  	if(cur_dram_gen != dram_gen){
     	  	   // this just needs to be deconfiged at the dimm level
     	  	   const uint8_t &DRAM_GEN_MISCOMPARE = cur_dram_gen;
@@ -163,9 +171,23 @@ fapi::ReturnCode mss_volt_vpp_offset(std::vector<fapi::Target> & i_targets)
     	  	   FAPI_ERR("Not all DRAM technology generations are the same.\nExiting....");
     	  	   return l_rc;
     	  	}//end if
+		//is a DDR4 type, go and set the DDR4 flag -> means that the vpp offset flag will be set
+		if(cur_dram_gen == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) {
+		   dram_gen_ddr4 = true;
+		}
 	     }//end else
 	  }
        }//end for
+
+       //if a DRAM gen was not found for this MC, then assume that this is a DDR4 DIMM to err on the side of caution
+       //please note: dram_gen_ddr4 flag is not set here intentionally, this is because the voltage offset is only desirable if a card is confirmed as DDR4
+       if(!dram_gen_found_mc) {
+          dram_gen_vector.push_back(fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4);
+       }
+       //otherwise, do the current DRAM gen for the card
+       else {
+          dram_gen_vector.push_back(cur_dram_gen);
+       }
     }//end for
     
     //found a bad VPD
@@ -189,7 +211,7 @@ fapi::ReturnCode mss_volt_vpp_offset(std::vector<fapi::Target> & i_targets)
     }
     
     //checks to see if the DIMMs are DDR3 DIMMs if so, return 0 and exit
-    if(dram_gen == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) {
+    if(!dram_gen_ddr4) {
        uint32_t param_vpp_voltage_mv = 0; 
        //debug output statement
        FAPI_INF("ATTR_MSS_VPP_OFFSET: %d",param_vpp_voltage_mv);
@@ -210,9 +232,9 @@ fapi::ReturnCode mss_volt_vpp_offset(std::vector<fapi::Target> & i_targets)
     if(enable == fapi::ENUM_ATTR_MSS_VPP_OFFSET_DISABLE_DISABLE) return l_rc;
 
     //gets the slope and intercepts
-    l_rc = FAPI_ATTR_GET(ATTR_MSS_VPP_SLOPE,NULL,vpp_slope); 
+    l_rc = FAPI_ATTR_GET(ATTR_MSS_VPP_SLOPE,&i_targets[0],vpp_slope);
     if(l_rc) return l_rc;
-    l_rc = FAPI_ATTR_GET(ATTR_MSS_VPP_SLOPE_INTERCEPT,NULL,vpp_intercept); 
+    l_rc = FAPI_ATTR_GET(ATTR_MSS_VPP_SLOPE_INTERCEPT,&i_targets[0],vpp_intercept);
     if(l_rc) return l_rc;
     //checks to make sure that none of the values are zeros.  If any of the values are 0's then 0 * any other value = 0
     if((vpp_slope * vpp_intercept) == 0) {
@@ -222,12 +244,15 @@ fapi::ReturnCode mss_volt_vpp_offset(std::vector<fapi::Target> & i_targets)
        FAPI_ERR("One or more dynamic VPP attributes is 0.\nExiting....");
        return l_rc;
     }
-    
+
 
     //continues computing VPP for DDR4
     //loops through all DIMMs
     num_chips=0;
     for(uint32_t i=0;i<i_targets.size();i++) {
+       //skips the curent target if it's not DDR4 (no DRAMs drawing power)
+       if(dram_gen_vector[i] != fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) continue;
+
        //resets the number of ranks and spares
        l_mbaChiplets.clear();
        l_rc=fapiGetChildChiplets(i_targets[i], fapi::TARGET_TYPE_MBA_CHIPLET, l_mbaChiplets, fapi::TARGET_STATE_PRESENT);