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| author | Prachi Gupta <pragupta@us.ibm.com> | 2015-03-10 11:49:45 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2015-03-11 22:04:14 -0500 |
| commit | df4522fe41d2857238861d8dec260fd4fa6aba38 (patch) | |
| tree | 270518f0adf511f42475faded667f8a8d292a15b /src/usr/hwpf/hwp/initfiles | |
| parent | e4a5d4324e63004760c0105733242b7d3c0ac406 (diff) | |
| download | talos-hostboot-df4522fe41d2857238861d8dec260fd4fa6aba38.tar.gz talos-hostboot-df4522fe41d2857238861d8dec260fd4fa6aba38.zip | |
SW292676: INITPROC: FSP&Hostboot - Catch up file versions - no function
Change-Id: I5b18c640be03572ccf802a91f46b2acd15238d3f
CQ:SW292676
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/15465
Reviewed-by: PRACHI GUPTA <pragupta@us.ibm.com>
Reviewed-by: Sangeetha T S <sangeet2@in.ibm.com>
Tested-by: Sangeetha T S <sangeet2@in.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/16273
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp/initfiles')
| -rwxr-xr-x | src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile index 843606996..b7b5e5beb 100755 --- a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile +++ b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile @@ -1,4 +1,4 @@ -#-- $Id: cen_ddrphy.initfile,v 1.33 2014/05/14 21:04:08 asaetow Exp $ +#-- $Id: cen_ddrphy.initfile,v 1.35 2014/05/28 14:46:21 asaetow Exp $ #-- $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/ #-- centaur/working/procedures/ec_ind/scoms/cen_ddrphy.initfile,v $ # @@ -6,6 +6,9 @@ #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +# 1.35 |asaetow |05/28/14| Removed v1.34 from working since we will not be GAing with those settings. +# | | | NOTE: Re-evaluation in progress on PLL settings for SP1. +# 1.34 |asaetow |05/22/14| Changed ADR/DP18 PLL charge pump setting from 33x3=99uA to 66x2=132uA. Based on Qual FA sample data's potential DTMOAT leakage suspect Lot7DVBT. # 1.33 |asaetow |05/14/14| Changed ADR/DP18 VCO bit61 from 0b1 to 0b0 and PLL_TUNEF bit54 from 0b1 to 0b0 to dampen noise. Based on Qual FA sample data. # | | | Note bit61 is VCO low range from >700MHz to <700MHz. # | | | Note bit54 is Cap from 2.5pF to 1.0pF. |
