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| author | Thi Tran <thi@us.ibm.com> | 2014-07-03 08:28:12 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-07-14 13:35:03 -0500 |
| commit | a7b87425064656ef3e81c17202b9a075ed1cabe8 (patch) | |
| tree | c42d995e9af6b9c0a797a82325c92420a851f87e /src/usr/hwpf/hwp/initfiles | |
| parent | 4d09b1c7db50af535e5b84e0bf848c3bba82e4d8 (diff) | |
| download | talos-hostboot-a7b87425064656ef3e81c17202b9a075ed1cabe8.tar.gz talos-hostboot-a7b87425064656ef3e81c17202b9a075ed1cabe8.zip | |
FW624741: Tuleta:Centaur: Trace Arrays Do Not Stop on Checkstop
Change-Id: I11181b8242afe2ff284d13c08d40c3476431e9a9
CQ:FW624741
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11971
Tested-by: Jenkins Server
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp/initfiles')
| -rw-r--r-- | src/usr/hwpf/hwp/initfiles/mbs_def.initfile | 37 |
1 files changed, 35 insertions, 2 deletions
diff --git a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile index d58633cb5..f8653137a 100644 --- a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile +++ b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile @@ -1,8 +1,9 @@ -#-- $Id: mbs_def.initfile,v 1.48 2014/05/20 20:37:38 baysah Exp $ +#-- $Id: mbs_def.initfile,v 1.49 2014/06/11 20:01:29 yctschan Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.49 |tschang | 6/10/14| Enabled clock stop on xstop for the trace arrays FW624741 #-- 1.48 |baysah |04/21/14| Added L4 Cleaner settings per rank group to improve memory performance #-- 1.47 |tschang | 3/19/14| SW252733 - L4 Cache UE Handling #-- 1.46 |tschang | 3/19/14| SW252733 - L4 Cache UE Handling typo @@ -421,11 +422,43 @@ define def_num_mbs_ranks = (MBA0.ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + MBA0.ATTR_E #--****************************************************************************** # scom 0x02011403 { # bits , scom_data ; -# 8 , 0b1 ; # int_parity_error - HW244827 and HW251643 +# 8 , 0b1 ; # int_parity_error - HW244827 and HW251643 # # } #--****************************************************************************** +#-- TRACE clock stop on checkstop MBA +#--****************************************************************************** +# TCM.EPS.DBG.DBG_MODE_REG + scom 0x03012300 { + bits , scom_data , ATTR_FUNCTIONAL, expr; + 7 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_TRACE_ARRAY_CLKSTOP_ON_XSTOP_FW624741 == 1); # EC2.0 or greater enable + } + +# TCM.EPS.DBG.DBG_TRACE_MODE_REG_2 + scom 0x0301230B { + bits , scom_data , ATTR_FUNCTIONAL, expr; + 17 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_TRACE_ARRAY_CLKSTOP_ON_XSTOP_FW624741 == 1); # EC2.0 or greater enable + } + + + +#--****************************************************************************** +#-- TRACE clock stop on checkstop MBS +#--****************************************************************************** +# TCN.EPS.DBG.DBG_MODE_REG + scom 0x02012300 { + bits , scom_data , ATTR_FUNCTIONAL, expr; + 7 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_TRACE_ARRAY_CLKSTOP_ON_XSTOP_FW624741 == 1); # EC2.0 or greater enable + } + +# TCN.EPS.DBG.DBG_TRACE_MODE_REG_2 + scom 0x0201230B { + bits , scom_data , ATTR_FUNCTIONAL, expr; + 17 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_TRACE_ARRAY_CLKSTOP_ON_XSTOP_FW624741 == 1); # EC2.0 or greater enable + } + +#--****************************************************************************** # HW246685 : Need RCE FIR bit if NCE/SCE/MPE/MCE on 2nd try # - Want to be able to see RCE reported even if we also have chip marks or symbol marks in place. # - To enable maint fix: set MBSTR(60)=1 to see the RCE in conjunction with the other errors |
