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| author | Josh Rispoli <jprispol@us.ibm.com> | 2014-08-15 13:12:41 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-08-27 16:06:45 -0500 |
| commit | 2aad6ac78e4ec5234b73646a211f16ec735bc3ef (patch) | |
| tree | 447c19bc3b42d63b9bb10f80857f585239e3ab8c /src/usr/hwpf/hwp/initfiles | |
| parent | ccf211bac5536dfed34a382ef612fc27dccda56c (diff) | |
| download | talos-hostboot-2aad6ac78e4ec5234b73646a211f16ec735bc3ef.tar.gz talos-hostboot-2aad6ac78e4ec5234b73646a211f16ec735bc3ef.zip | |
FW626918: INITPROC: restore support for IPL with deconfigured MBA
Change-Id: Ifb0ba11bc09bc6b6291c6b221d51c7532ba658f8
CQ:FW626918
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/12843
Reviewed-by: MATTHEW A. PLOETZ <maploetz@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/12845
Reviewed-by: Joshua P. Rispoli <jprispol@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp/initfiles')
| -rw-r--r-- | src/usr/hwpf/hwp/initfiles/mbs_def.initfile | 59 |
1 files changed, 41 insertions, 18 deletions
diff --git a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile index f8653137a..2c0b762c4 100644 --- a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile +++ b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile @@ -1,8 +1,9 @@ -#-- $Id: mbs_def.initfile,v 1.49 2014/06/11 20:01:29 yctschan Exp $ +#-- $Id: mbs_def.initfile,v 1.50 2014/08/12 14:22:13 yctschan Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.50 |tschang | 8/06/14| FW626918 - Changed L4 Cleaner settings per rank group to be able to handle deconfigured MBAs #-- 1.49 |tschang | 6/10/14| Enabled clock stop on xstop for the trace arrays FW624741 #-- 1.48 |baysah |04/21/14| Added L4 Cleaner settings per rank group to improve memory performance #-- 1.47 |tschang | 3/19/14| SW252733 - L4 Cache UE Handling @@ -413,6 +414,8 @@ define def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated = (def_mb #define def_mba01_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[0][1]); #define def_mba23_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][1]); define def_num_mbs_ranks = (MBA0.ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + MBA0.ATTR_EFF_NUM_RANKS_PER_DIMM[0][1] + MBA1.ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] + MBA1.ATTR_EFF_NUM_RANKS_PER_DIMM[1][1]); +define def_num_mba01_ranks = (MBA0.ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + MBA0.ATTR_EFF_NUM_RANKS_PER_DIMM[0][1]); +define def_num_mba23_ranks = (MBA1.ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] + MBA1.ATTR_EFF_NUM_RANKS_PER_DIMM[1][1]); @@ -612,11 +615,6 @@ scom 0x0201140F { #29:34 , 0x6 , any ; # MBCCFGQ_cln_wr_priority_wrq_lwmark_0_5 #35:48 , 0x1000 , any ; # MBCCFGQ_cln_wr_priority_dv_hwmark_0_13 #49:62 , 0x0FC0 , any ; # MBCCFGQ_cln_wr_priority_dv_lwmark_0_13 - 13:16 , 0b1111 , ( (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && ((def_num_mbs_ranks == 2 ) || (def_num_mbs_ranks == 4)) ); # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 is 15 for 2 and 4 rnkgrp - 13:16 , 0b0111 , ( (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mbs_ranks == 8 ) ); # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 is 7 for 8 rnkgrp - 17:22 , 0b100000 , ( (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mbs_ranks == 2 ) ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 32 for 2 rnkgrp - 17:22 , 0b010000 , ( (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mbs_ranks == 4 ) ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 16 for 4 rnkgrp - 17:22 , 0b001000 , ( (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mbs_ranks == 8 ) ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 8 for 8 rnkgrp 23:28 , 0b000111 , any ; # MBCCFGQ_cln_wr_priority_wrq_hwmark_0_5 is 7 for all rank groups 29:34 , 0b000110 , any ; # MBCCFGQ_cln_wr_priority_wrq_lwmark_0_5 is 6 for all rank groups 35:48 , 0b00001000000000 , any ; # MBCCFGQ_cln_wr_priority_dv_hwmark_0_13 is 512 for all rank groups @@ -624,6 +622,25 @@ scom 0x0201140F { } +scom 0x0201140F { + bits, scom_data , MBA0.ATTR_FUNCTIONAL, MBA1.ATTR_FUNCTIONAL, expr; + 13:16 , 0b1111 , 1 , 1 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && ((def_num_mbs_ranks == 2 ) || (def_num_mbs_ranks == 4)); # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 is 15 for 2 and 4 rnkgrp + 13:16 , 0b0111 , 1 , 1 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mbs_ranks == 8 ); # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 is 7 for 8 rnkgrp + 13:16 , 0b1111 , 1 , 0 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && ((def_num_mba01_ranks == 1 ) || (def_num_mba01_ranks == 2)); # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 is 15 for 2 and 4 rnkgrp + 13:16 , 0b0111 , 1 , 0 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mba01_ranks == 4 ); # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 is 7 for 8 rnkgrp + 13:16 , 0b1111 , 0 , 1 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && ((def_num_mba23_ranks == 1 ) || (def_num_mba23_ranks == 2)); # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 is 15 for 2 and 4 rnkgrp + 13:16 , 0b0111 , 0 , 1 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mba23_ranks == 4 ); # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 is 7 for 8 rnkgrp + 17:22 , 0b100000 , 1 , 1 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mbs_ranks == 2 ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 32 for 2 rnkgrp + 17:22 , 0b100000 , 1 , 0 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mba01_ranks == 1 ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 32 for 2 rnkgrp + 17:22 , 0b100000 , 0 , 1 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mba23_ranks == 1 ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 32 for 2 rnkgrp + 17:22 , 0b010000 , 1 , 1 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mbs_ranks == 4 ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 16 for 4 rnkgrp + 17:22 , 0b010000 , 1 , 0 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mba01_ranks == 2 ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 32 for 2 rnkgrp + 17:22 , 0b010000 , 0 , 1 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mba23_ranks == 2 ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 32 for 2 rnkgrp + 17:22 , 0b001000 , 1 , 1 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mbs_ranks == 8 ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 8 for 8 rnkgrp + 17:22 , 0b001000 , 1 , 0 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mba01_ranks == 4 ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 32 for 2 rnkgrp + 17:22 , 0b001000 , 0 , 1 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mba23_ranks == 4 ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 32 for 2 rnkgrp +} + ######################################## #MBA Swizzle Control Register (MBAXCRMS) ######################################## @@ -658,18 +675,24 @@ scom 0x0201140D { # MBSXCRQ MBS Address Translate Control Register # address interleave mode scom 0x0201140A { - bits, scom_data , expr; - 0:4 , 0b00000 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 0) || (MBA0.ATTR_FUNCTIONAL == 0) || (MBA1.ATTR_FUNCTIONAL == 0); # no MBA interleave - 0:4 , 0b10000 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 23) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # - 0:4 , 0b10001 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 24) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # - 0:4 , 0b10010 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 25) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # - 0:4 , 0b10011 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 26) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # - 0:4 , 0b10100 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 27) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # - 0:4 , 0b10101 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 28) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # - 0:4 , 0b10110 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 29) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # - 0:4 , 0b10111 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 30) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # - 0:4 , 0b11000 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 31) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # - 0:4 , 0b11001 , (ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 32) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1); # + bits, scom_data ,MBA0.ATTR_FUNCTIONAL, MBA1.ATTR_FUNCTIONAL, expr; + 0:4 , 0b00000 , 0 , 0 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 0) ; # no MBA interleave + 0:4 , 0b00000 , 0 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 0) ; # no MBA interleave + 0:4 , 0b00000 , 1 , 0 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 0) ; # no MBA interleave + 0:4 , 0b10000 , 1 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 23); # + 0:4 , 0b10001 , 1 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 24); # + 0:4 , 0b10010 , 1 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 25); # + 0:4 , 0b10011 , 1 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 26); # + 0:4 , 0b10100 , 1 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 27); # + 0:4 , 0b10101 , 1 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 28); # + 0:4 , 0b10110 , 1 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 29); # + 0:4 , 0b10111 , 1 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 30); # + 0:4 , 0b11000 , 1 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 31); # + 0:4 , 0b11001 , 1 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 32); # +} + +scom 0x0201140A { + bits, scom_data , expr; 5 , 0b0 , any ; # Z mode only } |
