SW314773: INITPROC: FSP&Hostboot - HWP updates for Naples that got missed

Change-Id: I46a0067d53efce644b0432433d8f1771d5ee213a
CQ:SW314773
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19206
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: PRACHI GUPTA <pragupta@us.ibm.com>
Tested-by: PRACHI GUPTA <pragupta@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19286
Tested-by: Jenkins Server
Tested-by: Jenkins OP Build CI
Tested-by: Jenkins OP HW
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

2 files changed, 324 insertions, 73 deletions

diff --git a/src/usr/hwpf/hwp/initfiles/p8.npu.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.npu.scom.initfile
index 7371070c4..c297e16c3 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.npu.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.npu.scom.initfile
@@ -1,4 +1,4 @@
-#-- $Id: p8.npu.scom.initfile,v 1.2 2014/12/11 00:24:12 camille Exp $
+#-- $Id: p8.npu.scom.initfile,v 1.6 2015/03/16 14:33:36 lonny Exp $
 #-------------------------------------------------------------------------------
 #--
 #-- (C) Copyright International Business Machines Corp. 2011
@@ -17,12 +17,110 @@ SyntaxVersion = 1
 #--******************************************************************************
 # -- ESNPUFIR
 #--******************************************************************************
-# spy name  ES.NPU.NP_AT.REG.FIR_MASK_REG
+# spy name  ES.NPU.NP_AT.REG.NPU_AT_ERR_HOLD
+# scom 0x0000000008013DA8 {
+#      bits,   	 scom_data        ;
+#     0:63,  	0x0000000000000001      ;
+#     }
+# 
+# # spy name  ES.NPU.NP_AT.REG.FIR_REG
+# scom 0x0000000008013D81 {
+#      bits,   	 scom_data        ;
+#     0:63,  	0x0000000000000000      ;
+#     }
+
+# start up procedure for the dl2tl parity error 
+#mask error bit 27
+# spy name  ES.NPU.NP_AT.REG.FIR_MASK_REG   
 scom 0x0000000008013D83 {
      bits,   	 scom_data        ;
-    0:63,  	0xE0002C02000F5F3F      ;
+    0:63,  	0xE0002C12000F5F3F      ;
+    }
+
+# set the clock speed in the gp0 registers
+# spy name  Perf register to set IOValids for nvlink (bits 54:57) and nvlink ref clock (52) 2:1 nvlink speed (18:19) = 0b01.
+scom 0x0000000008000004 {
+     bits,   	 scom_data        ;
+    0:63,  	0xFFFFDFFFFFFFFFFF      ;
+    }
+
+# # spy name  Perf register to set IOValids for nvlink (bits 54:57) and nvlink ref clock (52) 2:1 nvlink speed (18:19) = 0b01.
+# scom 0x0000000008000005 {
+#      bits,   	 scom_data        ;
+#     0:63,  	0x0000100000000000      ;
+#     }
+# 
+# # turn on the nvlink refclocks
+# # spy name  Perf register to set IOValids for nvlink (bits 54:57) and nvlink ref clock (52) 2:1 nvlink speed (18:19) = 0b01.
+# scom 0x0000000008000005 {
+#      bits,   	 scom_data        ;
+#     0:63,  	0x0000000000000800      ;
+#     }
+
+# turn on the iovalids
+# spy name  Perf register to set IOValids for nvlink (bits 54:57) and nvlink ref clock (52) 2:1 nvlink speed (18:19) = 0b01.
+scom 0x0000000008000005 {
+     bits,   	 scom_data        ;
+    0:63,  	0x0000100000000BC0      ;
+    }
+
+#  clear the first error and c_err_rpt hold registers
+# # spy name  ES.NPU.SL_WRAP0.NTL_WRAP0.NTL_ER_HOLD
+scom 0x0000000008013C29 {
+     bits,   	 scom_data        ;
+    0:63,  	0x0000000000000000      ;
+    }
+
+# spy name  ES.NPU.SL_WRAP0.NTL_WRAP0.NTL_FST_ERR_REG
+scom 0x0000000008013C2A {
+     bits,   	 scom_data        ;
+    0:63,  	0x0000000000000000      ;
+    }
+
+# spy name  ES.NPU.SL_WRAP0.NTL_WRAP1.NTL_ER_HOLD
+scom 0x0000000008013C69 {
+     bits,   	 scom_data        ;
+    0:63,  	0x0000000000000000      ;
+    }
+
+# spy name  ES.NPU.SL_WRAP0.NTL_WRAP1.NTL_FST_ERR_REG
+scom 0x0000000008013C6A {
+     bits,   	 scom_data        ;
+    0:63,  	0x0000000000000000      ;
     }
 
+# spy name  ES.NPU.SL_WRAP2.NTL_WRAP0.NTL_ER_HOLD
+scom 0x0000000008013D29 {
+     bits,   	 scom_data        ;
+    0:63,  	0x0000000000000000      ;
+    }
+
+# spy name  ES.NPU.SL_WRAP2.NTL_WRAP0.NTL_FST_ERR_REG
+scom 0x0000000008013D2A {
+     bits,   	 scom_data        ;
+    0:63,  	0x0000000000000000      ;
+    }
+
+# spy name  ES.NPU.SL_WRAP2.NTL_WRAP1.NTL_ER_HOLD
+scom 0x0000000008013D69 {
+     bits,   	 scom_data        ;
+    0:63,  	0x0000000000000000      ;
+    }
+
+# spy name  ES.NPU.SL_WRAP2.NTL_WRAP1.NTL_FST_ERR_REG
+scom 0x0000000008013D6A {
+     bits,   	 scom_data        ;
+    0:63,  	0x0000000000000000      ;
+    }
+
+
+# unmask error bit 27
+# # spy name  ES.NPU.NP_AT.REG.FIR_MASK_REG
+# scom 0x0000000008013D83 {
+#      bits,   	 scom_data        ;
+#     0:63,  	0xE0002C02000F5F3F      ;
+#     }
+
 # spy name  ES.NPU.NP_AT.REG.FIR_ACTION0_REG
 scom 0x0000000008013D86 {
     bits, 	scom_data        		;
@@ -35,6 +133,26 @@ scom 0x0000000008013D87 {
     0:63,  	0xFFFFFFFFFFFFFFFF      ;
     }
 
+# # spy name  ES.NPU.NP_AT.REG.FIR_WOF_REG
+# scom 0x0000000008013D88 {
+#      bits,   	 scom_data        ;
+#     0:63,  	0x0000000000000000      ;
+#     }
+
+
+# spy name  ES.NPU.NP_AT.REG.NPU_AT_CNFG0
+scom 0x0000000008013DAB {
+   bits,   	 scom_data   	      ;
+    0:63,  	0x0211000043500000      ;
+    }
+
+# If only 1 GPU will need to configure as below.
+# scom 0x0000000008013DAB {
+#    bits,   	 scom_data   	      ;
+#     0:63,  	0x0210000043510000      ;
+#     }
+
+
 # spy name  ES.NPU.NP_AT.REG.NPU_AT_LR_ER    (Lem enable)
 scom 0x0000000008013D9C {
      bits,   	 scom_data        ;
@@ -59,13 +177,105 @@ scom 0x0000000008013D9F {
     0:63,  	0x1CBFC1FCB7F0A000      ;
     }
 
+# spy name  ES.NPU.SL_WRAP0.NP_CQ.NP_CQ_LNK0.NXCQ_SCOM.NX_MISC_CONTROL_REG (hang pulses)
+scom 0x0000000008013C09 {
+    bits  ,  scom_data;
+    4:7   ,  0b0000;  #-- HANG_POLL_SCALE
+    8:11  ,  0b0011;  #-- HANG_DATA_SCALE
+   12:15  ,  0b1011;  #-- HANG_SHM_SCALE
+}
+
+# spy name  ES.NPU.SL_WRAP0.NP_CQ.NP_CQ_LNK1.NXCQ_SCOM.NX_MISC_CONTROL_REG (hang pulses)
+scom 0x0000000008013C49 {
+    bits  ,  scom_data;
+    4:7   ,  0b0000;  #-- HANG_POLL_SCALE
+    8:11  ,  0b0011;  #-- HANG_DATA_SCALE
+   12:15  ,  0b1011;  #-- HANG_SHM_SCALE
+}
+
+# spy name  ES.NPU.SL_WRAP2.NP_CQ.NP_CQ_LNK0.NXCQ_SCOM.NX_MISC_CONTROL_REG (hang pulses)
+scom 0x0000000008013D09 {
+    bits  ,  scom_data;
+    4:7   ,  0b0000;  #-- HANG_POLL_SCALE
+    8:11  ,  0b0011;  #-- HANG_DATA_SCALE
+   12:15  ,  0b1011;  #-- HANG_SHM_SCALE
+}
+
+# spy name  ES.NPU.SL_WRAP2.NP_CQ.NP_CQ_LNK1.NXCQ_SCOM.NX_MISC_CONTROL_REG (hang pulses)
+scom 0x0000000008013D49 {
+    bits  ,  scom_data;
+    4:7   ,  0b0000;  #-- HANG_POLL_SCALE
+    8:11  ,  0b0011;  #-- HANG_DATA_SCALE
+   12:15  ,  0b1011;  #-- HANG_SHM_SCALE
+}
+
+# spy name  ES.NPU.NP_AT.REG.NPU_AT_DEBUG  (Debug/trace control)
+scom 0x0000000008013DA9 {
+     bits,   	 scom_data        ;
+    0:63,  	0x7000000000000000      ;
+    }
+
+# spy name  ES.NPU.NP_AT.REG.NPU_AT_PMU_CTRL    (at pmu counter)
+scom 0x0000000008013DA6 {
+     bits,   	 scom_data        ;
+    0:63,  	0xF210145000000000      ;
+    }
+
+# spy name  ES.NPU.SL_WRAP0.NP_CQ.NP_CQ_LNK0.NXCQ_SCOM.NX_PB_ERR_RPT_0
+# scom 0x0000000008013C00 {
+#      bits,   	 scom_data        ;
+#     0:63,  	0x0000000000000000      ;
+#     }
+# 
+# # spy name  ES.NPU.SL_WRAP0.NP_CQ.NP_CQ_LNK0.NXCQ_SCOM.NX_PB_ERR_RPT_1
+# scom 0x0000000008013C01 {
+#      bits,   	 scom_data        ;
+#     0:63,  	0x0000000000000000      ;
+#     }
+# 
+# # spy name  ES.NPU.SL_WRAP0.NP_CQ.NP_CQ_LNK1.NXCQ_SCOM.NX_PB_ERR_RPT_0
+# scom 0x0000000008013C40 {
+#      bits,   	 scom_data        ;
+#     0:63,  	0x0000000000000000      ;
+#     }
+# 
+# # spy name  ES.NPU.SL_WRAP0.NP_CQ.NP_CQ_LNK1.NXCQ_SCOM.NX_PB_ERR_RPT_1
+# scom 0x0000000008013C41 {
+#      bits,   	 scom_data        ;
+#     0:63,  	0x0000000000000000      ;
+#     }
+# 
+# spy name  ES.NPU.SL_WRAP2.NP_CQ.NP_CQ_LNK0.NXCQ_SCOM.NX_PB_ERR_RPT_0
+# scom 0x0000000008013D00 {
+#      bits,   	 scom_data        ;
+#     0:63,  	0x0000000000000000      ;
+#     }
+# 
+# # spy name  ES.NPU.SL_WRAP2.NP_CQ.NP_CQ_LNK0.NXCQ_SCOM.NX_PB_ERR_RPT_1
+# scom 0x0000000008013D01 {
+#      bits,   	 scom_data        ;
+#     0:63,  	0x0000000000000000      ;
+#     }
+# 
+# # spy name  ES.NPU.SL_WRAP2.NP_CQ.NP_CQ_LNK1.NXCQ_SCOM.NX_PB_ERR_RPT_0
+# scom 0x0000000008013D40 {
+#      bits,   	 scom_data        ;
+#     0:63,  	0x0000000000000000      ;
+#     }
+# 
+# # spy name  ES.NPU.SL_WRAP2.NP_CQ.NP_CQ_LNK1.NXCQ_SCOM.NX_PB_ERR_RPT_1
+# scom 0x0000000008013D41 {
+#      bits,   	 scom_data        ;
+#     0:63,  	0x0000000000000000      ;
+#     }
+# 
 # spy name  ES.NPU.SL_WRAP0.NTL_WRAP0.NTL_PMU_CONTROL (ntl00 pmu counter)
 scom 0x0000000008013C27 {
      bits,   	 scom_data        ;
     0:63,  	0xF21045C200000000      ;
     }
 
-# spy name  ES.NPU.SL_WRAP0.NTL_WRAP1.NTL_PMU_CONTROL (ntl00 pmu counter)
+# spy name  ES.NPU.SL_WRAP0.NTL_WRAP1.NTL_PMU_CONTROL (ntl01 pmu counter)
 scom 0x0000000008013C67 {
      bits,   	 scom_data        ;
     0:63,  	0xF21045C200000000      ;
@@ -77,37 +287,63 @@ scom 0x0000000008013D27 {
     0:63,  	0xF21045C200000000      ;
     }
 
-# spy name  ES.NPU.SL_WRAP2.NTL_WRAP1.NTL_PMU_CONTROL (ntl20 pmu counter)
+# spy name  ES.NPU.SL_WRAP2.NTL_WRAP1.NTL_PMU_CONTROL (ntl21 pmu counter)
 scom 0x0000000008013D67 {
      bits,   	 scom_data        ;
     0:63,  	0xF21045C200000000      ;
     }
 
-# spy name  ES.NPU.NP_AT.REG.NPU_AT_PMU_CTRL    (at pmu counter)
-scom 0x0000000008013DA6 {
-     bits,   	 scom_data        ;
-    0:63,  	0xF210145000000000      ;
-    }
+# # spy name  ES.NPU.SL_WRAP0.NTL_WRAP0.NTL_ER_HOLD
+# scom 0x0000000008013C29 {
+#      bits,   	 scom_data        ;
+#     0:63,  	0x0000000000000000      ;
+#     }
+# 
+# # spy name  ES.NPU.SL_WRAP0.NTL_WRAP0.NTL_FST_ERR_REG
+# scom 0x0000000008013C2A {
+#      bits,   	 scom_data        ;
+#     0:63,  	0x0000000000000000      ;
+#     }
+# 
+# # spy name  ES.NPU.SL_WRAP0.NTL_WRAP1.NTL_ER_HOLD
+# scom 0x0000000008013C69 {
+#      bits,   	 scom_data        ;
+#     0:63,  	0x0000000000000000      ;
+#     }
+# 
+# spy name  ES.NPU.SL_WRAP0.NTL_WRAP1.NTL_FST_ERR_REG
+# scom 0x0000000008013C6A {
+#      bits,   	 scom_data        ;
+#     0:63,  	0x0000000000000000      ;
+#     }
+# 
+# # spy name  ES.NPU.SL_WRAP2.NTL_WRAP0.NTL_ER_HOLD
+# scom 0x0000000008013D29 {
+#      bits,   	 scom_data        ;
+#     0:63,  	0x0000000000000000      ;
+#     }
+# 
+# # spy name  ES.NPU.SL_WRAP2.NTL_WRAP0.NTL_FST_ERR_REG
+# scom 0x0000000008013D2A {
+#      bits,   	 scom_data        ;
+#     0:63,  	0x0000000000000000      ;
+#     }
+# 
+# # spy name  ES.NPU.SL_WRAP2.NTL_WRAP1.NTL_ER_HOLD
+# scom 0x0000000008013D69 {
+#      bits,   	 scom_data        ;
+#     0:63,  	0x0000000000000000      ;
+#     }
+# 
+# # spy name  ES.NPU.SL_WRAP2.NTL_WRAP1.NTL_FST_ERR_REG
+# scom 0x0000000008013D6A {
+#      bits,   	 scom_data        ;
+#     0:63,  	0x0000000000000000      ;
+#     }
 
-# spy name  ES.NPU.NP_AT.REG.NPU_AT_DEBUG  (Debug/trace control)
-scom 0x0000000008013DAB {
-     bits,   	 scom_data        ;
-    0:63,  	0x7000000000000000      ;
-    }
-
-# spy name  ES.NPU.NP_AT.REG.NPU_AT_CNFG0    (npu bar select)
-scom 0x0000000008013DA9 {
-     bits,   	 scom_data        ;
-    0:63,  	0x0211000043500000      ;
-    }
-
-# spy name  ES.NPU.SL_WRAP0.NP_CQ.NP_CQ_LNK0.NXCQ_SCOM.NP_BUID_REG   (npu bar select)
+# spy name  ES.NPU.SL_WRAP0.NP_CQ.NP_CQ_LNK0.NXCQ_SCOM.NP_BUID_REG    (Interrupt control)
 scom 0x0000000008013C13 {
      bits,   	 scom_data        ;
     0:63,  	0x0800000043500000      ;
     }
 
-
-# NPCQ control register?  scom-only        ??
-# NPCQ Int_lvl_REG register?  scom-only        ??
-
diff --git a/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile
index f69b6313c..a475183d6 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile
@@ -1,4 +1,4 @@
-#-- $Id: p8.nx.scom.initfile,v 1.14 2014/06/26 21:00:42 johnre Exp $
+#-- $Id: p8.nx.scom.initfile,v 1.15 2015/03/19 20:45:09 johnre Exp $
 #-------------------------------------------------------------------------------
 #--
 #-- (C) Copyright International Business Machines Corp. 2011
@@ -26,21 +26,29 @@ define sym_ci  = ( ((8*ATTR_FABRIC_NODE_ID) + (ATTR_FABRIC_CHIP_ID) + 1) * 4) ;
 define asym_ci = ( ((8*ATTR_FABRIC_NODE_ID) + (ATTR_FABRIC_CHIP_ID) + 1) * 16);
 
 
+#-- Naples does not have AMF engines.  Using chip attribute to identify Naples
+define def_amf_available     = (ATTR_CHIP_EC_FEATURE_NV_PRESENT == 0) ;
+
+
 #--------------------------------------------------------------------------------
 #-- SCOM initializations
 #--------------------------------------------------------------------------------
 
 #-- Engine Enable Register (0x02013041)
 scom 0x02013041 {
-    bits  ,  scom_data      ;
-    53    ,  0b1            ;  #-- ch7 ASYM enable
-    54    ,  0b1            ;  #-- ch6 ASYM enable
-    55    ,  0b1            ;  #-- ch5 ASYM enable
-    56    ,  0b1            ;  #-- ch4 ASYM enable
-    57    ,  0b1            ;  #-- ch3 SYM enable
-    58    ,  0b1            ;  #-- ch2 SYM enable
-    62    ,  0b1            ;  #-- ch1 842 enable
-    63    ,  0b1            ;  #-- ch0 842 enable
+    bits  , scom_data , expr                 ;
+    53    ,  0b0      , (!def_amf_available) ;  #-- ch7 ASYM enable
+    53    ,  0b1      , ( def_amf_available) ;
+    54    ,  0b0      , (!def_amf_available) ;  #-- ch6 ASYM enable
+    54    ,  0b1      , ( def_amf_available) ;
+    55    ,  0b0      , (!def_amf_available) ;  #-- ch5 ASYM enable
+    55    ,  0b1      , ( def_amf_available) ;
+    56    ,  0b0      , (!def_amf_available) ;  #-- ch4 ASYM enable
+    56    ,  0b1      , ( def_amf_available) ;
+    57    ,  0b1      , any                  ;  #-- ch3 SYM enable
+    58    ,  0b1      , any                  ;  #-- ch2 SYM enable
+    62    ,  0b1      , any                  ;  #-- ch1 842 enable
+    63    ,  0b1      , any                  ;  #-- ch0 842 enable
 }
 
 
@@ -80,11 +88,12 @@ scom 0x0201308A {
 
 #-- Asymmetric Coprocessor Config Register (0x0201308B)
 scom 0x0201308B {
-    bits  ,  scom_data      ;
-     2:14 ,  asym_ci        ;  #-- asym CI. function of node, chip id
-    18:23 ,  0b000010       ;  #-- asym CT
-    32:55 ,  0xfffff8       ;  #-- asym FC mask. enable 0-20
-    63    ,  0b1            ;  #-- asym enable
+    bits  ,  scom_data , expr                 ;
+     2:14 ,  asym_ci   , any                  ;  #-- asym CI. function of node, chip id
+    18:23 ,  0b000010  , any                  ;  #-- asym CT
+    32:55 ,  0xfffff8  , any                  ;  #-- asym FC mask. enable 0-20
+    63    ,  0b0       , (!def_amf_available) ;  #-- asym enable
+    63    ,  0b1       , ( def_amf_available) ;
 }
 
 
@@ -305,35 +314,41 @@ scom 0x02013107 {
 
 #-- DMA/Engine FIR Mask Register (0x02013103)
 scom 0x02013103 {
-    bits  ,  scom_data      ;
-     0    ,  0b1            ;   #-- mask      Reserved
-     1    ,  0b0            ;   #--           ICS invalid state error FIR bit
-     2:3  ,  0b11           ;   #-- mask      Reserved
-     4    ,  0b0            ;   #--           Channel 0 842 array corrected ECC error FIR bit" ;
-     5    ,  0b0            ;   #--           Channel 0 842 array uncorrectable ECC error FIR bit" ;
-     6    ,  0b0            ;   #--           Channel 1 842 array corrected ECC error FIR bit" ;
-     7    ,  0b0            ;   #--           Channel 1 842 array uncorrectable ECC error FIR bit" ;
-     8    ,  0b1            ;   #-- mask      DMA non-zero CSB CC detected FIR bit.  Programming error." ;
-     9    ,  0b0            ;   #--           DMA array correctable ECC error FIR bit" ;
-    10    ,  0b0            ;   #--           DMA outbound write/inbound read correctable ECC error FIR bit" ;
-    11:13 ,  0b000          ;   #--           Channel 5,6,7 AMF array corrected ECC error FIR bit" ;
-    14    ,  0b1            ;   #-- mask      Error from other SCOM satellites FIR bit" ;
-    15    ,  0b0            ;   #--           DMA invalid state error FIR bit.  Unrecoverable despite name" ;
-    16    ,  0b0            ;   #--           DMA invalid state error FIR bit" ;
-    17    ,  0b0            ;   #--           DMA array uncorrectable ECC error FIR bit" ;
-    18    ,  0b0            ;   #--           DMA outbound write/inbound read uncorrectable ECC error FIR bit" ;
-    19    ,  0b0            ;   #--           DMA inbound read error FIR bit" ;
-    20:27 ,  0b00000000     ;   #--           Channel 0-7 invalid state error FIR bit" ;
-    28:30 ,  0b000          ;   #--           Channel 5,6,7 AMF array uncorrectable ECC error FIR bit" ;
-    31    ,  0b0            ;   #--           UE error on CRB(CSB address, CCB) FIR bit" ;
-    32    ,  0b0            ;   #--           SUE error on CRB(CSB address, CCB) FIR bit" ;
-    33    ,  0b1            ;   #-- mask      SUE error on something other than CRB(CSB address, CCB) FIR bit" ;
-    34    ,  0b1            ;   #-- mask      Reserved
-    35    ,  0b1            ;   #-- mask      Reserved
-    36    ,  0b0            ;   #--           Channel 4 AMF array corrected ECC error FIR bit" ;
-    37    ,  0b0            ;   #--           Channel 4 AMF array uncorrectable ECC error FIR bit" ;
-    38    ,  0b0            ;   #--           PHYP uses to signal PRD during NX freeze
-    39:47 ,  0b111111111    ;   #-- mask      Reserved
-    48    ,  0b1            ;   #-- mask      FIR/SCOM satellite parity error FIR bit" ;
-    49    ,  0b1            ;   #-- mask      FIR/SCOM satellite parity error FIR bit duplicate"
+    bits  ,  scom_data      , expr                 ;
+     0    ,  0b1            , any                  ;   #-- mask      Reserved
+     1    ,  0b0            , any                  ;   #--           ICS invalid state error FIR bit
+     2:3  ,  0b11           , any                  ;   #-- mask      Reserved
+     4    ,  0b0            , any                  ;   #--           Channel 0 842 array corrected ECC error FIR bit" ;
+     5    ,  0b0            , any                  ;   #--           Channel 0 842 array uncorrectable ECC error FIR bit" ;
+     6    ,  0b0            , any                  ;   #--           Channel 1 842 array corrected ECC error FIR bit" ;
+     7    ,  0b0            , any                  ;   #--           Channel 1 842 array uncorrectable ECC error FIR bit" ;
+     8    ,  0b1            , any                  ;   #-- mask      DMA non-zero CSB CC detected FIR bit.  Programming error." ;
+     9    ,  0b0            , any                  ;   #--           DMA array correctable ECC error FIR bit" ;
+    10    ,  0b0            , any                  ;   #--           DMA outbound write/inbound read correctable ECC error FIR bit" ;
+    11:13 ,  0b111          , (!def_amf_available) ;   #--           Channel 5,6,7 AMF array corrected ECC error FIR bit" ;
+    11:13 ,  0b000          , ( def_amf_available) ;
+    14    ,  0b1            , any                  ;   #-- mask      Error from other SCOM satellites FIR bit" ;
+    15    ,  0b0            , any                  ;   #--           DMA invalid state error FIR bit.  Unrecoverable despite name" ;
+    16    ,  0b0            , any                  ;   #--           DMA invalid state error FIR bit" ;
+    17    ,  0b0            , any                  ;   #--           DMA array uncorrectable ECC error FIR bit" ;
+    18    ,  0b0            , any                  ;   #--           DMA outbound write/inbound read uncorrectable ECC error FIR bit" ;
+    19    ,  0b0            , any                  ;   #--           DMA inbound read error FIR bit" ;
+    20:23 ,  0b0000         , any                  ;   #--           Channel 0-3 invalid state error FIR bit" ;
+    24:27 ,  0b1111         , (!def_amf_available) ;   #--           Channel 4-7 invalid state error FIR bit" ;
+    24:27 ,  0b0000         , ( def_amf_available) ;
+    28:30 ,  0b111          , (!def_amf_available) ;   #--           Channel 5,6,7 AMF array uncorrectable ECC error FIR bit" ;
+    28:30 ,  0b000          , ( def_amf_available) ;
+    31    ,  0b0            , any                  ;   #--           UE error on CRB(CSB address, CCB) FIR bit" ;
+    32    ,  0b0            , any                  ;   #--           SUE error on CRB(CSB address, CCB) FIR bit" ;
+    33    ,  0b1            , any                  ;   #-- mask      SUE error on something other than CRB(CSB address, CCB) FIR bit" ;
+    34    ,  0b1            , any                  ;   #-- mask      Reserved
+    35    ,  0b1            , any                  ;   #-- mask      Reserved
+    36    ,  0b1            , (!def_amf_available) ;   #--           Channel 4 AMF array corrected ECC error FIR bit" ;
+    36    ,  0b0            , ( def_amf_available) ;
+    37    ,  0b1            , (!def_amf_available) ;   #--           Channel 4 AMF array uncorrectable ECC error FIR bit" ;
+    37    ,  0b0            , ( def_amf_available) ;
+    38    ,  0b0            , any                  ;   #--           PHYP uses to signal PRD during NX freeze
+    39:47 ,  0b111111111    , any                  ;   #-- mask      Reserved
+    48    ,  0b1            , any                  ;   #-- mask      FIR/SCOM satellite parity error FIR bit" ;
+    49    ,  0b1            , any                  ;   #-- mask      FIR/SCOM satellite parity error FIR bit duplicate"
 }