PON - Proc HW procedure update

Change-Id: I7168e7b02d9c7795ad16b76027e8a46edf24b161
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2984
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

1 files changed, 107 insertions, 0 deletions

diff --git a/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile
new file mode 100644
index 000000000..ef2c6b7b7
--- /dev/null
+++ b/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile
@@ -0,0 +1,107 @@
+#-- $Id: p8.mcs.scom.initfile,v 1.1 2012/10/08 03:24:14 jmcgill Exp $
+#-- CHANGE HISTORY:
+#--------------------------------------------------------------------------------
+#-- Version:|Author: | Date:  | Comment:
+#-- --------|--------|--------|--------------------------------------------------
+#--     1.00|baysah  |08/12/12|Created MCS init file
+#-- --------|--------|--------|--------------------------------------------------
+#--------------------------------------------------------------------------------
+# End of revision history
+#--------------------------------------------------------------------------------
+
+#--Master list of variables that can be used in this file is at:
+#--<Attribute Definition Location>
+
+SyntaxVersion = 1
+
+
+#--******************************************************************************
+#-- MC Mode0 Register Ship Mode
+#--******************************************************************************
+ scom 0x0000000002011807              {
+     bits ,                    scom_data        ;
+     0    ,                    0b1              ;              # MCMODE0Q_ENABLE_CMD_BYP_STUTTER
+     1    ,                    0b1              ;              # MCMODE0Q_RESERVED Reserved
+     2    ,                    0b1              ;              # MCMODE0Q_ENABLE_NS_RD_AO_SFU_FOR_DCBZ
+     3    ,                    0b1              ;              # MCMODE0Q_ENABLE_CENTAUR_LOCAL_CHECKSTOP_COMMAND
+     4:7  ,                    0xF              ;              # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD
+     8:11 ,                    0x0              ;              # MCMODE0Q_Number_of_CL_Entries_Reserved_for_Read
+     12:15,                    0x1              ;              # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_MIRRORED_OPS
+     16:19,                    0x0              ;              # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_WRITES
+     20:23,                    0x1              ;              # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_CP_WRITES
+     24:27,                    0x1              ;              # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_CP_IG
+     28:31,                    0x0              ;              # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_HTM_OPS
+     32:35,                    0x0              ;              # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_HA_ASSIST
+     36   ,                    0b1              ;              # MCMODE0Q_MCFGRP_19_IS_HO_BIT
+     37   ,                    0b1              ;              # MCMODE0Q_CL_CHANNEL_TIMEOUT_FORCES_CHANNEL_FAIL
+     38   ,                    0b1              ;              # MCMODE0Q_ENABLE_FAULT_LINE_FOR_GLOBAL_CHECKSTOP
+     39:43,                    0b00000          ;              # MCMODE0Q_RESERVED_39_43 Reserved
+     44:52,                    0b001100010      ;              # MCMODE0Q_ADDRESS_COLLISION_MODES
+     53   ,                    0b0              ;              # MCMODE0Q_INCLUDE_CP_IG_IN_CP_WRITE_FULLNESS_GROUP
+     54   ,                    0b1              ;              # MCMODE0Q_ENABLE_DMAWR_CMD_BIT
+     55   ,                    0b0              ;              # MCMODE0Q_ENABLE_READ_LFSR_DATA
+     56   ,                    0b0              ;              # MCMODE0Q_FORCE_CHANNEL_FAIL
+     57   ,                    0b0              ;              # MCMODE0Q_DISABLE_READ_CRC_ECC_BYPASS_TAKEN
+     58   ,                    0b0              ;              # MCMODE0Q_DISABLE_CL_AO_QUEUES
+     59:60,                    0b00             ;              # MCMODE0Q_ADDRESS_SELECT_LFSR_VALUE  (4k)
+     61   ,                    0b0              ;              # MCMODE0Q_ENABLE_CENTAUR_SYNC
+     62   ,                    0b0              ;              # MCMODE0Q_WRITE_DATA_BUFFER_ECC_CHECK_DISABLE
+     63   ,                    0b0              ;              # MCMODE0Q_WRITE_DATA_BUFFER_ECC_CORRECT_DISABLE
+
+ }
+
+
+#--******************************************************************************
+#-- MC Mode2 Register Ship Mode
+#--******************************************************************************
+ scom 0x0000000002011809              {
+     bits ,                    scom_data        ;
+     0    ,                    0b0              ;              # MCMODE2Q_FORCE_SFSTAT_GLOBAL
+     1:13 ,                    0b0000000000000  ;              # MCMODE2Q_DISABLE_WRITE_MDI_TO_ZERO
+     14   ,                    0b0              ;              # MCMODE2Q_DISABLE_SFU_OPERATIONS
+     15   ,                    0b0              ;              # MCMODE2Q_DISABLE_FASTPATH_QOS
+     16   ,                    0b0              ;              # MCMODE2Q_ENABLE_2K_SPEC_READ_DISABLE_COUNTERS
+     17   ,                    0b0              ;              # MCMODE2Q_ENABLE_ZERO_SPEC_HASH_ADDR_48_TO_50
+     18   ,                    0b0              ;              # MCMODE2Q_DISABLE_SPEC_DISABLE_HINT_BIT
+     19   ,                    0b0              ;              # MCMODE2Q_ENABLE_RESET_2K_COUNT_IF_HINT_BIT_SET
+     20:23,                    0x0              ;              # MCMODE2Q_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT
+     24:27,                    0x0              ;              # MCMODE2Q_D2K_SPEC_FILTER_COUNTER_LFSR_DEC__SELECT
+     28   ,                    0b0              ;              # MCMODE2Q_SPEC_READ_FILTER_NO_HASH_MODE
+     29   ,                    0b1              ;              # MCMODE2Q_ENABLE_CHANNEL_HANG
+     30:35,                    0b111111         ;              # MCMODE2Q_READ_SPECULATION_DISABLE_THRESHOLD
+     36:38,                    0b010            ;              # MCMODE2Q_CHANNEL_ARB_WRITE_HP_THRESHOLD
+     39   ,                    0b0              ;              # MCMODE2Q_DISABLE_BAD_CRESP_TO_CENTAUR
+     40   ,                    0b1              ;              # MCMODE2Q_ENABLE_CRC_BYPASS_ALWAYS
+     41:43,                    0b111            ;              # MCMODE2Q_CHANNEL_HANG_VALUE
+     44   ,                    0b1              ;              # MCMODE2Q_ENABLE_RD_HANG
+     45   ,                    0b1              ;              # MCMODE2Q_ENABLE_WR_HANG
+     46   ,                    0b1              ;              # MCMODE2Q_ENABLE_MIRROR_RD_HANG
+     47   ,                    0b1              ;              # MCMODE2Q_ENABLE_MIRROR_WR_HANG
+     48   ,                    0b1              ;              # MCMODE2Q_ENABLE_AO_HANG
+     49   ,                    0b1              ;              # MCMODE2Q_ENABLE_INBAND_HANG
+     50:52,                    0b111            ;              # MCMODE2Q_NONMIRROR_HANG_VALUE
+     53:55,                    0b111            ;              # MCMODE2Q_MIRROR_HANG_VALUE
+     56   ,                    0b1              ;              # MCMODE2Q_ENABLE_EMER_THROTTLE
+     57   ,                    0b0              ;              # MCMODE2Q_DRIVE_SHARED_PRESP_WITH_LOST_CLAIM
+     58   ,                    0b0              ;              # MCMODE2Q_DISABLE_SHARED_PRESP_ABORT
+     59   ,                    0b0              ;              # MCMODE2Q_DISABLE_RTY_LOST_CLAIM_PRESP
+     60   ,                    0b0              ;              # MCMODE2Q_DRIVE_BC4_WRITE_COMMAND
+     61   ,                    0b1              ;              # MCMODE2Q_ENABLE_CENTAUR_CHECKSTOP_COMMAND
+     62   ,                    0b1              ;              # MCMODE2Q_ENABLE_CENTAUR_TRACESTOP_COMMAND
+     63   ,                    0b0              ;              # MCMODE2Q_ENABLE_EVENT_BUS_B
+
+ }
+
+
+#--******************************************************************************
+#-- MC Busy Control Register Ship Mode
+#--******************************************************************************
+ scom 0x0000000002011818              {
+     bits ,                    scom_data        ;
+     0    ,                    0b0              ;              # MCBUSYQ_ENABLE_BUSY_COUNTERS
+     1:3  ,                    0b100            ;              # MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT (256 Cycles)
+     4:13 ,                    0b0000000000     ;              # MCBUSYQ_BUSY_COUNTER_THRESHOLD0
+     14:23,                    0b0000000000     ;              # MCBUSYQ_BUSY_COUNTER_THRESHOLD1
+     24:33,                    0b0000000000     ;              # MCBUSYQ_BUSY_COUNTER_THRESHOLD2
+     34:43,                    0b0000000000     ;              # MCBUSYQ_BUSY_COUNTER_THRESHOLD3
+}
\ No newline at end of file