Changes for Brazos 2z/3z Support

This commit has the hostboot changes for Brazos 2z/3z support along with
some attributes that Hostboot and HWSV share.  It also contains memory
XML and HWP changes from SW305517 and SW305518.

Change-Id: I71896dfac6946624bed3e216fe7823bd73e8e6bc
RTC: 125037
CQ:SW305518
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19306
Reviewed-by: PRACHI GUPTA <pragupta@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Michael D. Pardeik <pardeik@us.ibm.com>
Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com>
Tested-by: Michael Baiocchi <baiocchi@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19375
Tested-by: Jenkins Server
Tested-by: Jenkins OP Build CI
Reviewed-by: WILLIAM G. HOFFA <wghoffa@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Tested-by: Jenkins OP HW
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

5 files changed, 140 insertions, 17 deletions

diff --git a/src/usr/hwpf/hwp/dram_training/dram_training.C b/src/usr/hwpf/hwp/dram_training/dram_training.C
index a6d996033..0f811cfc0 100644
--- a/src/usr/hwpf/hwp/dram_training/dram_training.C
+++ b/src/usr/hwpf/hwp/dram_training/dram_training.C
@@ -79,6 +79,8 @@ const uint8_t VPO_NUM_OF_MEMBUF_TO_RUN = UNLIMITED_RUN;
 #include    "mss_draminit_trainadv/mss_draminit_training_advanced.H"
 #include    "mss_draminit_mc/mss_draminit_mc.H"
 #include    "proc_throttle_sync.H"
+#include    "../mc_config/mc_config.H"
+
 
 namespace   DRAM_TRAINING
 {
@@ -530,6 +532,75 @@ void*  call_mss_ddr_phy_reset( void *io_pArgs )
     return l_stepError.getErrorHandle();
 }
 
+//
+//  Wrapper function to call mss_post_draminit
+//
+void   mss_post_draminit( IStepError & l_stepError )
+{
+    errlHndl_t l_err = NULL;
+    bool rerun_vddr = false;
+
+    do {
+
+    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "mss_post_draminit entry" );
+
+    set_eff_config_attrs_helper(MC_CONFIG::POST_DRAM_INIT, rerun_vddr);
+
+    if ( rerun_vddr == false )
+    {
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                   "mss_post_draminit: nothing to do" );
+        break;
+    }
+
+    // Call mss_volt_vddr_offset to recalculate VDDR voltage
+
+    l_err = MC_CONFIG::setMemoryVoltageDomainOffsetVoltage<
+        TARGETING::ATTR_MSS_VOLT_VDDR_OFFSET_DISABLE,
+        TARGETING::ATTR_MEM_VDDR_OFFSET_MILLIVOLTS,
+        TARGETING::ATTR_VMEM_ID>();
+    if(l_err)
+    {
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "mss_post_draminit: "
+            "ERROR 0x%08X: setMemoryVoltageDomainOffsetVoltage for VDDR domain",
+            l_err->reasonCode());
+        l_stepError.addErrorDetails(l_err);
+        errlCommit(l_err,HWPF_COMP_ID);
+        break;
+    }
+    else
+    {
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                   "mss_post_draminit: mss_volt_vddr_offset(): SUCCESS");
+    }
+
+    // Call HWSV to call POWR code
+    // This fuction has compile-time binding for different platforms
+    l_err = platform_adjust_vddr_post_dram_init();
+
+    if( l_err )
+    {
+        TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                  "ERROR 0x%.8X: mss_post_draminit: "
+                  "platform_adjust_vddr_post_dram_init() returns error",
+                  l_err->reasonCode());
+
+        // Create IStep error log and cross reference to error that occurred
+        l_stepError.addErrorDetails( l_err );
+
+        // Commit Error
+        errlCommit( l_err, HWPF_COMP_ID );
+    }
+
+    } while(0);
+
+    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+            "mss_post_draminit exit" );
+
+    return;
+}
+
+
 
 //
 //  Wrapper function to call mss_draminit
@@ -593,6 +664,12 @@ void*    call_mss_draminit( void *io_pArgs )
 
     }   // endfor   mba's
 
+    // call POST_DRAM_INIT function
+    if(INITSERVICE::spBaseServicesEnabled())
+    {
+        mss_post_draminit(l_stepError);
+    }
+
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit exit" );
 
     return l_stepError.getErrorHandle();
diff --git a/src/usr/hwpf/hwp/dram_training/hbVddrMsg.C b/src/usr/hwpf/hwp/dram_training/hbVddrMsg.C
index 2119ed222..7198988ee 100644
--- a/src/usr/hwpf/hwp/dram_training/hbVddrMsg.C
+++ b/src/usr/hwpf/hwp/dram_training/hbVddrMsg.C
@@ -223,7 +223,7 @@ void HBVddrMsg::addMemoryVoltageDomains(
 ///////////////////////////////////////////////////////////////////////////////
 
 void HBVddrMsg::createVddrData(
-    const VDDR_MSG_TYPE     i_requestType,
+          VDDR_MSG_TYPE     i_requestType,
           RequestContainer& io_request) const
 {
     TRACFCOMP( g_trac_volt, ENTER_MRK "HBVddrMsg::createVddrData" );
@@ -302,7 +302,8 @@ void HBVddrMsg::createVddrData(
             io_request.erase(pInvalidEntries,io_request.end());
         }
 
-        if(   (i_requestType == HB_VDDR_ENABLE)
+        if( ( (i_requestType == HB_VDDR_ENABLE) ||
+              (i_requestType == HB_VDDR_POST_DRAM_INIT_ENABLE) )
            && (!membufTargetList.empty())      )
         {
             // Inhibit sending any request to turn on a domain with no voltage.
@@ -322,7 +323,7 @@ void HBVddrMsg::createVddrData(
 ///////////////////////////////////////////////////////////////////////////////
 // HBVddrMsg::sendMsg
 ///////////////////////////////////////////////////////////////////////////////
-errlHndl_t HBVddrMsg::sendMsg(uint32_t i_msgType) const
+errlHndl_t HBVddrMsg::sendMsg(VDDR_MSG_TYPE i_msgType) const
 {
     errlHndl_t l_err = NULL;
 
@@ -333,13 +334,9 @@ errlHndl_t HBVddrMsg::sendMsg(uint32_t i_msgType) const
     {
         RequestContainer l_request;
 
-        if ( (i_msgType == HB_VDDR_ENABLE) || (i_msgType == HB_VDDR_DISABLE) )
-        {
-            VDDR_MSG_TYPE msgType = (i_msgType == HB_VDDR_ENABLE)
-                ? HB_VDDR_ENABLE : HB_VDDR_DISABLE;
-            createVddrData(msgType, l_request);
-        }
-        else
+        if ( ! ( (i_msgType == HB_VDDR_ENABLE) ||
+                 (i_msgType == HB_VDDR_DISABLE) ||
+                 (i_msgType == HB_VDDR_POST_DRAM_INIT_ENABLE) ) )
         {
             TRACFCOMP(g_trac_volt, ERR_MRK "hbVddrMsg::send msg with non-"
                       "valid msg type%08X",i_msgType);
@@ -358,6 +355,8 @@ errlHndl_t HBVddrMsg::sendMsg(uint32_t i_msgType) const
                          fapi::RC_INCORRECT_MSG_TYPE, i_msgType);
             break;
         }
+        createVddrData(i_msgType, l_request);
+
 
         size_t l_dataCount = l_request.size();
 
@@ -544,7 +543,8 @@ errlHndl_t HBVddrMsg::processMsg(msg_t* i_Msg) const
             TRACFCOMP( g_trac_volt, INFO_MRK
                        "HBVddrMsg::processMsg l_msgType=x%08X",l_msgType );
             if ( (l_msgType == HB_VDDR_ENABLE) ||
-                 (l_msgType == HB_VDDR_DISABLE) )
+                 (l_msgType == HB_VDDR_DISABLE)||
+                 (l_msgType == HB_VDDR_POST_DRAM_INIT_ENABLE) )
             {
                 //process a VDDR message    
                 l_errLog=processVDDRmsg(i_Msg);
@@ -653,7 +653,7 @@ errlHndl_t platform_enable_vddr()
                        "SUCCESS :  host_enable_vddr()" );
         }
     }
-    else // simics stand-alone TULETTA
+    else // no FSP/mbox services available
     {
         TRACFCOMP(g_trac_volt,"call_host_enable_vddr"
                 "no-op because mbox not available");
@@ -683,7 +683,7 @@ errlHndl_t platform_disable_vddr()
                        "SUCCESS :  host_disable_vddr()" );
         }
     }
-    else  // simics stand-along TULETTA
+    else  // no FSP/mbox services available
     {
         TRACFCOMP(g_trac_volt,"call_host_disable_vddr"
                 "no-op because mbox not available");
@@ -692,3 +692,33 @@ errlHndl_t platform_disable_vddr()
     return l_err;
 }
 
+errlHndl_t platform_adjust_vddr_post_dram_init()
+{
+    errlHndl_t l_err = NULL;
+    if(INITSERVICE::spBaseServicesEnabled())
+    {
+        HBVddrMsg l_hbVddr;
+
+        l_err = l_hbVddr.sendMsg(HBVddrMsg::HB_VDDR_POST_DRAM_INIT_ENABLE);
+        if (l_err)
+        {
+            TRACFCOMP(g_trac_volt,
+                      "ERROR 0x%.8X: call_host_adjust_vddr_post_dram_init to "
+                      "sendMsg returns error",
+                      l_err->reasonCode());
+        }
+        else
+        {
+            TRACFCOMP( g_trac_volt,
+                       "SUCCESS :  host_adjust_vddr_post_dram_init()" );
+        }
+    }
+    else  // no FSP/mbox services available
+    {
+        TRACFCOMP(g_trac_volt,"call_host_adjust_vddr_post_dram_init()"
+                "no-op because mbox not available");
+    }
+
+    return l_err;
+}
+
diff --git a/src/usr/hwpf/hwp/dram_training/hbVddrMsg.H b/src/usr/hwpf/hwp/dram_training/hbVddrMsg.H
index f04019919..23f79fc14 100644
--- a/src/usr/hwpf/hwp/dram_training/hbVddrMsg.H
+++ b/src/usr/hwpf/hwp/dram_training/hbVddrMsg.H
@@ -5,7 +5,9 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
 /*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
 /* you may not use this file except in compliance with the License.       */
@@ -136,6 +138,7 @@ public:
     {
         HB_VDDR_ENABLE = 0x40000041,
         HB_VDDR_DISABLE = 0x40000042,
+        HB_VDDR_POST_DRAM_INIT_ENABLE = 0x40000043,
     };
 
     /**
@@ -180,7 +183,7 @@ public:
      *  @return N/A
      */
     void createVddrData(
-        const VDDR_MSG_TYPE     i_requestType,
+              VDDR_MSG_TYPE     i_requestType,
               RequestContainer& io_request) const;
 
     /**
@@ -199,7 +202,7 @@ public:
       *              return errl ==  NULL  -> success
       *              return errl !=  NULL  -> failure
      */
-    errlHndl_t sendMsg(uint32_t i_msgType) const;
+    errlHndl_t sendMsg(VDDR_MSG_TYPE i_msgType) const;
 
 private:
 
diff --git a/src/usr/hwpf/hwp/dram_training/palmetto_vddr.C b/src/usr/hwpf/hwp/dram_training/palmetto_vddr.C
index b456324a4..b0b7e47d7 100644
--- a/src/usr/hwpf/hwp/dram_training/palmetto_vddr.C
+++ b/src/usr/hwpf/hwp/dram_training/palmetto_vddr.C
@@ -356,3 +356,10 @@ errlHndl_t platform_disable_vddr()
     return for_each_vddr_domain_with_functional_memory(
         disableVddrViaGpioPinStrategy);
 }
+
+errlHndl_t platform_adjust_vddr_post_dram_init()
+{
+    // Not supported on palmetto
+    return NULL;
+}
+
diff --git a/src/usr/hwpf/hwp/dram_training/platform_vddr.H b/src/usr/hwpf/hwp/dram_training/platform_vddr.H
index 98c013535..b726aee0c 100644
--- a/src/usr/hwpf/hwp/dram_training/platform_vddr.H
+++ b/src/usr/hwpf/hwp/dram_training/platform_vddr.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
 /* [+] Google Inc.                                                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
@@ -43,6 +43,12 @@ errlHndl_t platform_enable_vspd();
 errlHndl_t platform_enable_vddr();
 
 /**
+ * @brief Adjust vddr on DIMMS with POST DRAM INITs
+ * @return NULL | error handle on error
+ */
+errlHndl_t platform_adjust_vddr_post_dram_init();
+
+/**
  * @brief Disable vddr on DIMMS
  * @return NULL | error handle on error
  */