SW272169: INITPROC: FSP&Hostboot - Add disable for delay

Change-Id: I9e4178c4aff019a0224bf4e21240dd56ef196f3f
CQ:SW272169
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/12617
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Tested-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/13085
Tested-by: Jenkins Server
Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

1 files changed, 28 insertions, 14 deletions

diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
index 01363c2a5..6120657d8 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit_training.C,v 1.87 2014/06/09 22:46:59 jdsloat Exp $
+// $Id: mss_draminit_training.C,v 1.90 2014/07/29 19:35:40 jdsloat Exp $
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -30,6 +30,9 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|------------------------------------------------
+//  1.90   | jdsloat  |29-JUL-14| disable for delay reset call moved to system level
+//  1.89   | jdsloat  |29-JUL-14| Added a disable for delay reset call 
+//  1.88   | jdsloat  |14-JUL-14| Fixed delay reset call 
 //  1.87   | jdsloat  |09-JUN-14| Fixed log numbering... Added additonal error logs for more debug ability in a training error situation.
 //  1.85   | jdsloat  |23-APL-14| Fixed attribute variable l_disable1_rdclk_fixed unitialized error in SW25701/v1.83
 //  1.84   | jdsloat  |23-APL-14| Fixed FAPI_ERR message within v1.83, mss_set_bbm_regs
@@ -271,11 +274,21 @@ ReturnCode mss_draminit_training(Target& i_target)
 
     fapi::ReturnCode l_rc;
 
-    //l_rc = mss_reset_delay_values(i_target);
-    //if (l_rc)
-    //{
-    //	return l_rc;
-    //}
+    uint8_t reset_disable;
+    l_rc = FAPI_ATTR_GET(ATTR_MSS_DRAMINIT_RESET_DISABLE, NULL, reset_disable);
+    if(l_rc) return l_rc;
+
+
+    if (reset_disable != ENUM_ATTR_MSS_DRAMINIT_RESET_DISABLE_DISABLE)
+    {
+
+	l_rc = mss_reset_delay_values(i_target);
+	if (l_rc)
+	{
+	return l_rc;
+	}
+
+    }
 
     l_rc = mss_draminit_training_cloned(i_target);
     if (l_rc)
@@ -478,6 +491,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
 	    rc = mss_execute_zq_cal(i_target, port);
 	    if(rc) return rc;
 
+
 #ifndef CONFIG_VPD_GETMACRO_USE_EFF_ATTR
             // Should only be called for DDR4 LRDIMMs, training code is in development. Does not effect any other configs
 	    if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) &&
@@ -489,9 +503,10 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
 		 if(rc) return rc;
             }
 #endif
+
 	}
 
-        if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) &&
+        if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) && 
 				(dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) )
         {
             FAPI_INF("Performing LRDIMM MB-DRAM training");
@@ -729,7 +744,6 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
                            if(rc) return rc;
                         }
 #endif
-
 		        //Set the config register
 			if(port == 0)
 			{
@@ -855,7 +869,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
 	return rc;
     }
 
-    // If we hit either of these States, the error callout originates from Mike Jones Bad Bit code.
+    // If we hit either of these States, the error callout originates from Mike Jones Bad Bit code. 
     if (complete_status == MSS_INIT_CAL_STALL)
     {
 	FAPI_ERR( "+++ Partial/Full calibration stall. Check Debug trace. +++");
@@ -3425,7 +3439,7 @@ fapi::ReturnCode mss_set_bbm_regs (const fapi::Target & mba_target)
 					 rc.setEcmdError(l_ecmdRc);
 					 return rc;
 				}
-
+				
 				for (uint8_t n=0; n < 4; n++)	// check each nibble
 				{
 					uint16_t nmask = 0xF000 >> (4*n);
@@ -3464,7 +3478,7 @@ fapi::ReturnCode mss_set_bbm_regs (const fapi::Target & mba_target)
 				}
 
 				FAPI_DBG("\t\tdisable1_data=0x%04X", disable1_data);
-
+				
 				// set disable0(dq) reg
 				l_ecmdRc = data_buffer.setHalfWord(3, l_data);
 				if (l_ecmdRc != ECMD_DBUF_SUCCESS)
@@ -3489,7 +3503,7 @@ fapi::ReturnCode mss_set_bbm_regs (const fapi::Target & mba_target)
 					FAPI_ERR("Error from fapiPutScom writing disable0 reg");
 					return rc;
 				}
-
+					
 				// set address for disable1(dqs) register
 				l_addr += l_disable1_addr_offset;
 				if (disable1_data != 0)
@@ -4071,7 +4085,7 @@ ReturnCode getC4dq2reg(const Target & i_mba, const uint8_t i_port,
                         			const uint8_t & DIMM = i_dimm;
                         			const uint8_t & RANK = i_rank;
 
-						FAPI_ERR("ATTR_VPD_DIMM_SPARE is invalid %u",
+						FAPI_ERR("ATTR_VPD_DIMM_SPARE is invalid %u", 
 							dimm_spare[i_port][i_dimm][i_rank]);
 						FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DIMM_SPARE_INPUT_ERROR);
 						return rc;
@@ -4166,7 +4180,7 @@ ReturnCode setC4dq2reg(const Target &i_mba, const uint8_t i_port,
 	uint8_t phy_lane;
 	uint8_t phy_block;
  	uint8_t data;
-
+	
     // get Centaur dq bitmap (C4 signal) order=[0:79], array of bytes
     rc = dimmGetBadDqBitmap(i_mba, i_port, i_dimm, i_rank, l_bbm);
     if (rc)