ISTEP 13: dram_training

RTC37081 - HWP Integration: mss_draminit. Add to Hostboot
RTC37087 - HWP Integration: mss_draminit_training. Add to Hostboot
RTC37093 - HWP Integration: mss_draminit_mc. Add to Hostboot

- branch mss_draminit
Checking in all 3 as one because of common files mss_funcs.H, memory_errors.xml
review fixes (remove extra trace, change draminit_mc target to centaur )
update to new levels of mss_func, mss_draminit and mss_draminit_mc

Depends on Change Ib83227b1: Add code to set MBA's under Centaurs functional

Change-Id: I77463d9b8482ad6bc1884baf05d6b6c2dde48b7c
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/707
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

11 files changed, 3193 insertions, 212 deletions

diff --git a/src/usr/hwpf/hwp/dram_training/dram_training.C b/src/usr/hwpf/hwp/dram_training/dram_training.C
index 82148913d..c765f52a4 100644
--- a/src/usr/hwpf/hwp/dram_training/dram_training.C
+++ b/src/usr/hwpf/hwp/dram_training/dram_training.C
@@ -20,11 +20,11 @@
 //  Origin: 30
 //
 //  IBM_PROLOG_END
-   
+
 /**
- *  @file dram_training.C                                                
+ *  @file dram_training.C
  *
- *  Support file for IStep: dram_training                                                    
+ *  Support file for IStep: dram_training
  *   Step 13 DRAM Training
  *
  *  *****************************************************************
@@ -64,8 +64,8 @@
 //      "dram_training_custom.C" and include the prototypes here.
 //  #include    "dram_training_custom.H"
 
-#include    "dram_training.H"          
-                                  
+#include    "dram_training.H"
+
 //  Uncomment these files as they become available:
 // #include    "host_disable_vddr/host_disable_vddr.H"
 // #include    "mc_pll_setup/mc_pll_setup.H"
@@ -73,13 +73,13 @@
 // #include    "host_enable_vddr/host_enable_vddr.H"
 // #include    "mss_initf/mss_initf.H"
 // #include    "mss_ddr_phy_reset/mss_ddr_phy_reset.H"
-// #include    "mss_draminit/mss_draminit.H"
+#include    "mss_draminit/mss_draminit.H"
 // #include    "mss_restore_dram_repair/mss_restore_dram_repair.H"
-// #include    "mss_draminit_training/mss_draminit_training.H"
+#include    "mss_draminit_training/mss_draminit_training.H"
 // #include    "mss_draminit_trainadv/mss_draminit_trainadv.H"
-// #include    "mss_draminit_mc/mss_draminit_mc.H"
+#include    "mss_draminit_mc/mss_draminit_mc.H"
 
-namespace   DRAM_TRAINING                                              
+namespace   DRAM_TRAINING
 {
 
 using   namespace   TARGETING;
@@ -98,15 +98,15 @@ void    call_host_disable_vddr( void *io_pArgs )
     fapi::ReturnCode    l_fapirc;
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_host_disable_vddr entry" );
-        
+
 #if 0
-    // @@@@@    CUSTOM BLOCK:   @@@@@    
+    // @@@@@    CUSTOM BLOCK:   @@@@@
     //  figure out what targets we need
     //  customize any other inputs
     //  set up loops to go through all targets (if parallel, spin off a task)
-    
+
     //  print call to hwp and dump physical path of the target(s)
-    TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                     "=====  host_disable_vddr HWP(? ? ? )",
                     ?
                     ?
@@ -115,21 +115,20 @@ void    call_host_disable_vddr( void *io_pArgs )
     EntityPath l_path;
     l_path  =   l_@targetN_target->getAttr<ATTR_PHYS_PATH>();
     l_path.dump();
-    TRACFCOMP( g_trac_mc_init, "===== " );   
 
-    // cast OUR type of target to a FAPI type of target.                         
+    // cast OUR type of target to a FAPI type of target.
     const fapi::Target l_fapi_@targetN_target(
                     TARGET_TYPE_MEMBUF_CHIP,
                     reinterpret_cast<void *>
                         (const_cast<TARGETING::Target*>(l_@targetN_target)) );
-                    
+
     //  call the HWP with each fapi::Target
     l_fapirc  =   host_disable_vddr( ? , ?, ? );
 
     //  process return code.
     if ( l_fapirc== fapi::FAPI_RC_SUCCESS )
     {
-        TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                 "SUCCESS :  host_disable_vddr HWP(? ? ? )" );
     }
     else
@@ -141,7 +140,7 @@ void    call_host_disable_vddr( void *io_pArgs )
                 "ERROR %d:  host_disable_vddr HWP(? ? ?) ",
                 static_cast<uint32_t>(l_fapirc) );
     }
-    // @@@@@    END CUSTOM BLOCK:   @@@@@    
+    // @@@@@    END CUSTOM BLOCK:   @@@@@
 #endif
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_host_disable_vddr exit" );
@@ -164,15 +163,15 @@ void    call_mc_pll_setup( void *io_pArgs )
     fapi::ReturnCode    l_fapirc;
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mc_pll_setup entry" );
-        
+
 #if 0
-    // @@@@@    CUSTOM BLOCK:   @@@@@    
+    // @@@@@    CUSTOM BLOCK:   @@@@@
     //  figure out what targets we need
     //  customize any other inputs
     //  set up loops to go through all targets (if parallel, spin off a task)
-    
+
     //  print call to hwp and dump physical path of the target(s)
-    TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                     "=====  mc_pll_setup HWP(? ? ? )",
                     ?
                     ?
@@ -181,21 +180,20 @@ void    call_mc_pll_setup( void *io_pArgs )
     EntityPath l_path;
     l_path  =   l_@targetN_target->getAttr<ATTR_PHYS_PATH>();
     l_path.dump();
-    TRACFCOMP( g_trac_mc_init, "===== " );   
 
-    // cast OUR type of target to a FAPI type of target.                         
+    // cast OUR type of target to a FAPI type of target.
     const fapi::Target l_fapi_@targetN_target(
                     TARGET_TYPE_MEMBUF_CHIP,
                     reinterpret_cast<void *>
                         (const_cast<TARGETING::Target*>(l_@targetN_target)) );
-                    
+
     //  call the HWP with each fapi::Target
     l_fapirc  =   mc_pll_setup( ? , ?, ? );
 
     //  process return code.
     if ( l_fapirc== fapi::FAPI_RC_SUCCESS )
     {
-        TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                 "SUCCESS :  mc_pll_setup HWP(? ? ? )" );
     }
     else
@@ -207,7 +205,7 @@ void    call_mc_pll_setup( void *io_pArgs )
                 "ERROR %d:  mc_pll_setup HWP(? ? ?) ",
                 static_cast<uint32_t>(l_fapirc) );
     }
-    // @@@@@    END CUSTOM BLOCK:   @@@@@    
+    // @@@@@    END CUSTOM BLOCK:   @@@@@
 #endif
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mc_pll_setup exit" );
@@ -230,15 +228,15 @@ void    call_mba_startclocks( void *io_pArgs )
     fapi::ReturnCode    l_fapirc;
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mba_startclocks entry" );
-        
+
 #if 0
-    // @@@@@    CUSTOM BLOCK:   @@@@@    
+    // @@@@@    CUSTOM BLOCK:   @@@@@
     //  figure out what targets we need
     //  customize any other inputs
     //  set up loops to go through all targets (if parallel, spin off a task)
-    
+
     //  print call to hwp and dump physical path of the target(s)
-    TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                     "=====  mba_startclocks HWP(? ? ? )",
                     ?
                     ?
@@ -247,21 +245,20 @@ void    call_mba_startclocks( void *io_pArgs )
     EntityPath l_path;
     l_path  =   l_@targetN_target->getAttr<ATTR_PHYS_PATH>();
     l_path.dump();
-    TRACFCOMP( g_trac_mc_init, "===== " );   
 
-    // cast OUR type of target to a FAPI type of target.                         
+    // cast OUR type of target to a FAPI type of target.
     const fapi::Target l_fapi_@targetN_target(
                     TARGET_TYPE_MEMBUF_CHIP,
                     reinterpret_cast<void *>
                         (const_cast<TARGETING::Target*>(l_@targetN_target)) );
-                    
+
     //  call the HWP with each fapi::Target
     l_fapirc  =   mba_startclocks( ? , ?, ? );
 
     //  process return code.
     if ( l_fapirc== fapi::FAPI_RC_SUCCESS )
     {
-        TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                 "SUCCESS :  mba_startclocks HWP(? ? ? )" );
     }
     else
@@ -273,7 +270,7 @@ void    call_mba_startclocks( void *io_pArgs )
                 "ERROR %d:  mba_startclocks HWP(? ? ?) ",
                 static_cast<uint32_t>(l_fapirc) );
     }
-    // @@@@@    END CUSTOM BLOCK:   @@@@@    
+    // @@@@@    END CUSTOM BLOCK:   @@@@@
 #endif
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mba_startclocks exit" );
@@ -296,15 +293,15 @@ void    call_host_enable_vddr( void *io_pArgs )
     fapi::ReturnCode    l_fapirc;
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_host_enable_vddr entry" );
-        
+
 #if 0
-    // @@@@@    CUSTOM BLOCK:   @@@@@    
+    // @@@@@    CUSTOM BLOCK:   @@@@@
     //  figure out what targets we need
     //  customize any other inputs
     //  set up loops to go through all targets (if parallel, spin off a task)
-    
+
     //  print call to hwp and dump physical path of the target(s)
-    TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                     "=====  host_enable_vddr HWP(? ? ? )",
                     ?
                     ?
@@ -313,21 +310,20 @@ void    call_host_enable_vddr( void *io_pArgs )
     EntityPath l_path;
     l_path  =   l_@targetN_target->getAttr<ATTR_PHYS_PATH>();
     l_path.dump();
-    TRACFCOMP( g_trac_mc_init, "===== " );   
 
-    // cast OUR type of target to a FAPI type of target.                         
+    // cast OUR type of target to a FAPI type of target.
     const fapi::Target l_fapi_@targetN_target(
                     TARGET_TYPE_MEMBUF_CHIP,
                     reinterpret_cast<void *>
                         (const_cast<TARGETING::Target*>(l_@targetN_target)) );
-                    
+
     //  call the HWP with each fapi::Target
     l_fapirc  =   host_enable_vddr( ? , ?, ? );
 
     //  process return code.
     if ( l_fapirc== fapi::FAPI_RC_SUCCESS )
     {
-        TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                 "SUCCESS :  host_enable_vddr HWP(? ? ? )" );
     }
     else
@@ -339,7 +335,7 @@ void    call_host_enable_vddr( void *io_pArgs )
                 "ERROR %d:  host_enable_vddr HWP(? ? ?) ",
                 static_cast<uint32_t>(l_fapirc) );
     }
-    // @@@@@    END CUSTOM BLOCK:   @@@@@    
+    // @@@@@    END CUSTOM BLOCK:   @@@@@
 #endif
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_host_enable_vddr exit" );
@@ -362,15 +358,15 @@ void    call_mss_initf( void *io_pArgs )
     fapi::ReturnCode    l_fapirc;
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_initf entry" );
-        
+
 #if 0
-    // @@@@@    CUSTOM BLOCK:   @@@@@    
+    // @@@@@    CUSTOM BLOCK:   @@@@@
     //  figure out what targets we need
     //  customize any other inputs
     //  set up loops to go through all targets (if parallel, spin off a task)
-    
+
     //  print call to hwp and dump physical path of the target(s)
-    TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                     "=====  mss_initf HWP(? ? ? )",
                     ?
                     ?
@@ -379,21 +375,20 @@ void    call_mss_initf( void *io_pArgs )
     EntityPath l_path;
     l_path  =   l_@targetN_target->getAttr<ATTR_PHYS_PATH>();
     l_path.dump();
-    TRACFCOMP( g_trac_mc_init, "===== " );   
 
-    // cast OUR type of target to a FAPI type of target.                         
+    // cast OUR type of target to a FAPI type of target.
     const fapi::Target l_fapi_@targetN_target(
                     TARGET_TYPE_MEMBUF_CHIP,
                     reinterpret_cast<void *>
                         (const_cast<TARGETING::Target*>(l_@targetN_target)) );
-                    
+
     //  call the HWP with each fapi::Target
     l_fapirc  =   mss_initf( ? , ?, ? );
 
     //  process return code.
     if ( l_fapirc== fapi::FAPI_RC_SUCCESS )
     {
-        TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                 "SUCCESS :  mss_initf HWP(? ? ? )" );
     }
     else
@@ -405,7 +400,7 @@ void    call_mss_initf( void *io_pArgs )
                 "ERROR %d:  mss_initf HWP(? ? ?) ",
                 static_cast<uint32_t>(l_fapirc) );
     }
-    // @@@@@    END CUSTOM BLOCK:   @@@@@    
+    // @@@@@    END CUSTOM BLOCK:   @@@@@
 #endif
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_initf exit" );
@@ -428,15 +423,15 @@ void    call_mss_ddr_phy_reset( void *io_pArgs )
     fapi::ReturnCode    l_fapirc;
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_ddr_phy_reset entry" );
-        
+
 #if 0
-    // @@@@@    CUSTOM BLOCK:   @@@@@    
+    // @@@@@    CUSTOM BLOCK:   @@@@@
     //  figure out what targets we need
     //  customize any other inputs
     //  set up loops to go through all targets (if parallel, spin off a task)
-    
+
     //  print call to hwp and dump physical path of the target(s)
-    TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                     "=====  mss_ddr_phy_reset HWP(? ? ? )",
                     ?
                     ?
@@ -445,21 +440,20 @@ void    call_mss_ddr_phy_reset( void *io_pArgs )
     EntityPath l_path;
     l_path  =   l_@targetN_target->getAttr<ATTR_PHYS_PATH>();
     l_path.dump();
-    TRACFCOMP( g_trac_mc_init, "===== " );   
 
-    // cast OUR type of target to a FAPI type of target.                         
+    // cast OUR type of target to a FAPI type of target.
     const fapi::Target l_fapi_@targetN_target(
                     TARGET_TYPE_MEMBUF_CHIP,
                     reinterpret_cast<void *>
                         (const_cast<TARGETING::Target*>(l_@targetN_target)) );
-                    
+
     //  call the HWP with each fapi::Target
     l_fapirc  =   mss_ddr_phy_reset( ? , ?, ? );
 
     //  process return code.
     if ( l_fapirc== fapi::FAPI_RC_SUCCESS )
     {
-        TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                 "SUCCESS :  mss_ddr_phy_reset HWP(? ? ? )" );
     }
     else
@@ -471,7 +465,7 @@ void    call_mss_ddr_phy_reset( void *io_pArgs )
                 "ERROR %d:  mss_ddr_phy_reset HWP(? ? ?) ",
                 static_cast<uint32_t>(l_fapirc) );
     }
-    // @@@@@    END CUSTOM BLOCK:   @@@@@    
+    // @@@@@    END CUSTOM BLOCK:   @@@@@
 #endif
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_ddr_phy_reset exit" );
@@ -494,51 +488,65 @@ void    call_mss_draminit( void *io_pArgs )
     fapi::ReturnCode    l_fapirc;
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit entry" );
-        
-#if 0
-    // @@@@@    CUSTOM BLOCK:   @@@@@    
-    //  figure out what targets we need
-    //  customize any other inputs
-    //  set up loops to go through all targets (if parallel, spin off a task)
-    
-    //  print call to hwp and dump physical path of the target(s)
-    TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
-                    "=====  mss_draminit HWP(? ? ? )",
-                    ?
-                    ?
-                    ? );
-    //  dump physical path to targets
-    EntityPath l_path;
-    l_path  =   l_@targetN_target->getAttr<ATTR_PHYS_PATH>();
-    l_path.dump();
-    TRACFCOMP( g_trac_mc_init, "===== " );   
 
-    // cast OUR type of target to a FAPI type of target.                         
-    const fapi::Target l_fapi_@targetN_target(
-                    TARGET_TYPE_MEMBUF_CHIP,
-                    reinterpret_cast<void *>
-                        (const_cast<TARGETING::Target*>(l_@targetN_target)) );
-                    
-    //  call the HWP with each fapi::Target
-    l_fapirc  =   mss_draminit( ? , ?, ? );
-
-    //  process return code.
-    if ( l_fapirc== fapi::FAPI_RC_SUCCESS )
+    // @@@@@    CUSTOM BLOCK:   @@@@@
+    //  mss_draminit wants centaur.mba's
+    //  Use PredicateIsFunctional to filter only functional chips
+    TARGETING::PredicateIsFunctional    l_isFunctional;
+    //  find all the MBA's in the system
+    TARGETING::PredicateCTM             l_mbaFilter(CLASS_UNIT, TYPE_MBA);
+    // declare a postfix expression widget
+    TARGETING::PredicatePostfixExpr l_functionalAndMbaFilter;
+    //  is-a-membuf-chip  is-functional   AND
+    l_functionalAndMbaFilter.push(&l_mbaFilter).push(&l_isFunctional).And();
+    // loop through all the targets, applying the filter,  and put the results in l_pMemBufs
+    TARGETING::TargetRangeFilter    l_pMbas(
+            TARGETING::targetService().begin(),
+            TARGETING::targetService().end(),
+            &l_functionalAndMbaFilter );
+
+    for (   uint8_t l_mbaNum=0 ;
+            l_pMbas ;
+            l_mbaNum++, ++l_pMbas
+    )
     {
-        TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
-                "SUCCESS :  mss_draminit HWP(? ? ? )" );
-    }
-    else
-    {
-        /**
-         * @todo fapi error - just print out for now...
-         */
+        //  make a local copy of the target for ease of use
+        const TARGETING::Target*  l_mba_target = *l_pMbas;
+
+        //  print call to hwp and dump physical path of the target(s)
         TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                "ERROR %d:  mss_draminit HWP(? ? ?) ",
-                static_cast<uint32_t>(l_fapirc) );
-    }
-    // @@@@@    END CUSTOM BLOCK:   @@@@@    
-#endif
+                "=====  mss_draminit HWP(  )" );
+        //  dump physical path to targets
+        EntityPath l_path;
+        l_path  =   l_mba_target->getAttr<ATTR_PHYS_PATH>();
+        l_path.dump();
+
+        // cast OUR type of target to a FAPI type of target.
+        const fapi::Target l_fapi_mba_target(
+                TARGET_TYPE_MBA_CHIPLET,
+                reinterpret_cast<void *>
+        (const_cast<TARGETING::Target*>(l_mba_target)) );
+
+        //  call the HWP with each fapi::Target
+        l_fapirc  =   mss_draminit( l_fapi_mba_target );
+
+        //  process return code.
+        if ( l_fapirc== fapi::FAPI_RC_SUCCESS )
+        {
+            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                    "SUCCESS :  mss_draminit HWP(? ? ? )" );
+        }
+        else
+        {
+            /**
+             * @todo fapi error - just print out for now...
+             */
+            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                    "ERROR %d:  mss_draminit HWP( ) ",
+                    static_cast<uint32_t>(l_fapirc) );
+        }
+    }   // endfor   mba's
+    // @@@@@    END CUSTOM BLOCK:   @@@@@
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit exit" );
 
@@ -560,15 +568,15 @@ void    call_mss_restore_dram_repair( void *io_pArgs )
     fapi::ReturnCode    l_fapirc;
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_restore_dram_repair entry" );
-        
+
 #if 0
-    // @@@@@    CUSTOM BLOCK:   @@@@@    
+    // @@@@@    CUSTOM BLOCK:   @@@@@
     //  figure out what targets we need
     //  customize any other inputs
     //  set up loops to go through all targets (if parallel, spin off a task)
-    
+
     //  print call to hwp and dump physical path of the target(s)
-    TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                     "=====  mss_restore_dram_repair HWP(? ? ? )",
                     ?
                     ?
@@ -577,21 +585,20 @@ void    call_mss_restore_dram_repair( void *io_pArgs )
     EntityPath l_path;
     l_path  =   l_@targetN_target->getAttr<ATTR_PHYS_PATH>();
     l_path.dump();
-    TRACFCOMP( g_trac_mc_init, "===== " );   
 
-    // cast OUR type of target to a FAPI type of target.                         
+    // cast OUR type of target to a FAPI type of target.
     const fapi::Target l_fapi_@targetN_target(
                     TARGET_TYPE_MEMBUF_CHIP,
                     reinterpret_cast<void *>
                         (const_cast<TARGETING::Target*>(l_@targetN_target)) );
-                    
+
     //  call the HWP with each fapi::Target
     l_fapirc  =   mss_restore_dram_repair( ? , ?, ? );
 
     //  process return code.
     if ( l_fapirc== fapi::FAPI_RC_SUCCESS )
     {
-        TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                 "SUCCESS :  mss_restore_dram_repair HWP(? ? ? )" );
     }
     else
@@ -603,7 +610,7 @@ void    call_mss_restore_dram_repair( void *io_pArgs )
                 "ERROR %d:  mss_restore_dram_repair HWP(? ? ?) ",
                 static_cast<uint32_t>(l_fapirc) );
     }
-    // @@@@@    END CUSTOM BLOCK:   @@@@@    
+    // @@@@@    END CUSTOM BLOCK:   @@@@@
 #endif
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_restore_dram_repair exit" );
@@ -626,51 +633,66 @@ void    call_mss_draminit_training( void *io_pArgs )
     fapi::ReturnCode    l_fapirc;
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit_training entry" );
-        
-#if 0
-    // @@@@@    CUSTOM BLOCK:   @@@@@    
-    //  figure out what targets we need
-    //  customize any other inputs
-    //  set up loops to go through all targets (if parallel, spin off a task)
-    
-    //  print call to hwp and dump physical path of the target(s)
-    TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
-                    "=====  mss_draminit_training HWP(? ? ? )",
-                    ?
-                    ?
-                    ? );
-    //  dump physical path to targets
-    EntityPath l_path;
-    l_path  =   l_@targetN_target->getAttr<ATTR_PHYS_PATH>();
-    l_path.dump();
-    TRACFCOMP( g_trac_mc_init, "===== " );   
 
-    // cast OUR type of target to a FAPI type of target.                         
-    const fapi::Target l_fapi_@targetN_target(
-                    TARGET_TYPE_MEMBUF_CHIP,
-                    reinterpret_cast<void *>
-                        (const_cast<TARGETING::Target*>(l_@targetN_target)) );
-                    
-    //  call the HWP with each fapi::Target
-    l_fapirc  =   mss_draminit_training( ? , ?, ? );
 
-    //  process return code.
-    if ( l_fapirc== fapi::FAPI_RC_SUCCESS )
-    {
-        TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
-                "SUCCESS :  mss_draminit_training HWP(? ? ? )" );
-    }
-    else
+    // @@@@@    CUSTOM BLOCK:   @@@@@
+    //  Use PredicateIsFunctional to filter only functional chips
+    TARGETING::PredicateIsFunctional    l_isFunctional;
+    //  find all the MBA's in the system
+    TARGETING::PredicateCTM             l_mbaFilter(CLASS_UNIT, TYPE_MBA);
+    // declare a postfix expression widget
+    TARGETING::PredicatePostfixExpr l_functionalAndMbaFilter;
+    //  is-a-membuf-chip  is-functional   AND
+    l_functionalAndMbaFilter.push(&l_mbaFilter).push(&l_isFunctional).And();
+    // loop through all the targets, applying the filter,  and put the results in l_pMemBufs
+    TARGETING::TargetRangeFilter    l_pMbas(
+            TARGETING::targetService().begin(),
+            TARGETING::targetService().end(),
+            &l_functionalAndMbaFilter );
+
+    for (   uint8_t l_mbaNum=0 ;
+            l_pMbas ;
+            l_mbaNum++, ++l_pMbas
+    )
     {
-        /**
-         * @todo fapi error - just print out for now...
-         */
+        //  make a local copy of the target for ease of use
+        const TARGETING::Target*  l_mba_target = *l_pMbas;
+
+        //  print call to hwp and dump physical path of the target(s)
         TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                "ERROR %d:  mss_draminit_training HWP(? ? ?) ",
-                static_cast<uint32_t>(l_fapirc) );
+                "=====  mss_draminit_training HWP( )" );
+        //  dump physical path to targets
+        EntityPath l_path;
+        l_path  =   l_mba_target->getAttr<ATTR_PHYS_PATH>();
+        l_path.dump();
+
+        // cast OUR type of target to a FAPI type of target.
+        const fapi::Target l_fapi_mba_target(
+                TARGET_TYPE_MBA_CHIPLET,
+                reinterpret_cast<void *>
+        (const_cast<TARGETING::Target*>(l_mba_target)) );
+
+        //  call the HWP with each fapi::Target
+        l_fapirc  =   mss_draminit_training( l_fapi_mba_target );
+
+        //  process return code.
+        if ( l_fapirc== fapi::FAPI_RC_SUCCESS )
+        {
+            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                    "SUCCESS :  mss_draminit_training HWP( )" );
+        }
+        else
+        {
+            /**
+             * @todo fapi error - just print out for now...
+             */
+            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                    "ERROR %d:  mss_draminit_training HWP( ) ",
+                    static_cast<uint32_t>(l_fapirc) );
+        }
     }
-    // @@@@@    END CUSTOM BLOCK:   @@@@@    
-#endif
+    // @@@@@    END CUSTOM BLOCK:   @@@@@
+
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit_training exit" );
 
@@ -692,15 +714,15 @@ void    call_mss_draminit_trainadv( void *io_pArgs )
     fapi::ReturnCode    l_fapirc;
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit_trainadv entry" );
-        
+
 #if 0
-    // @@@@@    CUSTOM BLOCK:   @@@@@    
+    // @@@@@    CUSTOM BLOCK:   @@@@@
     //  figure out what targets we need
     //  customize any other inputs
     //  set up loops to go through all targets (if parallel, spin off a task)
-    
+
     //  print call to hwp and dump physical path of the target(s)
-    TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                     "=====  mss_draminit_trainadv HWP(? ? ? )",
                     ?
                     ?
@@ -709,21 +731,20 @@ void    call_mss_draminit_trainadv( void *io_pArgs )
     EntityPath l_path;
     l_path  =   l_@targetN_target->getAttr<ATTR_PHYS_PATH>();
     l_path.dump();
-    TRACFCOMP( g_trac_mc_init, "===== " );   
 
-    // cast OUR type of target to a FAPI type of target.                         
+    // cast OUR type of target to a FAPI type of target.
     const fapi::Target l_fapi_@targetN_target(
                     TARGET_TYPE_MEMBUF_CHIP,
                     reinterpret_cast<void *>
                         (const_cast<TARGETING::Target*>(l_@targetN_target)) );
-                    
+
     //  call the HWP with each fapi::Target
     l_fapirc  =   mss_draminit_trainadv( ? , ?, ? );
 
     //  process return code.
     if ( l_fapirc== fapi::FAPI_RC_SUCCESS )
     {
-        TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                 "SUCCESS :  mss_draminit_trainadv HWP(? ? ? )" );
     }
     else
@@ -735,7 +756,7 @@ void    call_mss_draminit_trainadv( void *io_pArgs )
                 "ERROR %d:  mss_draminit_trainadv HWP(? ? ?) ",
                 static_cast<uint32_t>(l_fapirc) );
     }
-    // @@@@@    END CUSTOM BLOCK:   @@@@@    
+    // @@@@@    END CUSTOM BLOCK:   @@@@@
 #endif
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit_trainadv exit" );
@@ -758,51 +779,67 @@ void    call_mss_draminit_mc( void *io_pArgs )
     fapi::ReturnCode    l_fapirc;
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit_mc entry" );
-        
-#if 0
-    // @@@@@    CUSTOM BLOCK:   @@@@@    
-    //  figure out what targets we need
-    //  customize any other inputs
-    //  set up loops to go through all targets (if parallel, spin off a task)
-    
-    //  print call to hwp and dump physical path of the target(s)
-    TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
-                    "=====  mss_draminit_mc HWP(? ? ? )",
-                    ?
-                    ?
-                    ? );
-    //  dump physical path to targets
-    EntityPath l_path;
-    l_path  =   l_@targetN_target->getAttr<ATTR_PHYS_PATH>();
-    l_path.dump();
-    TRACFCOMP( g_trac_mc_init, "===== " );   
-
-    // cast OUR type of target to a FAPI type of target.                         
-    const fapi::Target l_fapi_@targetN_target(
-                    TARGET_TYPE_MEMBUF_CHIP,
-                    reinterpret_cast<void *>
-                        (const_cast<TARGETING::Target*>(l_@targetN_target)) );
-                    
-    //  call the HWP with each fapi::Target
-    l_fapirc  =   mss_draminit_mc( ? , ?, ? );
 
-    //  process return code.
-    if ( l_fapirc== fapi::FAPI_RC_SUCCESS )
+    // @@@@@    CUSTOM BLOCK:   @@@@@
+    //  Use PredicateIsFunctional to filter only functional chips
+    TARGETING::PredicateIsFunctional    l_isFunctional;
+    //  find all the Centaurs in the system
+    TARGETING::PredicateCTM             l_membufChipFilter(CLASS_CHIP, TYPE_MEMBUF);
+    // declare a postfix expression widget
+    TARGETING::PredicatePostfixExpr l_functionalAndMembufChipFilter;
+    //  is-a-membuf-chip  is-functional   AND
+    l_functionalAndMembufChipFilter.push(&l_membufChipFilter).push(&l_isFunctional).And();
+    // loop through all the targets, applying the filter,  and put the results in l_pMbas
+    TARGETING::TargetRangeFilter    l_pMemBufs(
+            TARGETING::targetService().begin(),
+            TARGETING::targetService().end(),
+            &l_functionalAndMembufChipFilter );
+
+    for (   uint8_t l_membufNum=0 ;
+            l_pMemBufs ;
+            l_membufNum++, ++l_pMemBufs
+    )
     {
-        TRACFCOMP( ISTEPS_TRACE::ISTEPS_TRACE::g_trac_isteps_traces_trace,
-                "SUCCESS :  mss_draminit_mc HWP(? ? ? )" );
-    }
-    else
-    {
-        /**
-         * @todo fapi error - just print out for now...
-         */
+        //  make a local copy of the target for ease of use
+        const TARGETING::Target*  l_membuf_target = *l_pMemBufs;
+
+        //  print call to hwp and dump physical path of the target(s)
         TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                "ERROR %d:  mss_draminit_mc HWP(? ? ?) ",
-                static_cast<uint32_t>(l_fapirc) );
+                "=====  mss_draminit_mc HWP( %d )",
+                l_membufNum );
+        //  dump physical path to targets
+        EntityPath l_path;
+        l_path  =   l_membuf_target->getAttr<ATTR_PHYS_PATH>();
+        l_path.dump();
+
+        // cast OUR type of target to a FAPI type of target.
+        const fapi::Target l_fapi_membuf_target(
+                TARGET_TYPE_MEMBUF_CHIP,
+                reinterpret_cast<void *>
+        (const_cast<TARGETING::Target*>(l_membuf_target)) );
+
+        //  call the HWP with each fapi::Target
+        l_fapirc  =   mss_draminit_mc( l_fapi_membuf_target );
+
+        //  process return code.
+        if ( l_fapirc== fapi::FAPI_RC_SUCCESS )
+        {
+            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                    "SUCCESS :  mss_draminit_mc HWP( %d )",
+                    l_membufNum );
+        }
+        else
+        {
+            /**
+             * @todo fapi error - just print out for now...
+             */
+            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                    "ERROR %d:  mss_draminit_mc HWP( %d ) ",
+                    static_cast<uint32_t>(l_fapirc),
+                    l_membufNum );
+        }
     }
-    // @@@@@    END CUSTOM BLOCK:   @@@@@    
-#endif
+    // @@@@@    END CUSTOM BLOCK:   @@@@@
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit_mc exit" );
 
diff --git a/src/usr/hwpf/hwp/dram_training/makefile b/src/usr/hwpf/hwp/dram_training/makefile
index 748f821ed..871f2701d 100644
--- a/src/usr/hwpf/hwp/dram_training/makefile
+++ b/src/usr/hwpf/hwp/dram_training/makefile
@@ -34,15 +34,29 @@ EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
 ## pointer to common HWP files
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
 
+##  NOTE: add the base istep dir here. 
+##@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/@istepname
+EXTRAINCDIR	+= ${ROOTPATH}/src/usr/hwpf/hwp/dram_training
+
 ##  Include sub dirs
 ##  NOTE: add a new EXTRAINCDIR when you add a new HWP
-## EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/??
-
-
-OBJS =  dram_training.o
-
-
+##@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/???
+EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_training
+EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_mc
+EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit
+
+##  NOTE: add new object files when you add a new HWP
+OBJS =  dram_training.o \
+        mss_draminit.o \
+        mss_funcs.o \
+        mss_draminit_mc.o \
+        mss_draminit_training.o
+   		
 ##  NOTE: add a new directory onto the vpaths when you add a new HWP
-## VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/??
+##@ VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/???
+VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_training
+VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_mc
+VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit
+
 
-include ${ROOTPATH}/config.mk
+include ${ROOTPATH}/config.mk
\ No newline at end of file
diff --git a/src/usr/hwpf/hwp/dram_training/memory_errors.xml b/src/usr/hwpf/hwp/dram_training/memory_errors.xml
new file mode 100644
index 000000000..ea80ddeef
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/memory_errors.xml
@@ -0,0 +1,86 @@
+<!--  IBM_PROLOG_BEGIN_TAG
+     This is an automatically generated prolog.
+   
+     $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_mc/memory_errors.xml $
+   
+     IBM CONFIDENTIAL
+   
+     COPYRIGHT International Business Machines Corp. 2012
+   
+     p1
+   
+     Object Code Only (OCO) source materials
+     Licensed Internal Code Source Materials
+     IBM HostBoot Licensed Internal Code
+   
+     The source code for this program is not published or other-
+     wise divested of its trade secrets, irrespective of what has
+     been deposited with the U.S. Copyright Office.
+   
+     Origin: 30
+   
+     IBM_PROLOG_END -->
+<hwpErrors>
+<!-- *********************************************************************** -->
+
+  <hwpError>
+    <rc>RC_MSS_RCD_PARITY_ERROR_PORT0</rc>
+    <description>An rcd parity error has been registered on port_0    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_RCD_PARITY_ERROR_PORT1</rc>
+    <description>An rcd parity error has been registered on port_1    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_RCD_PARITY_ERROR_LIMIT</rc>
+    <description>The number of rcd parity errors have exceeded the maximum allowable number    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_CCS_HUNG</rc>
+    <description>The ccs failed to return from in_progress status and failed to describe an error further.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_CCS_READ_MISCOMPARE</rc>
+    <description>The ccs errors at runtime and registers a read miscompare.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_CCS_UE_SUE</rc>
+    <description>The ccs errors at runtime and registers a UE or SUE    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_CCS_CAL_TIMEOUT</rc>
+    <description>The ccs errors at runtime and registers a calibration operation timeout    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_PLACE_HOLDER_ERROR</rc>
+    <description>Not for production code.  This return code is used for cases where the error code has not been approved yet.  Eventually, no code should use this error code.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_EFF_CONFIG_RANK_GROUP_RC_ERROR_001A</rc>
+    <description>Plug rule violation in EFF_CONFIG_RANK_GROUP.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_EFF_CONFIG_RC_ERROR_001A</rc>
+    <description>Plug rule violation in EFF_CONFIG.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_UNEXPECTED_MEM_CLK_STATUS</rc>
+    <description>A read of the memory clock status register returned an unexpected value.     </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_UNEXPECTED_NEST_CLK_STATUS</rc>
+    <description>A read of the nest clock status register returned an unexpected value.    </description>
+  </hwpError>
+
+</hwpErrors>
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
new file mode 100755
index 000000000..ed8540663
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
@@ -0,0 +1,992 @@
+//  IBM_PROLOG_BEGIN_TAG
+//  This is an automatically generated prolog.
+//
+//  $Source: src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C $
+//
+//  IBM CONFIDENTIAL
+//
+//  COPYRIGHT International Business Machines Corp. 2012
+//
+//  p1
+//
+//  Object Code Only (OCO) source materials
+//  Licensed Internal Code Source Materials
+//  IBM HostBoot Licensed Internal Code
+//
+//  The source code for this program is not published or other-
+//  wise divested of its trade secrets, irrespective of what has
+//  been deposited with the U.S. Copyright Office.
+//
+//  Origin: 30
+//
+//  IBM_PROLOG_END
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|  Author: |  Date:  | Comment:
+//---------|----------|---------|-----------------------------------------------
+//  1.22   | jdsloat  | 2/27/12 | Fixed hostboot parenthesis error
+//  1.21   | jdsloat  | 2/27/12 | Cycle through Ports local of MRS/RCD, CL shift fix, Initialization of address/CS, neg end bit bug fix
+//  1.20   | jdsloat  | 2/23/12 | Fixed CL typo in MRS load
+//  1.19   | jdsloat  | 2/23/12 | MRS per rank, Interpret MRS ENUM correctly, CSN initialized to 0xFF
+//  1.18   | jdsloat  | 2/16/12 | Initialize rc_num, add num_ranks ==1 to MRS, Fix BA position in MRS
+//  1.17   | jdsloat  | 2/14/12 | MBA target translation, if statement clarification, style fixes
+//  1.16   | jdsloat  | 2/08/12 | Target to Target&, Described target with comment
+//  1.15   | jdsloat  | 2/02/12 | Fixed attributes array sizes, added debug messagesTarget to Target&, Described target
+//  1.14   | jdsloat  | 1/19/12 | Tabs to 4 spaces - properly
+//  1.13   | jdsloat  | 1/16/12 | Tabs to 4 spaces
+//  1.12   | jdsloat  | 1/13/12 | Curly Brackets, capitalization, "mss_" prefix, argument prefixes, no include C's, RC checks
+//  1.11   | jdsloat  | 1/5/12  | Changed Attribute grab, cleaned up includes section, Got rid of Globals
+//  1.10   | jdsloat  | 12/08/11| Changed MRS load  RAS, CAS, WEN
+//  1.9    | jdsloat  | 12/07/11| CSN for 2 rank dimms 0x3 to 0xC
+//  1.8    | jdsloat  | 11/08/11| Cycling through Ports - fix
+//  1.7    | jdsloat  | 10/31/11| CCS Update - goto_inst now assumed to be +1, CCS_fail fix, CCS_status fix
+//  1.6    | jdsloat  | 10/18/11| RCD execution fix, debug messages
+//  1.5    | jdsloat  | 10/13/11| MRS fix, CCS count fix, get attribute fix, ecmdbuffer lengths within name
+//  1.4    | jdsloat  | 10/11/11| Fix CS Lines, dataBuffer.insert functions, ASSERT_RESETN_DRIVE_MEM_CLKS fix, attribute names
+//  1.3    | jdsloat  | 10/05/11| Convert integers to ecmdDataBufferBase in CCS_INST_1, CCS_INST_2, CCS_MODE
+//  1.2    | jdsloat  |04-OCT-11| Changing cen_funcs.C, cen_funcs.H to mss_funcs.C, mss_funcs.H
+//  1.1    | jdsloat  |04-OCT-11| First drop
+//---------|----------|---------|-----------------------------------------------
+//  1.6    | jdsloat  |29-Sep-11|Functional Changes: port flow, CCS changes, only configed CS, etc.  Compiles.
+//  1.5    | jdsloat  |22-Sep-11|Converted to FAPI, functional changes to match documentation
+//  1.3    | jdsloat  |14-Jul-11|Change GP4 register address from 1013 to 0x1013
+//  1.2    | jdsloat  |22-Apr-11|Moved CCS operations to Cen_funcs.C, draminit_training to cen_draminit_training.C
+//  1.1    | jdsloat  |31-Mar-11|First drop for centaur
+
+//----------------------------------------------------------------------
+//  FAPI function Includes
+//----------------------------------------------------------------------
+
+#include <fapi.H>
+
+//----------------------------------------------------------------------
+//  Centaur function Includes
+//----------------------------------------------------------------------
+#include <mss_funcs.H>
+
+
+//----------------------------------------------------------------------
+//  Constants
+//----------------------------------------------------------------------
+const uint8_t MAX_NUM_RANKS = 4;
+const uint8_t MAX_NUM_DIMMS = 2;
+const uint8_t MAX_NUM_PORTS = 2; 
+const uint8_t MRS0_BA = 0;
+const uint8_t MRS1_BA = 1;
+const uint8_t MRS2_BA = 2;
+const uint8_t MRS3_BA = 3;
+const uint16_t GP4_REG_0x1013 = 0x1013;
+
+
+extern "C" {
+
+using namespace fapi;
+
+ReturnCode mss_rcd_load( Target& i_target, uint32_t i_port_number, uint32_t& io_ccs_inst_cnt);
+ReturnCode mss_mrs_load( Target& i_target, uint32_t i_port_number, uint32_t& io_ccs_inst_cnt);
+ReturnCode mss_assert_resetn_drive_mem_clks( Target& i_target);
+ReturnCode mss_deassert_force_mclk_low( Target& i_target);
+
+
+ReturnCode mss_draminit(Target& i_target)
+{
+    // Target is centaur.mba
+    //
+
+    ReturnCode rc;
+    uint32_t port_number;
+    uint32_t ccs_inst_cnt = 0;
+    uint8_t dram_gen; 
+    uint8_t dimm_type; 
+
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, dram_gen);
+    if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type);
+    if(rc) return rc;
+
+
+    if ((!(dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM)) && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3))
+    {
+        //Commented because Master Attention Reg Check not written yet.
+        //Master Attntion Reg Check... Need to add appropriate call below.
+        //MASTER_ATTENTION_REG_CHECK();
+
+        // Step one: Deassert Force_mclk_low signal     
+        rc = mss_deassert_force_mclk_low(i_target);
+        if(rc)
+        {
+            FAPI_ERR(" deassert_force_mclk_low Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
+            return rc;
+        }
+
+
+        // Step two: Assert Resetn signal, Begin driving mem clks
+        rc = mss_assert_resetn_drive_mem_clks(i_target);
+        if(rc)
+        {
+            FAPI_ERR(" assert_resetn_drive_mem_clks Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
+            return rc;
+        }
+
+        // Cycle through Ports...
+        // Ports 0-1
+        for ( port_number = 0; port_number < MAX_NUM_PORTS; port_number++)
+        {
+            if (!(dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_UDIMM))
+            {
+                // Step three: Load RCD Control Words
+                rc = mss_rcd_load(i_target, port_number, ccs_inst_cnt);
+                if(rc)
+                {
+                    FAPI_ERR(" rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
+                    return rc;
+                }
+            }
+        }
+
+        // Cycle through Ports...
+        // Ports 0-1
+        for ( port_number = 0; port_number < MAX_NUM_PORTS; port_number++)
+        {
+            // Step four: Load MRS Setting
+            rc = mss_mrs_load(i_target, port_number, ccs_inst_cnt);
+            if(rc)
+            {
+                FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
+                return rc;
+            }
+
+        }
+
+        // Execute the contents of CCS array
+        if (ccs_inst_cnt  > 0)
+        {
+	    // Set the End bit on the last CCS Instruction
+            rc = mss_ccs_set_end_bit( i_target, ccs_inst_cnt-1);
+            if(rc)
+            {
+                FAPI_ERR("CCS_SET_END_BIT FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
+                return rc;
+            }
+
+            rc = mss_execute_ccs_inst_array(i_target, 10, 10);
+            if(rc)
+            {
+                FAPI_ERR(" EXECUTE_CCS_INST_ARRAY FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
+                return rc;
+            }
+
+            ccs_inst_cnt = 0;
+        }
+        else
+        {
+            FAPI_INF("No Memory configured.");
+        }
+
+
+        // TODO:
+        // This is Commented out because RCD Parity Check has not been written yet.
+        // Check RCD Parity
+        //rc = RCD_PARITY_CHECK(i_target);
+        //if(rc){
+            //FAPI_ERR(" RCD_PARITY_CHECK FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
+            //return rc;
+        //}
+
+        //Master Attntion Reg Check... Need to add appropriate call below.
+        //MASTER_ATTENTION_REG_CHECK();
+
+    }
+    else
+    {
+        FAPI_INF( "++ COMPLICATED FLOW GOES HERE ++");
+        // TODO:
+        // This is Commented out because COMPLICATED_FLOW_CONTROL has not been written yet.
+        //COMPLICATED_FLOW_CONTROL(); //--- currently dummy function
+    }
+    return rc;
+}
+
+
+
+ReturnCode mss_deassert_force_mclk_low (Target& i_target)
+{ 
+    ReturnCode rc;
+    uint32_t rc_num = 0;
+    ecmdDataBufferBase data_buffer(64);
+
+    FAPI_INF( "+++++++++++++++++++++ DEASSERTING FORCE MCLK LOW +++++++++++++++++++++");
+
+    // Read GP4 
+    rc = fapiGetCfamRegister(i_target, GP4_REG_0x1013, data_buffer);
+    if(rc)return rc;
+    // set bit 3 high
+    rc_num = data_buffer.setBit(4);
+    if(rc_num)
+    {
+        rc.setEcmdError(rc_num);
+        return rc;
+    }
+    //  Stick it back into GP4
+    rc = fapiPutCfamRegister(i_target, GP4_REG_0x1013, data_buffer);
+    if(rc)return rc;
+
+    return rc;
+}
+
+ReturnCode mss_assert_resetn_drive_mem_clks(
+            Target& i_target
+            )
+{    
+    // mcbist_ddr_resetn = 1 -- to deassert DDR RESET#
+    //mcbist_ddr_dphy_nclk = 01, mcbist_ddr_dphy_pclk = 10 -- to drive the memory clks
+
+    ReturnCode rc;
+    ReturnCode rc_buff;
+    uint32_t rc_num = 0;
+    ecmdDataBufferBase stop_on_err_1(1);
+    ecmdDataBufferBase ue_disable_1(1);
+    ecmdDataBufferBase data_sel_2(2);
+    ecmdDataBufferBase pclk_2(2);
+    rc_num = rc_num | pclk_2.insertFromRight((uint32_t) 2, 0, 2);
+    ecmdDataBufferBase nclk_2(2);
+    rc_num = rc_num | nclk_2.insertFromRight((uint32_t) 1, 0, 2);
+    ecmdDataBufferBase cal_time_cnt_16(16);
+    ecmdDataBufferBase resetn_1(1);
+    rc_num = rc_num | resetn_1.setBit(0);
+    ecmdDataBufferBase reset_recover_1(1);
+    ecmdDataBufferBase copy_spare_cke_1(1);
+
+    FAPI_INF( "+++++++++++++++++++++ ASSERTING RESETN, DRIVING MEM CLKS +++++++++++++++++++++");
+
+    if (rc_num)
+    {
+        FAPI_ERR( "mss_assert_resetn_drive_mem_clks: Error setting up buffers");
+        rc_buff.setEcmdError(rc_num);
+        return rc_buff;
+    }
+
+    // Setting CCS Mode 
+    rc = mss_ccs_mode(i_target,
+                      stop_on_err_1,
+                      ue_disable_1,
+                      data_sel_2,
+                      pclk_2,
+                      nclk_2,
+                      cal_time_cnt_16,
+                      resetn_1,
+                      reset_recover_1,
+                      copy_spare_cke_1);
+
+    return rc;
+}
+
+ReturnCode mss_rcd_load(
+            Target& i_target,
+            uint32_t i_port_number,
+            uint32_t& io_ccs_inst_cnt
+            )    {
+
+    ReturnCode rc;
+    ReturnCode rc_buff;
+    uint32_t rc_num = 0;
+    uint32_t dimm_number;
+    uint32_t rcd_number;
+
+    ecmdDataBufferBase rcd_cntl_wrd(4);
+    ecmdDataBufferBase rcd_cntl_wrd_tmp(64);
+    uint16_t num_ranks;
+
+    ecmdDataBufferBase address_16(16);
+    ecmdDataBufferBase bank_3(3);
+    ecmdDataBufferBase activate_1(1);
+    ecmdDataBufferBase rasn_1(1);
+    rc_num = rc_num | rasn_1.setBit(0);
+    ecmdDataBufferBase casn_1(1);
+    rc_num = rc_num | casn_1.setBit(0);
+    ecmdDataBufferBase wen_1(1);
+    rc_num = rc_num | wen_1.setBit(0);
+    ecmdDataBufferBase cke_4(4);
+    rc_num = rc_num | cke_4.clearBit(0,4);
+    ecmdDataBufferBase csn_8(8);
+    rc_num = rc_num | csn_8.setBit(0,8);
+    ecmdDataBufferBase odt_4(4);
+    rc_num = rc_num | odt_4.setBit(0,4);
+    ecmdDataBufferBase ddr_cal_type_4(4);
+
+    ecmdDataBufferBase num_idles_16(16);
+    ecmdDataBufferBase num_repeat_16(16);
+    ecmdDataBufferBase data_20(20);
+    ecmdDataBufferBase read_compare_1(1);
+    ecmdDataBufferBase rank_cal_4(4);
+    ecmdDataBufferBase ddr_cal_enable_1(1);
+    ecmdDataBufferBase ccs_end_1(1);
+
+    uint8_t num_ranks_array[2][2]; //[port][dimm]
+    uint64_t rcd_array[2][2]; //[port][dimm]
+
+    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array);
+    if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target, rcd_array);
+    if(rc) return rc;
+
+    // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles
+    rc_num = rc_num | address_16.clearBit(0, 16);
+    rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16);
+    rc = mss_ccs_inst_arry_0( i_target,
+                              io_ccs_inst_cnt,
+                              address_16,
+                              bank_3,
+                              activate_1,
+                              rasn_1,
+                              casn_1,
+                              wen_1,
+                              cke_4,
+                              csn_8,
+                              odt_4,
+                              ddr_cal_type_4,
+                              i_port_number);
+    if(rc) return rc; 
+    rc = mss_ccs_inst_arry_1( i_target,
+                              io_ccs_inst_cnt,
+                              num_idles_16,
+                              num_repeat_16,
+                              data_20,
+                              read_compare_1,
+                              rank_cal_4,
+                              ddr_cal_enable_1,
+                              ccs_end_1);
+    if(rc) return rc;
+    io_ccs_inst_cnt ++;
+
+    FAPI_INF( "+++++++++++++++++++++ LOADING RCD CONTROL WORDS FOR PORT %d +++++++++++++++++++++", i_port_number);
+
+    for ( dimm_number = 0; dimm_number < MAX_NUM_DIMMS; dimm_number++)
+    {
+        num_ranks = num_ranks_array[i_port_number][dimm_number];
+
+        if (num_ranks == 0)
+        {
+            FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d", i_port_number, dimm_number, num_ranks);
+        }
+        else
+        {
+            FAPI_INF( "RCD SETTINGS FOR PORT%d DIMM%d ", i_port_number, dimm_number);
+	    FAPI_INF( "RCD Control Word: 0x%016X", rcd_array[i_port_number][dimm_number]);
+
+            if (rc_num)
+            {
+                FAPI_ERR( "mss_rcd_load: Error setting up buffers");
+                rc_buff.setEcmdError(rc_num);
+                return rc_buff;
+            }
+
+            // ALL active CS lines at a time.
+            rc_num = rc_num | csn_8.setBit(0,8);
+            if (num_ranks == 1)
+            {
+                rc_num = rc_num | csn_8.clearBit(0+4*dimm_number);
+            }
+            else if (num_ranks == 2)
+            {
+                rc_num = rc_num | csn_8.clearBit(0+4*dimm_number);
+                rc_num = rc_num | csn_8.clearBit(1+4*dimm_number);
+            }
+            else if (num_ranks == 4)
+            {
+                rc_num = rc_num | csn_8.clearBit(0+4*dimm_number);
+                rc_num = rc_num | csn_8.clearBit(1+4*dimm_number);
+                rc_num = rc_num | csn_8.clearBit(2+4*dimm_number);
+                rc_num = rc_num | csn_8.clearBit(3+4*dimm_number);
+            }
+
+            ecmdDataBufferBase rcd_number_tmp(32);
+
+            // Propogate through the 16, 4-bit control words
+            for ( rcd_number = 0; rcd_number<= 15; rcd_number++)
+            {
+                rc_num = rc_num | address_16.clearBit(0, 16);
+                rc_num = rc_num | rcd_cntl_wrd_tmp.setDoubleWord(0, rcd_array[i_port_number][dimm_number]);  
+                rc_num = rc_num | rcd_cntl_wrd_tmp.extract(rcd_cntl_wrd, 4*rcd_number, 4);
+                rc_num = rc_num | rcd_number_tmp.setWord( 0 , rcd_number);
+
+                //control word code bits A0, A1, A2, BA2
+                rc_num = rc_num | address_16.insert(rcd_number_tmp, 13, 1, 29);
+                rc_num = rc_num | address_16.insert(rcd_number_tmp, 14, 1, 30);
+                rc_num = rc_num | address_16.insert(rcd_number_tmp, 15, 1, 31);
+                rc_num = rc_num | bank_3.insert(rcd_number_tmp, 2, 1, 28);
+
+                //control word values A3, A4, BA0, BA1
+                rc_num = rc_num | address_16.insert(rcd_cntl_wrd, 3, 2, 0);
+                rc_num = rc_num | bank_3.insert(rcd_cntl_wrd, 0, 2, 2);
+
+                // Send out to the CCS array 
+                rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 12, 0, 16);
+                rc = mss_ccs_inst_arry_0( i_target,
+                                          io_ccs_inst_cnt,
+                                          address_16,
+                                          bank_3,
+                                          activate_1,
+                                          rasn_1,
+                                          casn_1,
+                                          wen_1,
+                                          cke_4,
+                                          csn_8,
+                                          odt_4,
+                                          ddr_cal_type_4,
+                                          i_port_number);
+                if(rc) return rc;
+                rc = mss_ccs_inst_arry_1( i_target,
+                                          io_ccs_inst_cnt,
+                                          num_idles_16,
+                                          num_repeat_16,
+                                          data_20,
+                                          read_compare_1,
+                                          rank_cal_4,
+                                          ddr_cal_enable_1,
+                                          ccs_end_1);
+                if(rc) return rc;
+                io_ccs_inst_cnt ++;
+
+                if (rc_num)
+                {
+                    FAPI_ERR( "mss_rcd_load: Error setting up buffers");
+                    rc_buff.setEcmdError(rc_num);
+                    return rc_buff;
+                }
+            }
+        }
+    }
+    return rc;
+}
+
+ReturnCode mss_mrs_load(
+            Target& i_target,
+            uint32_t i_port_number,
+            uint32_t& io_ccs_inst_cnt
+            )
+{
+
+    uint32_t dimm_number;
+    uint32_t rank_number;
+    uint32_t mrs_number;
+    ReturnCode rc;  
+    ReturnCode rc_buff;
+    uint32_t rc_num = 0;
+
+    ecmdDataBufferBase address_16(16);
+    ecmdDataBufferBase bank_3(3);
+    ecmdDataBufferBase activate_1(1);
+    ecmdDataBufferBase rasn_1(1);
+    rc_num = rc_num | rasn_1.clearBit(0);
+    ecmdDataBufferBase casn_1(1);
+    rc_num = rc_num | casn_1.clearBit(0);
+    ecmdDataBufferBase wen_1(1);
+    rc_num = rc_num | wen_1.clearBit(0);
+    ecmdDataBufferBase cke_4(4);
+    rc_num = rc_num | cke_4.setBit(0,4);
+    ecmdDataBufferBase csn_8(8);
+    rc_num = rc_num | csn_8.setBit(0,8);
+    ecmdDataBufferBase odt_4(4);
+    rc_num = rc_num | odt_4.setBit(0,4);
+    ecmdDataBufferBase ddr_cal_type_4(4);
+
+    ecmdDataBufferBase num_idles_16(16);
+    ecmdDataBufferBase num_repeat_16(16);
+    ecmdDataBufferBase data_20(20);
+    ecmdDataBufferBase read_compare_1(1);
+    ecmdDataBufferBase rank_cal_4(4);
+    ecmdDataBufferBase ddr_cal_enable_1(1);
+    ecmdDataBufferBase ccs_end_1(1);
+
+    ecmdDataBufferBase mrs0(16); 
+    ecmdDataBufferBase mrs1(16);
+    ecmdDataBufferBase mrs2(16);
+    ecmdDataBufferBase mrs3(16);
+    uint16_t MRS0 = 0;
+    uint16_t MRS1 = 0;
+    uint16_t MRS2 = 0;
+    uint16_t MRS3 = 0;
+
+    uint16_t num_ranks = 0;
+
+    FAPI_INF( "+++++++++++++++++++++ LOADING MRS SETTINGS FOR PORT %d +++++++++++++++++++++", i_port_number);
+
+    uint8_t num_ranks_array[2][2]; //[port][dimm]
+    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array);
+    if(rc) return rc;
+
+    //Lines commented out in the following section are waiting for xml attribute adds
+    //MRS0
+    uint8_t dram_bl;
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_BL, &i_target, dram_bl);
+    if(rc) return rc;
+    uint8_t read_bt; //Read Burst Type 
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RBT, &i_target, read_bt);
+    if(rc) return rc;
+    uint8_t dram_cl;
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_CL, &i_target, dram_cl);
+    if(rc) return rc;
+    uint8_t test_mode; //TEST MODE 
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TM, &i_target, test_mode);
+    if(rc) return rc;
+    uint8_t dll_reset; //DLL Reset 
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_RESET, &i_target, dll_reset);
+    if(rc) return rc;
+    uint8_t dram_wr;
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR, &i_target, dram_wr);
+    if(rc) return rc;
+    uint8_t dll_precharge; //DLL Control For Precharge 
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_PPD, &i_target, dll_precharge);
+    if(rc) return rc;
+
+    if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_BL8)
+    {
+        dram_bl = 0x00;
+    }
+    else if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_OTF)
+    {
+        dram_bl = 0x80;
+    }
+    else if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_BC4)
+    {
+        dram_bl = 0x40;
+    }
+
+    if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_SEQUENTIAL)
+    {
+        read_bt = 0x00;
+    }
+    else if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_INTERLEAVE)
+    {
+        read_bt = 0xFF;
+    }
+
+    if ((dram_cl > 4)&&(dram_cl < 12))
+    {
+        dram_cl = (dram_cl - 4) << 1; 
+    }
+    else if ((dram_cl > 11)&&(dram_cl > 16))
+    {
+        dram_cl = ((dram_cl - 12) << 1) + 1;   
+    }
+    dram_cl = mss_reverse_8bits(dram_cl);
+
+    if (test_mode == ENUM_ATTR_EFF_DRAM_TM_NORMAL)
+    {
+        test_mode = 0x00;
+    }
+    else if (test_mode == ENUM_ATTR_EFF_DRAM_TM_TEST)
+    {
+        test_mode = 0xFF;
+    }
+
+    if (dll_reset == ENUM_ATTR_EFF_DRAM_DLL_RESET_YES)
+    {
+        dll_reset = 0xFF;
+    }
+    else if (dll_reset == ENUM_ATTR_EFF_DRAM_DLL_RESET_NO)
+    {
+        dll_reset = 0x00;
+    }
+
+    dram_wr = mss_reverse_8bits(dram_wr);
+
+    if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_SLOWEXIT)
+    {
+        dll_precharge = 0x00;
+    }
+    else if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_FASTEXIT)
+    {
+        dll_precharge = 0xFF;
+    }
+
+    //MRS1
+    uint8_t dll_enable; //DLL Enable 
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_ENABLE, &i_target, dll_enable);
+    if(rc) return rc;
+    uint8_t out_drv_imp_cntl[2][2];
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RON, &i_target, out_drv_imp_cntl);
+    if(rc) return rc;
+    uint8_t dram_rtt_nom[2][2][4];
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RTT_NOM, &i_target, dram_rtt_nom);
+    if(rc) return rc;
+    uint8_t dram_al;
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_AL, &i_target, dram_al);
+    if(rc) return rc;
+    uint8_t wr_lvl; //write leveling enable
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_LVL_ENABLE, &i_target, wr_lvl);
+    if(rc) return rc;
+    uint8_t tdqs_enable; //TDQS Enable 
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TDQS, &i_target, tdqs_enable);
+    if(rc) return rc;
+    uint8_t q_off; //Qoff - Output buffer Enable 
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_OUTPUT_BUFFER, &i_target, q_off);
+    if(rc) return rc;
+
+    if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_ENABLE)
+    {
+        dll_enable = 0x00;
+    }
+    else if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_DISABLE)
+    {
+        dll_enable = 0xFF;
+    }
+
+    if (dram_al == ENUM_ATTR_EFF_DRAM_AL_DISABLE)
+    {
+        dram_al = 0x00;
+    }
+    else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_1)
+    {
+        dram_al = 0x80;
+    }
+    else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MUNUS_2)
+    {
+        dram_al = 0x40;
+    }
+
+    if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_DISABLE)
+    {
+        wr_lvl = 0x00;
+    }
+    else if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_ENABLE)
+    {
+        wr_lvl = 0xFF;
+    }
+
+    if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_DISABLE)
+    {
+        tdqs_enable = 0x00;
+    }
+    else if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_ENABLE)
+    {
+        tdqs_enable = 0xFF;
+    }
+
+    if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_DISABLE)
+    {
+        q_off = 0xFF;
+    }
+    else if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_ENABLE)
+    {
+        q_off = 0x00;
+    }
+
+    //MRS2
+    uint8_t pt_arr_sr; //Partial Array Self Refresh  
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_PASR, &i_target, pt_arr_sr);
+    if(rc) return rc;
+    uint8_t cwl; // CAS Write Latency 
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_CWL, &i_target, cwl);
+    if(rc) return rc;
+    uint8_t auto_sr; // Auto Self-Refresh 
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_ASR, &i_target, auto_sr);
+    if(rc) return rc;
+    uint8_t sr_temp; // Self-Refresh Temp Range 
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_SRT, &i_target, sr_temp);
+    if(rc) return rc;
+    uint8_t dram_rtt_wr[2][2][4];
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RTT_WR, &i_target, dram_rtt_wr);
+    if(rc) return rc;
+
+    if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_FULL)
+    {
+        pt_arr_sr = 0x00;
+    }
+    else if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_FIRST_HALF)
+    {
+        pt_arr_sr = 0x80;
+    }
+    else if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_FIRST_QUARTER)
+    {
+        pt_arr_sr = 0x40;
+    }
+    else if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_FIRST_EIGHTH)
+    {
+        pt_arr_sr = 0xC0;
+    }
+    else if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_LAST_THREE_FOURTH)
+    {
+        pt_arr_sr = 0x20;
+    }
+    else if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_LAST_HALF)
+    {
+        pt_arr_sr = 0xA0;
+    }
+    else if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_LAST_QUARTER)
+    {
+        pt_arr_sr = 0x60;
+    }
+    else if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_LAST_EIGHTH)
+    {
+        pt_arr_sr = 0xE0;
+    }
+
+    cwl = mss_reverse_8bits(cwl - 5); 
+
+    if (auto_sr == ENUM_ATTR_EFF_DRAM_ASR_SRT)
+    {
+        auto_sr = 0x00;
+    }
+    else if (auto_sr == ENUM_ATTR_EFF_DRAM_ASR_ASR)
+    {
+        auto_sr = 0xFF;
+    }
+
+    if (sr_temp == ENUM_ATTR_EFF_DRAM_SRT_NORMAL)
+    {
+        sr_temp = 0x00;
+    }
+    else if (sr_temp == ENUM_ATTR_EFF_DRAM_SRT_EXTEND)
+    {
+        sr_temp = 0xFF;
+    }
+
+    //MRS3
+    uint8_t mpr_loc; // MPR Location 
+    rc = FAPI_ATTR_GET(ATTR_EFF_MPR_LOC, &i_target, mpr_loc);
+    if(rc) return rc;
+    uint8_t mpr_op; // MPR Operation Mode
+    rc = FAPI_ATTR_GET(ATTR_EFF_MPR_MODE, &i_target, mpr_op);
+    if(rc) return rc;
+
+    mpr_loc = mss_reverse_8bits(mpr_loc);
+
+    if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_ENABLE)
+    {
+        mpr_op = 0x00;
+    }
+    else if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_DISABLE)
+    {
+        mpr_op = 0xFF;
+    }
+
+    // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles
+    rc_num = rc_num | csn_8.setBit(0,8);
+    rc_num = rc_num | address_16.clearBit(0, 16);
+    rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16);
+    rc = mss_ccs_inst_arry_0( i_target,
+                              io_ccs_inst_cnt,
+                              address_16,
+                              bank_3,
+                              activate_1,
+                              rasn_1,
+                              casn_1,
+                              wen_1,
+                              cke_4,
+                              csn_8,
+                              odt_4,
+                              ddr_cal_type_4,
+                              i_port_number);	     
+    if(rc) return rc;
+    rc = mss_ccs_inst_arry_1( i_target,
+                              io_ccs_inst_cnt,
+                              num_idles_16,
+                              num_repeat_16,
+                              data_20,
+                              read_compare_1,
+                              rank_cal_4,
+                              ddr_cal_enable_1,
+                              ccs_end_1);  
+    if(rc) return rc;
+    io_ccs_inst_cnt ++;
+
+    // Dimm 0-1
+    for ( dimm_number = 0; dimm_number < MAX_NUM_DIMMS; dimm_number++)
+    {
+        num_ranks = num_ranks_array[i_port_number][dimm_number];
+
+        if (num_ranks == 0)
+        {
+            FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d ", i_port_number, dimm_number, num_ranks);
+        }
+        else
+        {
+            // Rank 0-3
+            for ( rank_number = 0; rank_number < MAX_NUM_RANKS; rank_number++)
+            {
+                    FAPI_INF( "MRS SETTINGS FOR PORT%d DIMM%d RANK%d", i_port_number, dimm_number, rank_number);
+
+                    rc_num = rc_num | csn_8.setBit(0,8);
+                    rc_num = rc_num | address_16.clearBit(0, 16);
+
+                    rc_num = rc_num | mrs0.insert((uint8_t) dram_bl, 0, 2, 0);
+                    rc_num = rc_num | mrs0.insert((uint8_t) dram_cl, 2, 1, 0);
+                    rc_num = rc_num | mrs0.insert((uint8_t) read_bt, 3, 1, 0);
+                    rc_num = rc_num | mrs0.insert((uint8_t) dram_cl, 4, 3, 1);
+                    rc_num = rc_num | mrs0.insert((uint8_t) test_mode, 7, 1);
+                    rc_num = rc_num | mrs0.insert((uint8_t) dll_reset, 8, 1);
+                    rc_num = rc_num | mrs0.insert((uint8_t) dram_wr, 9, 3);
+                    rc_num = rc_num | mrs0.insert((uint8_t) dll_precharge, 12, 1);
+                    rc_num = rc_num | mrs0.insert((uint8_t) 0x00, 13, 3);
+
+	            rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0);
+
+                    if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)
+                    {
+                        dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x00;
+                    }
+                    else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20)
+                    {
+                        dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x20;
+                    }
+                    else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30)
+                    {
+                        dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xA0;
+                    }
+                    else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40)
+                    {
+                        dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xC0;
+                    }
+                    else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM60)
+                    {
+                        dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x80;
+                    }
+                    else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM120)
+                    {
+                        dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x40;
+                    }
+
+                    if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_EFF_DRAM_RON_OHM40)
+                    {
+                        out_drv_imp_cntl[i_port_number][dimm_number] = 0x00;
+                    }
+                    else if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_EFF_DRAM_RON_OHM34)
+                    {
+                        out_drv_imp_cntl[i_port_number][dimm_number] = 0x80;
+                    }
+
+                    rc_num = rc_num | mrs1.insert((uint8_t) dll_enable, 0, 1, 0);
+                    rc_num = rc_num | mrs1.insert((uint8_t) out_drv_imp_cntl[i_port_number][dimm_number], 1, 1, 0);
+                    rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][0], 2, 1, 0);
+                    rc_num = rc_num | mrs1.insert((uint8_t) dram_al, 3, 2, 0);
+                    rc_num = rc_num | mrs1.insert((uint8_t) out_drv_imp_cntl[i_port_number][dimm_number], 5, 1, 1);
+                    rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][0], 6, 1, 2);
+                    rc_num = rc_num | mrs1.insert((uint8_t) wr_lvl, 7, 1, 0);
+                    rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 8, 1);
+                    rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][0], 9, 1, 3);
+                    rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 10, 1);
+                    rc_num = rc_num | mrs1.insert((uint8_t) tdqs_enable, 11, 1, 0);
+                    rc_num = rc_num | mrs1.insert((uint8_t) q_off, 12, 1, 0);
+                    rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 13, 3);
+
+        	    rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0);
+
+
+                    if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE)
+                    {
+                        dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x00;
+                    }
+                    else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60)
+                    {
+                        dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x80;
+                    }
+                    else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120)
+                    {
+                        dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x40;
+                    }
+
+                    rc_num = rc_num | mrs2.insert((uint8_t) pt_arr_sr, 0, 3);
+                    rc_num = rc_num | mrs2.insert((uint8_t) cwl, 3, 3);
+                    rc_num = rc_num | mrs2.insert((uint8_t) auto_sr, 6, 1);
+                    rc_num = rc_num | mrs2.insert((uint8_t) sr_temp, 7, 1);
+                    rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 8, 1);
+                    rc_num = rc_num | mrs2.insert((uint8_t) dram_rtt_wr[i_port_number][dimm_number][0], 9, 2);
+                    rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 10, 6);
+
+        	    rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0);
+     
+                    rc_num = rc_num | mrs3.insert((uint8_t) mpr_loc, 0, 2);
+                    rc_num = rc_num | mrs3.insert((uint8_t) mpr_op, 2, 1);
+                    rc_num = rc_num | mrs3.insert((uint16_t) 0x0000, 3, 13);
+
+        	    rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
+        	    FAPI_INF( "MRS 0: 0x%04X", MRS0);
+        	    FAPI_INF( "MRS 1: 0x%04X", MRS1);
+        	    FAPI_INF( "MRS 2: 0x%04X", MRS2);	
+                    FAPI_INF( "MRS 3: 0x%04X", MRS3);
+
+                    if (rc_num)
+                    {
+                        FAPI_ERR( "mss_mrs_load: Error setting up buffers");
+                        rc_buff.setEcmdError(rc_num);
+                        return rc_buff;
+                    }
+
+                    // Only corresponding CS to rank
+                    rc_num = rc_num | csn_8.setBit(0,8); 
+                    rc_num = rc_num | csn_8.clearBit(rank_number+4*dimm_number);
+              
+                    // Propogate through the 4 MRS cmds
+                    for ( mrs_number = 0; mrs_number < 4; mrs_number++)
+                    {
+     
+                        // Copying the current MRS into address buffer matching the MRS_array order
+                        // Setting the bank address
+                        if (mrs_number == 0)
+                        {
+                            rc_num = rc_num | address_16.insert(mrs2, 0, 16, 0);
+                            rc_num = rc_num | bank_3.insertFromRight((uint8_t) MRS2_BA, 0, 3);
+                        }
+                        else if ( mrs_number == 1)
+                        {
+                            rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0);
+                            rc_num = rc_num | bank_3.insertFromRight((uint8_t) MRS3_BA, 0, 3);
+                        }
+                        else if ( mrs_number == 2)
+                        {
+                            rc_num = rc_num | address_16.insert(mrs1, 0, 16, 0);
+                            rc_num = rc_num | bank_3.insertFromRight((uint8_t) MRS1_BA, 0, 3);
+                        }
+                        else if ( mrs_number == 3)
+                        {
+                            rc_num = rc_num | address_16.insert(mrs0, 0, 16, 0);
+                            rc_num = rc_num | bank_3.insertFromRight((uint8_t) MRS0_BA, 0, 3);
+                        }
+                
+                        if (rc_num)
+                        {
+                            FAPI_ERR( "mss_mrs_load: Error setting up buffers");
+                            rc_buff.setEcmdError(rc_num);
+                            return rc_buff;
+                        }
+                
+                        // Send out to the CCS array 
+                        rc = mss_ccs_inst_arry_0( i_target,
+                                          io_ccs_inst_cnt,
+                                          address_16,
+                                          bank_3,
+                                          activate_1,
+                                          rasn_1,
+                                          casn_1,
+                                          wen_1,
+                                          cke_4,
+                                          csn_8,
+                                          odt_4,
+                                          ddr_cal_type_4,
+                                          i_port_number);
+                        if(rc) return rc;
+                        rc = mss_ccs_inst_arry_1( i_target,
+                                          io_ccs_inst_cnt,
+                                          num_idles_16,
+                                          num_repeat_16,
+                                          data_20,
+                                          read_compare_1,
+                                          rank_cal_4,
+                                          ddr_cal_enable_1,
+                                          ccs_end_1);
+                        if(rc) return rc;
+                        io_ccs_inst_cnt ++;
+                    }
+            }
+        }
+    }
+    return rc;
+}
+
+} //end extern C
+
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.H b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.H
new file mode 100644
index 000000000..84c9edc3b
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.H
@@ -0,0 +1,72 @@
+//  IBM_PROLOG_BEGIN_TAG
+//  This is an automatically generated prolog.
+//
+//  $Source: src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.H $
+//
+//  IBM CONFIDENTIAL
+//
+//  COPYRIGHT International Business Machines Corp. 2012
+//
+//  p1
+//
+//  Object Code Only (OCO) source materials
+//  Licensed Internal Code Source Materials
+//  IBM HostBoot Licensed Internal Code
+//
+//  The source code for this program is not published or other-
+//  wise divested of its trade secrets, irrespective of what has
+//  been deposited with the U.S. Copyright Office.
+//
+//  Origin: 30
+//
+//  IBM_PROLOG_END
+// $Id: mss_draminit.H,v 1.5 2012/02/10 21:59:20 jdsloat Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_draminit.H,v $
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE       : mss_draminit.H
+// *! DESCRIPTION : see additional comments below
+// *! OWNER NAME  : Jacob Sloat     Email: jdsloat@us.ibm.com
+// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
+// *! ADDITIONAL COMMENTS :
+//
+// Header file for mss_draminit.
+//
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|  Author: |  Date:  | Comment:
+//---------|----------|---------|-----------------------------------------------
+//  1.4    | jdsloat  |  2/10/12| & fix
+//  1.3    | jdsloat  |  2/08/12| added description to target
+//  1.2    | jdsloat  |  1/13/12| added "fapi::" and "const" in typedef to match the call in the extern
+//  1.1    | jdsloat  | 11/18/11| Updated
+
+#ifndef MSS_DRAMINITHWPB_H_
+#define MSS_DRAMINITHWPB_H_
+
+#include <fapi.H>
+
+typedef fapi::ReturnCode (*mss_draminit_FP_t)(const fapi::Target& i_target);
+
+extern "C"
+{
+
+/**
+ * @brief Draminit procedure. Loading RCD and MRS into the drams.
+ *
+ * @param[in]  i_target  Reference to centaur.mba target
+ *
+ * @return ReturnCode
+ */
+
+fapi::ReturnCode mss_draminit(const fapi::Target& i_target);
+
+} // extern "C"
+
+#endif // MSS_DRAMINITHWPB_H_
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
new file mode 100644
index 000000000..d34a18646
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
@@ -0,0 +1,610 @@
+//  IBM_PROLOG_BEGIN_TAG
+//  This is an automatically generated prolog.
+//
+//  $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C $
+//
+//  IBM CONFIDENTIAL
+//
+//  COPYRIGHT International Business Machines Corp. 2012
+//
+//  p1
+//
+//  Object Code Only (OCO) source materials
+//  Licensed Internal Code Source Materials
+//  IBM HostBoot Licensed Internal Code
+//
+//  The source code for this program is not published or other-
+//  wise divested of its trade secrets, irrespective of what has
+//  been deposited with the U.S. Copyright Office.
+//
+//  Origin: 30
+//
+//  IBM_PROLOG_END
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE : cen_draminit_mc.C
+// *! DESCRIPTION : Procedure for handing over control to the MC
+// *! OWNER NAME :  David Cadigan   Email: dcadiga@us.ibm.com
+// *! BACKUP NAME : Mark Bellows   Email: bellows@us.ibm.com
+// #! ADDITIONAL COMMENTS :
+//
+//
+//Run cen_draminit_mc.C to complete the initialization sequence. This performs the steps of
+//***Set the IML Complete bit MBSSQ(2) (SCOM Addr: 0x02011417) to indicate that IML has completed
+//***Start the refresh engines
+//***Enabling periodic calibration and power management.
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|  Author: |  Date:  | Comment:
+//---------|----------|---------|-----------------------------------------------
+//  1.14   | jdsloat  |07-Mar-12| Fixed iml_complete to match target
+//  1.13   | jdsloat  |07-Mar-12| Changed to target centaur with getChildchip, fixed buffer insert
+//  1.12   | jdsloat  |20-Feb-12| Built control_bit_ecc and power_management, added ccs_mode_reset
+//  1.11   | jdsloat  |20-Feb-12| removing #include <fapiClientCapi.H>
+//  1.10   | jdsloat  |20-Feb-12| Made Constants, Fixed RC_buff checking, Num_ranks check
+//  1.10   | jdsloat  |10-Feb-12| updated formatting/style, fixed some addresses, removed mba23 calls
+//  1.9    | M Bellows|19-Jan-12| temporarily added includes and getconfig functions
+//  1.8    | M Bellows|12-Jan-12| fixed refresh address, temporarly disabled periodic cal, 
+//         |          |         | fixed unsigned long constants, fixed variable declaration 
+//         |          |         | for calibration registers"
+//  1.7    | D Cadigan| 011012  | Changed periodic cal routine to reflect changes in registers for Centaur1
+//  1.6    | D Cadigan| 12222011| Fixed insert again
+//  1.5    | D Cadigan| 12212011| Fixed insert for buffers, modified dram_freq to temporarily calculate a value based on the method in mss_freq
+//  1.4    | D Cadigan| 12092011| Added header file
+//  1.3    | D Cadigan| 09302011| Moved to FAPI VBU directory
+//  1.2    | D Cadigan| 09282011| Converted to fapi, enhanced procedures to take in some variables.  Still need to debug those functions
+//  1.1    | D Cadigan| 04072011| Initial Copy
+
+
+//------------------------------------------------------------------------------
+// To-Do's
+//------------------------------------------------------------------------------
+// 1) Move addresses to cen_scom_addresses.H
+// 2) Add in attributes after they are added to the XML
+//------------------------------------------------------------------------------
+
+//----------------------------------------------------------------------
+//  FAPI Includes
+//----------------------------------------------------------------------
+#include <fapi.H>
+
+//----------------------------------------------------------------------
+//  Centaur function Includes
+//----------------------------------------------------------------------
+#include <mss_funcs.H>
+
+
+
+extern "C" {
+
+using namespace fapi;
+
+
+//----------------------------------------------------------------------
+//  Subroutine declarations 
+//----------------------------------------------------------------------
+ReturnCode mss_start_refresh (Target& i_mbatarget, Target& i_centarget);
+ReturnCode mss_enable_periodic_cal(Target& i_target);
+ReturnCode mss_set_iml_complete(Target& i_target);
+ReturnCode mss_enable_power_management(Target& i_target);
+ReturnCode mss_enable_control_bit_ecc(Target& i_target);
+ReturnCode mss_ccs_mode_reset(Target& i_target);
+
+//----------------------------------------------------------------------
+//  Constants - Addresses - TODO: to be moved to cen_scom_addresses.H later
+//----------------------------------------------------------------------
+const uint32_t MBA01_REF0Q_0x03010432 = 0x03010432;
+//Master Registers
+const uint64_t DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143FULL = 0x8000C00B0301143FULL;
+const uint64_t DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301143FULL = 0x8001C00B0301143FULL;
+//ZQCal Control Registers - currently not being used, need to write in settings for these regs
+const uint64_t DPHY01_DDRPHY_PC_PER_ZCAL_CONFIG_P0_0x8000C00F0301143FULL = 0x8000C00F0301143FULL;
+const uint64_t DPHY01_DDRPHY_PC_PER_ZCAL_CONFIG_P1_0x8001C00F0301143FULL = 0x8001C00F0301143FULL;
+const uint32_t MBSSQ_0x02011417 = 0x02011417;
+// Power Management addresses
+const uint32_t MBA01_PM0Q_0x03010434 = 0x03010434;
+// ECC enable addresses
+const uint32_t MBS_ECC0_MBSECCQ_0x0201144A = 0x0201144A;
+const uint32_t MBS_ECC1_MBSECCQ_0x0201148A = 0x0201148A;
+
+ReturnCode mss_draminit_mc (Target& i_target)
+{
+// Target is centaur
+//
+    ReturnCode rc;
+    std::vector<fapi::Target> l_mbaChiplets;
+
+    // Get associated MBA's on this centaur
+    rc=fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_MBA_CHIPLET, l_mbaChiplets);
+    if (rc) return rc;
+
+    // Step One: Set IML COMPLETE
+    FAPI_INF( "+++ Setting IML Complete +++");
+    rc = mss_set_iml_complete(i_target);
+    if(rc)
+    {
+       FAPI_ERR("---Error During IML Complete Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
+       return rc;
+    }
+
+    // Loop through the 2 MBA's
+    for (uint32_t i=0; i < l_mbaChiplets.size(); i++)
+    {
+
+        // Step Two: Disable CCS address lines
+        FAPI_INF( "+++ Disabling CCS Address Lines +++");
+        rc = mss_ccs_mode_reset(l_mbaChiplets[i]);
+        if(rc)
+        {
+           FAPI_ERR("---Error During CCS Mode Reset rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
+           return rc;
+        }
+
+        // Step Three: Setup Refresh Controls
+        FAPI_INF( "+++ Setting Up Refresh Controls +++");
+        rc = mss_start_refresh(l_mbaChiplets[i],i_target);
+        if(rc)
+        {
+           FAPI_ERR("---Error During Refresh Control Setup and Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
+           return rc;
+        }
+
+        // Step Four: Setup Periodic Cals
+        FAPI_INF( "+++ Setting Up Periodic Cals +++");
+        rc = mss_enable_periodic_cal(l_mbaChiplets[i]);
+        if(rc)
+        {
+           FAPI_ERR("---Error During Periodic Cal Setup and Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
+           return rc;
+        }
+
+        // Step Five: Setup Power Management
+        FAPI_INF( "+++ Setting Up Power Management +++");
+        rc = mss_enable_power_management(l_mbaChiplets[i]);
+        if(rc)
+        {
+           FAPI_ERR("---Error During Power Management Setup and Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
+           return rc;
+        }
+  
+    }
+
+    // Step Six: Setup Control Bit ECC
+    FAPI_INF( "+++ Setting Up Control Bit ECC +++");
+    rc = mss_enable_control_bit_ecc(i_target);
+    if(rc)
+    {
+        FAPI_ERR("---Error During Control Bit ECC Setup rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
+        return rc;
+    }
+
+    return rc;
+}
+
+ReturnCode mss_start_refresh (Target& i_mbatarget, Target& i_centarget)
+{
+    //Target MBA, centaur
+
+    //Variables
+    ReturnCode rc;
+    ReturnCode rc_buff;
+    uint32_t rc_num = 0;
+
+    uint32_t refresh_interval = 0;
+    uint32_t refresh_interval_reset = 0;
+    uint32_t num_ranks = 0;
+
+    //Bit 0 is enable
+    //bit 4..7 cfg_refresh_priority_threshold
+    //bit 8..18 cfg_refresh_interval
+    //bit 19..29 cfg_refresh_reset_interval
+    //bit 30..39 cfg_trfc
+    //bit 40..49 cfg_refr_tsv_stack
+    //bit 50..60 cfg_refr_check_interval
+    ecmdDataBufferBase mba01_ref0q_data_buffer_64(64);
+
+
+    uint32_t dimm_freq;
+    rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &i_centarget, dimm_freq);
+    if(rc) return rc; 
+
+    //Configure Refresh based on system attributes MBA01
+    rc = fapiGetScom(i_mbatarget, MBA01_REF0Q_0x03010432, mba01_ref0q_data_buffer_64);
+    if(rc) return rc;
+
+    //Configure Refresh Priority  Hard coded to 8 refreshes 
+    rc_num = rc_num | mba01_ref0q_data_buffer_64.setBit(4);
+    
+    //Configure Refresh Interval
+    //MBA01 - Get number of ranks, then calculate refresh rate.  
+
+    // FAPI ATTR GET NUM RANKS
+    uint8_t num_ranks_array[2][2]; //[port][dimm]
+    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_mbatarget, num_ranks_array);
+    if(rc) return rc;
+
+    // Adding them up
+    num_ranks = num_ranks_array[0][0] + num_ranks_array[0][1]+ num_ranks_array[1][0] + num_ranks_array[1][1];
+
+    if (num_ranks == 0)
+    {
+        FAPI_INF("+++ No Configured Ranks for current target +++");
+    }
+    else
+    {
+        //Now program in the refresh rate for MBA01
+
+        // TODO: Waiting for tREFI to appear as attribute in XML file 
+        // Until then tREFI will be hardcoded 
+        uint16_t trefi = 6240; // given in Nclks = 3.9us (DDR3 Jedec) at 1600
+        //rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TREFI, &i_target, num_ranks_array);
+        //if(rc) return rc;
+
+        refresh_interval = (trefi/num_ranks)/8;
+        refresh_interval_reset = refresh_interval - 1;
+        rc_num = rc_num | mba01_ref0q_data_buffer_64.insert(refresh_interval, 8,10);
+        rc_num = rc_num | mba01_ref0q_data_buffer_64.insert(refresh_interval, 50,10);
+        rc_num = rc_num | mba01_ref0q_data_buffer_64.insert(refresh_interval_reset,19,10);
+        //tRFC
+        uint8_t trfc = 0;
+        rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TRFC, &i_mbatarget, trfc);
+        if(rc) return rc;
+
+        rc_num = rc_num | mba01_ref0q_data_buffer_64.insert(trfc, 30, 8);
+        rc_num = rc_num | mba01_ref0q_data_buffer_64.insert((uint8_t) 0, 38, 2);
+
+        //Enable Refresh
+        //MBA01
+        rc_num = rc_num | mba01_ref0q_data_buffer_64.setBit(0);
+        rc = fapiPutScom(i_mbatarget, MBA01_REF0Q_0x03010432, mba01_ref0q_data_buffer_64);
+        if(rc) return rc;
+
+        if (rc_num)
+        {
+            FAPI_ERR( "mss_start_refresh: Error setting up buffers");
+            rc_buff.setEcmdError(rc_num);
+            return rc_buff;
+        }
+
+        FAPI_INF("+++ Refresh Enabled +++");
+
+    }
+
+    return rc;
+}
+
+ReturnCode mss_enable_periodic_cal (Target& i_target)
+{
+    //Target MBA
+
+    //Procedure to setup and enable periodic cals
+    //Variables
+    ReturnCode rc;
+    ReturnCode rc_buff;
+    uint32_t rc_num  = 0;
+
+    //PER CAL Types  
+    //MBA01
+
+    // TODO: Waiting for these attributes in XML
+    // Used to pull enable bits.
+    //uint8_t memcal_interval;
+    //rc = FAPI_ATTR_GET(ATTR_EFF_MEMCAL_INTERVAL, &i_target, memcal_interval);
+    //if(rc) return rc;
+    //uint8_t zqcal_interval;
+    //rc = FAPI_ATTR_GET(ATTR_EFF_ZQCAL_INTERVAL, &i_target, zqcal_interval);
+    //if(rc) return rc;
+
+    uint32_t p0_per_zqcal_mba01_ena = 1;
+    uint32_t p0_per_sysclk_mba01_ena = 1;
+    uint32_t p0_per_rd_ck_mba01_ena = 1;
+    uint32_t p0_per_rd_dqs_mba01_ena = 1;
+    uint32_t p0_per_rd_center_mba01_ena = 1;
+    uint32_t p1_per_zqcal_mba01_ena = 1;
+    uint32_t p1_per_sysclk_mba01_ena = 1;
+    uint32_t p1_per_rd_ck_mba01_ena = 1;
+    uint32_t p1_per_rd_dqs_mba01_ena = 1;
+    uint32_t p1_per_rd_center_mba01_ena = 1;
+
+    // TODO: waiting for ZQ Cal and Mem Cal intevals in XML
+    // Example one hot code.  Not the real order/decode. 
+    //p0_per_zqcal_mba01_ena = 0x1 & zqcal_interval;
+    //p1_per_zqcal_mba01_ena = 0x2 & zqcal_interval >> 1;
+    //p0_per_sysclk_mba01_ena = 0x1 & memcal_interval;
+    //p0_per_rd_ck_mba01_ena = (0x2 & memcal_interval) >> 1;
+    //p0_per_rd_dqs_mba01_ena = (0x4 & memcal_interval) >> 2;
+    //p0_per_rd_center_mba01_ena = (0x8 & memcal_interval) >> 3;
+    //p1_per_sysclk_mba01_ena = 0x1 & memcal_interval;
+    //p1_per_rd_ck_mba01_ena = (0x2 & memcal_interval) >> 1;
+    //p1_per_rd_dqs_mba01_ena = (0x4 & memcal_interval) >> 2;
+    //p1_per_rd_center_mba01_ena = (0x8 & memcal_interval) >> 3;
+
+    //DDR Calibration Register Addresses - currently not in use, need to write in settings for these regs
+    //uint32_t mba01_cal0q = 0x0301040F;
+    //uint32_t mba01_cal1q = 0x03010410;
+    //uint32_t mba01_cal2q = 0x03010411;
+
+ 
+    ecmdDataBufferBase mba01_data_buffer_64_p0(64);
+    ecmdDataBufferBase mba01_data_buffer_64_p1(64);
+
+    //Determine whether or not we want to do a particular type of calibration on the given ranks
+    //ALL CALS CURRENTLY SET AS ON, ONLY CHECK RANK PAIRS PRESENT
+    //***mba01 Setup
+    rc_num = rc_num | mba01_data_buffer_64_p0.flushTo0();
+    rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143FULL, mba01_data_buffer_64_p0);
+    if(rc) return rc;
+
+    rc_num = rc_num | mba01_data_buffer_64_p1.flushTo0();
+    rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301143FULL, mba01_data_buffer_64_p1);
+    if(rc) return rc;
+
+    uint8_t primary_rank_group0_array[2]; //[rank]
+    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, primary_rank_group0_array);
+    if(rc) return rc;
+
+    uint8_t primary_rank_group1_array[2]; //[rank]
+    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, primary_rank_group1_array);
+    if(rc) return rc;
+
+    uint8_t primary_rank_group2_array[2]; //[rank]
+    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, primary_rank_group2_array);
+    if(rc) return rc;
+
+    uint8_t primary_rank_group3_array[2]; //[rank]
+    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, primary_rank_group3_array);
+    if(rc) return rc;
+
+    if(primary_rank_group0_array[0] != 255)
+    {
+       //Rank Group 0 Enabled
+       rc_num = rc_num | mba01_data_buffer_64_p0.setBit(48);
+    }
+    if(primary_rank_group1_array[0] != 255)
+    {
+       //Rank Group 1 Enabled
+       rc_num = rc_num | mba01_data_buffer_64_p0.setBit(49);
+    }
+    if(primary_rank_group2_array[0] != 255)
+    {
+       //Rank Group 2 Enabled
+       rc_num = rc_num | mba01_data_buffer_64_p0.setBit(50);
+    }
+    if(primary_rank_group3_array[0] != 255)
+    {
+       //Rank Group 3 Enabled
+       rc_num = rc_num | mba01_data_buffer_64_p0.setBit(51);
+    }
+    if(primary_rank_group0_array[1] != 255)
+    {
+       //Rank Group 0 Enabled
+       rc_num = rc_num | mba01_data_buffer_64_p1.setBit(48);
+    }
+    if(primary_rank_group1_array[1] != 255)
+    {
+       //Rank Group 1 Enabled
+       rc_num = rc_num | mba01_data_buffer_64_p1.setBit(49);
+    }
+    if(primary_rank_group2_array[1] != 255)
+    {
+       //Rank Group 2 Enabled
+       rc_num = rc_num | mba01_data_buffer_64_p1.setBit(50);
+    }
+    if(primary_rank_group3_array[1] != 255)
+    {
+       //Rank Group 3 Enabled
+       rc_num = rc_num | mba01_data_buffer_64_p1.setBit(51);
+    }
+
+   
+    
+    //p0
+    if(p0_per_zqcal_mba01_ena == 1)
+    {
+       rc_num = rc_num | mba01_data_buffer_64_p0.setBit(52);
+    }
+    if(p0_per_sysclk_mba01_ena == 1)
+    {
+       rc_num = rc_num | mba01_data_buffer_64_p0.setBit(53);
+    }
+    if(p0_per_rd_ck_mba01_ena == 1)
+    {
+       rc_num = rc_num | mba01_data_buffer_64_p0.setBit(54);
+    }
+    if(p0_per_rd_dqs_mba01_ena == 1)
+    {
+       rc_num = rc_num | mba01_data_buffer_64_p0.setBit(55);
+    }
+    if(p0_per_rd_center_mba01_ena == 1)
+    {
+       rc_num = rc_num | mba01_data_buffer_64_p0.setBit(56);
+    }
+
+    //p1
+    if(p1_per_zqcal_mba01_ena == 1)
+    {
+       rc_num = rc_num | mba01_data_buffer_64_p1.setBit(52);
+    }
+    if(p1_per_sysclk_mba01_ena == 1)
+    {
+       rc_num = rc_num | mba01_data_buffer_64_p1.setBit(53);
+    }
+    if(p1_per_rd_ck_mba01_ena == 1)
+    {
+       rc_num = rc_num | mba01_data_buffer_64_p1.setBit(54);
+    }
+    if(p1_per_rd_dqs_mba01_ena == 1)
+    {
+       rc_num = rc_num | mba01_data_buffer_64_p1.setBit(55);
+    }
+    if(p1_per_rd_center_mba01_ena == 1)
+    {
+       rc_num = rc_num | mba01_data_buffer_64_p1.setBit(56);
+    }
+    
+    //Write the mba_p01_PER_CAL_CFG_REG
+    rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143FULL, mba01_data_buffer_64_p0);
+    if(rc) return rc;
+    FAPI_INF("+++ Periodic Calibration Enabled p0+++");
+    rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301143FULL, mba01_data_buffer_64_p1);
+    if(rc) return rc;
+    FAPI_INF("+++ Periodic Calibration Enabled p1+++");
+
+    if (rc_num)
+    {
+        FAPI_ERR( "mss_enable_periodic_cal: Error setting up buffers");
+        rc_buff.setEcmdError(rc_num);
+        return rc_buff;
+    }
+
+    return rc;
+
+}
+
+ReturnCode mss_set_iml_complete (Target& i_target)
+{
+    //Target centaur
+
+    //Set IML Complete
+    //Variables
+    ReturnCode rc;
+    ReturnCode rc_buff;
+    uint32_t rc_num  = 0; 
+    ecmdDataBufferBase data_buffer_64(64);
+
+    rc = fapiGetScom(i_target, MBSSQ_0x02011417, data_buffer_64);
+    if(rc) return rc;
+
+    rc_num = rc_num | data_buffer_64.setBit(2);
+    if (rc_num)
+    {
+        FAPI_ERR( "mss_set_iml_complete: Error setting up buffers");
+        rc_buff.setEcmdError(rc_num);
+        return rc_buff;
+    }
+
+    rc = fapiPutScom(i_target, MBSSQ_0x02011417, data_buffer_64);
+    if(rc) return rc;
+
+    FAPI_INF("+++ IML Complete Enabled +++");
+    return rc;
+}
+
+ReturnCode mss_enable_control_bit_ecc (Target& i_target)
+{
+    //Target centaur
+
+    //Enable Control Bit ECC
+    //Variables
+    ReturnCode rc;
+    ReturnCode rc_buff;
+    uint32_t rc_num  = 0;
+    ecmdDataBufferBase ecc0_data_buffer_64(64);
+    ecmdDataBufferBase ecc1_data_buffer_64(64);
+
+    rc = fapiGetScom(i_target, MBS_ECC0_MBSECCQ_0x0201144A, ecc0_data_buffer_64);
+    if(rc) return rc;
+
+    rc = fapiGetScom(i_target, MBS_ECC1_MBSECCQ_0x0201148A, ecc0_data_buffer_64);
+    if(rc) return rc;
+
+    // Enable Memory ECC Check/Correct for MBA01
+    // This assumes that all other settings of this register
+    // are set in previous precedures or initfile. 
+    rc_num = rc_num | ecc0_data_buffer_64.clearBit(0);
+    rc_num = rc_num | ecc0_data_buffer_64.clearBit(1);
+
+    // Enable Memory ECC Check/Correct for MBA23
+    // This assumes that all other settings of this register
+    // are set in previous precedures or initfile. 
+    rc_num = rc_num | ecc1_data_buffer_64.clearBit(0);
+    rc_num = rc_num | ecc1_data_buffer_64.clearBit(1);
+
+    if (rc_num)
+    {
+        FAPI_ERR( "mss_enable_control_bit_ecc: Error setting up buffers");
+        rc_buff.setEcmdError(rc_num);
+        return rc_buff;
+    }
+
+    rc = fapiPutScom(i_target, MBS_ECC0_MBSECCQ_0x0201144A, ecc0_data_buffer_64);
+    if(rc) return rc;
+
+    rc = fapiPutScom(i_target, MBS_ECC1_MBSECCQ_0x0201148A, ecc0_data_buffer_64);
+    if(rc) return rc;
+
+    FAPI_INF("+++ mss_enable_control_bit_ecc complete +++");
+    return rc;
+}
+
+ReturnCode mss_enable_power_management (Target& i_target)
+{
+    // Target MBA
+    //Enable Power Management
+    //Variables
+    ReturnCode rc;
+    ReturnCode rc_buff;
+    uint32_t rc_num  = 0;
+    ecmdDataBufferBase pm_data_buffer_64(64);
+
+    rc = fapiGetScom(i_target, MBA01_PM0Q_0x03010434, pm_data_buffer_64);
+    if(rc) return rc;
+
+    // Enable power domain control
+    // This assumes that all other settings of this register
+    // are set in previous precedures or initfile. 
+    rc_num = rc_num | pm_data_buffer_64.setBit(2);
+
+    
+    if (rc_num)
+    {
+        FAPI_ERR( "mss_enable_control_bit_ecc: Error setting up buffers");
+        rc_buff.setEcmdError(rc_num);
+        return rc_buff;
+    }
+
+    rc = fapiPutScom(i_target, MBA01_PM0Q_0x03010434, pm_data_buffer_64);
+    if(rc) return rc;
+
+    FAPI_INF("+++ mss_enable_control_bit_ecc complete +++");
+    return rc;
+}
+
+ReturnCode mss_ccs_mode_reset (Target& i_target)
+{
+
+    //Target MBA
+    //Selects address data from the mainline
+    //Variables
+    ReturnCode rc;
+    ReturnCode rc_buff;
+    uint32_t rc_num  = 0;
+    ecmdDataBufferBase ccs_mode_data_buffer_64(64);
+
+    rc = fapiGetScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, ccs_mode_data_buffer_64);
+    if(rc) return rc;
+
+    rc_num = rc_num | ccs_mode_data_buffer_64.clearBit(29);
+
+    if (rc_num)
+    {
+        FAPI_ERR( "mss_enable_control_bit_ecc: Error setting up buffers");
+        rc_buff.setEcmdError(rc_num);
+        return rc_buff;
+    }
+
+    rc = fapiPutScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, ccs_mode_data_buffer_64);
+    if(rc) return rc;
+
+    FAPI_INF("+++ mss_ccs_mode_reset complete +++");
+    return rc;
+}
+
+} //end extern C
+
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.H
new file mode 100644
index 000000000..c99d5c910
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.H
@@ -0,0 +1,56 @@
+//  IBM_PROLOG_BEGIN_TAG
+//  This is an automatically generated prolog.
+//
+//  $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.H $
+//
+//  IBM CONFIDENTIAL
+//
+//  COPYRIGHT International Business Machines Corp. 2012
+//
+//  p1
+//
+//  Object Code Only (OCO) source materials
+//  Licensed Internal Code Source Materials
+//  IBM HostBoot Licensed Internal Code
+//
+//  The source code for this program is not published or other-
+//  wise divested of its trade secrets, irrespective of what has
+//  been deposited with the U.S. Copyright Office.
+//
+//  Origin: 30
+//
+//  IBM_PROLOG_END
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|   Date:  | Author:  | Comment:
+//---------|----------|----------|-----------------------------------------------
+//  1.4    | 03/07/12 | jdsloat  | changed target to centaur
+//  1.3    | 02/17/12 | jdsloat  | Added the other &
+//  1.1    | 02/02/12 | jdsloat  | Added & and description of target type
+//  1.0    | 12/08/11 | dcadiga  | First draft.
+
+#ifndef mss_draminit_mc_H_
+#define mss_draminit_mc_H_
+#include <fapi.H>
+
+typedef fapi::ReturnCode (*mss_draminit_mc_FP_t)(const fapi::Target& target);
+
+extern "C"
+{
+
+/**
+ * @brief Draminit MC procedure. Enable MC functions and set IML complete within centaur
+ *
+ * @param[in]  i_target  Reference to centaur target
+ *
+ * @return ReturnCode
+ */
+
+fapi::ReturnCode mss_draminit_mc(const fapi::Target& target);
+
+} // extern "C"
+
+#endif // mss_draminit_mc_H_
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
new file mode 100644
index 000000000..5fb616e11
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
@@ -0,0 +1,337 @@
+//  IBM_PROLOG_BEGIN_TAG
+//  This is an automatically generated prolog.
+//
+//  $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C $
+//
+//  IBM CONFIDENTIAL
+//
+//  COPYRIGHT International Business Machines Corp. 2012
+//
+//  p1
+//
+//  Object Code Only (OCO) source materials
+//  Licensed Internal Code Source Materials
+//  IBM HostBoot Licensed Internal Code
+//
+//  The source code for this program is not published or other-
+//  wise divested of its trade secrets, irrespective of what has
+//  been deposited with the U.S. Copyright Office.
+//
+//  Origin: 30
+//
+//  IBM_PROLOG_END
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|  Author: |  Date:  | Comment:
+//---------|----------|---------|------------------------------------------------
+//  1.17   | divyakum |20-Feb-12| Adding comments to include target type 
+//  1.16   | divyakum |20-Feb-12| Replaced calls to insertFromBin with setHalfWord and setBit functions
+//  1.15   | divyakum |14-Feb-12| Removed port field from mss_ccs_mode, mss_ccs_inst_arry_1, mss_execute_ccs_inst_array. 
+//         |          |         | NOTE: compatible with mss_funcs.H v1.19 or newer 
+//  1.14   | divyakum |10-Feb-12| Added/Modified error codes, var names and declarations to meet coding guidlines
+//  1.13   | divyakum |08-Feb-12| Modified Attributes to FAPI attributes
+//         |          |         | Added rc checking
+//  1.12   | divyakum |31-Jan-12| Modified number of ports to work with Brent's userlevel.   
+//  1.11   | divyakum |20-Jan-12| Modified print messages. Fixed indentations
+//  1.16   | divyakum |20-Jan-12| Fixed CCS func names to match mss_funcs.H ver 1.16
+//         | divyakum |         | Added resetn initialization. 
+//  1.15   | bellows  |23-Dec-11| Set poll count to 100, set the end bit and when to execute the array time
+//  1.14   | divyakum |21-Dec-11| Added more info prints. Fixed Execution of CCS
+//  1.13   | bellows  |20-Dec-11| Fixed up rank loop so that it goes over both DIMMs
+//  1.12   | jdsloat  |23-Nov-11| Incremented instruction number, added info messages
+//  1.11   | jdsloat  |21-Nov-11| Got rid of GOTO argument in CCS cmds.   
+//  1.10   | divyakum |18-Nov-11| Fixed function calls to match procedure name. 
+//  1.9    | divyakum |11-Oct-11| Fix to include mss_funcs instead of cen_funcs. 
+//	   |          |         | Changed usage of array attributes. 
+//         |          |         | NOTE: Needs to be compiled with mss_funcs v1.3.
+//  1.8    | divyakum |03-Oct-11| Removed primary_ranks_arrayvariable. Fixed rank loop for Socket1
+//  1.7    | divyakum |30-Sep-11| First drop for Centaur. This code compiles
+//  1.6    | divyakum |28-Sep-11| Added Error path with cal fails. 
+//         |          |         | Modified CCS_MODE, CCS_EXECUTE call
+//  1.5    | divyakum |27-Sep-11| Updated code to match with cen_funcs.H v.1.5 
+//  1.4    | divyakum |27-Sep-11| Added capability to issue CCS cmds to a port pair where possible.
+//  1.3    | divyakum |26-Sep-11| Added calls to attributes and CCS array for ZQ and initial calibrations. 
+//         |          |         | Added rank loopers. 
+//  1.2    | jdsloat  |14-Jul-11| Proper call name fix
+//  1.1    | jdsloat  |22-Apr-11| Initial draft
+
+//TODO:
+//Enable appropriate init cal steps in PC Initial Calibration Config0 based on CAL_STEP attribute 
+//Add error path when Cal fails 
+//Enable complex training procedure based on DIMM_TYPE
+//Check BAD BYTE attribute with DISABLE DP18
+//Figure out DISABLE DP18 mapping for each physical byte. 
+//Need to add cal_timer_cnt_mult to CCS_MODE func
+
+/**
+ * @brief Draminit Training procedure. Calibrating DRAMs
+ *
+ * @param[in]  i_target  Reference to MBA target
+ *
+ * @return ReturnCode
+ */
+
+//----------------------------------------------------------------------
+//  FAPI function Includes
+//----------------------------------------------------------------------
+
+#include <fapi.H>
+
+//----------------------------------------------------------------------
+//  Centaur function Includes
+//----------------------------------------------------------------------
+#include <mss_funcs.H>
+
+//------------End My Includes-------------------------------------------
+
+
+
+extern "C" {
+
+using namespace fapi;
+
+ReturnCode mss_draminit_training(Target& target);
+
+ReturnCode mss_draminit_training(Target& target)
+{
+    // Target is centaur.mba
+    //Enums and Constants
+    enum size 
+    {
+       MAX_NUM_PORT = 2,
+       MAX_NUM_DIMM = 2,
+       MAX_NUM_GROUP = 4,
+       INVALID = 255
+    };
+    uint32_t NUM_POLL = 100;
+ 
+    ReturnCode rc;
+    ReturnCode buffer_rc;
+
+    //Issue ZQ Cal first per rank   
+    uint32_t instruction_number = 0;
+    ecmdDataBufferBase address_buffer_16(16);
+    buffer_rc = buffer_rc | address_buffer_16.setHalfWord(0, 0x0020); //Set A10 bit for ZQCal Long
+    ecmdDataBufferBase bank_buffer_8(8);
+    buffer_rc = buffer_rc | bank_buffer_8.flushTo0();
+    ecmdDataBufferBase activate_buffer_1(1);
+    buffer_rc = buffer_rc | activate_buffer_1.flushTo0();
+    ecmdDataBufferBase rasn_buffer_1(1);
+    buffer_rc = buffer_rc | rasn_buffer_1.flushTo1(); //For ZQCal rasn = 1; casn = 1; wen = 0;
+    ecmdDataBufferBase casn_buffer_1(1);
+    buffer_rc = buffer_rc | casn_buffer_1.flushTo1();
+    ecmdDataBufferBase wen_buffer_1(1);
+    buffer_rc = buffer_rc | wen_buffer_1.flushTo1();
+    ecmdDataBufferBase cke_buffer_8(8);
+    buffer_rc = buffer_rc | cke_buffer_8.flushTo1();
+    ecmdDataBufferBase csn_buffer_8(8);
+    buffer_rc = buffer_rc | csn_buffer_8.flushTo1();
+    ecmdDataBufferBase odt_buffer_8(8);
+    buffer_rc = buffer_rc | odt_buffer_8.flushTo0(); 
+    ecmdDataBufferBase test_buffer_4(4);
+    buffer_rc = buffer_rc | test_buffer_4.setBit(1); // 11XX:Initial Calibration, 01XX:External ZQ calibration
+ 
+    ecmdDataBufferBase num_idles_buffer_16(16);
+    buffer_rc = buffer_rc | num_idles_buffer_16.setHalfWord(0, 0x0400); //1024 for ZQCal
+    ecmdDataBufferBase num_repeat_buffer_16(16);
+    buffer_rc = buffer_rc | num_repeat_buffer_16.flushTo0();
+    ecmdDataBufferBase data_buffer_20(20);
+    buffer_rc = buffer_rc | data_buffer_20.flushTo0();
+    ecmdDataBufferBase read_compare_buffer_1(1);
+    buffer_rc = buffer_rc | read_compare_buffer_1.flushTo0();
+    ecmdDataBufferBase rank_cal_buffer_3(3); 
+    buffer_rc = buffer_rc | rank_cal_buffer_3.flushTo0();
+    ecmdDataBufferBase ddr_cal_enable_buffer_1(1);
+    buffer_rc = buffer_rc | ddr_cal_enable_buffer_1.flushTo1();
+    ecmdDataBufferBase ccs_end_buffer_1(1);
+    buffer_rc = buffer_rc | ccs_end_buffer_1.flushTo0();
+ 
+
+    ecmdDataBufferBase stop_on_err_buffer_1(1);
+    buffer_rc = buffer_rc | stop_on_err_buffer_1.flushTo0();
+    ecmdDataBufferBase ue_disable_buffer_1(1);
+    buffer_rc = buffer_rc | ue_disable_buffer_1.flushTo0();
+    ecmdDataBufferBase data_sel_buffer_2(2);
+    ecmdDataBufferBase pclk_buffer_2(2);
+    ecmdDataBufferBase nclk_buffer_2(2);
+    ecmdDataBufferBase cal_time_cnt_buffer_16(16);
+    buffer_rc = buffer_rc | cal_time_cnt_buffer_16.flushTo1();
+    ecmdDataBufferBase resetn_buffer_1(1);
+    buffer_rc = buffer_rc | resetn_buffer_1.setBit(0);
+    ecmdDataBufferBase reset_recover_buffer_1(1);
+    ecmdDataBufferBase copy_spare_cke_buffer_1(1);
+ 
+    if(buffer_rc)
+    {
+        FAPI_ERR( "Error setting up buffers");
+        return buffer_rc;
+    }
+
+    uint32_t current_rank = 0;
+    uint32_t port = 0;
+    uint32_t start_rank = 0;
+
+    uint8_t num_ranks_array[2][2]; //num_ranks_array[port][dimm]
+    uint8_t primary_ranks_array[4][2]; //primary_ranks_array[group][port]
+
+    //populate num_ranks_array
+    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &target, num_ranks_array);
+    if(rc) return rc;
+ 
+    //populate primary_ranks_arrays_array
+    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &target, primary_ranks_array[0]);
+    if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &target, primary_ranks_array[1]);
+    if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &target, primary_ranks_array[2]);
+    if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &target, primary_ranks_array[3]);
+    if(rc) return rc;
+   
+    for(port = 0; port < MAX_NUM_PORT; port++)
+    {
+        for(uint32_t dimm = 0; dimm < MAX_NUM_DIMM; dimm++) 
+        {
+            start_rank=(4 * dimm);
+            for(current_rank = start_rank; current_rank < start_rank + num_ranks_array[port][dimm]; current_rank++) {
+                FAPI_INF( "+++++++++++++++ Sending zqcal to port: %d rank: %d +++++++++++++++", port, current_rank);
+                buffer_rc = buffer_rc | test_buffer_4.setBit(1);
+                buffer_rc = buffer_rc | num_idles_buffer_16.setHalfWord(0,0x0400);
+                if(buffer_rc)
+                {
+                    FAPI_ERR( "Error setting up buffers");
+                    return buffer_rc;
+                }
+                //Need to add cal_timer_cnt_mult to CCS_MODE func
+                rc = mss_ccs_mode(target, stop_on_err_buffer_1, ue_disable_buffer_1, data_sel_buffer_2, pclk_buffer_2, nclk_buffer_2, cal_time_cnt_buffer_16, resetn_buffer_1, reset_recover_buffer_1, copy_spare_cke_buffer_1);
+                if(rc) return rc;
+                buffer_rc = buffer_rc | csn_buffer_8.flushTo1(); 
+                buffer_rc = buffer_rc | csn_buffer_8.clearBit(current_rank);
+                if(buffer_rc)
+                {
+                    FAPI_ERR( "Error setting up buffers");
+                    return buffer_rc;
+                }
+                if(instruction_number == 28)
+                {
+                    //CCS array is full. Issue execute.
+                    FAPI_INF( "+++++++++++++++ Execute CCS array on port: %d +++++++++++++++", port);
+                    buffer_rc = buffer_rc | ccs_end_buffer_1.flushTo1();
+                    buffer_rc = buffer_rc | bank_buffer_8.flushTo0();
+                    buffer_rc = buffer_rc | activate_buffer_1.flushTo0();
+                    buffer_rc = buffer_rc | cke_buffer_8.flushTo1();
+                    buffer_rc = buffer_rc | odt_buffer_8.flushTo0();
+                    if(buffer_rc)
+                    {
+                        FAPI_ERR( "Error setting up buffers");
+                        return buffer_rc;
+                    }
+                    rc = mss_ccs_inst_arry_0(target, instruction_number, address_buffer_16, bank_buffer_8, activate_buffer_1, rasn_buffer_1, casn_buffer_1, wen_buffer_1, cke_buffer_8, csn_buffer_8, odt_buffer_8, test_buffer_4, port);
+                    if(rc) return rc;
+                    rc = mss_ccs_inst_arry_1(target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_3, ddr_cal_enable_buffer_1, ccs_end_buffer_1);
+                    if(rc) return rc;
+                    rc = mss_execute_ccs_inst_array(target, NUM_POLL, 60);
+                    if(rc) return rc;
+                    instruction_number = 0;
+                } 
+                else 
+                {
+                    buffer_rc = buffer_rc | ccs_end_buffer_1.flushTo0();
+                    rc = mss_ccs_inst_arry_0(target, instruction_number, address_buffer_16, bank_buffer_8, activate_buffer_1, rasn_buffer_1, casn_buffer_1, wen_buffer_1, cke_buffer_8, csn_buffer_8, odt_buffer_8, test_buffer_4, port);
+                    if(rc) return rc;
+                    rc = mss_ccs_inst_arry_1(target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_3, ddr_cal_enable_buffer_1, ccs_end_buffer_1);
+                    if(rc) return rc;
+                } 
+     	        instruction_number++;
+            }
+        }   
+        buffer_rc = buffer_rc | test_buffer_4.setBit(0, 2);
+        buffer_rc = buffer_rc | num_idles_buffer_16.flushTo1();
+        buffer_rc = buffer_rc | odt_buffer_8.flushTo0();
+        buffer_rc = buffer_rc | csn_buffer_8.flushTo1();
+        buffer_rc = buffer_rc | cke_buffer_8.flushTo1();
+        buffer_rc = buffer_rc | wen_buffer_1.flushTo1();
+        buffer_rc = buffer_rc | casn_buffer_1.flushTo1();
+        buffer_rc = buffer_rc | rasn_buffer_1.flushTo1();
+        buffer_rc = buffer_rc | activate_buffer_1.flushTo0();
+        buffer_rc = buffer_rc | bank_buffer_8.flushTo0();
+        buffer_rc = buffer_rc | address_buffer_16.flushTo0();
+        if(buffer_rc)
+        {
+            FAPI_ERR( "Error setting up buffers");
+            return buffer_rc;
+        }
+
+        for(uint32_t group = 0; group < MAX_NUM_GROUP; group++)
+        {
+            if(primary_ranks_array[group][port] != INVALID) 
+            {   
+                //Check if rank group exists
+  	        FAPI_INF( "+++++++++++++++ Sending init cal to port %d rank group: %d +++++++++++++++", port, group);
+                if(instruction_number == 28) 
+                {
+                    //CCS array is full. Issue execute. 
+                    //Reset CCS array and start populating instructions
+                    buffer_rc = buffer_rc | ccs_end_buffer_1.flushTo1();
+                    rc = mss_ccs_inst_arry_0(target, instruction_number, address_buffer_16, bank_buffer_8, activate_buffer_1, rasn_buffer_1, casn_buffer_1, wen_buffer_1, cke_buffer_8, csn_buffer_8, odt_buffer_8, test_buffer_4, port);
+                    if(rc) return rc;
+                    buffer_rc = buffer_rc | rank_cal_buffer_3.insert(primary_ranks_array[group][port], 0, 3, 0);
+                    rc = mss_ccs_inst_arry_1(target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_3, ddr_cal_enable_buffer_1, ccs_end_buffer_1);
+                    if(rc) return rc;
+                    FAPI_INF( "+++++++++++++++ Execute CCS array on port: %d +++++++++++++++", port);
+                    rc = mss_execute_ccs_inst_array( target, NUM_POLL, 60);
+                    if(rc) return rc;
+                    instruction_number = 0;
+                }
+                else 
+                {
+                    buffer_rc = buffer_rc | ccs_end_buffer_1.flushTo0();
+                    rc = mss_ccs_inst_arry_0(target, instruction_number, address_buffer_16, bank_buffer_8, activate_buffer_1, rasn_buffer_1, casn_buffer_1, wen_buffer_1, cke_buffer_8, csn_buffer_8, odt_buffer_8, test_buffer_4, port);
+                    if(rc) return rc;
+                    buffer_rc = buffer_rc | rank_cal_buffer_3.insert(primary_ranks_array[group][port], 0, 3, 0);
+                    rc = mss_ccs_inst_arry_1(target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_3, ddr_cal_enable_buffer_1, ccs_end_buffer_1);
+                    if(rc) return rc;
+                }
+                instruction_number++;
+            }
+        }
+        if(instruction_number > 0) 
+        {
+            //execute CCS array even though it's not full before moving on to the next port. 
+            buffer_rc = buffer_rc | ccs_end_buffer_1.flushTo1();
+            buffer_rc = buffer_rc | ddr_cal_enable_buffer_1.flushTo0();
+            if(buffer_rc)
+            {
+                FAPI_ERR( "Error setting up buffers");
+                return buffer_rc;
+            }
+            rc = mss_ccs_inst_arry_0(target, instruction_number, address_buffer_16, bank_buffer_8, activate_buffer_1, rasn_buffer_1, casn_buffer_1, wen_buffer_1, cke_buffer_8, csn_buffer_8, odt_buffer_8, test_buffer_4, port);
+            if(rc) return rc;
+            buffer_rc = buffer_rc | rank_cal_buffer_3.flushTo0();
+            rc = mss_ccs_inst_arry_1(target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_3, ddr_cal_enable_buffer_1, ccs_end_buffer_1);
+            if(rc) return rc;
+            FAPI_INF( "+++++++++++++++ Execute CCS array on port: %d +++++++++++++++", port);
+            rc = mss_execute_ccs_inst_array( target, NUM_POLL, 60);
+            if(rc) return rc;
+            instruction_number = 0;
+            buffer_rc = buffer_rc | ddr_cal_enable_buffer_1.flushTo1();
+            buffer_rc = buffer_rc | ccs_end_buffer_1.flushTo0();
+            if(buffer_rc)
+            {
+                FAPI_ERR( "Error setting up buffers");
+                return buffer_rc;
+            }
+            
+        }  
+    } 
+    for(port = 0; port < 2; port++)
+    {
+       FAPI_INF( "+++++++++++++++ Check Cal Status on port: %d (PLACE HOLDER!) +++++++++++++++", port);
+    }
+    return rc; 
+}
+} //end extern C
+
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.H
new file mode 100644
index 000000000..d00e1d0a4
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.H
@@ -0,0 +1,54 @@
+//  IBM_PROLOG_BEGIN_TAG
+//  This is an automatically generated prolog.
+//
+//  $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.H $
+//
+//  IBM CONFIDENTIAL
+//
+//  COPYRIGHT International Business Machines Corp. 2012
+//
+//  p1
+//
+//  Object Code Only (OCO) source materials
+//  Licensed Internal Code Source Materials
+//  IBM HostBoot Licensed Internal Code
+//
+//  The source code for this program is not published or other-
+//  wise divested of its trade secrets, irrespective of what has
+//  been deposited with the U.S. Copyright Office.
+//
+//  Origin: 30
+//
+//  IBM_PROLOG_END
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|   Date:  | Author:  | Comment:
+//---------|----------|----------|-----------------------------------------------
+//  1.1    | 02/20/12 | divyakum | Added target description
+//  1.0    | 11/14/11 | divyakum | First draft.
+
+#ifndef mss_draminit_training_H_
+#define mss_draminit_training_H_
+#include <fapi.H>
+
+typedef fapi::ReturnCode (*mss_draminit_training_FP_t)(const fapi::Target target);
+
+extern "C"
+{
+
+/**
+ * @brief Draminit Training procedure. Calibrating DRAMs
+ *
+ * @param[in]  target  Reference to centaur.mba target
+ *
+ * @return ReturnCode
+ */
+
+fapi::ReturnCode mss_draminit_training(const fapi::Target target);
+
+} // extern "C"
+
+#endif // mss_draminit_training_H_
diff --git a/src/usr/hwpf/hwp/dram_training/mss_funcs.C b/src/usr/hwpf/hwp/dram_training/mss_funcs.C
new file mode 100644
index 000000000..01cb3f1b8
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_funcs.C
@@ -0,0 +1,519 @@
+//  IBM_PROLOG_BEGIN_TAG
+//  This is an automatically generated prolog.
+//
+//  $Source: src/usr/hwpf/hwp/dram_training/mss_funcs.C $
+//
+//  IBM CONFIDENTIAL
+//
+//  COPYRIGHT International Business Machines Corp. 2012
+//
+//  p1
+//
+//  Object Code Only (OCO) source materials
+//  Licensed Internal Code Source Materials
+//  IBM HostBoot Licensed Internal Code
+//
+//  The source code for this program is not published or other-
+//  wise divested of its trade secrets, irrespective of what has
+//  been deposited with the U.S. Copyright Office.
+//
+//  Origin: 30
+//
+//  IBM_PROLOG_END
+/* File mss_funcs.C created by SLOAT JACOB D. (JAKE),2D3970 on Fri Apr 22 2011. */
+
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2007
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE : mss_funcs.C
+// *! DESCRIPTION : Tools for centaur procedures
+// *! OWNER NAME : jdsloat@us.ibm.com
+// *! BACKUP NAME :
+// #! ADDITIONAL COMMENTS :
+//
+// General purpose funcs
+
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|  Author: |  Date:  | Comment:
+//---------|----------|---------|-----------------------------------------------
+//  1.23   | jdsloat  | 3/05/12 | ccs_inst_arry0 address fields reversed - needed to delete commented code out
+//  1.22   | jdsloat  | 2/17/12 | ccs_inst_arry0 address fields reversed
+//  1.21   | jdsloat  | 2/17/12 | FAPI ERRORs uncommented
+//  1.20   | jdsloat  | 2/16/12 | Initialize rc_num
+//  1.19   | 2/14/12  |  jdsloat| MBA translation, elminate unnecesary RC returns, got rid of some port arguments
+//  1.18   | 2/08/12  |  jdsloat| Target to Target&, Added Error reporting
+//  1.17   | 2/02/12  |  jdsloat| Initialized reg_address to 0 
+//  1.16   | 1/19/12  |  jdsloat| tabs to 4 spaces - properly, cke fix in mss_ccs_inst_arry_0
+//  1.15   | 1/16/12  |  jdsloat| tabs to 4 spaces
+//  1.14   | 1/13/12  |  jdsloat| Capatilization, curley brackets, "mss_" prefix, adding rc checks, argument prefixes, includes, RC checks
+//  1.13   | 1/6/12   |  jdsloat| Got rid of Globals
+//  1.12   | 12/23/11 | bellows | Printout poll count 
+//  1.11   | 12/20/11 | bellows | Fixed up ODT default value of 00 for CCS
+//  1.10   | 12/16/11 | bellows | Bit number correction for ras,cas,wen and cal_type
+//  1.9    | 12/14/11 | bellows | Fixed Bank and Address bit reversals restored others
+//  1.8    | 12/13/11 | jdsloat | Insert from right fix
+//  1.7    | 12/13/11 | jdsloat | Bank Address shift for reserved bit - 3 bits long, invert several fields in CCS0
+//  1.6    | 10/31/11 | jdsloat | CCS Update - goto_inst now assumed to be +1, CCS_fail fix, CCS_status fix
+//  1.5    | 10/18/11 | jdsloat | Debug Messages
+//  1.4    | 10/13/11 | jdsloat | End of CCS array check fix
+//  1.3    | 10/11/11 | jdsloat | Fix CS Lines, dataBuffer.insert functions
+//  1.2    | 10/05/11 | jdsloat | Convert integers to ecmdDataBufferBase in CCS_INST_1, CCS_INST_2, CCS_MODE
+//  1.1    | 10/04/11 | jdsloat | First drop of Centaur in FAPI dir
+//---------|----------|---------|-----------------------------------------------
+//  1.7    | 09/29/11 | jdsloat | Functional Changes: port flow, CCS changes, only configed CS, CCS overflow precaution etc.  Compiles.
+//  1.6    | 09/26/11 | jdsloat | Added port information.
+//  1.5    | 09/22/11 | jdsloat | Full update to FAPI.  Functional changes to match procedure.
+//  1.4    | 09/13/11 | jdsloat | First attempt at FAPI upgrade - attributes still in ecmd.
+//  1.1    | 06/27/11 | jdsloat | CCS function update
+//  1.00   | 04/22/11 | jdsloat | First drop of Centaur
+
+//----------------------------------------------------------------------
+//  Includes
+//----------------------------------------------------------------------
+
+#include <fapi.H>
+#include <mss_funcs.H>
+using namespace fapi;
+
+ReturnCode mss_ccs_set_end_bit(
+            Target& i_target,
+            uint32_t i_instruction_number
+              )
+{
+    uint32_t reg_address = 0;
+    uint32_t rc_num = 0;
+    ReturnCode rc;
+    ecmdDataBufferBase data_buffer(64);
+
+    reg_address = i_instruction_number + CCS_INST_ARRY1_AB_REG0_0x03010635;
+
+    FAPI_INF( "Setting End Bit.");
+
+    rc = fapiGetScom(i_target, reg_address, data_buffer);
+    if(rc) return rc;
+    rc_num = data_buffer.setBit(58);
+    rc.setEcmdError( rc_num);
+    if(rc) return rc;
+    rc = fapiPutScom(i_target, reg_address, data_buffer);
+    if(rc) return rc;
+
+    return rc;
+}
+
+ReturnCode mss_ccs_inst_arry_0(
+            Target& i_target,
+            uint32_t& io_instruction_number,
+            ecmdDataBufferBase i_address,
+            ecmdDataBufferBase i_bank,
+            ecmdDataBufferBase i_activate,
+            ecmdDataBufferBase i_rasn,
+            ecmdDataBufferBase i_casn,
+            ecmdDataBufferBase i_wen,
+            ecmdDataBufferBase i_cke,
+            ecmdDataBufferBase i_csn,
+            ecmdDataBufferBase i_odt,
+            ecmdDataBufferBase i_ddr_cal_type,
+            uint32_t i_port
+              )
+{
+    //Example Use:
+    //CCS_INST_ARRY_0( i_target, io_instruction_number, i_address, i_bank, i_activate, i_rasn, i_casn, i_wen, i_cke, i_csn, i_odt, i_ddr_cal_type, i_port);
+    ReturnCode rc;
+    ReturnCode rc_buff;
+    uint32_t rc_num = 0;
+    uint32_t reg_address = 0;
+    ecmdDataBufferBase data_buffer(64);
+
+    if (io_instruction_number >= 31)
+    {
+        uint32_t num_retry = 10;
+        uint32_t timer = 10;
+        rc = mss_ccs_set_end_bit( i_target, 30);
+        if(rc) return rc;
+        rc = mss_execute_ccs_inst_array( i_target, num_retry, timer);
+        if(rc) return rc;
+        io_instruction_number = 0;
+    }
+
+    reg_address = io_instruction_number + CCS_INST_ARRY0_AB_REG0_0x03010615;
+
+    rc_num = rc_num | data_buffer.insert(i_cke, 24, 4, 0);
+    rc_num = rc_num | data_buffer.insert(i_cke, 28, 4, 0);
+
+    if (i_port == 0)
+    {
+        rc_num = rc_num | data_buffer.insert(i_csn, 32, 8, 0);
+        rc_num = rc_num | data_buffer.insertFromRight((uint8_t)0xFF,40,8);
+        rc_num = rc_num | data_buffer.insert(i_odt, 48, 4, 0);
+        rc_num = rc_num | data_buffer.insertFromRight((uint8_t)0x00,52,4);
+    }
+    else
+    {
+        rc_num = rc_num | data_buffer.insert((uint8_t)0xFF,32,8);
+        rc_num = rc_num | data_buffer.insert(i_csn, 40, 8, 0);
+        rc_num = rc_num | data_buffer.insertFromRight((uint8_t)0x00,48,4);
+        rc_num = rc_num | data_buffer.insert(i_odt, 52, 4, 0);
+    }
+
+    //Placing bits into the data buffer
+    i_bank.reverse();
+    rc_num = rc_num | data_buffer.insert( i_address, 0, 16, 0);
+    rc_num = rc_num | data_buffer.insert( i_bank, 17, 3, 0);
+    rc_num = rc_num | data_buffer.insert( i_activate, 20, 1, 0);
+    rc_num = rc_num | data_buffer.insert( i_rasn, 21, 1, 0);
+    rc_num = rc_num | data_buffer.insert( i_casn, 22, 1, 0);
+    rc_num = rc_num | data_buffer.insert( i_wen, 23, 1, 0);
+    rc_num = rc_num | data_buffer.insert( i_ddr_cal_type, 56, 4, 0);
+
+    if (rc_num)
+    {
+        FAPI_ERR( "mss_ccs_inst_arry_0: Error setting up buffers");
+        rc_buff.setEcmdError(rc_num);
+        return rc_buff;
+    }
+
+    rc = fapiPutScom(i_target, reg_address, data_buffer);
+
+    return rc;
+}
+
+ReturnCode mss_ccs_inst_arry_1(
+            Target& i_target,
+            uint32_t& io_instruction_number,
+            ecmdDataBufferBase i_num_idles,
+            ecmdDataBufferBase i_num_repeat,
+            ecmdDataBufferBase i_data,
+            ecmdDataBufferBase i_read_compare,
+            ecmdDataBufferBase i_rank_cal,
+            ecmdDataBufferBase i_ddr_cal_enable,
+            ecmdDataBufferBase i_ccs_end
+            )
+{
+
+    //Example Use:
+    //CCS_INST_ARRY_1( i_target, io_instruction_number, i_num_idles, i_num_repeat, i_data, i_read_compare, i_rank_cal, i_ddr_cal_enable, i_ccs_end);
+    ReturnCode rc;
+    ReturnCode rc_buff;
+    uint32_t rc_num = 0; 
+    uint32_t reg_address = 0;
+    ecmdDataBufferBase goto_inst(5);
+
+    if (io_instruction_number >= 31)
+    {
+        uint32_t num_retry = 10;
+        uint32_t timer = 10;
+        rc = mss_ccs_set_end_bit( i_target, 30);
+        if(rc) return rc;
+        rc = mss_execute_ccs_inst_array( i_target, num_retry, timer);
+        if(rc) return rc;
+        io_instruction_number = 0;
+    }
+
+    reg_address = io_instruction_number + CCS_INST_ARRY1_AB_REG0_0x03010635;
+
+    ecmdDataBufferBase data_buffer(64);
+
+    rc_num = rc_num | goto_inst.insertFromRight(io_instruction_number + 1, 0, 5);
+
+    //Setting up a CSS Instruction Array Type 1
+    rc_num = rc_num | data_buffer.insert( i_num_idles, 0, 16, 0);
+    rc_num = rc_num | data_buffer.insert( i_num_repeat, 16, 16, 0);
+    rc_num = rc_num | data_buffer.insert( i_data, 32, 20, 0);
+    rc_num = rc_num | data_buffer.insert( i_read_compare, 52, 1, 0);
+    rc_num = rc_num | data_buffer.insert( i_rank_cal, 53, 4, 0);
+    rc_num = rc_num | data_buffer.insert( i_ddr_cal_enable, 57, 1, 0);
+    rc_num = rc_num | data_buffer.insert( i_ccs_end, 58, 1, 0);
+    rc_num = rc_num | data_buffer.insert( goto_inst, 59, 5, 0);
+
+    if (rc_num)
+    {
+        FAPI_ERR( "mss_ccs_inst_arry_1: Error setting up buffers");
+        rc_buff.setEcmdError(rc_num);
+        return rc_buff;
+    }
+
+    rc = fapiPutScom(i_target, reg_address, data_buffer);
+
+    return rc;
+}
+
+ReturnCode mss_ccs_mode(
+            Target& i_target,
+            ecmdDataBufferBase i_stop_on_err,
+            ecmdDataBufferBase i_ue_disable,
+            ecmdDataBufferBase i_data_sel,
+            ecmdDataBufferBase i_pclk,
+            ecmdDataBufferBase i_nclk,
+            ecmdDataBufferBase i_cal_time_cnt,
+            ecmdDataBufferBase i_resetn,
+            ecmdDataBufferBase i_reset_recover,
+            ecmdDataBufferBase i_copy_spare_cke
+              )
+{
+    ecmdDataBufferBase data_buffer(64);
+    ReturnCode rc;
+    ReturnCode rc_buff;
+    uint32_t rc_num = 0;
+
+
+    rc = fapiGetScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer);
+    if(rc) return rc;
+
+    //Setting up CCS mode
+    rc_num = rc_num | data_buffer.insert( i_stop_on_err, 0, 1, 0);
+    rc_num = rc_num | data_buffer.insert( i_ue_disable, 1, 1, 0);
+    rc_num = rc_num | data_buffer.insert( i_data_sel, 2, 2, 0);
+    rc_num = rc_num | data_buffer.insert( i_nclk, 4, 2, 0);
+    rc_num = rc_num | data_buffer.insert( i_pclk, 6, 2, 0);
+    rc_num = rc_num | data_buffer.insert( i_cal_time_cnt, 8, 16, 0);
+    rc_num = rc_num | data_buffer.insert( i_resetn, 24, 1, 0);
+    rc_num = rc_num | data_buffer.insert( i_reset_recover, 25, 1, 0);
+    rc_num = rc_num | data_buffer.insert( i_copy_spare_cke, 26, 1, 0);
+
+    if (rc_num)
+    {
+        FAPI_ERR( "mss_ccs_mode: Error setting up buffers");
+        rc_buff.setEcmdError(rc_num);
+        return rc_buff;
+    }
+
+    rc = fapiPutScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer);
+    if(rc) return rc;
+
+    return rc;
+}
+
+ReturnCode mss_ccs_start_stop(
+            Target& i_target,
+            bool i_start_stop
+              )
+{
+    ReturnCode rc;
+    ReturnCode rc_buff;
+    uint32_t rc_num = 0;
+    ecmdDataBufferBase data_buffer(64);
+
+
+    rc = fapiGetScom(i_target, CCS_CNTLQ_AB_REG_0x030106A5, data_buffer);
+    if(rc) return rc;
+
+    if (i_start_stop == MSS_CCS_START)
+    {
+        rc_num = rc_num | data_buffer.setBit(0,1);
+        FAPI_INF(" Executing contents of CCS." );
+    }
+    else if (i_start_stop == MSS_CCS_STOP)
+    {
+        rc_num = rc_num | data_buffer.setBit(1,1);
+        FAPI_INF(" Halting execution of the CCS." );
+    }
+
+    if (rc_num)
+    {
+        FAPI_ERR( "mss_ccs_start_stop: Error setting up buffers");
+        rc_buff.setEcmdError(rc_num);
+        return rc_buff;
+    }
+    
+    rc = fapiPutScom(i_target, CCS_CNTLQ_AB_REG_0x030106A5, data_buffer);
+
+    return rc;
+}
+
+ReturnCode mss_ccs_status_query( Target& i_target, mss_ccs_status_query_result& io_status)    {
+
+    ecmdDataBufferBase data_buffer(64);
+    ReturnCode rc;
+
+    rc = fapiGetScom(i_target, CCS_STATQ_AB_REG_0x030106A6, data_buffer);
+    if(rc) return rc;
+
+    if (data_buffer.getBit(2))
+    {
+        io_status = MSS_STAT_QUERY_FAIL;
+        return rc;
+    }
+    else if (data_buffer.getBit(0))
+    {
+        io_status = MSS_STAT_QUERY_IN_PROGRESS;
+        return rc;
+    }
+    else if (data_buffer.getBit(1))
+    {
+        io_status = MSS_STAT_QUERY_PASS;
+    }
+    else 
+    {
+        FAPI_INF("CCS Status Undetermined.");
+    }
+    return rc;
+}
+
+ReturnCode mss_ccs_fail_type(
+            Target& i_target
+            )
+{
+    ecmdDataBufferBase data_buffer(64);
+    ReturnCode rc;
+
+    rc = fapiGetScom(i_target, CCS_STATQ_AB_REG_0x030106A6, data_buffer);
+    if(rc) return rc;
+
+    if (data_buffer.getBit(3))
+    {
+        FAPI_ERR("CCS returned a FAIL condtion of \"Read Miscompare\" ");
+        FAPI_SET_HWP_ERROR(rc, RC_MSS_CCS_READ_MISCOMPARE);
+    } 
+    else if (data_buffer.getBit(4))
+    {
+        FAPI_ERR("CCS returned a FAIL condition of \"UE or SUE Error\" ");
+        FAPI_SET_HWP_ERROR(rc, RC_MSS_CCS_UE_SUE);
+    }
+    else if (data_buffer.getBit(5))
+    {
+        FAPI_ERR("CCS returned a FAIL condition of \"Calibration Operation Time Out\" ");
+        FAPI_SET_HWP_ERROR(rc, RC_MSS_CCS_CAL_TIMEOUT);
+    }
+
+    return rc;
+}
+
+ReturnCode mss_execute_ccs_inst_array(
+        Target& i_target,
+        uint32_t i_num_poll,
+        uint32_t i_wait_timer
+            )
+{
+    enum mss_ccs_status_query_result status = MSS_STAT_QUERY_IN_PROGRESS;
+    uint32_t count = 0;
+    ReturnCode rc;
+
+    rc = mss_ccs_start_stop( i_target, MSS_CCS_START);
+    if(rc) return rc;
+
+    while ((count < i_num_poll) && (status == MSS_STAT_QUERY_IN_PROGRESS))
+    {
+        rc = mss_ccs_status_query( i_target, status);
+        if(rc) return rc;
+        count++;
+        fapiDelay(i_wait_timer, i_wait_timer);
+    }
+
+    FAPI_INF("CCS Executed Polling %d times.", count);
+
+    if (status == MSS_STAT_QUERY_FAIL)
+    {
+        FAPI_ERR("CCS FAILED");    
+        rc = mss_ccs_fail_type(i_target);
+        if(rc) return rc;
+        FAPI_ERR("CCS has returned a fail.");
+    }
+    else if (status == MSS_STAT_QUERY_IN_PROGRESS)
+    {        
+        FAPI_ERR("CCS Operation Hung");
+        FAPI_ERR("CCS has returned a IN_PROGRESS status and considered Hung.");
+        rc = mss_ccs_fail_type(i_target);
+        if(rc)
+	{
+	    return rc;
+	}
+	else
+	{
+            FAPI_ERR("Returning a CCS HUNG RC Value.");
+	    FAPI_SET_HWP_ERROR(rc, RC_MSS_CCS_HUNG);
+	    return rc;
+	}
+    }
+    else if (status == MSS_STAT_QUERY_PASS)
+    {
+        FAPI_INF("CCS Executed Successfully.");
+    }
+    else 
+    {
+        FAPI_INF("CCS Status Undetermined.");
+    }
+
+    return rc;
+}
+
+uint32_t mss_reverse_32bits(uint32_t i_x)
+{
+    //reversing bit order of a 32 bit uint
+    i_x = (((i_x & 0xaaaaaaaa) >> 1) | ((i_x & 0x55555555) << 1));
+    i_x = (((i_x & 0xcccccccc) >> 2) | ((i_x & 0x33333333) << 2));
+    i_x = (((i_x & 0xf0f0f0f0) >> 4) | ((i_x & 0x0f0f0f0f) << 4));
+    i_x = (((i_x & 0xff00ff00) >> 8) | ((i_x & 0x00ff00ff) << 8));
+    return((i_x >> 16) | (i_x << 16));
+}
+
+uint8_t mss_reverse_8bits(uint8_t i_number){
+
+    //reversing bit order of a 8 bit uint
+    uint8_t temp = 0;
+    for (uint8_t loop = 0; loop < 8; loop++)
+    {
+        uint8_t bit = (i_number&(1<<loop))>>loop;
+        temp |= bit<<(7-loop);
+    }
+    return temp;
+}
+
+
+
+ReturnCode mss_rcd_parity_check(
+            Target& i_target,
+            uint32_t i_port
+            )
+{
+    //checks all ports for a parity error
+    ecmdDataBufferBase data_buffer(64);
+    ReturnCode rc;
+    ReturnCode rc_buff;
+    uint32_t rc_num = 0;
+    uint8_t port_0_error = 0;
+    uint8_t port_1_error = 0;
+    uint8_t rcd_parity_fail = 0;
+
+    rc = fapiGetScom(i_target, MBA01_CALFIR_REG_0x03010402, data_buffer);
+    if(rc) return rc;
+
+    rc_num = rc_num | data_buffer.extract(&port_0_error, 4, 1);
+    rc_num = rc_num | data_buffer.extract(&port_1_error, 7, 1);
+    rc_num = rc_num | data_buffer.extract(&rcd_parity_fail, 5, 1);
+    if (rc_num)
+    {
+        FAPI_ERR( "mss_rcd_parity_check: Error setting up buffers");
+        rc_buff.setEcmdError(rc_num);
+        return rc_buff;
+    }
+
+    FAPI_INF("Checking for RCD Parity Error.");
+
+    if (rcd_parity_fail)
+    {
+        FAPI_ERR("Ports 0 and 1 has exceeded a maximum number of RCD Parity Errors.");
+        FAPI_SET_HWP_ERROR(rc, RC_MSS_RCD_PARITY_ERROR_LIMIT);
+    }
+    else if ((port_0_error) && (i_port == 0))
+    {
+        FAPI_ERR("Port 0 has recorded an RCD Parity Error. ");
+        FAPI_SET_HWP_ERROR(rc, RC_MSS_RCD_PARITY_ERROR_PORT0);
+    }
+    else if ((port_1_error) && (i_port == 1))
+    {
+        FAPI_ERR("Port 1 has recorded an RCD Parity Error. ");
+        FAPI_SET_HWP_ERROR(rc, RC_MSS_RCD_PARITY_ERROR_PORT1);
+    }
+    else
+    {
+        FAPI_INF("No RCD Parity Errors on Port %d.", i_port);
+    }
+
+    return rc;
+}
diff --git a/src/usr/hwpf/hwp/dram_training/mss_funcs.H b/src/usr/hwpf/hwp/dram_training/mss_funcs.H
new file mode 100644
index 000000000..84143c3ff
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_funcs.H
@@ -0,0 +1,204 @@
+//  IBM_PROLOG_BEGIN_TAG
+//  This is an automatically generated prolog.
+//
+//  $Source: src/usr/hwpf/hwp/dram_training/mss_funcs.H $
+//
+//  IBM CONFIDENTIAL
+//
+//  COPYRIGHT International Business Machines Corp. 2012
+//
+//  p1
+//
+//  Object Code Only (OCO) source materials
+//  Licensed Internal Code Source Materials
+//  IBM HostBoot Licensed Internal Code
+//
+//  The source code for this program is not published or other-
+//  wise divested of its trade secrets, irrespective of what has
+//  been deposited with the U.S. Copyright Office.
+//
+//  Origin: 30
+//
+//  IBM_PROLOG_END
+/* File mss_funcs.H created by SLOAT JACOB D. (JAKE),2D3970 on Fri Apr 22 2011. */
+
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2007
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE : mss_funcs.H
+// *! DESCRIPTION : Tools for centaur procedures
+// *! OWNER NAME :
+// *! BACKUP NAME :
+// #! ADDITIONAL COMMENTS :
+//
+// CCS related and general utility functions.
+
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|  Author: |  Date:  | Comment:
+//---------|----------|---------|-----------------------------------------------
+//  1.10   | 2/14/12  | jdsloat | Comment section filled in, elimated unnecessary constant, added enums
+//  1.9    | 2/08/12  | jdsloat | Target to Target&
+//  1.8    | 2/02/12  | jdsloat | Added fapi:: to arguments in function prototypes
+//  1.7    | 1/13/12  | jdsloat | Capatilization, cleaned up includes, address names, "mss_" prefix, argument prefix
+//  1.6    | 1/6/12   | jdsloat | Added a function call
+//  1.5    | 1/5/12   | jdsloat | Got rid of Globals
+//  1.4    | 10/31/11 | jdsloat | CCS Update - goto_inst now assumed to be +1, CCS_fail fix, CCS_status fix
+//  1.3    | 10/06/11 | jdsloat | argument data type fix
+//  1.2    | 10/05/11 | jdsloat | Convert integers to ecmdDataBufferBase in CCS_INST_1, CCS_INST_2, CCS_MODE
+//  1.1    | 10/04/11 | jdsloat | First drop of Centaur in FAPI dir
+//---------|----------|---------|-----------------------------------------------
+//  1.6    | 09/29/11 | jdsloat | global CCS counts, port added to calls, temp dimms defined as #
+//  1.5    | 09/27/11 | jdsloat | Added port information.
+//  1.4    | 09/22/11 | jdsloat | Full update to FAPI.  Functional changes to match procedure.
+//  1.3    | 09/13/11 | jdsloat | First attempt at FAPI upgrade - attributes still in ecmd
+//  1.00   | 04/22/11 | jdsloat | First drop of Centaur
+
+#ifndef _MSS_FUNCS_H
+#define _MSS_FUNCS_H
+
+//----------------------------------------------------------------------
+//  Constants for CCS Operations
+//----------------------------------------------------------------------
+const uint64_t CCS_INST_ARRY0_AB_REG0_0x03010615 = 0x03010615;
+const uint64_t CCS_INST_ARRY1_AB_REG0_0x03010635 = 0x03010635;
+
+const uint64_t CCS_CNTLQ_AB_REG_0x030106A5 =   0x030106A5;
+const uint64_t CCS_MODEQ_AB_REG_0x030106A7 =   0x030106A7;
+const uint64_t CCS_STATQ_AB_REG_0x030106A6 =   0x030106A6;
+const uint64_t MBA01_CALFIR_REG_0x03010402 =   0x03010402;
+
+
+//----------------------------------------------------------------------
+//  Enums for CCS Operations
+//----------------------------------------------------------------------
+
+enum mss_ccs_status_query_result
+{
+    MSS_STAT_QUERY_PASS = 1,
+    MSS_STAT_QUERY_IN_PROGRESS = 2,
+    MSS_STAT_QUERY_FAIL = 3
+};
+
+
+
+const bool MSS_CCS_START = 0;
+const bool MSS_CCS_STOP = 1;
+
+
+//----------------------------------------------------------------------
+//  CCS FUNCS
+//----------------------------------------------------------------------
+
+//--------------------------------------------------------------
+// mss_ccs_inst_arry_0
+// Adding information to the CCS - 0 instruction array by index
+// Target = centaur.mba
+//--------------------------------------------------------------
+fapi::ReturnCode mss_ccs_inst_arry_0( fapi::Target& i_target,
+                                      uint32_t& io_instruction_number,
+                                      ecmdDataBufferBase i_address,
+                                      ecmdDataBufferBase i_bank,
+                                      ecmdDataBufferBase i_activate,
+                                      ecmdDataBufferBase i_rasn,
+                                      ecmdDataBufferBase i_casn,
+                                      ecmdDataBufferBase i_wen,
+                                      ecmdDataBufferBase i_cke,
+                                      ecmdDataBufferBase i_csn,
+                                      ecmdDataBufferBase i_odt,
+                                      ecmdDataBufferBase i_ddr_cal_type,
+                                      uint32_t i_port);
+
+//--------------------------------------------------------------
+// mss_ccs_inst_arry_1
+// Adding information to the CCS - 1 instruction array by index
+// Target = centaur.mba
+//--------------------------------------------------------------
+fapi::ReturnCode mss_ccs_inst_arry_1( fapi::Target& i_target,
+                                      uint32_t& io_instruction_number,
+                                      ecmdDataBufferBase i_num_idles,
+                                      ecmdDataBufferBase i_num_repeat,
+                                      ecmdDataBufferBase i_data,
+                                      ecmdDataBufferBase i_read_compare,
+                                      ecmdDataBufferBase i_rank_cal,
+                                      ecmdDataBufferBase i_ddr_cal_enable,
+                                      ecmdDataBufferBase i_ccs_end);
+
+//-----------------------------------------
+// mss_ccs_status_query
+// Querying the status of the CCS
+// Target = centaur.mba
+//-----------------------------------------
+fapi::ReturnCode mss_ccs_status_query( fapi::Target& i_target,
+                                       mss_ccs_status_query_result& io_status);
+
+//-----------------------------------------
+// mss_ccs_start_stop
+// Issuing a start or stop of the CCS
+// Target = centaur.mba
+//-----------------------------------------
+fapi::ReturnCode mss_ccs_start_stop( fapi::Target& i_target,
+                                     uint32_t i_start_stop);
+
+//----------------------------------------------
+// mss_ccs_mode
+// Adding info the the Mode Register of the CCS
+// Target = centaur.mba
+//----------------------------------------------
+fapi::ReturnCode mss_ccs_mode( fapi::Target& i_target,
+                               ecmdDataBufferBase i_stop_on_err,
+                               ecmdDataBufferBase i_ue_disable,
+                               ecmdDataBufferBase i_data_sel,
+                               ecmdDataBufferBase i_pclk,
+                               ecmdDataBufferBase i_nclk,
+                               ecmdDataBufferBase i_cal_time_cnt,
+                               ecmdDataBufferBase i_resetn,
+                               ecmdDataBufferBase i_reset_recover,
+                               ecmdDataBufferBase i_copy_spare_cke);
+
+//-----------------------------------------
+// mss_ccs_fail_type
+// Extracting the type of ccs fail
+// Target = centaur.mba
+//-----------------------------------------
+fapi::ReturnCode mss_ccs_fail_type( fapi::Target& i_target);
+
+//-----------------------------------
+// mss_execute_ccs_inst_array
+// Execute the CCS intruction array
+// Target = centaur.mba
+//-----------------------------------
+fapi::ReturnCode mss_execute_ccs_inst_array( fapi::Target& i_target,
+                                             uint32_t i_num_poll,
+                                             uint32_t i_wait_timer);
+
+//-------------------------------------------
+// mss_ccs_set_end_bit
+// Setting the End location of the CCS array
+// Target = centaur.mba
+//-------------------------------------------
+fapi::ReturnCode mss_ccs_set_end_bit( fapi::Target& i_target,
+                                      uint32_t i_instruction_number);
+
+//--------------------------------------------------------
+// mss_rcd_parity_check
+// Checking the Parity Error Bits associated with the RCD
+// Target = centaur.mba
+//--------------------------------------------------------
+fapi::ReturnCode mss_rcd_parity_check(fapi::Target& i_target,
+                                      uint32_t i_port);
+
+//-----------------------------------------
+// mss_reverse_32bits, mss_reverse_8bits
+// Reversing bit order of 8 or 32 bit uint
+//-----------------------------------------
+uint32_t mss_reverse_32bits( uint32_t i_x);
+uint8_t mss_reverse_8bits(uint8_t i_number);
+
+#endif /* _MSS_FUNCS_H */
+