summaryrefslogtreecommitdiffstats
path: root/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C
diff options
context:
space:
mode:
authorThi Tran <thi@us.ibm.com>2013-07-26 08:54:45 -0500
committerA. Patrick Williams III <iawillia@us.ibm.com>2013-07-30 16:34:21 -0500
commit8bd7985c3ffa660b4712643a060c826af99d8949 (patch)
treecaa9357dfd6437b9b41674f897c7e955a6fe8177 /src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C
parentc36a26b29d41692add94bddf66d0005a67dda174 (diff)
downloadtalos-hostboot-8bd7985c3ffa660b4712643a060c826af99d8949.tar.gz
talos-hostboot-8bd7985c3ffa660b4712643a060c826af99d8949.zip
INITPROC: Hostboot - Updated HWPs from defect SW213883
SW213883 Change-Id: I54f74de5103e62ee49d9e83155ae1a968f4b06d5 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5588 Tested-by: Jenkins Server Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C')
-rw-r--r--src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C30
1 files changed, 27 insertions, 3 deletions
diff --git a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C
index b94b5fbdd..689dc7672 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C
@@ -5,7 +5,7 @@
/* */
/* IBM CONFIDENTIAL */
/* */
-/* COPYRIGHT International Business Machines Corp. 2012 */
+/* COPYRIGHT International Business Machines Corp. 2012,2013 */
/* */
/* p1 */
/* */
@@ -20,7 +20,7 @@
/* Origin: 30 */
/* */
/* IBM_PROLOG_END_TAG */
-// $Id: mss_scominit.C,v 1.15 2012/11/12 03:08:50 mwuu Exp $
+// $Id: mss_scominit.C,v 1.17 2013/07/02 21:05:23 mwuu Exp $
//------------------------------------------------------------------------------
// *! (C) Copyright International Business Machines Corp. 2011
// *! All Rights Reserved -- Property of IBM
@@ -41,6 +41,8 @@
//------------------------------------------------------------------------------
// Version:| Author: | Date: | Comment:
//---------|----------|---------|-----------------------------------------------
+// 1.17 | menlowuu |02-JUL-13| Fixed vector insert for L4 targets
+// 1.16 | menlowuu |02-JUL-13| Added L4 targets for MBS initfile
// 1.15 | menlowuu |11-NOV-12| Removed include of dimmBadDqBitmapFuncs.H>
// 1.14 | menlowuu |09-NOV-12| Removed mss_set_bbm_regs FN since now handled
// in draminit_training.
@@ -91,7 +93,7 @@ extern "C" {
ReturnCode mss_scominit(const Target & i_target) {
ReturnCode rc;
- std::vector<Target> vector_targets;
+ std::vector<Target> vector_targets, vector_l4_targets;
const char* mbs_if[] = {
"mbs_def.if",
/* "mbs_mcbist.if" // moved into mbs_def file */
@@ -130,6 +132,28 @@ ReturnCode mss_scominit(const Target & i_target) {
// insert centaur target at beginning of vector
vector_targets.insert(vector_targets.begin(),i_target);
+ FAPI_INF("Getting L4 targets");
+ // Get L4 vectors
+ rc = fapiGetChildChiplets(i_target, TARGET_TYPE_L4,
+ vector_l4_targets, TARGET_STATE_PRESENT);
+
+ if (rc)
+ {
+ FAPI_ERR("Error from fapiGetChildChiplets getting L4 targets!");
+ FAPI_ERR("RC = 0x%x", static_cast<uint32_t>(rc));
+ return (rc);
+ }
+
+ if (vector_l4_targets.size() != 1)
+ {
+ FAPI_ERR("Error target does not have L4!");
+ FAPI_ERR("RC = 0x%x", static_cast<uint32_t>(rc));
+ return (rc);
+ }
+
+ // insert L4 targets at the end
+ vector_targets.insert(vector_targets.end(),vector_l4_targets.begin(), vector_l4_targets.end());
+
// run mbs initfile...
uint8_t num_mbs_files = sizeof(mbs_if)/sizeof(char*);
for (uint8_t itr=0; itr < num_mbs_files; itr++)
OpenPOWER on IntegriCloud