SW289468: INITPROC: FSP&Hostboot - Changes for Naples

CMVC-Coreq: 947204
CQ:SW289468
Change-Id: I5d139ba3a6b003d05e8841e27f2414859010ea4a
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/14867
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/14910
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

5 files changed, 134 insertions, 46 deletions

diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C
index dd560543d..fd008021b 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_pcie_config.C,v 1.9 2014/08/27 14:53:48 jmcgill Exp $
+// $Id: proc_pcie_config.C,v 1.10 2014/11/18 17:41:59 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_config.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -97,12 +97,14 @@ fapi::ReturnCode proc_pcie_config_pbcq(
 //             clear FIR/WOF
 //             initialize FIR action settings
 //             reset FIR masks
-// parameters: i_target => processor chip target
+// parameters: i_target  => processor chip target
+//             i_num_phb => number of PHB units
 // returns: FAPI_RC_SUCCESS if all actions are successful,
 //          else error
 //------------------------------------------------------------------------------
 fapi::ReturnCode proc_pcie_config_pbcq_fir(
-    const fapi::Target & i_target)
+    const fapi::Target & i_target,
+    uint8_t i_num_phb)
 {
     fapi::ReturnCode rc;
     uint32_t rc_ecmd = 0;
@@ -113,7 +115,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir(
     FAPI_INF("proc_pcie_config_pbcq_fir: Start");
 
     // loop over all PHBs
-    for (size_t i = 0; i < PROC_PCIE_CONFIG_NUM_PHB; i++)
+    for (size_t i = 0; i < i_num_phb; i++)
     {
         // clear FIR
         rc_ecmd |= data.flushTo0();
@@ -133,7 +135,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir(
                      i, PROC_PCIE_CONFIG_PCIE_NEST_FIR[i]);
             break;
         }
-
+    
         // clear FIR WOF
         rc = fapiPutScom(i_target,
                          PROC_PCIE_CONFIG_PCIE_NEST_FIR_WOF[i],
@@ -144,7 +146,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir(
                      i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_WOF[i]);
             break;
         }
-
+    
         // set action0
         rc_ecmd |= data.setDoubleWord(0, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0_VAL);
         if (rc_ecmd)
@@ -154,7 +156,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir(
             rc.setEcmdError(rc_ecmd);
             break;
         }
-
+    
         rc = fapiPutScom(i_target,
                          PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0[i],
                          data);
@@ -164,7 +166,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir(
                      i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0[i]);
             break;
         }
-
+    
         // set action1
         rc_ecmd |= data.setDoubleWord(0, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1_VAL);
         if (rc_ecmd)
@@ -174,7 +176,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir(
             rc.setEcmdError(rc_ecmd);
             break;
         }
-
+    
         rc = fapiPutScom(i_target,
                          PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1[i],
                          data);
@@ -184,7 +186,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir(
                      i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1[i]);
             break;
         }
-
+    
         // set mask
         rc_ecmd |= data.setDoubleWord(0, PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK_VAL);
         if (rc_ecmd)
@@ -194,7 +196,7 @@ fapi::ReturnCode proc_pcie_config_pbcq_fir(
             rc.setEcmdError(rc_ecmd);
             break;
         }
-
+    
         rc = fapiPutScom(i_target,
                          PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK[i],
                          data);
@@ -218,6 +220,7 @@ fapi::ReturnCode proc_pcie_config(
 {
     fapi::ReturnCode rc;
     uint8_t pcie_enabled;
+    uint8_t num_phb;
 
     // mark HWP entry
     FAPI_INF("proc_pcie_config: Start");
@@ -247,6 +250,16 @@ fapi::ReturnCode proc_pcie_config(
         // atttribute is set)
         if (pcie_enabled == fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE)
         {
+            // determine PHB configuration
+            rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_NUM_PHB,
+                               &i_target,
+                               num_phb);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_pcie_config: Error from FAPI_ATTR_GET (ATTR_PROC_PCIE_NUM_PHB)");
+                break;
+            }
+
             rc = proc_pcie_config_pbcq(i_target);
             if (!rc.ok())
             {
@@ -254,7 +267,7 @@ fapi::ReturnCode proc_pcie_config(
                 break;
             }
 
-            rc = proc_pcie_config_pbcq_fir(i_target);
+            rc = proc_pcie_config_pbcq_fir(i_target, num_phb);
             if (!rc.ok())
             {
                 FAPI_ERR("proc_pcie_config: Error from proc_pcie_config_pbcq_fir");
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H
index 1ab683f2f..564471d99 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_pcie_config.H,v 1.4 2014/02/03 15:58:53 jmcgill Exp $
+// $Id: proc_pcie_config.H,v 1.5 2014/11/18 17:41:59 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_config.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -57,41 +57,46 @@
 const char * const PROC_PCIE_CONFIG_PHASE2_IF = "p8.pe.phase2.scom.if";
 
 // PCIe physical constants
-const uint8_t PROC_PCIE_CONFIG_NUM_PHB = 3;
+const uint8_t PROC_PCIE_CONFIG_NUM_PHB = 4;
 
 const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR[PROC_PCIE_CONFIG_NUM_PHB] =
 {
     PCIE0_FIR_0x02012000,
     PCIE1_FIR_0x02012400,
-    PCIE2_FIR_0x02012800
+    PCIE2_FIR_0x02012800,
+    PCIE3_FIR_0x02012C00
 };
 
 const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_WOF[PROC_PCIE_CONFIG_NUM_PHB] =
 {
     PCIE0_FIR_WOF_0x02012008,
     PCIE1_FIR_WOF_0x02012408,
-    PCIE2_FIR_WOF_0x02012808
+    PCIE2_FIR_WOF_0x02012808,
+    PCIE3_FIR_WOF_0x02012C08
 };
 
 const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0[PROC_PCIE_CONFIG_NUM_PHB] =
 {
     PCIE0_FIR_ACTION0_0x02012006,
     PCIE1_FIR_ACTION0_0x02012406,
-    PCIE2_FIR_ACTION0_0x02012806
+    PCIE2_FIR_ACTION0_0x02012806,
+    PCIE3_FIR_ACTION0_0x02012C06
 };
 
 const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1[PROC_PCIE_CONFIG_NUM_PHB] =
 {
     PCIE0_FIR_ACTION1_0x02012007,
     PCIE1_FIR_ACTION1_0x02012407,
-    PCIE2_FIR_ACTION1_0x02012807
+    PCIE2_FIR_ACTION1_0x02012807,
+    PCIE3_FIR_ACTION1_0x02012C07
 };
 
 const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK[PROC_PCIE_CONFIG_NUM_PHB] =
 {
     PCIE0_FIR_MASK_0x02012003,
     PCIE1_FIR_MASK_0x02012403,
-    PCIE2_FIR_MASK_0x02012803
+    PCIE2_FIR_MASK_0x02012803,
+    PCIE3_FIR_MASK_0x02012C03
 };
 
 const uint64_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0_VAL = 0x5B0F819000000000ULL;
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C
index 3d2148aa5..a4e986408 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_setup_bars.C,v 1.24 2014/08/05 20:43:38 jmcgill Exp $
+// $Id: proc_setup_bars.C,v 1.25 2014/11/18 17:43:18 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -948,6 +948,17 @@ fapi::ReturnCode proc_setup_bars_process_chip(
         FAPI_DBG("proc_setup_bars_process_chip: Target: %s",
                  io_smp_chip.chip->this_chip.toEcmdString());
 
+        // determine number of PHBs
+        FAPI_DBG("proc_setup_bars_process_chip: Querying PHB configuration");
+        rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_NUM_PHB,
+                           &(io_smp_chip.chip->this_chip),
+                           io_smp_chip.num_phb);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_PROC_PCIE_NUM_PHB");
+            break;
+        }
+
         // get PCIe/DSMP mux attributes
         FAPI_DBG("proc_setup_bars_process_chip: Querying PCIe/DSMP mux attribute");
         rc = proc_fab_smp_get_pcie_dsmp_mux_attrs(&(io_smp_chip.chip->this_chip),
@@ -1469,6 +1480,7 @@ fapi::ReturnCode proc_setup_bars_l3_write_local_chip_memory_bar_attr(
 // function: wrapper function to write PCIe BARs specific to enabled local
 //           chip non-mirrored/mirrored memory ranges
 // parameters: i_target             => chip target
+//             i_num_phb            => number of PHBs
 //             i_non_mirrored_range => structure representing chip non-mirrored
 //                                     address range
 //             i_mirrored_range     => structure representing chip mirrored
@@ -1478,6 +1490,7 @@ fapi::ReturnCode proc_setup_bars_l3_write_local_chip_memory_bar_attr(
 //------------------------------------------------------------------------------
 fapi::ReturnCode proc_setup_bars_pcie_write_local_chip_memory_bars(
     const fapi::Target& i_target,
+    const uint8_t i_num_phb,
     const proc_setup_bars_addr_range& i_non_mirrored_range,
     const proc_setup_bars_addr_range& i_mirrored_range)
 {
@@ -1487,7 +1500,7 @@ fapi::ReturnCode proc_setup_bars_pcie_write_local_chip_memory_bars(
     FAPI_DBG("proc_setup_bars_pcie_write_local_chip_memory_bars: Start");
     // loop over all units
     for (uint8_t u = 0;
-         u < PROC_SETUP_BARS_PCIE_NUM_UNITS;
+         u < i_num_phb;
          u++)
     {
         if (i_non_mirrored_range.enabled)
@@ -1677,6 +1690,7 @@ fapi::ReturnCode proc_setup_bars_l3_write_local_node_memory_bar_attr(
 // function: wrapper function to write PCIe BARs specific to enabled local
 //           node non-mirrored/mirrored memory ranges
 // parameters: i_target             => chip target
+//             i_num_phb            => number of PHBs
 //             i_non_mirrored_range => structure representing node non-mirrored
 //                                     address range
 //             i_mirrored_range     => structure representing node mirrored
@@ -1686,6 +1700,7 @@ fapi::ReturnCode proc_setup_bars_l3_write_local_node_memory_bar_attr(
 //------------------------------------------------------------------------------
 fapi::ReturnCode proc_setup_bars_pcie_write_local_node_memory_bars(
     const fapi::Target& i_target,
+    const uint8_t i_num_phb,
     const proc_setup_bars_addr_range& i_non_mirrored_range,
     const proc_setup_bars_addr_range& i_mirrored_range)
 {
@@ -1695,7 +1710,7 @@ fapi::ReturnCode proc_setup_bars_pcie_write_local_node_memory_bars(
     FAPI_DBG("proc_setup_bars_pcie_write_local_node_memory_bars: Start");
     // loop over all units
     for (uint8_t u = 0;
-         u < PROC_SETUP_BARS_PCIE_NUM_UNITS;
+         u < i_num_phb;
          u++)
     {
         if (i_non_mirrored_range.enabled)
@@ -1740,6 +1755,7 @@ fapi::ReturnCode proc_setup_bars_pcie_write_local_node_memory_bars(
 //           chip near/far foreign memory ranges
 //           NOTE: only links which are marked for processing will be acted on
 // parameters: i_target              => chip target
+//             i_num_phb             => number of PHBs
 //             i_process_links       => array of boolean values dictating which
 //                                      links should be acted on (one per link)
 //             i_foreign_near_ranges => array of structures representing
@@ -1751,6 +1767,7 @@ fapi::ReturnCode proc_setup_bars_pcie_write_local_node_memory_bars(
 //------------------------------------------------------------------------------
 fapi::ReturnCode proc_setup_bars_pcie_write_foreign_memory_bars(
     const fapi::Target& i_target,
+    const uint8_t i_num_phb,
     const bool i_process_links[PROC_FAB_SMP_NUM_F_LINKS],
     const proc_setup_bars_addr_range i_foreign_near_ranges[PROC_FAB_SMP_NUM_F_LINKS],
     const proc_setup_bars_addr_range i_foreign_far_ranges[PROC_FAB_SMP_NUM_F_LINKS])
@@ -1762,7 +1779,7 @@ fapi::ReturnCode proc_setup_bars_pcie_write_foreign_memory_bars(
 
     // loop over all units
     for (uint8_t u = 0;
-         (u < PROC_SETUP_BARS_PCIE_NUM_UNITS) && (rc.ok());
+         (u < i_num_phb) && (rc.ok());
          u++)
     {
         // process ranges
@@ -1811,6 +1828,7 @@ fapi::ReturnCode proc_setup_bars_pcie_write_foreign_memory_bars(
 //------------------------------------------------------------------------------
 // function: wrapper function to write enabled PCIe IO BARs
 // parameters: i_target       => chip target
+//             i_num_phb      => number of PHBs
 //             io_addr_ranges => 2D array of address range structures
 //                               encapsulating attribute values
 //                               (first dimension = unit, second dimension =
@@ -1821,6 +1839,7 @@ fapi::ReturnCode proc_setup_bars_pcie_write_foreign_memory_bars(
 //------------------------------------------------------------------------------
 fapi::ReturnCode proc_setup_bars_pcie_write_io_bar_regs(
     const fapi::Target& i_target,
+    const uint8_t i_num_phb,
     const proc_setup_bars_addr_range addr_ranges[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT])
 {
     // return code
@@ -1830,7 +1849,7 @@ fapi::ReturnCode proc_setup_bars_pcie_write_io_bar_regs(
     FAPI_DBG("proc_setup_bars_pcie_write_io_bar_regs: Start");
     // loop over all units
     for (uint8_t u = 0;
-         u < PROC_SETUP_BARS_PCIE_NUM_UNITS;
+         u < i_num_phb;
          u++)
     {
         // enable bit/mask bit per range
@@ -2040,6 +2059,15 @@ fapi::ReturnCode proc_setup_bars_pcie_write_io_bar_regs(
 //   PCIE2 IO BAR2                            (PCIE2_IO_BAR2_0x02012842)
 //   PCIE2 IO BAR Enable                      (PCIE2_IO_BAR_EN_0x02012845)
 //
+//   PCIE3 Nodal Non-Mirrored BAR             (PCIE3_NODAL_BAR0_0x02012C10)
+//   PCIE3 Nodal Mirrored BAR                 (PCIE3_NODAL_BAR1_0x02012C11)
+//   PCIE3 IO BAR0                            (PCIE3_IO_BAR0_0x02012C40)
+//   PCIE3 IO BAR0 Mask                       (PCIE3_IO_MASK0_0x02012C43)
+//   PCIE3 IO BAR1                            (PCIE3_IO_BAR1_0x02012C41)
+//   PCIE3 IO BAR1 Mask                       (PCIE3_IO_MASK1_0x02012C44)
+//   PCIE3 IO BAR2                            (PCIE3_IO_BAR2_0x02012C42)
+//   PCIE3 IO BAR Enable                      (PCIE3_IO_BAR_EN_0x02012C45)
+//
 //------------------------------------------------------------------------------
 fapi::ReturnCode
 proc_setup_bars_write_local_chip_region_bars(
@@ -2346,6 +2374,7 @@ proc_setup_bars_write_local_chip_region_bars(
         {
             rc = proc_setup_bars_pcie_write_local_chip_memory_bars(
                 i_smp_chip.chip->this_chip,
+                i_smp_chip.num_phb,
                 i_smp_chip.non_mirrored_range,
                 i_smp_chip.mirrored_range);
             if (!rc.ok())
@@ -2360,6 +2389,7 @@ proc_setup_bars_write_local_chip_region_bars(
         {
             rc = proc_setup_bars_pcie_write_io_bar_regs(
                 i_smp_chip.chip->this_chip,
+                i_smp_chip.num_phb,
                 i_smp_chip.pcie_ranges);
             if (!rc.ok())
             {
@@ -2405,6 +2435,9 @@ proc_setup_bars_write_local_chip_region_bars(
 //   PCIE2 Group Non-Mirrored BAR             (PCIE2_GROUP_BAR0_0x02012812)
 //   PCIE2 Group Mirrored BAR                 (PCIE2_GROUP_BAR1_0x02012813)
 //
+//   PCIE3 Group Non-Mirrored BAR             (PCIE3_GROUP_BAR0_0x02012C12)
+//   PCIE3 Group Mirrored BAR                 (PCIE3_GROUP_BAR1_0x02012C13)
+//
 //------------------------------------------------------------------------------
 fapi::ReturnCode
 proc_setup_bars_write_local_node_region_bars(
@@ -2511,6 +2544,7 @@ proc_setup_bars_write_local_node_region_bars(
         {
             rc = proc_setup_bars_pcie_write_local_node_memory_bars(
                 i_smp_chip.chip->this_chip,
+                i_smp_chip.num_phb,
                 i_smp_node.non_mirrored_range,
                 i_smp_node.mirrored_range);
             if (!rc.ok())
@@ -2718,11 +2752,16 @@ proc_setup_bars_write_remote_node_region_bars(
 //   PCIE1 F1 Near BAR                        (PCIE1_NEAR_BAR_F1_0x02012416)
 //   PCIE1 F1 Far BAR                         (PCIE1_FAR_BAR_F1_0x02012417)
 //
-//   PCIE2 F0 Near BAR                        (PCIE2_NEAR_BAR_F0_0x02012484)
+//   PCIE2 F0 Near BAR                        (PCIE2_NEAR_BAR_F0_0x02012814)
 //   PCIE2 F0 Far BAR                         (PCIE2_FAR_BAR_F0_0x02012815)
 //   PCIE2 F1 Near BAR                        (PCIE2_NEAR_BAR_F1_0x02012816)
 //   PCIE2 F1 Far BAR                         (PCIE2_FAR_BAR_F1_0x02012817)
 //
+//   PCIE3 F0 Near BAR                        (PCIE3_NEAR_BAR_F0_0x02012C14)
+//   PCIE3 F0 Far BAR                         (PCIE3_FAR_BAR_F0_0x02012C15)
+//   PCIE3 F1 Near BAR                        (PCIE3_NEAR_BAR_F1_0x02012C16)
+//   PCIE3 F1 Far BAR                         (PCIE3_FAR_BAR_F1_0x02012C17)
+//
 //------------------------------------------------------------------------------
 fapi::ReturnCode
 proc_setup_bars_write_foreign_region_bars(
@@ -2746,6 +2785,7 @@ proc_setup_bars_write_foreign_region_bars(
         {
             rc = proc_setup_bars_pcie_write_foreign_memory_bars(
                 i_smp_chip.chip->this_chip,
+                i_smp_chip.num_phb,
                 process_links,
                 i_smp_chip.foreign_near_ranges,
                 i_smp_chip.foreign_far_ranges);
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_defs.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_defs.H
index 4cc618325..f05058f54 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_defs.H
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_defs.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
+/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -22,13 +22,13 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_setup_bars_defs.H,v 1.1 2014/08/05 20:43:46 jmcgill Exp $
+// $Id: proc_setup_bars_defs.H,v 1.2 2014/11/18 17:43:18 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars_defs.H,v $
 //------------------------------------------------------------------------------
 // *|
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
-// *! *** ***
+// *! ***  ***
 // *|
 // *! TITLE       : proc_setup_bars_defs.H
 // *! DESCRIPTION : Structure/constant definitions for proc_setup_bars HWP (FAPI)
@@ -94,7 +94,7 @@ const uint8_t PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES = 8;
 const uint8_t PROC_SETUP_BARS_NUM_MIRRORED_RANGES = 4;
 
 // PCIe unit contstants
-const uint8_t PROC_SETUP_BARS_PCIE_NUM_UNITS = 3;
+const uint8_t PROC_SETUP_BARS_PCIE_NUM_UNITS = 4;
 const uint8_t PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT = 3;
 
 
@@ -242,6 +242,8 @@ struct proc_setup_bars_smp_chip
     // partial good attributes
     bool nx_enabled;
     bool pcie_enabled;
+    // number of valid PCIe PHBs
+    uint8_t num_phb;
     // select for PCIe/DSMP mux (one per link)
     bool pcie_not_f_link[PROC_FAB_SMP_NUM_F_LINKS];
     // real address ranges covered by resources on this chip
@@ -982,28 +984,32 @@ const uint32_t PROC_SETUP_BARS_PCIE_CHIP_NON_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_N
 {
     PCIE0_NODAL_BAR0_0x02012010,
     PCIE1_NODAL_BAR0_0x02012410,
-    PCIE2_NODAL_BAR0_0x02012810
+    PCIE2_NODAL_BAR0_0x02012810,
+    PCIE3_NODAL_BAR0_0x02012C10,
 };
 
 const uint32_t PROC_SETUP_BARS_PCIE_CHIP_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS] =
 {
     PCIE0_NODAL_BAR1_0x02012011,
     PCIE1_NODAL_BAR1_0x02012411,
-    PCIE2_NODAL_BAR1_0x02012811
+    PCIE2_NODAL_BAR1_0x02012811,
+    PCIE3_NODAL_BAR1_0x02012C11
 };
 
 const uint32_t PROC_SETUP_BARS_PCIE_NODE_NON_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS] =
 {
     PCIE0_GROUP_BAR0_0x02012012,
     PCIE1_GROUP_BAR0_0x02012412,
-    PCIE2_GROUP_BAR0_0x02012812
+    PCIE2_GROUP_BAR0_0x02012812,
+    PCIE3_GROUP_BAR0_0x02012C12
 };
 
 const uint32_t PROC_SETUP_BARS_PCIE_NODE_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS] =
 {
     PCIE0_GROUP_BAR1_0x02012013,
     PCIE1_GROUP_BAR1_0x02012413,
-    PCIE2_GROUP_BAR1_0x02012813
+    PCIE2_GROUP_BAR1_0x02012813,
+    PCIE3_GROUP_BAR1_0x02012C13
 };
 
 const uint32_t PROC_SETUP_BARS_PCIE_FOREIGN_NEAR_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_FAB_SMP_NUM_F_LINKS] =
@@ -1019,6 +1025,10 @@ const uint32_t PROC_SETUP_BARS_PCIE_FOREIGN_NEAR_BAR[PROC_SETUP_BARS_PCIE_NUM_UN
     {
         PCIE2_NEAR_BAR_F0_0x02012814,
         PCIE2_NEAR_BAR_F1_0x02012816
+    },
+    {
+        PCIE3_NEAR_BAR_F0_0x02012C14,
+        PCIE3_NEAR_BAR_F1_0x02012C16
     }
 };
 
@@ -1035,6 +1045,10 @@ const uint32_t PROC_SETUP_BARS_PCIE_FOREIGN_FAR_BAR[PROC_SETUP_BARS_PCIE_NUM_UNI
     {
         PCIE2_FAR_BAR_F0_0x02012815,
         PCIE2_FAR_BAR_F1_0x02012817
+    },
+    {
+        PCIE3_FAR_BAR_F0_0x02012C15,
+        PCIE3_FAR_BAR_F1_0x02012C17
     }
 };
 
@@ -1091,6 +1105,10 @@ const uint32_t PROC_SETUP_BARS_PCIE_BAR_REGS_MMIO[PROC_SETUP_BARS_PCIE_NUM_UNITS
     {
         PCIE2_IO_BAR0_0x02012840,
         PCIE2_IO_BAR1_0x02012841
+    },
+    {
+        PCIE3_IO_BAR0_0x02012C40,
+        PCIE3_IO_BAR1_0x02012C41
     }
 };
 
@@ -1124,6 +1142,10 @@ const uint32_t PROC_SETUP_BARS_PCIE_BAR_MASK_REGS_MMIO[PROC_SETUP_BARS_PCIE_NUM_
     {
         PCIE2_IO_MASK0_0x02012843,
         PCIE2_IO_MASK1_0x02012844
+    },
+    {
+        PCIE3_IO_MASK0_0x02012C43,
+        PCIE3_IO_MASK1_0x02012C44
     }
 };
 
@@ -1165,6 +1187,10 @@ const uint32_t PROC_SETUP_BARS_PCIE_BAR_REGS_PHB[PROC_SETUP_BARS_PCIE_NUM_UNITS]
     {
         PCIE2_IO_BAR2_0x02012842,
         PCIE2_ASB_BAR_0x0901280B
+    },
+    {
+        PCIE3_IO_BAR2_0x02012C42,
+        PCIE3_ASB_BAR_0x09012C0B
     }
 };
 
@@ -1179,7 +1205,8 @@ const uint32_t PROC_SETUP_BARS_PCIE_BAR_EN_REGS[PROC_SETUP_BARS_PCIE_NUM_UNITS]
 {
     PCIE0_IO_BAR_EN_0x02012045,
     PCIE1_IO_BAR_EN_0x02012445,
-    PCIE2_IO_BAR_EN_0x02012845
+    PCIE2_IO_BAR_EN_0x02012845,
+    PCIE3_IO_BAR_EN_0x02012C45
 };
 
 // ETU Reset register field/bit definitions
@@ -1187,7 +1214,8 @@ const uint32_t PROC_SETUP_BARS_PCIE_ETU_RESET_REGS[PROC_SETUP_BARS_PCIE_NUM_UNIT
 {
     PCIE0_ETU_RESET_0x0901200A,
     PCIE1_ETU_RESET_0x0901240A,
-    PCIE2_ETU_RESET_0x0901280A
+    PCIE2_ETU_RESET_0x0901280A,
+    PCIE3_ETU_RESET_0x09012C0A
 };
 
 
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml
index d157828ec..9a6516302 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml
@@ -5,7 +5,9 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- COPYRIGHT International Business Machines Corp. 2012,2014              -->
+<!-- Contributors Listed Below - COPYRIGHT 2012,2015                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
 <!--                                                                        -->
 <!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
 <!-- you may not use this file except in compliance with the License.       -->
@@ -20,7 +22,7 @@
 <!-- permissions and limitations under the License.                         -->
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
-<!-- $Id: proc_setup_bars_mmio_attributes.xml,v 1.4 2013/05/23 19:42:28 jmcgill Exp $ -->
+<!-- $Id: proc_setup_bars_mmio_attributes.xml,v 1.5 2014/11/18 17:44:22 jmcgill Exp $ -->
 <!-- proc_setup_bars_mmio_attributes.xml -->
 <attributes>
   <!-- ********************************************************************* -->
@@ -267,12 +269,12 @@
       creator: platform
       consumer: proc_setup_bars
       firmware notes:
-        first dimension: PCIE unit number (0:2)
+        first dimension: PCIE unit number (0:3)
         second dimension: BAR number (0:2)
     </description>
     <valueType>uint8</valueType>
     <enum>DISABLE = 0x0, ENABLE = 0x1</enum>
-    <array>3,3</array>
+    <array>4 3</array>
     <platInit/>
     <persistRuntime/>
   </attribute>
@@ -285,13 +287,13 @@
       consumer: proc_setup_bars
       firmware notes:
         64-bit address representing BAR RA
-        first dimension: PCIE unit number (0:2)
+        first dimension: PCIE unit number (0:3)
         second dimension: BAR number (0:2)
         NOTE: BAR0/1 registers cover RA 14:47
         NOTE: BAR2 registers covers RA 14:51
     </description>
     <valueType>uint64</valueType>
-    <array>3,3</array>
+    <array>4 3</array>
     <platInit/>
     <persistRuntime/>
   </attribute>
@@ -303,7 +305,7 @@
       creator: platform
       consumer: proc_setup_bars
       firmware notes:
-        first dimension: PCIE unit number (0:2)
+        first dimension: PCIE unit number (0:3)
         second dimension: BAR number (0:2)
         NOTE: supported BAR0/1 sizes are from 64KB-1PB
         NOTE: only supported BAR2 size is 4KB
@@ -347,7 +349,7 @@
        64_KB = 0x0000000000010000,
         4_KB = 0x0000000000001000
     </enum>
-    <array>3,3</array>
+    <array>4 3</array>
     <platInit/>
     <persistRuntime/>
   </attribute>