Access Bad DQ via ATTR_BAD_DQ_BITMAP and show unconnected DQs

Change-Id: Id703749de7c08aef337904a2dccac3af2e90a108
RTC: 72937
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5510
Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: William H. Schwartz <whs@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

1 files changed, 60 insertions, 4 deletions

diff --git a/src/usr/hwpf/hwp/dimm_spd_attributes.xml b/src/usr/hwpf/hwp/dimm_spd_attributes.xml
index 12eea1672..38d50c5f6 100644
--- a/src/usr/hwpf/hwp/dimm_spd_attributes.xml
+++ b/src/usr/hwpf/hwp/dimm_spd_attributes.xml
@@ -485,10 +485,11 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs
     <id>ATTR_SPD_BAD_DQ_DATA</id>
     <targetType>TARGET_TYPE_DIMM</targetType>
     <description>
-        Bad DQ pin data stored in DIMM SPD. This data is in a special format.
-        This must only be called by a firmware HWP that knows how to decode the data.       
-        HWP/PLAT firmware that needs to get/set the Bad DQ Bitmap from a Centaur
-        DQ point of view must call the dimmBadDqBitmapAccessHwp HWP.
+        Bad DQ pin data stored in DIMM SPD. This data is in a special fomat.
+        This must only be called by a firmware HWP that knows how to
+        decode the data. HWP/PLAT firmware that needs to get/set the
+        Bad DQ Bitmap from a Centaur DQ point of view must use the
+        ATTR_BAD_DQ_BITMAP attribute.
     </description>
     <valueType>uint8</valueType>
     <array>80</array>
@@ -1298,4 +1299,59 @@ file
 </attribute>
 -->
 
+
+<attribute>
+    <id>ATTR_BAD_DQ_BITMAP</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Bad DQ bitmap from a Centaur:MBA point of view.
+        The data is a 10 byte bitmap for each of 4 possible ranks.
+        The bad DQ data is stored in DIMM SPD, it is stored in a special format
+        and is translated to a DIMM Connector point of view for IS-DIMMs.
+        All of these details are hidden from the user of this attribute.
+    </description>
+    <valueType>uint8</valueType>
+    <array>4 10</array>
+    <platInit/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_DIMM_SPARE</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Spare DRAM availability for each rank on the DIMM.
+        There are 8 DQ lines to spare DRAMs.
+        - NO_SPARE: No spare DRAMs
+        - LOW_NIBBLE:  x4 DRAMs in use, one spare DRAM connected to SP_DQ0-3
+        - HIGH_NIBBLE: x4 DRAMs in use, one spare DRAM connected to SP_DQ4-7
+        - FULL_BYTE: Either
+          1/ x4 DRAMs in use, two spare DRAMs connected to SP_DQ0-7
+          2/ x8 DRAMs in use, one spare DRAM connected to SP_DQ0-7
+        For C-DIMMs, this is in a VPD field : Record:VSPD, Keyword:AM
+        For IS-DIMMs, the platform should return 0 indicating
+          no spares for any rank.
+        The top 2 bits are for rank 0 e.g:
+          if (((val AND 0xc0) >> 6) ==
+                ENUM_ATTR_VPD_DIMM_SPARE_LOW_NIBBLE) {...}
+        The next 2 bits are for rank 1 e.g:
+          if (((val AND 0x30) >> 4) ==
+                ENUM_ATTR_VPD_DIMM_SPARE_NO_SPARE) {...}
+        The next 2 bits are for rank 2 e.g:
+          if (((val AND 0x0c) >> 2) ==
+                ENUM_ATTR_VPD_DIMM_SPARE_HIGH_NIBBLE) {...}
+        The bottom 2 bits are for rank 3 e.g:
+          if ((val AND 0x03) ==
+               ENUM_ATTR_VPD_DIMM_SPARE_FULL_BYTE) {...}
+    </description>
+    <valueType>uint8</valueType>
+    <enum>
+        NO_SPARE = 0x00,
+        LOW_NIBBLE = 0x01,
+        HIGH_NIBBLE = 0x02,
+        FULL_BYTE = 0x03
+    </enum>
+    <platInit/>
+</attribute>
+
 </attributes>