diff options
author | vanlee <vanlee@us.ibm.com> | 2013-03-19 23:55:00 -0500 |
---|---|---|
committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-03-20 09:03:54 -0500 |
commit | 98947f1f7f8094304fd6ac2e8a9bdd21b449900a (patch) | |
tree | 7ddcbbde140db57f03460e1009b6cf018b98f0ad /src/usr/hwpf/hwp/build_winkle_images/p8_slw_build | |
parent | adf4b255432f86cbd563be6f9d56ca0b50b78dd9 (diff) | |
download | talos-hostboot-98947f1f7f8094304fd6ac2e8a9bdd21b449900a.tar.gz talos-hostboot-98947f1f7f8094304fd6ac2e8a9bdd21b449900a.zip |
HWP: Integrate cen_xip_customize into hostboot
Change-Id: Ib4098f329d94b5b7138e311b9a6393a69d716239
RTC: 64603
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3603
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp/build_winkle_images/p8_slw_build')
9 files changed, 1688 insertions, 258 deletions
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_delta_scan_rw.h b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_delta_scan_rw.h index 22792afcd..4699072ea 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_delta_scan_rw.h +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_delta_scan_rw.h @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_delta_scan_rw.h,v 1.35 2013/02/13 00:24:08 cmolsen Exp $ +// $Id: p8_delta_scan_rw.h,v 1.38 2013/03/06 18:21:46 cmolsen Exp $ #define OVERRIDE_OFFSET 8 // Byte offset of forward pointer's addr relative // to base forward pointer's addr. #define SIZE_IMAGE_BUF_MAX 5000000 // Max ~50MB image buffer size. @@ -36,10 +36,13 @@ #define L2_SINGLE_MEMBER_ENABLE_TOC_NAME "l2_single_member_enable_mask" #define PROC_PIB_REPR_VECTOR_TOC_NAME "proc_sbe_pibmem_repair_vector" #define NEST_SKEWADJUST_VECTOR_TOC_NAME "proc_sbe_nest_skewadjust_vector" -#define MAX_PLL_RING_SIZE 128 // Bytes +#define MAX_PLL_RING_SIZE 128 // Bytes #define PERV_BNDY_PLL_RING_TOC_NAME "perv_bndy_pll_ring" #define PERV_BNDY_PLL_RING_ALT_TOC_NAME "perv_bndy_pll_ring_alt" -#define MAX_CEN_PLL_RING_SIZE 80 // Bytes +#define MAX_FUNC_L3_RING_LIST_ENTRIES 64 +#define MAX_FUNC_L3_RING_SIZE 7000 // Bytes +#define FUNC_L3_RING_TOC_NAME "ex_func_l3_ring" +#define MAX_CEN_PLL_RING_SIZE 80 // Bytes #define TP_PLL_BNDY_RING_ALT_TOC_NAME "tp_pll_bndy_ring_alt" /***** Scan setting *****/ @@ -233,12 +236,9 @@ int create_wiggle_flip_prg( uint32_t i_chipletID, uint32_t **o_wfInline, uint32_t *o_wfInlineLenInWords, -#ifdef IMGBUILD_PPD_ENFORCE_SCAN_DELAY + uint8_t i_flushOptimization, uint32_t i_scanMaxRotate, uint32_t i_waitsScanDelay); -#else - uint32_t i_scanMaxRotate); -#endif uint64_t calc_ring_layout_entry_offset( uint8_t i_typeRingLayout, diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help.C b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help.C index 091f25d3e..6a69ed4cb 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help.C +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_image_help.C,v 1.48 2013/02/13 00:22:12 cmolsen Exp $ +// $Id: p8_image_help.C,v 1.52 2013/03/01 22:24:11 cmolsen Exp $ // /*------------------------------------------------------------------------------*/ /* *! TITLE : p8_image_help.C */ @@ -123,12 +123,9 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s uint32_t i_chipletID, // Chiplet ID uint32_t **o_wfInline, // location of the PORE instructions data stream uint32_t *o_wfInlineLenInWords, // final length of data stream -#ifdef IMGBUILD_PPD_ENFORCE_SCAN_DELAY + uint8_t i_flushOptimization, // flush optimize or not uint32_t i_scanMaxRotate, // Max rotate bit len on 38xxx, or polling threshold on 39xxx. uint32_t i_waitsScanDelay) // Temporary debug support. -#else - uint32_t i_scanMaxRotate) // Max rotate bit len on 38xxx, or polling threshold on 39xxx. -#endif { uint32_t rc=0; uint32_t i=0; @@ -227,27 +224,15 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s return ctx.error; } -#ifdef IMGBUILD_PPD_WF_WORST_CASE_PIB - uint32_t poreCTR=0; - // Save CTR value and restore it when done. -/* - pore_MV(&ctx, A1, CTR); - if (ctx.error > 0) { - MY_ERR("***WORST CASE PIB(1) rc = %d", ctx.error); - return ctx.error; - } -*/ -#endif - // Preload the scan data/shift reg with the scan header check word. // pore_imm64b = ((uint64_t)scanRingCheckWord) << 32; // pore_LI(&ctx, D0, pore_imm64b ); // pore_STD(&ctx, D0, scanRing_baseAddr, P0); pore_STI(&ctx, scanRing_baseAddr, P0, pore_imm64b); -#ifdef IMGBUILD_PPD_ENFORCE_SCAN_DELAY - pore_WAITS(&ctx, i_waitsScanDelay); -#endif + if (i_waitsScanDelay) { + pore_WAITS(&ctx, i_waitsScanDelay); + } if (ctx.error > 0) { MY_ERR("***STI(1) rc = %d", ctx.error); return ctx.error; @@ -314,36 +299,14 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s return ctx.error; } #else -#ifdef IMGBUILD_PPD_WF_WORST_CASE_PIB - PoreInlineLocation srcwc1=0,tgtwc1=0; - poreCTR = rotateLen/i_scanMaxRotate-1; - if (poreCTR>=0) { - scanRing_poreAddr = scanRing_baseAddr | i_scanMaxRotate; - pore_LS(&ctx, CTR, poreCTR); - PORE_LOCATION(&ctx, tgtwc1); - pore_LD(&ctx, D0, scanRing_poreAddr, P1); - PORE_LOCATION(&ctx, srcwc1); - pore_LOOP(&ctx, tgtwc1); - pore_inline_branch_fixup(&ctx, srcwc1, tgtwc1); - } - scanRing_poreAddr = scanRing_baseAddr | (rotateLen-i_scanMaxRotate*(poreCTR+1)); - pore_LD(&ctx, D0, scanRing_poreAddr, P1); - if (ctx.error > 0) { - MY_ERR("***WORST CASE PIB(1) rc = %d", ctx.error); - return ctx.error; - } -#else scanRing_poreAddr = scanRing_baseAddr | rotateLen; pore_LD(&ctx, D0, scanRing_poreAddr, P1); -#ifdef IMGBUILD_PPD_ENFORCE_SCAN_DELAY // pore_WAITS(&ctx, i_waitsScanDelay); -#endif if (ctx.error > 0) { MY_ERR("***LD D0 rc = %d", ctx.error); return ctx.error; } #endif -#endif } // End of if (rotateLen>0) @@ -362,38 +325,55 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s // current shift register content when loaded. // -------------------------------------------------------------------- // Take snapshot of present content of shift reg and put in D1. - pore_LD(&ctx, D1, scanRing_baseAddr, P1); -#ifdef IMGBUILD_PPD_ENFORCE_SCAN_DELAY -// pore_WAITS(&ctx, i_waitsScanDelay); -#endif - // Calculate shift reg cleanup mask and put in D0. The intent is to - // clear bit in the ring data positions while keeping any header - // check word content untouched. - clean_up_shift_reg_mask = 0xffffffff>>bitShift; - pore_imm64b = ((uint64_t)clean_up_shift_reg_mask) << 32; - pore_LI(&ctx, D0, pore_imm64b ); - // Cleanup shift register snapshot and put in D1. - pore_AND(&ctx, D1, D0, D1); - // Put ring data in D0. Note, any dirty content was removed earlier. - pore_imm64b = ((uint64_t)myRev32(i_deltaRing[i])) << 32; - pore_LI(&ctx, D0, pore_imm64b ); - // Finally, combine the ring data and the shift reg content and put in D0. - pore_OR(&ctx, D0, D0, D1); - pore_STD(&ctx, D0, scanRing_poreAddr, P0); + if (i_flushOptimization) { + pore_LD(&ctx, D1, scanRing_baseAddr, P1); +// pore_WAITS(&ctx, i_waitsScanDelay); + // Calculate shift reg cleanup mask and put in D0. The intent is to + // clear bit in the ring data positions while keeping any header + // check word content untouched. + clean_up_shift_reg_mask = 0xffffffff>>bitShift; + pore_imm64b = ((uint64_t)clean_up_shift_reg_mask) << 32; + pore_LI(&ctx, D0, pore_imm64b ); + // Cleanup shift register snapshot and put in D1. + pore_AND(&ctx, D1, D0, D1); + // Put ring data in D0. + // Note, any dirty content was removed earlier. + pore_imm64b = ((uint64_t)myRev32(i_deltaRing[i])) << 32; + pore_LI(&ctx, D0, pore_imm64b ); + // Finally, combine the ring data and the shift reg content and put in D0. + pore_OR(&ctx, D0, D0, D1); + pore_STD(&ctx, D0, scanRing_poreAddr, P0); + } + else { + pore_LD(&ctx, D1, scanRing_baseAddr, P1); + // Bring ring data in as an immediate. + // Note, any dirty content was removed earlier. + pore_imm64b = ((uint64_t)myRev32(i_deltaRing[i])) << 32; + pore_XORI(&ctx, D0, D1, pore_imm64b); + pore_STD(&ctx, D0, scanRing_poreAddr, P0); + } } else { // -------------------------------------------------------------------- // Not the last word OR the last word has exactly 32-bit of ring data. // -------------------------------------------------------------------- - pore_imm64b = ((uint64_t)myRev32(i_deltaRing[i])) << 32; -// pore_LI(&ctx, D0, pore_imm64b ); - pore_STI(&ctx, scanRing_poreAddr, P0, pore_imm64b); + if (i_flushOptimization) { + pore_imm64b = ((uint64_t)myRev32(i_deltaRing[i])) << 32; + // Shift it in by bitShift bits. +// pore_LI(&ctx, D0, pore_imm64b ); +// pore_STD(&ctx, D0, scanRing_poreAddr, P0); + pore_STI(&ctx, scanRing_poreAddr, P0, pore_imm64b); + } + else { + pore_LD(&ctx, D1, scanRing_baseAddr, P1); + pore_imm64b = ((uint64_t)myRev32(i_deltaRing[i])) << 32; + pore_XORI(&ctx, D0, D1, pore_imm64b); + pore_STD(&ctx, D0, scanRing_poreAddr, P0); + } + } + if (i_waitsScanDelay) { + pore_WAITS(&ctx, i_waitsScanDelay); } - // Shift it in by bitShift bits. -// pore_STD(&ctx, D0, scanRing_poreAddr, P0); -#ifdef IMGBUILD_PPD_ENFORCE_SCAN_DELAY - pore_WAITS(&ctx, i_waitsScanDelay); -#endif if (ctx.error > 0) { MY_ERR("***STI(2) (or STD) rc = %d", ctx.error); return ctx.error; @@ -436,17 +416,11 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s rotateLen = rotateLen - SCAN_MAX_ROTATE_LONG; } #else -#ifdef IMGBUILD_PPD_WF_WORST_CASE_PIB - // There is no max rotateLen issue in this case since we rotate 32 bits - // at a time. -#else if (rotateLen>i_scanMaxRotate) { //scanRing_poreAddr = scanRing_baseAddr | rotateLen; scanRing_poreAddr = scanRing_baseAddr | i_scanMaxRotate; pore_LD(&ctx, D0, scanRing_poreAddr, P1); -#ifdef IMGBUILD_PPD_ENFORCE_SCAN_DELAY // pore_WAITS(&ctx, i_waitsScanDelay); -#endif if (ctx.error > 0) { MY_ERR("***LD D0 rc = %d", ctx.error); return ctx.error; @@ -455,7 +429,6 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s rotateLen = rotateLen - i_scanMaxRotate; } #endif -#endif } //end of else (i_deltaRing==0) @@ -492,51 +465,17 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s } rotateLen=0; #else -#ifdef IMGBUILD_PPD_WF_WORST_CASE_PIB - PoreInlineLocation srcwc2=0,tgtwc2=0; - poreCTR = rotateLen/i_scanMaxRotate-1; - if (poreCTR>=0) { - scanRing_poreAddr = scanRing_baseAddr | i_scanMaxRotate; - pore_LS(&ctx, CTR, poreCTR); - PORE_LOCATION(&ctx, tgtwc2); - pore_LD(&ctx, D0, scanRing_poreAddr, P1); - PORE_LOCATION(&ctx, srcwc2); - pore_LOOP(&ctx, tgtwc2); - pore_inline_branch_fixup(&ctx, srcwc2, tgtwc2); - } - scanRing_poreAddr = scanRing_baseAddr | (rotateLen-i_scanMaxRotate*(poreCTR+1)); - pore_LD(&ctx, D0, scanRing_poreAddr, P1); - if (ctx.error > 0) { - MY_ERR("***WORST CASE PIB(2) rc = %d", ctx.error); - return ctx.error; - } - rotateLen=0; -#else scanRing_poreAddr=scanRing_baseAddr | rotateLen; pore_LD(&ctx, D0, scanRing_poreAddr, P1); -#ifdef IMGBUILD_PPD_ENFORCE_SCAN_DELAY // pore_WAITS(&ctx, i_waitsScanDelay); -#endif if (ctx.error > 0) { MY_ERR("***LD D0 rc = %d", ctx.error); return ctx.error; } rotateLen=0; #endif -#endif } -/* -#ifdef IMGBUILD_PPD_WF_WORST_CASE_PIB - // Restore CTR value. - pore_MV(&ctx, CTR, A1); - if (ctx.error > 0) { - MY_ERR("***WORST CASE PIB(5) rc = %d", ctx.error); - return ctx.error; - } -#endif -*/ - // Finally, check that our header check word went through in one piece. // Note, we first do the MC-READ-AND check, then the MC-READ-OR check // @@ -567,9 +506,7 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s } // ...Load the output check word... pore_LD(&ctx, D0, scanRing_baseAddr, P1); -#ifdef IMGBUILD_PPD_ENFORCE_SCAN_DELAY // pore_WAITS(&ctx, i_waitsScanDelay); -#endif // Compare against the reference header check word... pore_XORI( &ctx, D0, D0, ((uint64_t)scanRingCheckWord) << 32); PORE_LOCATION( &ctx, src5); @@ -611,8 +548,10 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s pore_HALT( &ctx); PORE_LOCATION( &ctx, tgt8); // pore_LI( &ctx, D0, 0x0); // Do shadowing by setpulse. +// pore_MR( &ctx, D0, D1); // pore_STD( &ctx, D0, GENERIC_CLK_SCAN_UPDATEDR_0x0003A000, P0); pore_STI(&ctx, GENERIC_CLK_SCAN_UPDATEDR_0x0003A000, P0, 0x0); +// pore_WAITS(&ctx, i_waitsScanDelay); pore_RET( &ctx); if (ctx.error > 0) { MY_ERR("***LD, XORI, BRANZ, RET or HALT went wrong rc = %d", ctx.error); @@ -1502,7 +1441,7 @@ int write_vpd_ring_to_ipl_image(void *io_image, uint32_t rc=0, bufLC; uint8_t chipletId, idxVector=0; uint32_t sizeRs4Launch, sizeRs4Ring; - uint32_t sizeImageIn; + uint32_t sizeImageIn,sizeImage; PoreInlineContext ctx; uint32_t asmInitLC=0; uint32_t asmBuffer[ASM_RS4_LAUNCH_BUF_SIZE/4]; @@ -1629,6 +1568,7 @@ int write_vpd_ring_to_ipl_image(void *io_image, idxVector = 0; // Write ring block to image. + sbe_xip_image_size( io_image, &sizeImage); rc = write_ring_block_to_image(io_image, i_ringName, bufRs4RingBlock, @@ -1637,8 +1577,12 @@ int write_vpd_ring_to_ipl_image(void *io_image, 0, io_sizeImageOut); if (rc) { - MY_ERR("write_ring_block_to_image() failed w/rc=%i",rc); - MY_ERR("Check p8_delta_scan_rw.h for meaning of IMGBUILD_xyz rc code."); + MY_ERR("write_ring_block_to_image() failed w/rc=%i \n",rc); + MY_ERR("Check p8_delta_scan_rw.h for meaning of IMGBUILD_xyz rc code. \n"); + MY_ERR("Ring name: %s\n ", i_ringName); + MY_ERR("Size of image before wrbti() call: %i\n ", sizeImage); + MY_ERR("Size of ring block being added: %i\n ", sizeRs4RingBlock); + MY_ERR("Max size of image allowed: %i\n ", io_sizeImageOut); return IMGBUILD_ERR_RING_WRITE_TO_IMAGE; } @@ -1670,10 +1614,13 @@ int write_vpd_ring_to_slw_image(void *io_image, uint32_t rc=0, bufLC; uint8_t chipletId, idxVector=0; uint32_t sizeRingRaw=0, sizeRingRawChk; - uint32_t sizeImageIn; + uint32_t sizeImageIn,sizeImage; uint32_t *wfInline=NULL; uint32_t wfInlineLenInWords; uint64_t scanMaxRotate=SCAN_ROTATE_DEFAULT; + uint64_t waitsScanDelay=0; + uint64_t twinHaltOpCodes; + uint32_t iFill; MY_INF("i_ringName=%s; \n", i_ringName); @@ -1723,8 +1670,6 @@ int write_vpd_ring_to_slw_image(void *io_image, MY_INF("Continuing...; "); } -#ifdef IMGBUILD_PPD_ENFORCE_SCAN_DELAY - uint64_t waitsScanDelay=10; // Temporary support for enforcing delay after scan WF scoms. // Also remove all references and usages of waitsScanDelay in this file. rc = sbe_xip_get_scalar( io_image, "waits_delay_for_scan", &waitsScanDelay); @@ -1732,7 +1677,6 @@ int write_vpd_ring_to_slw_image(void *io_image, MY_ERR("Error obtaining waits_delay_for_scan keyword.\n"); return IMGBUILD_ERR_XIP_MISC; } -#endif wfInline = (uint32_t*)i_bufRs4Ring; // Reuse this buffer (HB buf1) for wiggle-flip prg. wfInlineLenInWords = i_sizeBufTmp/4; // Assuming same size of both HB buf1 and buf2. @@ -1742,12 +1686,9 @@ int write_vpd_ring_to_slw_image(void *io_image, (uint32_t)i_bufRs4Ring->iv_chipletId, &wfInline, &wfInlineLenInWords, // Is 8-byte aligned on return. -#ifdef IMGBUILD_PPD_ENFORCE_SCAN_DELAY + i_bufRs4Ring->iv_flushOptimization, (uint32_t)scanMaxRotate, (uint32_t)waitsScanDelay); -#else - (uint32_t)scanMaxRotate); -#endif if (rc) { MY_ERR("create_wiggle_flip_prg() failed w/rc=%i; ",rc); return IMGBUILD_ERR_WF_CREATE; @@ -1778,9 +1719,11 @@ int write_vpd_ring_to_slw_image(void *io_image, sizeWfRingBlock = ((sizeRingRaw-1)/32 + 1) * 4 * WF_WORST_CASE_SIZE_FAC + WF_ENCAP_SIZE; sizeWfRingBlock = (uint32_t)myByteAlign(8, sizeWfRingBlock); - memset((void*)((uint64_t)bufWfRingBlock+entryOffsetWfRingBlock), - 0, - sizeWfRingBlock-entryOffsetWfRingBlock); + // Fill void with "halt" instructions, 0x02000000 (LE). Note, void is whole multiple of 8x. + twinHaltOpCodes = myRev64((uint64_t)0x02000000<<32 | (uint64_t)0x02000000); + for (iFill=0; iFill<(sizeWfRingBlock-entryOffsetWfRingBlock); iFill=iFill+8) { + *(uint64_t*)((uint64_t)bufWfRingBlock+entryOffsetWfRingBlock+iFill) = twinHaltOpCodes; + } } // Quick check to see if final ring block size will fit in HB buffer. if (sizeWfRingBlock>sizeWfRingBlockMax) { @@ -1811,6 +1754,7 @@ int write_vpd_ring_to_slw_image(void *io_image, idxVector = 0; // Write ring block to image. + sbe_xip_image_size( io_image, &sizeImage); rc = write_ring_block_to_image(io_image, i_ringName, bufWfRingBlock, @@ -1821,6 +1765,10 @@ int write_vpd_ring_to_slw_image(void *io_image, if (rc) { MY_ERR("write_ring_block_to_image() failed w/rc=%i; \n",rc); MY_ERR("Check p8_delta_scan_rw.h for meaning of IMGBUILD_xyz rc code; \n"); + MY_ERR("Ring name: %s\n ", i_ringName); + MY_ERR("Size of image before wrbti() call: %i\n ", sizeImage); + MY_ERR("Size of ring block being added: %i\n ", sizeWfRingBlock); + MY_ERR("Max size of image allowed: %i\n ", io_sizeImageOut); return IMGBUILD_ERR_RING_WRITE_TO_IMAGE; } diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C new file mode 100644 index 000000000..52ce97be3 --- /dev/null +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C @@ -0,0 +1,747 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: p8_pore_table_gen_api_fixed.C,v 1.6 2013/03/08 18:18:21 cmolsen Exp $ +// +/*------------------------------------------------------------------------------*/ +/* *! (C) Copyright International Business Machines Corp. 2012 */ +/* *! All Rights Reserved -- Property of IBM */ +/* *! *** IBM Confidential *** */ +/*------------------------------------------------------------------------------*/ +/* *! TITLE : p8_pore_table_gen_api_fixed.C */ +/* *! DESCRIPTION : PORE SLW table generaion APIs */ +/* *! OWNER NAME : Michael Olsen Email: cmolsen@us.ibm.com */ +/* *! USAGE : To build for PHYP command-line - */ +// buildecmdprcd_cmo -D "p8_pore_table_gen_api_fixed.C" -d "p8_pore_table_static_data.c,sbe_xip_image.c,pore_inline_assembler.c" -u "SLW_COMMAND_LINE_RAM" p8_pore_table_gen_api_fixed_main.C +// Other usages: +// +/* *! COMMENTS : - Start file: p7p_pore_api.c */ +// - The DYNAMIC_RAM_TABLE_PPD was dropped in v1.12 of this +// code. See v1.12 for explanation and code implementation. +// +/*------------------------------------------------------------------------------*/ + +#define __P8_PORE_TABLE_GEN_API_C +#include <HvPlicModule.H> +#include <p8_pore_api_custom.h> +#include <p8_pore_table_gen_api.H> +#include <p8_delta_scan_rw.h> + +/* +// io_image - pointer to SLW image +// i_modeBuild - 0: HB/IPL mode, 1: PHYP/Rebuild mode, 2: SRAM mode. +// i_regName - unswizzled enum SPR value (NOT a name) +// i_regData - data to write +// i_coreIndex - core ID +// i_threadIndex - thread to operate on, API changes thread num to 0 for shared +// SPRs, except for HRMOR which is always done on thread 3 to be +// the last SPR +*/ +uint32_t p8_pore_gen_cpureg_fixed( void *io_image, + uint8_t i_modeBuild, + uint32_t i_regName, + uint64_t i_regData, + uint32_t i_coreId, // [0:15] + uint32_t i_threadId) +{ + uint32_t rc=0, rcLoc=0, iCount=0; + int i=0, iReg=-1; + uint64_t xipSlwRamSection; + void *hostSlwRamSection; + void *hostSlwSectionFixed; + uint64_t xipRamTableThis; + void *hostRamVector; + void *hostRamTableThis; + void *hostRamEntryThis, *hostRamEntryNext; + uint8_t bNewTable=0, bFound=0; + uint8_t bEntryEnd=1, headerType=0; + SbeXipSection xipSection; + SbeXipItem xipTocItem; + RamTableEntry ramEntryThis, *ramEntryNext; + uint32_t sprSwiz=0; + + // ------------------------------------------------------------------------- + // Validate Ramming parameters. + // + // ...check mode build + if (i_modeBuild>P8_SLW_MODEBUILD_MAX_VALUE) { + MY_ERR("modeBuild=%i invalid. Valid range is [0;%i].", + i_modeBuild,P8_SLW_MODEBUILD_MAX_VALUE); + rcLoc = 1; + } + // ...check register value + bFound = 0; + for (i=0;i<SLW_SPR_REGS_SIZE;i++) { + if (i_regName==SLW_SPR_REGS[i].value) { + bFound = 1; + iReg = i; + break; + } + } + if (!bFound) { + MY_ERR("Register value = %i is not supported.\n",i_regName); + MY_ERR("The following registers are supported:\n"); + for (i=0;i<SLW_SPR_REGS_SIZE;i++) + MY_ERR("\t(%s,%i)\n",SLW_SPR_REGS[i].name,SLW_SPR_REGS[i].value); + rcLoc = 1; + } + // ...check core ID + if (i_coreId>=SLW_MAX_CORES) { + MY_ERR("Core ID = %i is not within valid range of [0;%i]\n",i_coreId,SLW_MAX_CORES-1); + rcLoc = 1; + } + // ...check thread ID + if (i_threadId>=SLW_CORE_THREADS) { + MY_ERR("Thread ID = %i is not within valid range of [0;%i]\n",i_threadId,SLW_CORE_THREADS-1); + rcLoc = 1; + } + if (rcLoc) + return IMGBUILD_ERR_RAM_INVALID_PARM; + rcLoc = 0; + + // ------------------------------------------------------------------------- + // Get pointer to SLW section where Ram table resides + // NB! Only needed for modeBuild==2 ! + // + if (i_modeBuild==P8_SLW_MODEBUILD_IPL || + i_modeBuild==P8_SLW_MODEBUILD_REBUILD) { // Fixed image. + // CMO-20130114: Remove this asap. Only for fixed img transition. - Begin + // hostSlwSectionFixed isn't needed for modeBuild=0,1 ! + hostSlwSectionFixed = (void*)( (uintptr_t)io_image + + FIXED_SLW_IMAGE_SIZE - + FIXED_FFDC_SECTION_SIZE - + FIXED_SLW_SECTION_SIZE ); + // We may want to continue calling this because it would be practical to + // crosscheck the section size. Though, the offset is NOT reliable ! + rc = sbe_xip_get_section( io_image, SBE_XIP_SECTION_SLW, &xipSection); + if (rc) { + MY_ERR("Probably invalid section name for SBE_XIP_SECTION_SLW.\n"); + return IMGBUILD_ERR_GET_SECTION; + } + hostSlwRamSection = (void*)((uintptr_t)io_image + xipSection.iv_offset); + if (hostSlwSectionFixed!=hostSlwRamSection) { + MY_DBG("hostSlwSectionFixed != hostSlwRamSection(from image).\n"); + } + else { + MY_DBG("hostSlwSectionFixed == hostSlwRamSection(from image).\n"); + } + hostSlwRamSection = hostSlwSectionFixed; + // CMO-20130114: Remove this asap. Only for fixed img transition. - End + } + else { // SRAM non-fixed image. + rc = sbe_xip_get_section( io_image, SBE_XIP_SECTION_SLW, &xipSection); + if (rc) { + MY_ERR("Probably invalid section name for SBE_XIP_SECTION_SLW.\n"); + return IMGBUILD_ERR_GET_SECTION; + } + hostSlwRamSection = (void*)((uintptr_t)io_image + xipSection.iv_offset); + sbe_xip_host2pore( io_image, hostSlwRamSection, &xipSlwRamSection); + } + + // ------------------------------------------------------------------------- + // Cross check SPR register and table defines + // + if (SLW_SPR_REGS_SIZE!=(SLW_MAX_CPUREGS_CORE+SLW_MAX_CPUREGS_THREADS)) { + MY_ERR("Defines in *.H header file not in sync.\n"); + return IMGBUILD_ERR_RAM_HDRS_NOT_SYNCED; + } + if (xipSection.iv_size!=FIXED_SLW_SECTION_SIZE) { + MY_ERR("Fixed SLW table size in *.H header file differs from SLW section size in image.\n"); + MY_ERR("Check code or image version.\n"); + return IMGBUILD_ERR_RAM_HDRS_NOT_SYNCED; + } + + // ------------------------------------------------------------------------- + // Summarize parameters and checking results. + // + MY_INF("Input parameter checks - OK\n"); + MY_INF("\tMode build= %i\n",i_modeBuild); + MY_INF("\tRegister = (%s,%i)\n",SLW_SPR_REGS[iReg].name,SLW_SPR_REGS[iReg].value); + MY_INF("\tCore ID = %i\n",i_coreId); + MY_INF("\tThread ID = %i\n",i_threadId); + MY_INF("Image validation and size checks - OK\n"); + MY_INF("\tSLW section size= %i\n",xipSection.iv_size); + + // ------------------------------------------------------------------------- + // Locate RAM vector and locate RAM table associated with "This" core ID. + // + if (i_modeBuild==P8_SLW_MODEBUILD_IPL || + i_modeBuild==P8_SLW_MODEBUILD_REBUILD) { // Fixed image. + hostRamTableThis = (void*)( (uintptr_t)io_image + + FIXED_SLW_IMAGE_SIZE - + FIXED_FFDC_SECTION_SIZE - + FIXED_SLW_SECTION_SIZE + + SLW_RAM_TABLE_SPACE_PER_CORE*i_coreId ); + if (*(uintptr_t*)hostRamTableThis) { // Table content NOT empty. + bNewTable = 0; // So, NOT new table. + } + else { // Table content empty. + bNewTable = 1; // So, new table. + } + } + else { // SRAM non-fixed image. + rc = sbe_xip_find( io_image, SLW_HOST_REG_VECTOR_TOC_NAME, &xipTocItem); + if (rc) { + MY_ERR("Probably invalid key word for SLW_HOST_REG_VECTOR_TOC_NAME.\n"); + return IMGBUILD_ERR_KEYWORD_NOT_FOUND; + } + sbe_xip_pore2host( io_image, xipTocItem.iv_address, &hostRamVector); + xipRamTableThis = myRev64(*((uint64_t*)hostRamVector + i_coreId)); + if (xipRamTableThis) { + sbe_xip_pore2host( io_image, xipRamTableThis, &hostRamTableThis); + bNewTable = 0; + } + else { + hostRamTableThis = (void*)( (uintptr_t)hostSlwRamSection + + SLW_RAM_TABLE_SPACE_PER_CORE*i_coreId ); + bNewTable = 1; + } + } + + // ------------------------------------------------------------------------- + // Determine insertion point, hostRamEntryThis, of new RAM entry + // + if (bNewTable) { + // Append to beginning of agreed upon static Ram table position for this coreId. + hostRamEntryThis = hostRamTableThis; + if (i_modeBuild==P8_SLW_MODEBUILD_SRAM) { + // Update RAM vector (since it is currently NULL) + *((uint64_t*)hostRamVector + i_coreId) = + myRev64( xipSlwRamSection + + SLW_RAM_TABLE_SPACE_PER_CORE*i_coreId ); + } + bEntryEnd = 1; + } + else { + // Insert at end of existing Ram table for this coreId. + hostRamEntryNext = hostRamTableThis; + ramEntryNext = (RamTableEntry*)hostRamEntryNext; + iCount = 1; + while ((myRev32(ramEntryNext->header) & RAM_HEADER_END_MASK_C)==0) { + if (iCount>=SLW_MAX_CPUREGS_OPS) { + MY_ERR("Bad table! Header end bit not found and RAM table full (=%i entries).\n",SLW_MAX_CPUREGS_OPS); + return IMGBUILD_ERR_RAM_TABLE_END_NOT_FOUND; + } + hostRamEntryNext = (void*)((uint8_t*)hostRamEntryNext + XIPSIZE_RAM_ENTRY); + ramEntryNext = (RamTableEntry*)hostRamEntryNext; + iCount++; + } + if (iCount<SLW_MAX_CPUREGS_OPS) { + // ...zero out previous END bit in header + if ((myRev32(ramEntryNext->header) & RAM_HEADER_END_MASK_C)) { + ramEntryNext->header = ramEntryNext->header & myRev32(~RAM_HEADER_END_MASK_C); + } + else { + MY_ERR("We should never get here. Check code. Dumping data:\n"); + MY_ERR("myRev32(ramEntryNext->header) = 0x%08x\n",myRev32(ramEntryNext->header)); + MY_ERR("RAM_HEADER_END_MASK_C = 0x%08x\n",RAM_HEADER_END_MASK_C); + return IMGBUILD_ERR_RAM_CODE; + } + } + else { + MY_ERR("RAM table is full. Max %i entries allowed.\n",SLW_MAX_CPUREGS_OPS); + return IMGBUILD_ERR_RAM_TABLE_FULL; + } + // ...this is the spot for the new entry + hostRamEntryThis = (void*)((uint8_t*)hostRamEntryNext + XIPSIZE_RAM_ENTRY); + bEntryEnd = 1; + } + + + // ------------------------------------------------------------------------- + // Create, or modify, the RAM entry. + // + if (i_regName==P8_MSR_MSR) { + // ...do the MSR header + headerType = 0x1; // MTMSRD header. + ramEntryThis.header = ( ((uint32_t)bEntryEnd) << RAM_HEADER_END_START_C & RAM_HEADER_END_MASK_C ) | + ( ((uint32_t)headerType) << RAM_HEADER_TYPE_START_C & RAM_HEADER_TYPE_MASK_C ); + // ...do the MSR instr + ramEntryThis.instr = RAM_MTMSRD_INSTR_TEMPL_C; + } + else { + // ...do the SPR header + headerType = 0x0; // MTSPR header. + ramEntryThis.header = ( ((uint32_t)bEntryEnd) << RAM_HEADER_END_START_C & RAM_HEADER_END_MASK_C ) | + ( ((uint32_t)headerType) << RAM_HEADER_TYPE_START_C & RAM_HEADER_TYPE_MASK_C ) | + ( i_regName << RAM_HEADER_SPRN_START_C & RAM_HEADER_SPRN_MASK_C ) | + ( i_threadId << RAM_HEADER_THREAD_START_C & RAM_HEADER_THREAD_MASK_C ); + // ...do the SPR instr + sprSwiz = i_regName>>5 | (i_regName & 0x0000001f)<<5; + if (sprSwiz!=SLW_SPR_REGS[iReg].swizzled) { + MY_ERR("Inconsistent swizzle rules implemented. Check code. Dumping data.\n"); + MY_ERR("\tsprSwiz (on-the-fly-calc)=%i\n",sprSwiz); + MY_ERR("\tSLW_SPR_REGS[%i].swizzled=%i\n",iReg,SLW_SPR_REGS[iReg].swizzled); + return IMGBUILD_ERR_RAM_CODE; + } + ramEntryThis.instr = RAM_MTSPR_INSTR_TEMPL_C | ( ( sprSwiz<<RAM_MTSPR_SPR_START_C ) & RAM_MTSPR_SPR_MASK_C ); + } + // ...do the data + ramEntryThis.data = i_regData; + // ...summarize new table entry data + MY_INF("New table entry data (host format):\n"); + MY_INF("\theader = 0x%08x\n",ramEntryThis.header); + MY_INF("\tinstr = 0x%08x\n",ramEntryThis.instr); + MY_INF("\tdata = 0x%016llx\n",ramEntryThis.data); + + // ------------------------------------------------------------------------- + // Insert the new RAM entry into the table in BE format. + // + ramEntryNext = (RamTableEntry*)hostRamEntryThis; + // ...some redundant checking + if (bNewTable) { + // For any new table, the insertion location should be clean. We check for this here. + if (myRev32(ramEntryNext->header)!=0) { + MY_ERR("WARNING : Table entry location should be empty for a new table. Check code and image. Dumping data:\n"); + MY_ERR("\theader = 0x%08x\n",myRev32(ramEntryNext->header)); + MY_ERR("\tinstr = 0x%08x\n",myRev32(ramEntryNext->instr)); + MY_ERR("\tdata = 0x%016llx\n",myRev64(ramEntryNext->data)); + rc = IMGBUILD_WARN_RAM_TABLE_CONTAMINATION; + } + } + ramEntryNext->header = myRev32(ramEntryThis.header); + ramEntryNext->instr = myRev32(ramEntryThis.instr); + ramEntryNext->data = myRev64(ramEntryThis.data); + + return rc; +} + + +/* +// io_image - Pointer to SLW image. +// i_modeBuild - 0: HB/IPL mode, 1: PHYP/Rebuild mode, 2: SRAM mode. +// i_scomAddr - Scom address. +// i_coreId - The core ID [0:15]. +// i_scomData - Data to write to scom register. +// i_operation - What to do with the scom addr and data. +// i_section - 0: General Scoms, 1: L2 cache, 2: L3 cache. +*/ +uint32_t p8_pore_gen_scom_fixed( void *io_image, + uint8_t i_modeBuild, + uint32_t i_scomAddr, + uint32_t i_coreId, // [0:15] + uint64_t i_scomData, + uint32_t i_operation, // [0:5] + uint32_t i_section) // [0,1,2] +{ + uint32_t rc=0, rcLoc=0, iEntry=0; + uint32_t chipletId=0; + uint32_t operation=0; + uint32_t entriesCount=0, entriesMatch=0, entriesNOP=0; + void *hostSlwSection; + void *hostSlwSectionFixed; + uint64_t xipScomTableThis; + void *hostScomVector, *hostScomTableThis; + void *hostScomEntryNext; // running entry pointer + void *hostScomEntryMatch=NULL; // pointer to entry that matches scomAddr + void *hostScomEntryRET=NULL; // pointer to first return instr after table + void *hostScomEntryNOP=NULL; // pointer to first nop IIS + uint8_t bufIIS[XIPSIZE_SCOM_ENTRY], bufNOP[4], bufRET[4]; + SbeXipSection xipSection; + SbeXipItem xipTocItem; + PoreInlineContext ctx; + + // ------------------------------------------------------------------------- + // Validate Scom parameters. + // + // ...check if valid Scom register (is there anything we can do here to check?) + // Skipping check. We blindly trust caller. + // + // ...check mode build + if (i_modeBuild>P8_SLW_MODEBUILD_MAX_VALUE) { + MY_ERR("modeBuild=%i invalid. Valid range is [0;%i].", + i_modeBuild,P8_SLW_MODEBUILD_MAX_VALUE); + rcLoc = 1; + } + // ...check Scom operation + if (i_operation<P8_PORE_SCOM_FIRST_OP || i_operation>P8_PORE_SCOM_LAST_OP) { + MY_ERR("Scom operation = %i is not within valid range of [%d;%d]\n", + i_operation, P8_PORE_SCOM_FIRST_OP, P8_PORE_SCOM_LAST_OP); + rcLoc = 1; + } + // ...check that core ID corresponds to valid chiplet ID + chipletId = i_coreId + P8_CID_EX_LOW; + if (chipletId<P8_CID_EX_LOW || chipletId>P8_CID_EX_HIGH) { + MY_ERR("Chiplet ID = 0x%02x is not within valid range of [0x%02x;0x%02x]\n", + chipletId, P8_CID_EX_LOW, P8_CID_EX_HIGH); + rcLoc = 1; + } + if (rcLoc) + return IMGBUILD_ERR_SCOM_INVALID_PARM; + rcLoc = 0; + + // ------------------------------------------------------------------------- + // Get pointer to SLW section where Scom table resides + // NB! Only needed for modeBuild==2 ! + // + if (i_modeBuild==P8_SLW_MODEBUILD_IPL || + i_modeBuild==P8_SLW_MODEBUILD_REBUILD) { // Fixed image. + // CMO-20130114: Remove this asap. Only for fixed img transition. - Begin + // hostSlwSectionFixed isn't needed for modeBuild=0,1 ! + hostSlwSectionFixed = (void*)( (uintptr_t)io_image + + FIXED_SLW_IMAGE_SIZE - + FIXED_FFDC_SECTION_SIZE - + FIXED_SLW_SECTION_SIZE ); + // We may want to continue calling this because it would be practical to + // crosscheck the section size. Though, the offset is NOT reliable ! + rc = sbe_xip_get_section( io_image, SBE_XIP_SECTION_SLW, &xipSection); + if (rc) { + MY_ERR("Probably invalid section name for SBE_XIP_SECTION_SLW.\n"); + return IMGBUILD_ERR_GET_SECTION; + } + hostSlwSection = (void*)((uintptr_t)io_image + xipSection.iv_offset); + if (hostSlwSectionFixed!=hostSlwSection) { + MY_DBG("hostSlwSectionFixed != hostSlwSection(from image).\n"); + } + else { + MY_DBG("hostSlwSectionFixed == hostSlwSection(from image).\n"); + } + hostSlwSection = hostSlwSectionFixed; + // CMO-20130114: Remove this asap. Only for fixed img transition. - End + } + else { // SRAM non-fixed image. + rc = sbe_xip_get_section( io_image, SBE_XIP_SECTION_SLW, &xipSection); + if (rc) { + MY_ERR("Probably invalid section name for SBE_XIP_SECTION_SLW.\n"); + return IMGBUILD_ERR_GET_SECTION; + } + hostSlwSection = (void*)((uintptr_t)io_image + xipSection.iv_offset); + } + + // ------------------------------------------------------------------------- + // Check .slw section size and cross-check w/header define. + // + if (xipSection.iv_size!=FIXED_SLW_SECTION_SIZE) { + MY_ERR("SLW table size in *.H header file (=%i) differs from SLW section size in image (=%i).\n",FIXED_SLW_SECTION_SIZE,xipSection.iv_size); + MY_ERR("Check code or image version.\n"); + return IMGBUILD_ERR_SCOM_HDRS_NOT_SYNCD; + } + + // ------------------------------------------------------------------------- + // Summarize parameters and checking results. + // + MY_INF("Input parameter checks - OK\n"); + MY_INF("\tRegister = 0x%08x\n",i_scomAddr); + MY_INF("\tOperation = %i\n",i_operation); + MY_INF("\tSection = %i\n",i_section); + MY_INF("\tCore ID = %i\n",i_coreId); + MY_INF("Image validation and size checks - OK\n"); + MY_INF("\tSLW section size= %i\n",xipSection.iv_size); + + // ------------------------------------------------------------------------- + // Locate Scom vector according to i_section and then locate Scom table + // associated with "This" core ID. + // + if (i_modeBuild==P8_SLW_MODEBUILD_IPL || + i_modeBuild==P8_SLW_MODEBUILD_REBUILD) { // Fixed image. + switch (i_section) { + case P8_SCOM_SECTION_NC: + hostScomTableThis = (void*)( (uintptr_t)hostSlwSection + + SLW_RAM_TABLE_SIZE + + SLW_SCOM_TABLE_SPACE_PER_CORE_NC*i_coreId ); + break; + case P8_SCOM_SECTION_L2: + hostScomTableThis = (void*)( (uintptr_t)hostSlwSection + + SLW_RAM_TABLE_SIZE + + SLW_SCOM_TABLE_SIZE_NC + + SLW_SCOM_TABLE_SPACE_PER_CORE_L2*i_coreId ); + break; + case P8_SCOM_SECTION_L3: + hostScomTableThis = (void*)( (uintptr_t)hostSlwSection + + SLW_RAM_TABLE_SIZE + + SLW_SCOM_TABLE_SIZE_NC + + SLW_SCOM_TABLE_SIZE_L2 + + SLW_SCOM_TABLE_SPACE_PER_CORE_L3*i_coreId ); + break; + default: + MY_ERR("Invalid value for i_section (=%i).\n",i_section); + MY_ERR("Valid values for i_section = [%i,%i,%i].\n", + P8_SCOM_SECTION_NC,P8_SCOM_SECTION_L2,P8_SCOM_SECTION_L3); + return IMGBUILD_ERR_SCOM_INVALID_SUBSECTION; + break; + } + } + else { // SRAM non-fixed image. + switch (i_section) { + case P8_SCOM_SECTION_NC: + rc = sbe_xip_find( io_image, SLW_HOST_SCOM_NC_VECTOR_TOC_NAME, &xipTocItem); + if (rc) { + MY_ERR("Probably invalid key word for SLW_HOST_SCOM_NC_VECTOR_TOC_NAME.\n"); + return IMGBUILD_ERR_KEYWORD_NOT_FOUND; + } + break; + case P8_SCOM_SECTION_L2: + rc = sbe_xip_find( io_image, SLW_HOST_SCOM_L2_VECTOR_TOC_NAME, &xipTocItem); + if (rc) { + MY_ERR("Probably invalid key word for SLW_HOST_SCOM_L2_VECTOR_TOC_NAME.\n"); + return IMGBUILD_ERR_KEYWORD_NOT_FOUND; + } + break; + case P8_SCOM_SECTION_L3: + rc = sbe_xip_find( io_image, SLW_HOST_SCOM_L3_VECTOR_TOC_NAME, &xipTocItem); + if (rc) { + MY_ERR("Probably invalid key word for SLW_HOST_SCOM_L3_VECTOR_TOC_NAME.\n"); + return IMGBUILD_ERR_KEYWORD_NOT_FOUND; + } + break; + default: + MY_ERR("Invalid value for i_section (=%i).\n",i_section); + MY_ERR("Valid values for i_section = [%i,%i,%i].\n", + P8_SCOM_SECTION_NC,P8_SCOM_SECTION_L2,P8_SCOM_SECTION_L3); + return IMGBUILD_ERR_SCOM_INVALID_SUBSECTION; + } + MY_INF("xipTocItem.iv_address = 0x%016llx\n",xipTocItem.iv_address); + sbe_xip_pore2host( io_image, xipTocItem.iv_address, &hostScomVector); + MY_INF("hostScomVector = 0x%016llx\n",(uint64_t)hostScomVector); + xipScomTableThis = myRev64(*((uint64_t*)hostScomVector + i_coreId)); + MY_INF("xipScomTableThis = 0x%016llx\n",xipScomTableThis); + if (xipScomTableThis) { + sbe_xip_pore2host( io_image, xipScomTableThis, &hostScomTableThis); + } + else { // Should never be here. + MY_ERR("Code or image bug. Scom vector table entries should never be null.\n"); + return IMGBUILD_ERR_CHECK_CODE; + } + } + + // + // Determine where to place/do Scom action and if entry already exists. + // Insertion rules: + // - If entry doesn't exist, insert at first NOP. (Note that if you don't do + // this, then the table might potentially overflow since the max table size + // doesn't include NOP entries.) + // - If no NOP found, insert at first RET. + // + + // First, create search strings for addr, nop and ret. + // Note, the following IIS will also be used in case of + // - i_operation==append + // - i_operation==replace + pore_inline_context_create( &ctx, (void*)bufIIS, XIPSIZE_SCOM_ENTRY, 0, 0); + pore_LS( &ctx, P1, chipletId); + pore_STI( &ctx, i_scomAddr, P1, i_scomData); + if (ctx.error > 0) { + MY_ERR("pore_LS or _STI generated rc = %d", ctx.error); + return IMGBUILD_ERR_PORE_INLINE_ASM; + } + pore_inline_context_create( &ctx, (void*)bufRET, 4, 0, 0); + pore_RET( &ctx); + if (ctx.error > 0) { + MY_ERR("pore_RET generated rc = %d", ctx.error); + return IMGBUILD_ERR_PORE_INLINE_ASM; + } + pore_inline_context_create( &ctx, (void*)bufNOP, 4, 0, 0); + pore_NOP( &ctx); + if (ctx.error > 0) { + MY_ERR("pore_NOP generated rc = %d", ctx.error); + return IMGBUILD_ERR_PORE_INLINE_ASM; + } + + // Second, search for addr and nop in relevant coreId table until first RET. + // Note: + // - We go through ALL entries until first RET instr. We MUST find a RET instr, + // though we don't check for overrun until later. (Should be improved.) + // - Count number of entries and check for overrun, though we'll continue + // searching until we find an RET. (Should be improved.) + // - The STI(+SCOM_addr) opcode is in the 2nd word of the Scom entry. + // - For an append operation, if a NOP is found (before a RET obviously), the + // SCOM is replacing that NNNN sequence. + hostScomEntryNext = hostScomTableThis; + MY_DBG("hostScomEntryNext (addr): 0x%016llx\n ",(uint64_t)hostScomEntryNext); + while (*(uint32_t*)hostScomEntryNext!=*(uint32_t*)bufRET) { + entriesCount++; + MY_DBG("Number of SCOM entries: %i\n ",entriesCount); + if (*((uint32_t*)bufIIS+1)==*((uint32_t*)hostScomEntryNext+1) && entriesMatch==0) {// +1 skips 1st word in Scom entry (which loads the PC in an LS operation.) + hostScomEntryMatch = hostScomEntryNext; + entriesMatch++; + } + if (*(uint32_t*)hostScomEntryNext==*(uint32_t*)bufNOP && entriesNOP==0) { + hostScomEntryNOP = hostScomEntryNext; + entriesNOP++; + } + hostScomEntryNext = (void*)((uintptr_t)hostScomEntryNext + XIPSIZE_SCOM_ENTRY); + } + hostScomEntryRET = hostScomEntryNext; // The last EntryNext is always the first RET. + + switch (i_section) { + case P8_SCOM_SECTION_NC: + if (entriesCount>=SLW_MAX_SCOMS_NC) { + MY_ERR("SCOM table NC is full. Max %i entries allowed.\n",SLW_MAX_SCOMS_NC); + return IMGBUILD_ERR_CHECK_CODE; + } + break; + case P8_SCOM_SECTION_L2: + if (entriesCount>=SLW_MAX_SCOMS_L2) { + MY_ERR("SCOM table L2 is full. Max %i entries allowed.\n",SLW_MAX_SCOMS_L2); + return IMGBUILD_ERR_CHECK_CODE; + } + break; + case P8_SCOM_SECTION_L3: + if (entriesCount>=SLW_MAX_SCOMS_L3) { + MY_ERR("SCOM table L3 is full. Max %i entries allowed.\n",SLW_MAX_SCOMS_L3); + return IMGBUILD_ERR_CHECK_CODE; + } + break; + default: + MY_ERR("Invalid value for i_section (=%i).\n",i_section); + MY_ERR("Valid values for i_section = [%i,%i,%i].\n", + P8_SCOM_SECTION_NC,P8_SCOM_SECTION_L2,P8_SCOM_SECTION_L3); + return IMGBUILD_ERR_SCOM_INVALID_SUBSECTION; + } + + // + // Further qualify (translate) operation and IIS. + // + if (i_operation==P8_PORE_SCOM_APPEND) { + operation = i_operation; + } + else if (i_operation==P8_PORE_SCOM_REPLACE) { + if (hostScomEntryMatch) + // ... do a replace + operation = i_operation; + else + // ... do an append + operation = P8_PORE_SCOM_APPEND; + } + else if (i_operation==P8_PORE_SCOM_NOOP) { + // ...overwrite earlier bufIIS from the search step + pore_inline_context_create( &ctx, (void*)bufIIS, XIPSIZE_SCOM_ENTRY, 0, 0); + pore_NOP( &ctx); + pore_NOP( &ctx); + pore_NOP( &ctx); + pore_NOP( &ctx); + if (ctx.error > 0) { + MY_ERR("*** _NOP generated rc = %d", ctx.error); + return IMGBUILD_ERR_PORE_INLINE_ASM; + } + operation = i_operation; + } + else if (i_operation==P8_PORE_SCOM_AND || + i_operation==P8_PORE_SCOM_OR) { + operation = i_operation; + } + else if (i_operation==P8_PORE_SCOM_RESET) { + // ... create RNNN instruction sequence. + pore_inline_context_create( &ctx, (void*)bufIIS, XIPSIZE_SCOM_ENTRY, 0, 0); + pore_RET( &ctx); + pore_NOP( &ctx); + pore_NOP( &ctx); + pore_NOP( &ctx); + if (ctx.error > 0) { + MY_ERR("***_RET or _NOP generated rc = %d", ctx.error); + return IMGBUILD_ERR_PORE_INLINE_ASM; + } + operation = i_operation; + } + else { + MY_ERR("Scom operation = %i is not within valid range of [%d;%d]\n", + i_operation, P8_PORE_SCOM_FIRST_OP, P8_PORE_SCOM_LAST_OP); + return IMGBUILD_ERR_SCOM_INVALID_PARM; + } + + // ------------------------------------------------------------------------- + // Assuming pre-allocated Scom table (after pre-allocated Ram table): + // - Table is pre-filled with RNNN ISS. + // - Each core Id has dedicated space, uniformly distributed by SLW_MAX_SCOMS_NC* + // XIPSIZE_SCOM_ENTRY. + // - Remember to check for more than SLW_MAX_SCOMS_NC entries! + switch (operation) { + + case P8_PORE_SCOM_APPEND: // Append a Scom at first occurring NNNN or RNNN, + if (hostScomEntryNOP) { + // ... replace the NNNN + MY_INF("Append at NOP\n"); + memcpy(hostScomEntryNOP,(void*)bufIIS,XIPSIZE_SCOM_ENTRY); + } + else if (hostScomEntryRET) { + // ... replace the RNNN + MY_INF("Append at RET\n"); + memcpy(hostScomEntryRET,(void*)bufIIS,XIPSIZE_SCOM_ENTRY); + } + else { + // We should never be here. + MY_ERR("In case=_SCOM_APPEND: EntryRET=NULL is impossible. Check code.\n"); + return IMGBUILD_ERR_CHECK_CODE; + } + break; + case P8_PORE_SCOM_REPLACE: // Replace existing Scom with new data + if (hostScomEntryMatch) { + // ... do a vanilla replace + MY_INF("Replace existing Scom\n"); + memcpy(hostScomEntryMatch,(void*)bufIIS,XIPSIZE_SCOM_ENTRY); + } + else { + // We should never be here. + MY_ERR("In case=_SCOM_REPLACE: EntryMatch=NULL is impossible. Check code.\n"); + return IMGBUILD_ERR_CHECK_CODE; + } + break; + case P8_PORE_SCOM_NOOP: + if (hostScomEntryMatch) { + // ... do a vanilla replace + MY_INF("Replace existing Scom w/NOPs\n"); + memcpy(hostScomEntryMatch,(void*)bufIIS,XIPSIZE_SCOM_ENTRY); + } + else { + // do nothing, and assume everything is fine, since we did no damage. + } + break; + case P8_PORE_SCOM_OR: // Overlay Scom data onto existing data by bitwise OR + if (hostScomEntryMatch) { + // ... do an OR on the data (which is the 2nd DWord in the entry) + MY_INF("Overlay existing Scom - OR case\n"); + *((uint64_t*)hostScomEntryMatch+1) = + *((uint64_t*)hostScomEntryMatch+1) | myRev64(i_scomData); + } + else { + MY_ERR("No Scom entry found to do OR operation with.\n"); + return IMGBUILD_ERR_SCOM_ENTRY_NOT_FOUND; + } + break; + case P8_PORE_SCOM_AND: // Overlay Scom data onto existing data by bitwise AND + if (hostScomEntryMatch) { + // ... do an AND on the data (which is the 2nd DWord in the entry) + MY_INF("Overlay existing Scom - AND case\n"); + *((uint64_t*)hostScomEntryMatch+1) = + *((uint64_t*)hostScomEntryMatch+1) & myRev64(i_scomData); + } + else { + MY_ERR("No Scom entry found to do AND operation with.\n"); + return IMGBUILD_ERR_SCOM_ENTRY_NOT_FOUND; + } + break; + case P8_PORE_SCOM_RESET: // Reset (delete) table. Refill w/RNNN ISS. + MY_INF("Reset table\n"); + hostScomEntryNext = hostScomTableThis; + for ( iEntry=0; iEntry<entriesCount; iEntry++) { + memcpy( hostScomEntryNext, (void*)bufIIS, XIPSIZE_SCOM_ENTRY); + hostScomEntryNext = (void*)((uintptr_t)hostScomEntryNext + XIPSIZE_SCOM_ENTRY); + } + break; + default: + MY_ERR("Impossible value of operation (=%i). Check code.\n",operation); + return IMGBUILD_ERR_CHECK_CODE; + + } // End of switch(operation) + + return rc; +} diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_slw_build.C b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_slw_build.C index bf7a26e29..96beebdee 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_slw_build.C +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_slw_build.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_slw_build.C,v 1.10 2013/02/08 02:48:58 cmolsen Exp $ +// $Id: p8_slw_build.C,v 1.21 2013/03/14 03:07:11 cmolsen Exp $ /*------------------------------------------------------------------------------*/ /* *! TITLE : p8_slw_build */ /* *! DESCRIPTION : Extracts and decompresses delta ring states from EPROM */ @@ -91,17 +91,15 @@ ReturnCode p8_slw_build( const fapi::Target &i_target, uint32_t *io_sizeImageOut) { ReturnCode rc; - uint8_t l_uint8 = 0; - uint32_t ddLevel=0; - uint8_t sysPhase=1; // Build an SLW image. - + uint8_t l_uint8 = 0; + uint32_t ddLevel=0; + uint8_t sysPhase=1; uint32_t rcLoc=0, rcSearch=0, i, countWF=0; uint32_t sizeImage=0, sizeImageOutMax, sizeImageTmp, sizeImageOld; - //uint8_t *deltaRingDxed=NULL; CompressedScanData *deltaRingRS4=NULL; DeltaRingLayout rs4RingLayout; - void *nextRing=NULL; - uint32_t ringBitLen=0; //ringByteLen=0, ringTrailBits=0; + void *nextRing=NULL; + uint32_t ringBitLen=0; uint32_t *wfInline=NULL; uint32_t wfInlineLenInWords; uint64_t scanMaxRotate=SCAN_ROTATE_DEFAULT; @@ -232,10 +230,9 @@ ReturnCode p8_slw_build( const fapi::Target &i_target, } FAPI_DBG("Image size (after .pibmem0 delete): %i",sizeImage); - // ========================================================================== - // Get DD level from FAPI attributes. - // ========================================================================== -// rc = FAPI_ATTR_GET(ATTR_EC, &i_target, l_uint8); + // + // DD level. + // rc = FAPI_ATTR_GET_PRIVILEGED(ATTR_EC, &i_target, l_uint8); ddLevel = (uint32_t)l_uint8; if (rc) { @@ -243,8 +240,73 @@ ReturnCode p8_slw_build( const fapi::Target &i_target, return rc; } + +#ifndef IMGBUILD_PPD_IGNORE_XIPC + // ========================================================================== + // Get various FAPI attributes and variables needed for ring unraveling. + // ========================================================================== + uint8_t attrAsyncSafeMode=0, bAsyncSafeMode; + uint32_t attrFuncL3RingList[MAX_FUNC_L3_RING_LIST_ENTRIES]={0}; + uint8_t attrFuncL3RingData[MAX_FUNC_L3_RING_SIZE]={0}; + uint32_t attrFuncL3RingLength=0; + SbeXipItem xipTocItem; + uint64_t xipFuncL3RingVector=0; + uint32_t iEntry; + + // Safe mode status. + // + rc = FAPI_ATTR_GET(ATTR_PROC_FABRIC_ASYNC_SAFE_MODE, NULL, attrAsyncSafeMode); + FAPI_DBG("--> attrAsyncSafeMode = 0x%x ",attrAsyncSafeMode); + if (rc) { + FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_FABRIC_ASYNC_SAFE_MODE) returned error."); + return rc; + } + bAsyncSafeMode = attrAsyncSafeMode; + FAPI_DBG("--> bAsyncSafeMode = 0x%x ",bAsyncSafeMode); + + // Obtain ex_func_l3_ring overlay data and length from attributes. + // Obtain ring name and ring's vector location from image. + // + FAPI_DBG("--> (1) Check if we should modify the ex_func_l3_ring with attribute data."); + if (!bAsyncSafeMode) { + FAPI_DBG("--> (1) Yes, we should modify the ex_func_l3_ring with attribute data."); + // Get overlay ring from attributes. + rc = FAPI_ATTR_GET(ATTR_PROC_EX_FUNC_L3_DELTA_DATA, &i_target, attrFuncL3RingList); + if (rc) { + FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_EX_FUNC_L3_DELTA_DATA) returned error."); + return rc; + } + rc = FAPI_ATTR_GET(ATTR_PROC_EX_FUNC_L3_LENGTH, &i_target, attrFuncL3RingLength); + if (rc) { + FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_EX_FUNC_L3_LENGTH) returned error."); + return rc; + } + //attrFuncL3RingLength = 0xBEBA; + for (iEntry=0; iEntry<MAX_FUNC_L3_RING_LIST_ENTRIES; iEntry++) { + if (attrFuncL3RingList[iEntry]!=0xffff0000) { + attrFuncL3RingData[attrFuncL3RingList[iEntry]>>16] = (uint8_t)((attrFuncL3RingList[iEntry]<<24)>>24); + } + else + break; + } + FAPI_DBG("Overlay [raw] ring created. "); + // Get ring name from xip image. + rcLoc = sbe_xip_find((void*)i_imageIn, FUNC_L3_RING_TOC_NAME, &xipTocItem); + if (rcLoc) { + FAPI_ERR("sbe_xip_find() failed w/rc=%i", rcLoc); + FAPI_ERR("Probable cause:"); + FAPI_ERR("\tThe keyword (=%s) was not found.", FUNC_L3_RING_TOC_NAME); + uint32_t & RC_LOCAL = rcLoc; + FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_KEYWORD_NOT_FOUND_ERROR); + return rc; + } + xipFuncL3RingVector = xipTocItem.iv_address; + } +#endif + + /*************************************************************************** - * SEARCH LOOP - Begin * + * SEARCH LOOP - Begin * ***************************************************************************/ do { @@ -298,6 +360,7 @@ ReturnCode p8_slw_build( const fapi::Target &i_target, NULL, // No need to pass a separate out image sizeImageTmp, sysPhase, + 2, // We're only interested in SRAM mode for non-fixed img. buf1, sizeBuf1, buf2, @@ -310,9 +373,9 @@ ReturnCode p8_slw_build( const fapi::Target &i_target, return rc; } FAPI_INF("Xip customization done."); -#endif - sizeImageTmp = sizeImageOutMax; +#else // Initialize .slw section with PORE table. + sizeImageTmp = sizeImageOutMax; rcLoc = initialize_slw_section( i_imageOut, &sizeImageTmp); if (rcLoc) { @@ -329,6 +392,8 @@ ReturnCode p8_slw_build( const fapi::Target &i_target, return rc; } FAPI_INF("SLW section allocated for Ramming and Scomming tables."); +#endif + // Update host_runtime_scom pointer to point to sub_slw_runtime_scom rcLoc = update_runtime_scom_pointer( i_imageOut); if (rcLoc==IMGBUILD_ERR_KEYWORD_NOT_FOUND) { @@ -373,18 +438,11 @@ ReturnCode p8_slw_build( const fapi::Target &i_target, // Decompress RS4 delta state. // ========================================================================== FAPI_DBG("--> Decompressing RS4 delta ring."); - // Note: deltaRingDxed is left-aligned. If converting to uint32_t, do BE->LE flip. - //deltaRingDxed = NULL; - //rcLoc = rs4_decompress( &deltaRingDxed, - // &ringBitLen, - // deltaRingRS4); rcLoc = _rs4_decompress((uint8_t*)buf2, sizeBuf2, &ringBitLen, deltaRingRS4); if (rcLoc) { - //FAPI_ERR("\trs4_decompress() failed: rc=%i",rcLoc); - //if (deltaRingDxed) free(deltaRingDxed); FAPI_ERR("\t_rs4_decompress() failed: rc=%i",rcLoc); if (buf2) free(buf2); uint32_t & RC_LOCAL=rcLoc; @@ -394,6 +452,79 @@ ReturnCode p8_slw_build( const fapi::Target &i_target, FAPI_DBG("\tDecompression successful.\n"); +#ifndef IMGBUILD_PPD_IGNORE_XIPC + // ========================================================================== + // CUSTOMIZE item: Overlay ex_func_l3_ring. + // Retrieval method: Attribute. + // Note: Check if ex_func_l3_ring's vector address matches current backPtr. + // If so, perform OR operation with new attribute data for this ring. + // Assumptions: + // - Base ring only. + // - Correct DD level rings only. + // ========================================================================== + uint8_t byteExisting=0, byteOverlay=0, bGoodByte=1; + uint32_t iByte, sizeRingInBytes; + FAPI_DBG("--> (2) Check if we should modify the ex_func_l3_ring with attribute data."); + if (!bAsyncSafeMode) { + FAPI_DBG("--> (2) Yes, we should modify the ex_func_l3_ring with attribute data."); + // Find ring match by comparing backItemPtr and ring lengths. Note that + // we can't use fwdPtr for finding a match since we don't know which DD + // level ring it ended up pointing at. + if (xipFuncL3RingVector==myRev64(rs4RingLayout.backItemPtr) && + attrFuncL3RingLength==myRev32(deltaRingRS4->iv_length)) { + // Perform OR between the existing ring and attribute ring. + sizeRingInBytes = (attrFuncL3RingLength-1)/8 + 1; + bGoodByte = 1; +//// FAPI_DBG("Byte[ # ]: ER OR FR "); + FAPI_DBG("Byte[ # ]: ER OR =ER? "); + FAPI_DBG("-----------------------"); + for (iByte=0; (iByte<sizeRingInBytes && bGoodByte); iByte++) { +//// FAPI_DBG("Byte[%4i]: %02x ", +//// iByte, +//// *((uint8_t*)buf2+iByte)); + if (*(attrFuncL3RingData+iByte)) { + // Check there are 0-bits in the existing byte where there are + // 1-bits in the overlay byte. + byteExisting = *((uint8_t*)buf2+iByte); + byteOverlay = *(&attrFuncL3RingData[0]+iByte); + if (byteExisting!=(byteExisting & ~byteOverlay)) { + FAPI_ERR("Byte[%4i]: %02x %02x %02x <-violation",iByte,byteExisting,byteOverlay,byteExisting&~byteOverlay); + bGoodByte = 0; + break; + } + else { + FAPI_DBG("Byte[%4i]: %02x %02x %02x ",iByte,byteExisting,byteOverlay,byteExisting&~byteOverlay); + } + // Only update existing ring when there's content in overlay data. +//// FAPI_DBG("Byte[%4i]: %02x %02x %02x ", +//// iByte, +//// *((uint8_t*)buf2+iByte), +//// *(&attrFuncL3RingData[0]+iByte), +//// *((uint8_t*)buf2+iByte) | *(&attrFuncL3RingData[0]+iByte)); + *((uint8_t*)buf2+iByte) = byteExisting | byteOverlay; +//// FAPI_DBG("Byte[%4i]: %02x ", +//// iByte, +//// *((uint8_t*)buf2+iByte)); + } +//// FAPI_DBG("Byte[%4i]: %02x ", +//// iByte, +//// *((uint8_t*)buf2+iByte)); + } + FAPI_DBG("-----------------------"); + if (!bGoodByte) { + FAPI_ERR("The existing ex_l3_func_ring has 1-bits in overlay locations. "); + if (buf2) free(buf2); + uint32_t & DATA_FAIL_BYTE_NO = iByte; + uint8_t & DATA_EXISTING_RING_BYTE = byteExisting; + uint8_t & DATA_OVERLAY_RING_BYTE = byteOverlay; + FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_L3_FUNC_OVERLAY_ERROR); + return rc; + } + } + } +#endif + + // ========================================================================== // Create Wiggle-Flip Programs (but first resolve max rotate status.) // ========================================================================== @@ -423,11 +554,8 @@ ReturnCode p8_slw_build( const fapi::Target &i_target, FAPI_INF("Continuing...\n"); } -#ifdef IMGBUILD_PPD_ENFORCE_SCAN_DELAY + // Support for enforcing delay after WF scan write scoms. uint64_t waitsScanDelay=10; - // Temporary support for enforcing delay after scan WF scoms. - // Also remove all references and usages of waitsScanDelay in this file and in - // p8_image_help.C. rcLoc = sbe_xip_get_scalar( (void*)i_imageIn, "waits_delay_for_scan", &waitsScanDelay); if (rcLoc) { FAPI_ERR("Error obtaining waits_delay_for_scan keyword.\n"); @@ -436,7 +564,6 @@ ReturnCode p8_slw_build( const fapi::Target &i_target, FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_UNKNOWN_XIP_ERROR); return rc; } -#endif wfInline = (uint32_t*)buf1; wfInlineLenInWords = sizeBuf1/4; @@ -444,14 +571,11 @@ ReturnCode p8_slw_build( const fapi::Target &i_target, ringBitLen, myRev32(deltaRingRS4->iv_scanSelect), (uint32_t)deltaRingRS4->iv_chipletId, - &wfInline, + &wfInline, &wfInlineLenInWords, -#ifdef IMGBUILD_PPD_ENFORCE_SCAN_DELAY + deltaRingRS4->iv_flushOptimization, (uint32_t)scanMaxRotate, (uint32_t)waitsScanDelay); -#else - (uint32_t)scanMaxRotate); -#endif if (rcLoc) { FAPI_ERR("create_wiggle_flip_prg() failed w/rcLoc=%i",rcLoc); //if (deltaRingDxed) free(deltaRingDxed); @@ -497,15 +621,6 @@ ReturnCode p8_slw_build( const fapi::Target &i_target, sizeImageOld = sizeImageTmp; countWF++; - - // ========================================================================== - // Clean up - // ========================================================================== - //if (deltaRingDxed) free(deltaRingDxed); - // 2012-11-14: CMO- Do NOT free buf1 or buf2 here! They are used in xip_customize(). - // And once these buffers are actually passed as parms to slw_build, - // stop freeing them inside slw_build!!!!!!!! - // ========================================================================== // Are we done? // ========================================================================== @@ -530,6 +645,7 @@ ReturnCode p8_slw_build( const fapi::Target &i_target, NULL, // No need to pass a separate out image sizeImageTmp, sysPhase, + 2, // We're only interested in SRAM mode for non-fixed img. buf1, sizeBuf1, buf2, @@ -542,9 +658,9 @@ ReturnCode p8_slw_build( const fapi::Target &i_target, return rc; } FAPI_INF("Xip customization done."); -#endif +#else + // Initialize .slw section with PORE table. sizeImageTmp = sizeImageOutMax; - // Initialize .slw section with PORE table. rcLoc = initialize_slw_section( i_imageOut, &sizeImageTmp); if (rcLoc) { @@ -561,13 +677,16 @@ ReturnCode p8_slw_build( const fapi::Target &i_target, return rc; } FAPI_INF("SLW section initialized for Ramming and Scomming tables."); - // Update host_runtime_scom pointer to point to sub_slw_runtime_scom +#endif + + // Update host_runtime_scom pointer to point to sub_slw_runtime_scom rcLoc = update_runtime_scom_pointer(i_imageOut); if (rcLoc==IMGBUILD_ERR_KEYWORD_NOT_FOUND) { uint32_t &RC_LOCAL=rcLoc; FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_KEYWORD_NOT_FOUND_ERROR); return rc; } + // Report final size. sbe_xip_image_size( i_imageOut, io_sizeImageOut); FAPI_INF("Final SLW image size: %i", *io_sizeImageOut); diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_slw_build.H b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_slw_build.H index ca6ad7e57..831c51d46 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_slw_build.H +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_slw_build.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,16 +20,37 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_slw_build.H,v 1.2 2012/09/17 19:42:43 cmolsen Exp $ +// $Id: p8_slw_build.H,v 1.4 2013/02/12 23:25:58 cmolsen Exp $ #include <fapi.H> +#include <p8_scan_compression.H> + typedef fapi::ReturnCode (*p8_slw_build_FP_t) ( const fapi::Target&, const void*, uint32_t, void*, uint32_t*); +typedef fapi::ReturnCode (*p8_slw_build_fixed_FP_t) ( const fapi::Target&, + void*, + void*, + uint32_t&, + const uint8_t, + void*, + const uint32_t, + void*, + const uint32_t ); + +typedef fapi::ReturnCode (*p8_slw_repair_FP_t) (const fapi::Target&, + void*, + CompressedScanData*, + void*, + const uint32_t, + void*, + const uint32_t); + + extern "C" { // Description: FAPI HWP entry point. p8_slw_build() constructs the @@ -47,4 +68,52 @@ extern "C" uint32_t i_sizeImageIn, void *i_imageOut, uint32_t *io_sizeImageOut); + + + // Description: FAPI HWP entry point. p8_slw_build_fixed() constructs the + // fixed Sleep-Winkle (SLW) image in mainstore during Hostboot + // IPL, PHYP rebuild and non-fixed image for SRAM. + // Parameters: i_target: Processor chip target. + // *i_imageIn: Pointer to input Reference image (from PNOR). + // *i_imageOut: Pointer to output SLW image. + // &io_sizeImageOut: In: Max size of output img. + // Out: Final size of output img. + // i_modeBuild: 0: HB/IPL mode, 1: PHYP/Rebuild mode, + // 2: SRAM mode. + // *i_buf1: Temp buffer 1 for dexed RS4 ring. (Caller + // allocs/frees.) + // i_sizeBuf1: Size of buf1. + // *i_buf2: Temp buffer 2 for WF ring. (Caller + // allocs/frees.) + // i_sizeBuf2: Size of buf2. + fapi::ReturnCode p8_slw_build_fixed( const fapi::Target &i_target, + void *i_imageIn, + void *i_imageOut, + uint32_t &io_sizeImageOut, + const uint8_t i_modeBuild, + void *i_buf1, + const uint32_t i_sizeBuf1, + void *i_buf2, + const uint32_t i_sizeBuf2 ); + + + // Description: FAPI HWP entry point. p8_slw_repair() updates the L2 (core) + // and L3 (eco) cashes during concurrent rebuilds. + // Parameters: i_target: Processor chip target. + // *io_image: Pointer to SLW image. + // *i_bufRs4: Pointer to the RS4 ring data. + // *i_buf1: Temp buffer 1 for dexed RS4 ring. (Caller + // allocs/frees.) + // i_sizeBuf1: Size of buf1. + // *i_buf2: Temp buffer 2 for WF ring. (Caller + // allocs/frees.) + // i_sizeBuf2: Size of buf2. + fapi::ReturnCode p8_slw_repair( const fapi::Target &i_target, + void *io_image, + CompressedScanData *i_bufRs4, + void *i_buf1, + const uint32_t i_sizeBuf1, + void *i_buf2, + const uint32_t i_sizeBuf2); + } diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_slw_build_errors.xml b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_slw_build_errors.xml index df9487970..5acb92c56 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_slw_build_errors.xml +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_slw_build_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> <!-- --> <!-- p1 --> <!-- --> @@ -31,6 +31,28 @@ </hwpError> <!-- *********************************************************************** --> <hwpError> + <rc>RC_PROC_SLWB_BUF_PTR_ERROR</rc> + <description>Supplied buffer(s) is invalid.</description> + <ffdc>DATA_BUF1_PTR</ffdc> + <ffdc>DATA_BUF2_PTR</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_SLWB_BUF_SIZE_NOT_FIXED</rc> + <description>Supplied buffer size(s) differs from agreed upon fixed ring buffer size.</description> + <ffdc>DATA_BUF1_SIZE</ffdc> + <ffdc>DATA_BUF2_SIZE</ffdc> + <ffdc>DATA_BUF_SIZE_FIXED</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_SLWB_IMAGE_SIZE_NOT_FIXED</rc> + <description>Supplied max output image size differs from agreed upon fixed SLW image size.</description> + <ffdc>DATA_IMG_SIZE_MAX</ffdc> + <ffdc>DATA_IMG_SIZE_FIXED</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> <rc>RC_PROC_SLWB_IMAGE_SIZE_MISMATCH</rc> <description>Supplied image size differs from size in image header.</description> <ffdc>DATA_IMG_SIZE_INP</ffdc> @@ -45,12 +67,32 @@ </hwpError> <!-- *********************************************************************** --> <hwpError> + <rc>RC_PROC_SLWB_RING_BLOCK_TOO_LARGE</rc> + <description>Ring block is too large.</description> + <ffdc>DATA_RING_BLOCK_SIZEOFTHIS</ffdc> + <ffdc>DATA_SIZE_OF_BUF1</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_SLWB_RING_BLOCK_ALIGN_ERROR</rc> + <description>Problem with WF ring block alignment.</description> + <ffdc>DATA_RING_BLOCK_ENTRYOFFSET</ffdc> + <ffdc>DATA_RING_BLOCK_SIZEOFTHIS</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_SLWB_IMGBUILD_ERROR</rc> + <description>Local IMGBUILD_xyz error from non-FAPI routine. Check rc code in p8_delta_scan_rw.h.</description> + <ffdc>RC_LOCAL</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> <rc>RC_PROC_SLWB_MAX_IMAGE_SIZE_EXCEEDED</rc> <description>Estimated image size exceeds max allowed size.</description> <ffdc>DATA_IMG_SIZE_OLD</ffdc> <ffdc>DATA_IMG_SIZE_EST</ffdc> <ffdc>DATA_IMG_SIZE_MAX</ffdc> -</hwpError> + </hwpError> <!-- *********************************************************************** --> <hwpError> <rc>RC_PROC_SLWB_INTERNAL_IMAGE_ERR</rc> @@ -83,6 +125,14 @@ </hwpError> <!-- *********************************************************************** --> <hwpError> + <rc>RC_PROC_SLWB_L3_FUNC_OVERLAY_ERROR</rc> + <description>Existing ring has 1-bits in overlay locations.</description> + <ffdc>DATA_FAIL_BYTE_NO</ffdc> + <ffdc>DATA_EXISTING_RING_BYTE</ffdc> + <ffdc>DATA_OVERLAY_RING_BYTE</ffdc> +</hwpError> + <!-- *********************************************************************** --> + <hwpError> <rc>RC_PROC_SLWB_WF_CREATION_ERROR</rc> <description>Wiggle-flip programming failed.</description> <ffdc>RC_LOCAL</ffdc> @@ -101,6 +151,12 @@ </hwpError> <!-- *********************************************************************** --> <hwpError> + <rc>RC_PROC_SLWB_CREATE_FIXED_IMAGE_ERROR</rc> + <description>Error associated with creating and initializing fixed image and fixed .slw and .ffdc sections.</description> + <ffdc>RC_LOCAL</ffdc> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> <rc>RC_PROC_SLWB_KEYWORD_NOT_FOUND_ERROR</rc> <description>A keyword in the XIP image was not found.</description> <ffdc>RC_LOCAL</ffdc> @@ -119,6 +175,11 @@ </hwpError> <!-- *********************************************************************** --> <hwpError> + <rc>RC_PROC_SLWB_BAD_CODE_OR_PARM</rc> + <description>Shouldn't be in this code section or invalid parm.</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> <rc>RC_PROC_SLWB_MEMORY_ERROR</rc> <description>Memory allocation error.</description> <ffdc>RC_LOCAL</ffdc> diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize.C b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize.C index 4ab947f25..b23b06fe4 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize.C +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_xip_customize.C,v 1.25 2013/02/13 01:55:59 cmolsen Exp $ +// $Id: p8_xip_customize.C,v 1.37 2013/03/18 16:08:32 cmolsen Exp $ /*------------------------------------------------------------------------------*/ /* *! TITLE : p8_xip_customize */ /* *! DESCRIPTION : Obtains repair rings from VPD and adds them to either */ @@ -30,9 +30,9 @@ /* *! EXTENDED DESCRIPTION : */ // /* *! USAGE : To build (for Hostboot) - */ -// buildfapiprcd -c "sbe_xip_image.c,pore_inline_assembler.c,p8_ring_identification.c" -C "p8_image_help.C,p8_image_help_base.C,p8_scan_compression.C" -e "$PROC_PATH/../../xml/error_info/p8_xip_customize_errors.xml,../../../../../../hwpf/hwp/xml/attribute_info/chip_attributes.xml,../../../../../../hwpf/hwp/xml/error_info/mvpd_errors.xml" p8_xip_customize.C -// To build (for VBU/command-line) - assuming getMvpdRing_x86.so already exist. -// buildfapiprcd -r ver-13-0 -c "sbe_xip_image.c,pore_inline_assembler.c,p8_ring_identification.c" -C "p8_image_help.C,p8_image_help_base.C,p8_scan_compression.C" -e "../../xml/error_info/p8_xip_customize_errors.xml,../../../../../../hwpf/hwp/xml/attribute_info/chip_attributes.xml,../../../../../../hwpf/hwp/xml/error_info/mvpd_errors.xml" -u "XIPC_COMMAND_LINE" p8_xip_customize.C +// buildfapiprcd -c "sbe_xip_image.c,pore_inline_assembler.c,p8_ring_identification.c" -C "p8_image_help.C,p8_image_help_base.C,p8_scan_compression.C,p8_pore_table_gen_api_fixed.C" -e "$PROC_PATH/../../xml/error_info/p8_xip_customize_errors.xml,$HWPF_PATH/hwp/xml/error_info/mvpd_errors.xml" p8_xip_customize.C +// To build (for VBU/command-line) - +// buildfapiprcd -r ver-13-0 -c "sbe_xip_image.c,pore_inline_assembler.c,p8_ring_identification.c" -C "p8_image_help.C,p8_image_help_base.C,p8_scan_compression.C,p8_pore_table_gen_api_fixed.C" -e "../../xml/error_info/p8_xip_customize_errors.xml,../../../../../../hwpf/hwp/xml/error_info/mvpd_errors.xml" -u "XIPC_COMMAND_LINE" p8_xip_customize.C // Other usages - // using "IMGBUILD_PPD_IGNORE_VPD" will ignore adding MVPD rings. // using "IMGBUILD_PPD_IGNORE_VPD_FIELD" will ignore using fapiGetMvpdField. @@ -50,6 +50,8 @@ #include <p8_xip_customize.H> #include <p8_delta_scan_rw.h> #include <p8_ring_identification.H> +#include <p8_pore_table_gen_api.H> +#include <p8_scom_addresses.H> extern "C" { @@ -59,27 +61,50 @@ using namespace fapi; // const fapi::Target &i_target: Processor chip target. // void *i_imageIn: Ptr to input IPL or input/output SLW image. // void *i_imageOut: Ptr to output IPL img. (Ignored for SLW/RAM imgs.) -// uint32_t io_sizeImageOut: In: Max size of IPL/SRAM img. Out: Final size. +// uint32_t io_sizeImageOut: In: Max size of IPL/SRAM workspace/img. Out: Final size. +// MUST equal FIXED_SEEPROM_WORK_SPACE for IPL Seeprom build. // uint8_t i_sysPhase: 0: IPL 1: SLW +// uint8_t i_modeBuild: 0: HB/IPL 1: PHYP/Rebuild 2: SRAM // void *i_buf1: Temp buffer 1 for dexed RS4 ring. Caller allocs/frees. +// Space MUST equal FIXED_RING_BUF_SIZE // uint32_t i_sizeBuf1: Size of buf1. +// MUST equal FIXED_RING_BUF_SIZE // void *i_buf2: Temp buffer 2 for WF ring. Caller allocs/frees. +// Space MUST equal FIXED_RING_BUF_SIZE // uint32_t i_sizeBuf22 Size of buf2. +// MUST equal FIXED_RING_BUF_SIZE // ReturnCode p8_xip_customize( const fapi::Target &i_target, void *i_imageIn, void *i_imageOut, uint32_t &io_sizeImageOut, const uint8_t i_sysPhase, + const uint8_t i_modeBuild, void *i_buf1, const uint32_t i_sizeBuf1, void *i_buf2, const uint32_t i_sizeBuf2 ) { fapi::ReturnCode rcFapi, rc=FAPI_RC_SUCCESS; - uint32_t rcLoc=0; - void *imageOut; - uint32_t sizeImage, sizeImageIn, sizeImageOutMax; + uint32_t rcLoc=0; + void *imageOut; + uint32_t sizeImage, sizeImageIn, sizeImageOutMax, sizeImageMax; + uint32_t iVec=0; + uint64_t attrCombGoodVec[MAX_CHIPLETS]={ (uint64_t(0xfedcba98)<<32)+0x76543210 }; + void *hostCombGoodVec; + uint32_t attrL2SingleMember=0; + void *hostL2SingleMember; + SbeXipItem xipTocItem; + uint32_t attrL2RT0Eps, attrL2RT1Eps, attrL2RT2Eps, attrL2WEps; + uint8_t attrL2ForceRT2Eps; + uint32_t attrL3RT0Eps, attrL3RT1Eps, attrL3RT2Eps, attrL3WEps; + uint8_t attrL3ForceRT2Eps; + uint64_t attrL3BAR1, attrL3BAR2, attrL3BARMask; + uint64_t scomData; + uint8_t coreId, bScomEntry; + uint32_t sizeImageTmp; + uint64_t ptrTmp1, ptrTmp2; + uint32_t dataTmp1, dataTmp2, dataTmp3; SBE_XIP_ERROR_STRINGS(errorStrings); @@ -99,11 +124,36 @@ ReturnCode p8_xip_customize( const fapi::Target &i_target, FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_INTERNAL_IMAGE_ERR); return rc; } + FAPI_INF("Input image:\n location=0x%016llx\n size=%i\n", + (uint64_t)i_imageIn, sizeImageIn); - // Second, if IPL phase, copy input image to supplied mainstore location. + // Second, if IPL phase, check image and buffer sizes and copy input image to + // output mainstore [work] location. // if (i_sysPhase==0) { imageOut = i_imageOut; + FAPI_INF("Output image:\n location=0x%016llx\n size (max)=%i\n", + (uint64_t)imageOut, sizeImageOutMax); + // + // First, we'll check image size. + // + if (sizeImageOutMax!=FIXED_SEEPROM_WORK_SPACE) { + FAPI_ERR("Max work space for output image (=%i) is not equal to FIXED_SEEPROM_WORK_SPACE (=%i).\n", + sizeImageOutMax,FIXED_SEEPROM_WORK_SPACE); + sizeImageTmp = FIXED_SEEPROM_WORK_SPACE; + uint32_t & DATA_IMG_SIZE_MAX = sizeImageOutMax; + uint32_t & DATA_IMG_SIZE_WORK_SPACE = sizeImageTmp; + FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_IMAGE_WORK_SPACE_MESS); + return rc; + } + if (sizeImageOutMax<sizeImageIn) { + FAPI_ERR("Max output image size (=%i) is smaller than input image size (=%i).", + sizeImageOutMax,sizeImageIn); + uint32_t & DATA_IMG_SIZE = sizeImageIn; + uint32_t & DATA_IMG_SIZE_MAX = sizeImageOutMax; + FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_IMAGE_SIZE_MESS); + return rc; + } memcpy( imageOut, i_imageIn, sizeImageIn); sbe_xip_image_size(imageOut, &sizeImage); rcLoc = sbe_xip_validate(imageOut, sizeImage); @@ -121,22 +171,49 @@ ReturnCode p8_xip_customize( const fapi::Target &i_target, FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_MS_IMAGE_SIZE_MISMATCH); return rc; } - FAPI_DBG("IPL phase: Input image (w/location=0x%016llx) copied to output image and validated w/size=%i bytes and location=0x%016llx", - (uint64_t)i_imageIn, sizeImageIn, (uint64_t)imageOut); + // + // Next, we'll check the ring buffers. + // + if (!i_buf1 || !i_buf2) { + FAPI_ERR("The [assumed] pre-allocated ring buffers, i_buf1/2, do not exist."); + ptrTmp1 = (uint64_t)i_buf1; + ptrTmp2 = (uint64_t)i_buf2; + uint64_t & DATA_BUF1_PTR = ptrTmp1; + uint64_t & DATA_BUF2_PTR = ptrTmp2; + FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_BUF_PTR_ERROR); + return rc; + } + if (i_sizeBuf1!=FIXED_RING_BUF_SIZE || i_sizeBuf2!=FIXED_RING_BUF_SIZE) { + FAPI_ERR("Supplied ring buffer size(s) differs from agreed upon fixed size."); + FAPI_ERR("Supplied ring buf1 size: %i",i_sizeBuf1); + FAPI_ERR("Supplied ring buf2 size: %i",i_sizeBuf2); + FAPI_ERR("Agreed upon fixed ring buf size: %i",FIXED_RING_BUF_SIZE); + dataTmp1 = i_sizeBuf1; + dataTmp2 = i_sizeBuf2; + dataTmp3 = FIXED_RING_BUF_SIZE; + uint32_t & DATA_BUF1_SIZE = dataTmp1; + uint32_t & DATA_BUF2_SIZE = dataTmp2; + uint32_t & DATA_BUF_SIZE_FIXED = dataTmp3; + FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_BUF_SIZE_NOT_FIXED); + return rc; + } } - else // Output image is same as input image in SLW case (even for an SRAM build). + else { + // Output image is same as input image in SLW case (even for an SRAM build). imageOut = i_imageIn; + } - // Customization defines. - // - uint32_t iVec=0; - uint64_t attrCombGoodVec[MAX_CHIPLETS]={ (uint64_t(0xfedcba98)<<32)+0x76543210 }; - void *hostCombGoodVec; - uint32_t attrL2SingleMember=0; - void *hostL2SingleMember; - SbeXipItem xipTocItem; - - // -------------------------------------------------------------------------- + + // ========================================================================== + // ========================================================================== + // *---------* + // CUSTOMIZATION OF | VECTORS | + // *---------* + // ========================================================================== + // ========================================================================== + + + // ========================================================================== // CUSTOMIZE item: Combined good vectors update. // Retrieval method: Attribute. // System phase: IPL and SLW sysPhase. @@ -144,7 +221,7 @@ ReturnCode p8_xip_customize( const fapi::Target &i_target, // Note: We will use the content of these vectors to determine if each // chiplet is functional. This is to avoid the messy "walking the // chiplets approach" using fapiGetChildChiplets(). - // -------------------------------------------------------------------------- + // ========================================================================== rc = FAPI_ATTR_GET(ATTR_CHIP_REGIONS_TO_ENABLE, &i_target, attrCombGoodVec); if (rc) { @@ -167,15 +244,14 @@ ReturnCode p8_xip_customize( const fapi::Target &i_target, *((uint64_t*)hostCombGoodVec+iVec) = myRev64(attrCombGoodVec[iVec]); FAPI_DBG(" After=0x%016llX\n",*((uint64_t*)hostCombGoodVec+iVec)); } - // -------------------------------------------------------------------------- + + + // ========================================================================== // CUSTOMIZE item: L2 "single member mode" enable. // Retrieval method: Attribute. // System phase: IPL and SLW sysPhase. - // Note: The 32 vectors are listed in order from chiplet 0x00 to 0x1f. - // Note: We will use the content of these vectors to determine if each - // chiplet is functional. This is to avoid the messy "walking the - // chiplets approach" using fapiGetChildChiplets(). - // -------------------------------------------------------------------------- + // Note: Governs if which cores' L2 may be flipped into single member mode. + // ========================================================================== rc = FAPI_ATTR_GET(ATTR_EX_L2_SINGLE_MEMBER_ENABLE, &i_target, attrL2SingleMember); if (rc) { @@ -194,19 +270,22 @@ ReturnCode p8_xip_customize( const fapi::Target &i_target, sbe_xip_pore2host( imageOut, xipTocItem.iv_address, &hostL2SingleMember); FAPI_DBG("Dumping [initial] global variable content of l2_single_member_enable_mask, and then the updated value:\n"); FAPI_DBG("l2_single_member_enable_mask: Before=0x%016llX\n",*(uint64_t*)hostL2SingleMember); - *(uint64_t*)hostL2SingleMember = (uint64_t)myRev32(attrL2SingleMember); + *(uint64_t*)hostL2SingleMember = myRev64((uint64_t)attrL2SingleMember<<32); FAPI_DBG(" After =0x%016llX\n",*(uint64_t*)hostL2SingleMember); + #ifndef IMGBUILD_PPD_IGNORE_VPD_FIELD void *hostPibmemRepairVec, *hostNestSkewAdjVec; uint8_t *bufVpdField; uint32_t sizeVpdField=0; uint8_t *byteField, *byteVector; - // -------------------------------------------------------------------------- + // ========================================================================== // CUSTOMIZE item: Update 20 swizzled bits for PIB repair vector. // Retrieval method: MVPD field. // System phase: IPL sysPhase. - // -------------------------------------------------------------------------- + // Note: Mvpd field data is returned in BE format. + // ========================================================================== + if (i_sysPhase==0) { bufVpdField = (uint8_t*)i_buf1; sizeVpdField = i_sizeBuf1; // We have to use fixed and max size buffer. @@ -248,11 +327,13 @@ ReturnCode p8_xip_customize( const fapi::Target &i_target, FAPI_INF("VPD field value (unalterd & in BE))=0x%016llX\n",*(uint64_t*)bufVpdField); } - // -------------------------------------------------------------------------- + + // ========================================================================== // CUSTOMIZE item: Update nest skewadjust vector. // Retrieval method: MVPD field. // System phase: IPL sysPhase. - // -------------------------------------------------------------------------- + // ========================================================================== + if (i_sysPhase==0) { bufVpdField = (uint8_t*)i_buf1; sizeVpdField = i_sizeBuf1; // We have to use fixed and max size buffer. @@ -296,12 +377,21 @@ ReturnCode p8_xip_customize( const fapi::Target &i_target, #endif + // ========================================================================== + // ========================================================================== + // *-------* + // CUSTOMIZATION OF | RINGS | SECTION + // *-------* + // ========================================================================== + // ========================================================================== + + #ifndef IMGBUILD_PPD_IGNORE_PLL_UPDATE - // -------------------------------------------------------------------------- + // ========================================================================== // CUSTOMIZE item: Update PLL ring (perv_bndy_pll_ring_alt). // Retrieval method: Attribute. // System phase: IPL sysPhase. - // -------------------------------------------------------------------------- + // ========================================================================== if (i_sysPhase==0) { uint32_t tmp32Const1, tmp32Const2; @@ -399,7 +489,7 @@ ReturnCode p8_xip_customize( const fapi::Target &i_target, (uint64_t)attrScanSelect<<32, 0, attrChipletId, - 0 ); + 1 ); // Always flush optimize for base rings. if (rcLoc) { FAPI_ERR("_rs4_compress() failed w/rc=%i",rcLoc); uint32_t &RC_LOCAL=rcLoc; @@ -497,9 +587,9 @@ ReturnCode p8_xip_customize( const fapi::Target &i_target, FAPI_ERR("FAPI_ATTR_GET_PRIVILEGED() failed w/rc=%i and ddLevel=0x%02x",(uint32_t)rc,attrDdLevel); return rc; } - bufPllRingAltBlock->ddLevel = (uint32_t)attrDdLevel; - bufPllRingAltBlock->sysPhase = i_sysPhase; - bufPllRingAltBlock->override = 0; + bufPllRingAltBlock->ddLevel = myRev32((uint32_t)attrDdLevel); + bufPllRingAltBlock->sysPhase = i_sysPhase; + bufPllRingAltBlock->override = 0; bufPllRingAltBlock->reserved1 = 0; bufPllRingAltBlock->reserved2 = 0; bufLC = (uint32_t)entryOffsetPllRingAltBlock; @@ -521,7 +611,7 @@ ReturnCode p8_xip_customize( const fapi::Target &i_target, FAPI_ERR(" Size of ring block = %i", sizeOfThisPllRingAltBlock); uint32_t &DATA_SIZE_OF_RS4_LAUNCH=sizeRs4Launch; tmp32Const1=(uint32_t)entryOffsetPllRingAltBlock; - uint32_t &DATA_RING_BLOCK_ENTRYOFFSET=tmp32Const1; + uint32_t &DATA_RING_BLOCK_ENTRYOFFSET=tmp32Const1; uint32_t &DATA_RING_BLOCK_SIZEOFTHIS=sizeOfThisPllRingAltBlock; FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_RING_BLOCK_ALIGN_ERROR); return rc; @@ -538,7 +628,8 @@ ReturnCode p8_xip_customize( const fapi::Target &i_target, 0, 0, 0, - sizeImageOutMax ); + MAX_SEEPROM_IMAGE_SIZE); // OK, since sysPhase=0. +// SBE_XIP_SECTION_RINGS); if (rcLoc) { FAPI_ERR("write_ring_block_to_image() failed w/rc=%i",rcLoc); FAPI_ERR("Check p8_delta_scan_rw.h for meaning of IMGBUILD_xyz rc code."); @@ -552,11 +643,12 @@ ReturnCode p8_xip_customize( const fapi::Target &i_target, #ifndef IMGBUILD_PPD_IGNORE_VPD - // -------------------------------------------------------------------------- - // CUSTOMIZE item: Add #G and #R rings. - // Applies to both sysPhase modes: IPL and SLW. - // For SLW, only update ex_ chiplet rings. - // -------------------------------------------------------------------------- + // ========================================================================== + // CUSTOMIZE item: Add #G and #R rings. + // Retrieval method: MVPD + // System phase: Applies to both sysPhase modes: IPL and SLW. + // Notes: For SLW, only update ex_ chiplet rings. + // ========================================================================== /*************************************************************************** * CHIPLET WALK LOOP - Begin * @@ -702,9 +794,9 @@ ReturnCode p8_xip_customize( const fapi::Target &i_target, else { // Add VPD ring to image. if (!bRingAlreadyAdded) { - sizeImageOut = sizeImageOutMax; rcLoc = 0; if (i_sysPhase==0) { + sizeImageOut = MAX_SEEPROM_IMAGE_SIZE; // Add VPD ring to --->>> IPL <<<--- image rcLoc = write_vpd_ring_to_ipl_image( imageOut, @@ -715,8 +807,10 @@ ReturnCode p8_xip_customize( const fapi::Target &i_target, (char*)(ring_id_list+iRing)->ringNameImg, (void*)i_buf2, //HB buf2 i_sizeBuf2); +// SBE_XIP_SECTION_RINGS); } else { + sizeImageOut = sizeImageOutMax; // Add VPD ring to --->>> SLW <<<--- image rcLoc = write_vpd_ring_to_slw_image( imageOut, @@ -727,7 +821,7 @@ ReturnCode p8_xip_customize( const fapi::Target &i_target, (char*)(ring_id_list+iRing)->ringNameImg, (void*)i_buf2, //HB buf2 i_sizeBuf2, - (ring_id_list+iRing)->bWcSpace); + (ring_id_list+iRing)->bWcSpace); } if (rcLoc) { if (i_sysPhase==0) { @@ -751,9 +845,383 @@ ReturnCode p8_xip_customize( const fapi::Target &i_target, } #endif - i_imageOut = imageOut; - sbe_xip_image_size( imageOut, &io_sizeImageOut); + + // ========================================================================== + // ========================================================================== + // *-----* + // CUSTOMIZATION OF | SLW | SECTION + // *-----* + // ========================================================================== + // ========================================================================== + + if (i_sysPhase==1) { + + // ========================================================================== + // INITIALIZE item: .slw section (aka runtime section). + // Retrieval method: N/A + // System phase: SLW sysPhase. + // Note: This item was originally in slw_build but has to be put here for + // practical reasons. + // ========================================================================== + + switch (i_modeBuild) { + // -------------------------------------------------------------------- + // case 0: IPL mode. + // - This is first time SLW image is built. Go all out. + // -------------------------------------------------------------------- + case P8_SLW_MODEBUILD_IPL: // IPL mode. + rcLoc = create_and_initialize_fixed_image(imageOut); + if (rcLoc) { + uint32_t & RC_LOCAL=rcLoc; + FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_CREATE_FIXED_IMAGE_ERROR); + return rc; + } + FAPI_INF("IPL mode build: Fixed SLW and FFDC sections allocated and SLW section initialized for Ramming and Scomming tables."); + break; + // -------------------------------------------------------------------- + // case 1: Rebuild mode - Nothing to do. + // - Image size already fixed at 1MB during IPL mode. + // - Fixed positioning of .slw and .ffdc already done during IPL mode. + // -------------------------------------------------------------------- + case P8_SLW_MODEBUILD_REBUILD: // Rebuild mode. (Need to update Ram/Scom vectors.) + rcLoc = create_and_initialize_fixed_image(imageOut); + if (rcLoc) { + uint32_t & RC_LOCAL=rcLoc; + FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_CREATE_FIXED_IMAGE_ERROR); + return rc; + } + FAPI_INF("Rebuild mode build: Fixed SLW and FFDC sections allocated and SLW section initialized for Ramming and Scomming tables."); + break; + // -------------------------------------------------------------------- + // case 2: SRAM mode. + // - Assumption: slw_build() called by OCC. + // - Need to make image as slim as possible. + // - Do not append .fit. + // - Position .slw right after .rings. + // - Do not append .ffdc. + // -------------------------------------------------------------------- + case P8_SLW_MODEBUILD_SRAM: // SRAM mode. + sizeImageTmp = sizeImageOutMax; + rcLoc = initialize_slw_section(imageOut, + &sizeImageTmp); + if (rcLoc) { + if (rcLoc==IMGBUILD_ERR_IMAGE_TOO_LARGE) { + uint32_t & DATA_IMG_SIZE_NEW=sizeImageTmp; + uint32_t & DATA_IMG_SIZE_MAX=sizeImageOutMax; + FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_MAX_IMAGE_SIZE_EXCEEDED); + } + else { + uint32_t & RC_LOCAL=rcLoc; + FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_APPEND_SLW_SECTION_ERROR); + } + return rc; + } + FAPI_INF("SRAM mode build: SLW section allocated for Ramming and Scomming tables."); + break; + // Default case - Should never get here. + default: + FAPI_ERR("Bad code, or bad modeBuild (=%i) parm.",i_modeBuild); + FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_BAD_CODE_OR_PARM); + return rc; + } + + + // ========================================================================== + // CUSTOMIZE item: L2 and L3 Epsilon config register SCOM table updates. + // Retrieval method: Attribute. + // System phase: IPL and SLW sysPhase. + // ========================================================================== + + // L2 + // + rc = FAPI_ATTR_GET(ATTR_L2_R_T0_EPS, NULL, attrL2RT0Eps); + if (rc) { + FAPI_ERR("FAPI_ATTR_GET(ATTR_L2_R_T0_EPS) returned error.\n"); + return rc; + } + rc = FAPI_ATTR_GET(ATTR_L2_R_T1_EPS, NULL, attrL2RT1Eps); + if (rc) { + FAPI_ERR("FAPI_ATTR_GET(ATTR_L2_R_T1_EPS) returned error.\n"); + return rc; + } + rc = FAPI_ATTR_GET(ATTR_L2_R_T2_EPS, NULL, attrL2RT2Eps); + if (rc) { + FAPI_ERR("FAPI_ATTR_GET(ATTR_L2_R_T2_EPS) returned error.\n"); + return rc; + } + rc = FAPI_ATTR_GET(ATTR_L2_W_EPS, NULL, attrL2WEps); + if (rc) { + FAPI_ERR("FAPI_ATTR_GET(ATTR_L2_W_EPS) returned error.\n"); + return rc; + } + rc = FAPI_ATTR_GET(ATTR_L2_FORCE_R_T2_EPS, NULL, attrL2ForceRT2Eps); + if (rc) { + FAPI_ERR("FAPI_ATTR_GET(ATTR_L2_FORCE_R_T2_EPS) returned error.\n"); + return rc; + } + bScomEntry = 0; + scomData = ( (uint64_t)attrL2RT0Eps <<(63-8) & (uint64_t)0x1ff<<(63-8) ) | + ( (uint64_t)attrL2RT1Eps <<(63-17) & (uint64_t)0x1ff<<(63-17) ) | + ( (uint64_t)attrL2RT2Eps <<(63-28) & (uint64_t)0x7ff<<(63-28) ) | + ( (uint64_t)attrL2WEps <<(63-35) & (uint64_t)0x07f<<(63-35) ) | + ( (uint64_t)attrL2ForceRT2Eps<<(63-36) & (uint64_t)0x001<<(63-36) ); + FAPI_DBG("scomData =0x%016llx",scomData); + for (coreId=0; coreId<=15; coreId++) { + if (attrCombGoodVec[P8_CID_EX_LOW+coreId]) { + rcLoc = p8_pore_gen_scom_fixed( + imageOut, + 2, // modeBuild=2 (SRAM) for now. Change when switch to fixed img. + (uint32_t)EX_L2_CERRS_RD_EPS_REG_0x10012814, // Scom addr. + coreId, // The core ID. + scomData, + 1, // Repl first matching Scom addr,if any, or add to EOT. + 0); // Put in general Scom section. + if (rcLoc) { + FAPI_ERR("\tUpdating SCOM NC table w/L2 Epsilon data unsuccessful.\n"); + uint32_t & RC_LOCAL = rcLoc; + FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_GEN_SCOM_ERROR); + return rc; + } + bScomEntry = 1; + } + } + if (bScomEntry) { + FAPI_INF("Updating SCOM NC table w/L2 Epsilon data successful.\n"); + } + else { + FAPI_INF("No active cores found. Did not update SCOM NC table w/L3 Epsilon data (2).\n"); + } + + // L3 + // + rc = FAPI_ATTR_GET(ATTR_L3_R_T0_EPS, NULL, attrL3RT0Eps); + if (rc) { + FAPI_ERR("FAPI_ATTR_GET(ATTR_L3_R_T0_EPS) returned error.\n"); + return rc; + } + rc = FAPI_ATTR_GET(ATTR_L3_R_T1_EPS, NULL, attrL3RT1Eps); + if (rc) { + FAPI_ERR("FAPI_ATTR_GET(ATTR_L3_R_T1_EPS) returned error.\n"); + return rc; + } + rc = FAPI_ATTR_GET(ATTR_L3_R_T2_EPS, NULL, attrL3RT2Eps); + if (rc) { + FAPI_ERR("FAPI_ATTR_GET(ATTR_L3_R_T2_EPS) returned error.\n"); + return rc; + } + rc = FAPI_ATTR_GET(ATTR_L3_FORCE_R_T2_EPS, NULL, attrL3ForceRT2Eps); + if (rc) { + FAPI_ERR("FAPI_ATTR_GET(ATTR_L3_FORCE_R_T2_EPS) returned error.\n"); + return rc; + } + rc = FAPI_ATTR_GET(ATTR_L3_W_EPS, NULL, attrL3WEps); + if (rc) { + FAPI_ERR("FAPI_ATTR_GET(ATTR_L3_W_EPS) returned error.\n"); + return rc; + } + bScomEntry = 0; + scomData = ( (uint64_t)attrL3RT0Eps <<(63-8) & (uint64_t)0x1ff<<(63-8) ) | + ( (uint64_t)attrL3RT1Eps <<(63-17) & (uint64_t)0x1ff<<(63-17) ) | + ( (uint64_t)attrL3RT2Eps <<(63-28) & (uint64_t)0x7ff<<(63-28) ) | + ( (uint64_t)attrL3ForceRT2Eps<<(63-30) & (uint64_t)0x003<<(63-30) ); + FAPI_DBG("scomData =0x%016llx",scomData); + for (coreId=0; coreId<=15; coreId++) { + if (attrCombGoodVec[P8_CID_EX_LOW+coreId]) { + rcLoc = p8_pore_gen_scom_fixed( + imageOut, + 2, // modeBuild=2 (SRAM) for now. Change when switch to fixed img. + (uint32_t)EX_L3_CERRS_RD_EPS_REG_0x10010829, // Scom addr. + coreId, // The core ID. + scomData, + 1, // Repl first matching Scom addr,if any, or add to EOT. + 0); // Put in general Scom section. + if (rcLoc) { + FAPI_ERR("\tUpdating SCOM NC table w/L3 Epsilon data (1) unsuccessful.\n"); + uint32_t & RC_LOCAL = rcLoc; + FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_GEN_SCOM_ERROR); + return rc; + } + bScomEntry = 1; + } + } + if (bScomEntry) { + FAPI_INF("Updating SCOM NC table w/L3 Epsilon data (1) successful.\n"); + } + else { + FAPI_INF("No active cores found. Did not update SCOM NC table w/L3 Epsilon data (1).\n"); + } + + bScomEntry = 0; + scomData = ( (uint64_t)attrL3WEps <<(63-6) & (uint64_t)0x07f<<(63-6) ); + FAPI_DBG("scomData =0x%016llx",scomData); + for (coreId=0; coreId<=15; coreId++) { + if (attrCombGoodVec[P8_CID_EX_LOW+coreId]) { + rcLoc = p8_pore_gen_scom_fixed( + imageOut, + 2, // modeBuild=2 (SRAM) for now. Change when switch to fixed img. + (uint32_t)EX_L3_CERRS_WR_EPS_REG_0x1001082A, // Scom addr. + coreId, // The core ID. + scomData, + 1, // Repl first matching Scom addr,if any, or add to EOT. + 0); // Put in general Scom section. + if (rcLoc) { + FAPI_ERR("\tUpdating SCOM NC table w/L3 Epsilon data (2) unsuccessful.\n"); + uint32_t & RC_LOCAL = rcLoc; + FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_GEN_SCOM_ERROR); + return rc; + } + bScomEntry = 1; + } + } + if (bScomEntry) { + FAPI_INF("Updating SCOM NC table w/L3 Epsilon data (2) successful.\n"); + } + else { + FAPI_INF("No active cores found. Did not update SCOM NC table w/L3 Epsilon data (2).\n"); + } + + // ========================================================================== + // CUSTOMIZE item: L3 BAR config register SCOM table updates. + // Retrieval method: Attribute. + // System phase: IPL and SLW sysPhase. + // ========================================================================== + + rc = FAPI_ATTR_GET(ATTR_PROC_L3_BAR1_REG, &i_target, attrL3BAR1); + if (rc) { + FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_L3_BAR1_REG) returned error.\n"); + return rc; + } + + rc = FAPI_ATTR_GET(ATTR_PROC_L3_BAR2_REG, &i_target, attrL3BAR2); + if (rc) { + FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_L3_BAR2_REG) returned error.\n"); + return rc; + } + + rc = FAPI_ATTR_GET(ATTR_PROC_L3_BAR_GROUP_MASK_REG, &i_target, attrL3BARMask); + if (rc) { + FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_L3_BAR_GROUP_MASK_REG) returned error.\n"); + return rc; + } + + bScomEntry = 0; + scomData = ( (uint64_t)attrL3BAR1); + FAPI_DBG("scomData =0x%016llx",scomData); + for (coreId=0; coreId<=15; coreId++) { + if (attrCombGoodVec[P8_CID_EX_LOW+coreId]) { + rcLoc = p8_pore_gen_scom_fixed( + imageOut, + 2, // modeBuild=2 (SRAM) for now. Change when switch to fixed img. + (uint32_t)EX_L3_BAR1_REG_0x1001080B, // Scom addr. + coreId, // The core ID. + scomData, + 1, // Repl first matching Scom addr,if any, or add to EOT. + 0); // Put in general Scom section. + if (rcLoc) { + FAPI_ERR("\tUpdating SCOM NC table w/L3 BAR data (1) unsuccessful.\n"); + uint32_t & RC_LOCAL = rcLoc; + FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_GEN_SCOM_ERROR); + return rc; + } + bScomEntry = 1; + } + } + if (bScomEntry) { + FAPI_INF("Updating SCOM NC table w/L3 BAR (1) successful.\n"); + } + else { + FAPI_INF("No active cores found. Did not update SCOM NC table w/L3 BAR data (1).\n"); + } + + bScomEntry = 0; + scomData = ( (uint64_t)attrL3BAR2); + FAPI_DBG("scomData =0x%016llx",scomData); + for (coreId=0; coreId<=15; coreId++) { + if (attrCombGoodVec[P8_CID_EX_LOW+coreId]) { + rcLoc = p8_pore_gen_scom_fixed( + imageOut, + 2, // modeBuild=2 (SRAM) for now. Change when switch to fixed img. + (uint32_t)EX_L3_BAR2_REG_0x10010813, // Scom addr. + coreId, // The core ID. + scomData, + 1, // Repl first matching Scom addr,if any, or add to EOT. + 0); // Put in general Scom section. + if (rcLoc) { + FAPI_ERR("\tUpdating SCOM NC table w/L3 BAR data (2) unsuccessful.\n"); + uint32_t & RC_LOCAL = rcLoc; + FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_GEN_SCOM_ERROR); + return rc; + } + bScomEntry = 1; + } + } + if (bScomEntry) { + FAPI_INF("Updating SCOM NC table w/L3 BAR (2) successful.\n"); + } + else { + FAPI_INF("No active cores found. Did not update SCOM NC table w/L3 BAR data (2).\n"); + } + + bScomEntry = 0; + scomData = ( (uint64_t)attrL3BARMask); + FAPI_DBG("scomData =0x%016llx",scomData); + for (coreId=0; coreId<=15; coreId++) { + if (attrCombGoodVec[P8_CID_EX_LOW+coreId]) { + rcLoc = p8_pore_gen_scom_fixed( + imageOut, + 2, // modeBuild=2 (SRAM) for now. Change when switch to fixed img. + (uint32_t)EX_L3_BAR_GROUP_MASK_REG_0x10010816, // Scom addr. + coreId, // The core ID. + scomData, + 1, // Repl first matching Scom addr,if any, or add to EOT. + 0); // Put in general Scom section. + if (rcLoc) { + FAPI_ERR("\tUpdating SCOM NC table w/L3 BAR data (3) unsuccessful.\n"); + uint32_t & RC_LOCAL = rcLoc; + FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_GEN_SCOM_ERROR); + return rc; + } + bScomEntry = 1; + } + } + if (bScomEntry) { + FAPI_INF("Updating SCOM NC table w/L3 BAR (3) successful.\n"); + } + else { + FAPI_INF("No active cores found. Did not update SCOM NC table w/L3 BAR data (3).\n"); + } + + } // End of if (i_sysPhase==1) + + + // + // Done customizing, yeah!! + // + + i_imageOut = imageOut; // Note, imageOut=i_imageIn for SLW but =i_imageOut for IPL. + sbe_xip_image_size( i_imageOut, &io_sizeImageOut); + if (i_sysPhase==0) + sizeImageMax = MAX_SEEPROM_IMAGE_SIZE; + else + sizeImageMax = sizeImageOutMax; + + FAPI_INF("XIPC: Final output image:\n "); + FAPI_INF(" location=0x%016llx\n size (actual)=%i\n size (max allowed)=%i\n ", + (uint64_t)i_imageOut, io_sizeImageOut, sizeImageMax); + FAPI_INF("XIPC: Input image (just for reference):\n "); + FAPI_INF(" location=0x%016llx\n size=%i\n ", + (uint64_t)i_imageIn, sizeImageIn); + + if (io_sizeImageOut>sizeImageMax) { + FAPI_ERR("XIPC: Final output image size (=%i) exceeds max size allowed (=%i).", + io_sizeImageOut, sizeImageMax); + uint32_t & DATA_IMG_SIZE = io_sizeImageOut; + uint32_t & DATA_IMG_SIZE_MAX = sizeImageMax; + FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_IMAGE_SIZE_MESS); + return rc; + } + return FAPI_RC_SUCCESS; } diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize.H b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize.H index 780513b27..ce00d5f7c 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize.H +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_xip_customize.H,v 1.5 2012/12/07 18:23:01 cmolsen Exp $ +// $Id: p8_xip_customize.H,v 1.6 2013/02/22 06:02:29 cmolsen Exp $ #include <fapi.H> @@ -30,15 +30,16 @@ typedef fapi::ReturnCode (*fapiGetMvpdField_FP_t) ( const fapi::MvpdRecord i_rec uint8_t * const i_pBuffer, uint32_t &io_fieldSize); -typedef fapi::ReturnCode (*p8_xip_customize_FP_t) ( const fapi::Target&, - void*, - void*, - uint32_t&, - const uint8_t, - void*, - const uint32_t, - void*, - const uint32_t ); +typedef fapi::ReturnCode (*p8_xip_customize_FP_t) ( const fapi::Target&, + void*, + void*, + uint32_t&, + const uint8_t, + const uint8_t, + void*, + const uint32_t, + void*, + const uint32_t ); extern "C" { @@ -47,28 +48,30 @@ extern "C" // Function declares. // - // Description: - // FAPI HWP entry point for p8_xip_customize(). - // proc_xip_customize() adds VPD rings to the IPL and SLW images and updates - // various vectors in the images. - // - // Parameters: - // fapi::Target &i_target: Processor chip target. + // Description: + // FAPI HWP entry point for p8_xip_customize(). + // p8_xip_customize() adds VPD rings to the IPL and SLW images and updates + // various vectors in the images. + // + // Parameters: + // fapi::Target &i_target: Processor chip target. // void *i_imageIn: Ptr to input IPL or SLW image. // void *i_imageOut: Ptr to output IPL img. (Ignored for SLW/RAM imgs.) // uint32_t &io_sizeImageOut: In: Max size of IPL/SRAM img. Out: Final size. // uint8_t i_sysPhase: 0: IPL 1: SLW + // uint8_t i_modeBuild: 0: HB/IPL 1: PHYP/Rebuild 2: SRAM // void *i_buf1: Temp buffer1 for dexed RS4 ring. Caller allocs/frees. // uint32_t i_sizeBuf1: Size of buf1. // void *i_buf2: Temp buffer2 for WF ring. Caller allocs/frees. // uint32_t i_sizeBuf22 Size of buf2. - fapi::ReturnCode p8_xip_customize( const fapi::Target &i_target, - void *i_imageIn, - void *i_imageOut, - uint32_t &io_sizeImageOut, - const uint8_t i_sysPhase, - void *i_buf1, - const uint32_t i_sizeBuf1, - void *i_buf2, - const uint32_t i_sizeBuf2 ); + fapi::ReturnCode p8_xip_customize( const fapi::Target &i_target, + void *i_imageIn, + void *i_imageOut, + uint32_t &io_sizeImageOut, + const uint8_t i_sysPhase, + const uint8_t i_modeBuild, + void *i_buf1, + const uint32_t i_sizeBuf1, + void *i_buf2, + const uint32_t i_sizeBuf2 ); } diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize_errors.xml b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize_errors.xml index eac3d2f2c..20b727be0 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize_errors.xml +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize_errors.xml @@ -64,6 +64,21 @@ </hwpError> <!-- *********************************************************************** --> <hwpError> + <rc>RC_PROC_XIPC_BUF_PTR_ERROR</rc> + <description>Supplied buffer(s) is invalid.</description> + <ffdc>DATA_BUF1_PTR</ffdc> + <ffdc>DATA_BUF2_PTR</ffdc> +</hwpError> +<!-- *********************************************************************** --> +<hwpError> + <rc>RC_PROC_XIPC_BUF_SIZE_NOT_FIXED</rc> + <description>Supplied buffer size(s) differs from agreed upon fixed ring buffer size.</description> + <ffdc>DATA_BUF1_SIZE</ffdc> + <ffdc>DATA_BUF2_SIZE</ffdc> + <ffdc>DATA_BUF_SIZE_FIXED</ffdc> +</hwpError> +<!-- *********************************************************************** --> +<hwpError> <rc>RC_PROC_XIPC_IMAGE_UPDATE_ERROR</rc> <description>Error associated with updating mainstore image.</description> <ffdc>RC_LOCAL</ffdc> |