Hacks for strict-aliasing violations in procedures.

Change-Id: Ibaf2a3cc2f8386c8bdb27bf95288cb2518112f49
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4040
Reviewed-by: MIKE J. JONES <mjjones@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

1 files changed, 37 insertions, 37 deletions

diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C
index 52ce97be3..e3cd8e8d4 100644
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C
+++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C
@@ -35,7 +35,7 @@
 //                  Other usages:
 //
 /* *! COMMENTS :    - Start file: p7p_pore_api.c                                */
-//                  - The DYNAMIC_RAM_TABLE_PPD was dropped in v1.12 of this 
+//                  - The DYNAMIC_RAM_TABLE_PPD was dropped in v1.12 of this
 //                    code. See v1.12 for explanation and code implementation.
 //
 /*------------------------------------------------------------------------------*/
@@ -52,14 +52,14 @@
 // i_regName -     unswizzled enum SPR value (NOT a name)
 // i_regData -     data to write
 // i_coreIndex -   core ID
-// i_threadIndex - thread to operate on, API changes thread num to 0 for shared 
-//                 SPRs, except for HRMOR which is always done on thread 3 to be 
+// i_threadIndex - thread to operate on, API changes thread num to 0 for shared
+//                 SPRs, except for HRMOR which is always done on thread 3 to be
 //                 the last SPR
 */
 uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
                               uint8_t   i_modeBuild,
-                              uint32_t  i_regName, 
-                              uint64_t  i_regData, 
+                              uint32_t  i_regName,
+                              uint64_t  i_regData,
                               uint32_t  i_coreId,   // [0:15]
                               uint32_t  i_threadId)
 {
@@ -78,7 +78,7 @@ uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
   SbeXipItem    xipTocItem;
   RamTableEntry ramEntryThis, *ramEntryNext;
   uint32_t  sprSwiz=0;
-  
+
   // -------------------------------------------------------------------------
   // Validate Ramming parameters.
   //
@@ -117,7 +117,7 @@ uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
   if (rcLoc)
     return IMGBUILD_ERR_RAM_INVALID_PARM;
   rcLoc = 0;
-  
+
   // -------------------------------------------------------------------------
   // Get pointer to SLW section where Ram table resides
   // NB! Only needed for modeBuild==2 !
@@ -126,11 +126,11 @@ uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
       i_modeBuild==P8_SLW_MODEBUILD_REBUILD)  {  // Fixed image.
     // CMO-20130114: Remove this asap. Only for fixed img transition. - Begin
     //               hostSlwSectionFixed isn't needed for modeBuild=0,1 !
-    hostSlwSectionFixed = (void*)( (uintptr_t)io_image + 
+    hostSlwSectionFixed = (void*)( (uintptr_t)io_image +
                                    FIXED_SLW_IMAGE_SIZE -
                                    FIXED_FFDC_SECTION_SIZE -
                                    FIXED_SLW_SECTION_SIZE );
-    // We may want to continue calling this because it would be practical to 
+    // We may want to continue calling this because it would be practical to
     // crosscheck the section size.  Though, the offset is NOT reliable !
     rc = sbe_xip_get_section( io_image, SBE_XIP_SECTION_SLW, &xipSection);
     if (rc)  {
@@ -165,7 +165,7 @@ uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
     return IMGBUILD_ERR_RAM_HDRS_NOT_SYNCED;
   }
   if (xipSection.iv_size!=FIXED_SLW_SECTION_SIZE)  {
-    MY_ERR("Fixed SLW table size in *.H header file differs from SLW section size in image.\n"); 
+    MY_ERR("Fixed SLW table size in *.H header file differs from SLW section size in image.\n");
     MY_ERR("Check code or image version.\n");
     return IMGBUILD_ERR_RAM_HDRS_NOT_SYNCED;
   }
@@ -180,7 +180,7 @@ uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
   MY_INF("\tThread ID = %i\n",i_threadId);
   MY_INF("Image validation and size checks - OK\n");
   MY_INF("\tSLW section size=  %i\n",xipSection.iv_size);
-  
+
   // -------------------------------------------------------------------------
   // Locate RAM vector and locate RAM table associated with "This" core ID.
   //
@@ -211,7 +211,7 @@ uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
       bNewTable = 0;
     }
     else  {
-      hostRamTableThis = (void*)( (uintptr_t)hostSlwRamSection + 
+      hostRamTableThis = (void*)( (uintptr_t)hostSlwRamSection +
                                   SLW_RAM_TABLE_SPACE_PER_CORE*i_coreId );
       bNewTable = 1;
     }
@@ -225,8 +225,8 @@ uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
     hostRamEntryThis = hostRamTableThis;
     if (i_modeBuild==P8_SLW_MODEBUILD_SRAM)  {
       // Update RAM vector (since it is currently NULL)
-      *((uint64_t*)hostRamVector + i_coreId) = 
-                           myRev64( xipSlwRamSection + 
+      *((uint64_t*)hostRamVector + i_coreId) =
+                           myRev64( xipSlwRamSection +
                                     SLW_RAM_TABLE_SPACE_PER_CORE*i_coreId );
     }
     bEntryEnd = 1;
@@ -285,7 +285,7 @@ uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
                           ( ((uint32_t)headerType) << RAM_HEADER_TYPE_START_C   & RAM_HEADER_TYPE_MASK_C )   |
                           (            i_regName   << RAM_HEADER_SPRN_START_C   & RAM_HEADER_SPRN_MASK_C )   |
                           (            i_threadId  << RAM_HEADER_THREAD_START_C & RAM_HEADER_THREAD_MASK_C );
-    // ...do the SPR instr 
+    // ...do the SPR instr
     sprSwiz = i_regName>>5 | (i_regName & 0x0000001f)<<5;
     if (sprSwiz!=SLW_SPR_REGS[iReg].swizzled)  {
       MY_ERR("Inconsistent swizzle rules implemented. Check code. Dumping data.\n");
@@ -328,7 +328,7 @@ uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
 
 /*
 // io_image -    Pointer to SLW image.
-// i_modeBuild - 0: HB/IPL mode, 1: PHYP/Rebuild mode, 2: SRAM mode. 
+// i_modeBuild - 0: HB/IPL mode, 1: PHYP/Rebuild mode, 2: SRAM mode.
 // i_scomAddr -  Scom address.
 // i_coreId -    The core ID [0:15].
 // i_scomData -  Data to write to scom register.
@@ -338,7 +338,7 @@ uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
 uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
                             uint8_t    i_modeBuild,
                             uint32_t   i_scomAddr,
-                            uint32_t   i_coreId,     // [0:15] 
+                            uint32_t   i_coreId,     // [0:15]
                             uint64_t   i_scomData,
                             uint32_t   i_operation,  // [0:5]
                             uint32_t   i_section)    // [0,1,2]
@@ -359,7 +359,7 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
   SbeXipSection xipSection;
   SbeXipItem    xipTocItem;
   PoreInlineContext ctx;
-  
+
   // -------------------------------------------------------------------------
   // Validate Scom parameters.
   //
@@ -388,7 +388,7 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
   if (rcLoc)
     return IMGBUILD_ERR_SCOM_INVALID_PARM;
   rcLoc = 0;
- 
+
   // -------------------------------------------------------------------------
   // Get pointer to SLW section where Scom table resides
   // NB! Only needed for modeBuild==2 !
@@ -397,11 +397,11 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
       i_modeBuild==P8_SLW_MODEBUILD_REBUILD)  {  // Fixed image.
     // CMO-20130114: Remove this asap. Only for fixed img transition. - Begin
     //               hostSlwSectionFixed isn't needed for modeBuild=0,1 !
-    hostSlwSectionFixed = (void*)( (uintptr_t)io_image + 
+    hostSlwSectionFixed = (void*)( (uintptr_t)io_image +
                                    FIXED_SLW_IMAGE_SIZE -
                                    FIXED_FFDC_SECTION_SIZE -
                                    FIXED_SLW_SECTION_SIZE );
-    // We may want to continue calling this because it would be practical to 
+    // We may want to continue calling this because it would be practical to
     // crosscheck the section size.  Though, the offset is NOT reliable !
     rc = sbe_xip_get_section( io_image, SBE_XIP_SECTION_SLW, &xipSection);
     if (rc)  {
@@ -446,9 +446,9 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
   MY_INF("\tCore ID   = %i\n",i_coreId);
   MY_INF("Image validation and size checks - OK\n");
   MY_INF("\tSLW section size=  %i\n",xipSection.iv_size);
-  
+
   // -------------------------------------------------------------------------
-  // Locate Scom vector according to i_section and then locate Scom table 
+  // Locate Scom vector according to i_section and then locate Scom table
   //   associated with "This" core ID.
   //
   if (i_modeBuild==P8_SLW_MODEBUILD_IPL ||
@@ -531,7 +531,7 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
   //   doesn't include NOP entries.)
   // - If no NOP found, insert at first RET.
   //
-  
+
   // First, create search strings for addr, nop and ret.
   // Note, the following IIS will also be used in case of
   // - i_operation==append
@@ -555,7 +555,7 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
     MY_ERR("pore_NOP generated rc = %d", ctx.error);
     return IMGBUILD_ERR_PORE_INLINE_ASM;
   }
-  
+
   // Second, search for addr and nop in relevant coreId table until first RET.
   // Note:
   // - We go through ALL entries until first RET instr. We MUST find a RET instr,
@@ -563,25 +563,25 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
   // - Count number of entries and check for overrun, though we'll continue
   //   searching until we find an RET. (Should be improved.)
   // - The STI(+SCOM_addr) opcode is in the 2nd word of the Scom entry.
-  // - For an append operation, if a NOP is found (before a RET obviously), the 
+  // - For an append operation, if a NOP is found (before a RET obviously), the
   //   SCOM is replacing that NNNN sequence.
   hostScomEntryNext = hostScomTableThis;
   MY_DBG("hostScomEntryNext (addr): 0x%016llx\n ",(uint64_t)hostScomEntryNext);
-  while (*(uint32_t*)hostScomEntryNext!=*(uint32_t*)bufRET)  {
+  while (memcmp(hostScomEntryNext, bufRET, sizeof(uint32_t))) {
     entriesCount++;
     MY_DBG("Number of SCOM entries: %i\n ",entriesCount);
     if (*((uint32_t*)bufIIS+1)==*((uint32_t*)hostScomEntryNext+1) && entriesMatch==0)  {// +1 skips 1st word in Scom entry (which loads the PC in an LS operation.)
       hostScomEntryMatch = hostScomEntryNext;
       entriesMatch++;
     }
-    if (*(uint32_t*)hostScomEntryNext==*(uint32_t*)bufNOP && entriesNOP==0)  {
+    if ((0 == memcmp(hostScomEntryNext, bufNOP, sizeof(uint32_t))) && entriesNOP==0)  {
       hostScomEntryNOP = hostScomEntryNext;
       entriesNOP++;
     }
     hostScomEntryNext = (void*)((uintptr_t)hostScomEntryNext + XIPSIZE_SCOM_ENTRY);
   }
   hostScomEntryRET = hostScomEntryNext; // The last EntryNext is always the first RET.
-  
+
   switch (i_section)  {
   case P8_SCOM_SECTION_NC:
     if (entriesCount>=SLW_MAX_SCOMS_NC)  {
@@ -657,7 +657,7 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
       i_operation, P8_PORE_SCOM_FIRST_OP, P8_PORE_SCOM_LAST_OP);
     return IMGBUILD_ERR_SCOM_INVALID_PARM;
   }
-  
+
   // -------------------------------------------------------------------------
   // Assuming pre-allocated Scom table (after pre-allocated Ram table):
   // - Table is pre-filled with RNNN ISS.
@@ -666,7 +666,7 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
   // - Remember to check for more than SLW_MAX_SCOMS_NC entries!
   switch (operation)  {
 
-  case P8_PORE_SCOM_APPEND:  // Append a Scom at first occurring NNNN or RNNN,  
+  case P8_PORE_SCOM_APPEND:  // Append a Scom at first occurring NNNN or RNNN,
     if (hostScomEntryNOP)  {
       // ... replace the NNNN
       MY_INF("Append at NOP\n");
@@ -701,7 +701,7 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
       MY_INF("Replace existing Scom w/NOPs\n");
       memcpy(hostScomEntryMatch,(void*)bufIIS,XIPSIZE_SCOM_ENTRY);
     }
-    else  { 
+    else  {
       // do nothing, and assume everything is fine, since we did no damage.
     }
     break;
@@ -709,10 +709,10 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
     if (hostScomEntryMatch)  {
       // ... do an OR on the data (which is the 2nd DWord in the entry)
       MY_INF("Overlay existing Scom - OR case\n");
-      *((uint64_t*)hostScomEntryMatch+1) = 
+      *((uint64_t*)hostScomEntryMatch+1) =
         *((uint64_t*)hostScomEntryMatch+1) | myRev64(i_scomData);
     }
-    else  { 
+    else  {
       MY_ERR("No Scom entry found to do OR operation with.\n");
       return IMGBUILD_ERR_SCOM_ENTRY_NOT_FOUND;
     }
@@ -721,10 +721,10 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
     if (hostScomEntryMatch)  {
       // ... do an AND on the data (which is the 2nd DWord in the entry)
       MY_INF("Overlay existing Scom - AND case\n");
-      *((uint64_t*)hostScomEntryMatch+1) = 
+      *((uint64_t*)hostScomEntryMatch+1) =
         *((uint64_t*)hostScomEntryMatch+1) & myRev64(i_scomData);
     }
-    else  { 
+    else  {
       MY_ERR("No Scom entry found to do AND operation with.\n");
       return IMGBUILD_ERR_SCOM_ENTRY_NOT_FOUND;
     }
@@ -740,7 +740,7 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
   default:
     MY_ERR("Impossible value of operation (=%i). Check code.\n",operation);
     return IMGBUILD_ERR_CHECK_CODE;
-  
+
   }  // End of switch(operation)
 
   return rc;