diff options
| author | Matt Ploetz <maploetz@us.ibm.com> | 2014-03-10 13:00:56 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-03-13 14:13:59 -0500 |
| commit | fd579042a3d2f4a865f0f3c6c329e7948bc02b4b (patch) | |
| tree | 5945ee7e1e17f36cd6e6c79c712859cdd798a0e5 /src/usr/hwpf/hwp/activate_powerbus/proc_build_smp | |
| parent | 28d4676d9b0928a81717bc636a789c0383f80568 (diff) | |
| download | talos-hostboot-fd579042a3d2f4a865f0f3c6c329e7948bc02b4b.tar.gz talos-hostboot-fd579042a3d2f4a865f0f3c6c329e7948bc02b4b.zip | |
INITPROC: Hostboot - SW249242 RAS update Horton 2 and 3/8
Change-Id: Ib82fe45e26959586fb3b2a7c527f29a2c6396bc7
CQ: SW249242
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9450
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp/activate_powerbus/proc_build_smp')
13 files changed, 2085 insertions, 1261 deletions
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C index f7955914e..44dd7fdc0 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp.C,v 1.13 2013/11/13 01:44:13 jmcgill Exp $ +// $Id: proc_build_smp.C,v 1.15 2014/02/26 18:13:01 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp.C,v $ //------------------------------------------------------------------------------ // *| @@ -39,12 +39,13 @@ //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ -#include "proc_build_smp.H" -#include "proc_build_smp_epsilon.H" -#include "proc_build_smp_fbc_nohp.H" -#include "proc_build_smp_fbc_ab.H" -#include "proc_build_smp_fbc_cd.H" -#include "proc_build_smp_adu.H" +#include <proc_build_smp.H> +#include <proc_build_smp_epsilon.H> +#include <proc_build_smp_fbc_nohp.H> +#include <proc_build_smp_fbc_ab.H> +#include <proc_build_smp_fbc_cd.H> +#include <proc_build_smp_adu.H> + extern "C" { @@ -72,8 +73,10 @@ extern "C" // invalid, // RC_PROC_BUILD_SMP_CORE_FLOOR_FREQ_RATIO_ERR if cache/nest frequency // ratio is unsupported, +// RC_PROC_BUILD_SMP_CORE_FREQ_RANGE_ERR if invalid relationship exists +// between ceiling/nominal/floor core frequency attributes, // RC_PROC_FAB_SMP_ASYNC_SAFE_MODE_ATTR_ERR if attribute value is -// invalid, +// invalid, // else error //------------------------------------------------------------------------------ fapi::ReturnCode proc_build_smp_process_system( @@ -89,8 +92,6 @@ fapi::ReturnCode proc_build_smp_process_system( do { - - // ToDO: link to attribute if PB AVP mode support is needed io_smp.avp_mode = false; // get PB frequency attribute @@ -162,9 +163,9 @@ fapi::ReturnCode proc_build_smp_process_system( if (!((io_smp.freq_core_ceiling >= io_smp.freq_core_nom) && (io_smp.freq_core_nom >= io_smp.freq_core_floor))) { - const uint32_t& CEILING = io_smp.freq_core_ceiling; - const uint32_t& NOM = io_smp.freq_core_nom; - const uint32_t& FLOOR = io_smp.freq_core_floor; + const uint32_t& FREQ_CORE_CEILING = io_smp.freq_core_ceiling; + const uint32_t& FREQ_CORE_NOM = io_smp.freq_core_nom; + const uint32_t& FREQ_CORE_FLOOR = io_smp.freq_core_floor; FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_CORE_FREQ_RANGE_ERR); break; @@ -232,11 +233,11 @@ fapi::ReturnCode proc_build_smp_process_system( { case 1: io_smp.pump_mode = PROC_FAB_SMP_PUMP_MODE1; - FAPI_DBG("proc_build_smp_process_system: ATTR_FABRIC_PROC_PUMP_MODE = NODAL_IS_CHIP_GROUP_IS_GROUP"); + FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_FABRIC_PUMP_MODE = NODAL_IS_CHIP_GROUP_IS_GROUP"); break; case 2: io_smp.pump_mode = PROC_FAB_SMP_PUMP_MODE2; - FAPI_DBG("proc_build_smp_process_system: ATTR_FABRIC_PROC_PUMP_MODE = NODAL_AND_GROUP_IS_GROUP"); + FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_FABRIC_PUMP_MODE = NODAL_AND_GROUP_IS_GROUP"); break; default: FAPI_ERR("proc_build_smp_process_system: Invalid fabric pump mode attribute value 0x%02X", @@ -424,11 +425,11 @@ fapi::ReturnCode proc_build_smp_process_system( { case 0: io_smp.async_safe_mode = false; - FAPI_DBG("proc_build_smp_process_system: ATTR_FABRIC_PROC_ASYNC_SAFE_MODE = false"); + FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_FABRIC_ASYNC_SAFE_MODE = false"); break; case 1: io_smp.async_safe_mode = true; - FAPI_DBG("proc_build_smp_process_system: ATTR_FABRIC_PROC_ASYNC_SAFE_MODE = true"); + FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_FABRIC_ASYNC_SAFE_MODE = true"); break; default: FAPI_ERR("proc_build_smp_process_system: Invalid fabric async safe mode attribute value 0x%02X", @@ -708,7 +709,7 @@ fapi::ReturnCode proc_build_smp_process_chip( nx_enabled); if (!rc.ok()) { - FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_PROC_NX_ENABLE"); + FAPI_ERR("proc_build_smp_process_chip: Error querying ATTR_PROC_NX_ENABLE"); break; } @@ -718,7 +719,7 @@ fapi::ReturnCode proc_build_smp_process_chip( x_enabled); if (!rc.ok()) { - FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_PROC_X_ENABLE"); + FAPI_ERR("proc_build_smp_process_chip: Error querying ATTR_PROC_X_ENABLE"); break; } @@ -728,7 +729,7 @@ fapi::ReturnCode proc_build_smp_process_chip( a_enabled); if (!rc.ok()) { - FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_PROC_A_ENABLE"); + FAPI_ERR("proc_build_smp_process_chip: Error querying ATTR_PROC_A_ENABLE"); break; } @@ -738,7 +739,7 @@ fapi::ReturnCode proc_build_smp_process_chip( pcie_enabled); if (!rc.ok()) { - FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_PROC_PCIE_ENABLE"); + FAPI_ERR("proc_build_smp_process_chip: Error querying ATTR_PROC_PCIE_ENABLE"); break; } @@ -773,7 +774,7 @@ fapi::ReturnCode proc_build_smp_process_chip( // are valid, // RC_PROC_BUILD_SMP_MASTER_DESIGNATION_ERR if node/system master // error is detected based on chip state and input paramters, -// RC_PROC_BUILD_SMP_INVALID_OPERATION if an unsupported operation +// RC_PROC_BUILD_SMP_INVALID_OPERATION_ERR if an unsupported operation // is specified // RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if shadow registers are not // equivalent, @@ -887,6 +888,7 @@ fapi::ReturnCode proc_build_smp_set_master_config( if (rc.ok() && error) { FAPI_ERR("proc_build_smp_set_master_config: Node/system master designation error"); + const fapi::Target& TARGET = io_smp_chip.chip->this_chip; const uint8_t& OP = i_op; const bool& MASTER_CHIP_SYS_CURR = io_smp_chip.master_chip_sys_curr; const bool& MASTER_CHIP_NODE_CURR = io_smp_chip.master_chip_node_curr; @@ -918,7 +920,7 @@ fapi::ReturnCode proc_build_smp_set_master_config( // fabric node/chip IDs are detected, // RC_PROC_BUILD_SMP_MASTER_DESIGNATION_ERR if node/system master // is detected based on chip state and input paramters, -// RC_PROC_BUILD_SMP_INVALID_OPERATION if an unsupported operation +// RC_PROC_BUILD_SMP_INVALID_OPERATION_ERR if an unsupported operation // is specified // RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if shadow registers are not // equivalent, @@ -966,6 +968,8 @@ fapi::ReturnCode proc_build_smp_insert_chip( if (!ret.second) { FAPI_ERR("proc_build_smp_insert_chip: Error encountered adding node to SMP"); + const fapi::Target & TARGET = io_smp_chip.chip->this_chip; + const proc_fab_smp_node_id & NODE_ID = node_id; FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_NODE_ADD_INTERNAL_ERR); break; @@ -983,8 +987,10 @@ fapi::ReturnCode proc_build_smp_insert_chip( if (p_iter != io_smp.nodes[node_id].chips.end()) { FAPI_ERR("proc_build_smp_insert_chip: Duplicate fabric node ID / chip ID found"); - const uint8_t& NODE_ID = node_id; - const uint8_t& CHIP_ID = chip_id; + const fapi::Target & TARGET1 = io_smp_chip.chip->this_chip; + const fapi::Target & TARGET2 = p_iter->second.chip->this_chip; + const proc_fab_smp_node_id & NODE_ID = node_id; + const proc_fab_smp_chip_id & CHIP_ID = chip_id; FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_DUPLICATE_FABRIC_ID_ERR); break; @@ -998,7 +1004,7 @@ fapi::ReturnCode proc_build_smp_insert_chip( io_smp); if (!rc.ok()) { - FAPI_ERR("proc_build_smp_insert_chip: Error from proc_fab_smp_set_master_config"); + FAPI_ERR("proc_build_smp_insert_chip: Error from proc_build_smp_set_master_config"); break; } @@ -1034,10 +1040,18 @@ fapi::ReturnCode proc_build_smp_insert_chip( // do not specify a new fabric system master, // RC_PROC_BUILD_SMP_MASTER_DESIGNATION_ERR if node/system master // error is detected based on chip state and input paramters, -// RC_PROC_BUILD_SMP_INVALID_OPERATION if an unsupported operation +// RC_PROC_BUILD_SMP_INVALID_OPERATION_ERR if an unsupported operation // is specified // RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if shadow registers are not // equivalent, +// RC_PROC_BUILD_SMP_AX_PARTIAL_GOOD_ERR if partial good attribute +// state does not allow for action on target, +// RC_PROC_BUILD_SMP_PCIE_PARTIAL_GOOD_ERR if partial good attribute +// state does not allow for action on target, +// RC_PROC_BUILD_SMP_LINK_TARGET_TYPE_ERR if link target type is +// unsupported, +// RC_PROC_BUILD_SMP_INVALID_TOPOLOGY if specified fabric topology +// is illegal, // else error //------------------------------------------------------------------------------ fapi::ReturnCode proc_build_smp_process_chips( @@ -1047,6 +1061,7 @@ fapi::ReturnCode proc_build_smp_process_chips( { // return code fapi::ReturnCode rc; + uint32_t rc_ecmd = 0; // mark function entry FAPI_DBG("proc_build_smp_process_chips: Start"); @@ -1088,6 +1103,7 @@ fapi::ReturnCode proc_build_smp_process_chips( break; } + // ensure that new master was designated if (!io_smp.master_chip_curr_set) { FAPI_ERR("proc_build_smp_process_chips: No system master specified!"); @@ -1098,12 +1114,15 @@ fapi::ReturnCode proc_build_smp_process_chips( break; } + // based on master designation, and operation phase, + // determine whether each chip will be quiesced as a result + // of switch activity for (n_iter = io_smp.nodes.begin(); - (n_iter != io_smp.nodes.end()) && (rc.ok()); + n_iter != io_smp.nodes.end(); n_iter++) { for (p_iter = n_iter->second.chips.begin(); - (p_iter != n_iter->second.chips.end()) && (rc.ok()); + p_iter != n_iter->second.chips.end(); p_iter++) { if (((i_op == SMP_ACTIVATE_PHASE1) && @@ -1119,10 +1138,210 @@ fapi::ReturnCode proc_build_smp_process_chips( } } } - if (!rc.ok()) + + // check that fabric topology is logically valid + // 1) in a given node, all chips are connected to every other + // chip in the node, by an X bus + // 2) each chip is connected to its partner chip (with same chip id) + // in every other node, by an A bus + + // build set of all valid node ids in system + FAPI_DBG("proc_build_smp_process_chips: Checking fabric topology"); + ecmdDataBufferBase node_ids_in_system(PROC_FAB_SMP_NUM_NODE_IDS); + for (n_iter = io_smp.nodes.begin(); + n_iter != io_smp.nodes.end(); + n_iter++) { + FAPI_DBG("proc_build_smp_process_chips: Adding n%d", n_iter->first); + rc_ecmd |= node_ids_in_system.setBit(n_iter->first); + } + if (rc_ecmd) + { + FAPI_ERR("proc_build_smp_process_chips: Error 0x%x forming system node ID set data buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); break; } + + // iterate over all nodes + for (n_iter = io_smp.nodes.begin(); + n_iter != io_smp.nodes.end(); + n_iter++) + { + // build set of all valid chip ids in node + ecmdDataBufferBase chip_ids_in_node(PROC_FAB_SMP_NUM_CHIP_IDS); + for (p_iter = n_iter->second.chips.begin(); + p_iter != n_iter->second.chips.end(); + p_iter++) + { + FAPI_DBG("proc_build_smp_process_chips: Adding n%d:p%d", + n_iter->first, p_iter->first); + rc_ecmd |= chip_ids_in_node.setBit(p_iter->first); + } + if (rc_ecmd) + { + FAPI_ERR("proc_build_smp_process_chips: Error 0x%x forming node %d chip ID set data buffer", + rc_ecmd, n_iter->first); + rc.setEcmdError(rc_ecmd); + break; + } + + // iterate over all chips in current node + for (p_iter = n_iter->second.chips.begin(); + p_iter != n_iter->second.chips.end(); + p_iter++) + { + FAPI_DBG("proc_build_smp_process_chips: Processing links for n%d:p%d", + n_iter->first, p_iter->first); + std::vector<fapi::Target *> x_link_targets; + x_link_targets.push_back(&(p_iter->second.chip->x0_chip)); + x_link_targets.push_back(&(p_iter->second.chip->x1_chip)); + x_link_targets.push_back(&(p_iter->second.chip->x2_chip)); + x_link_targets.push_back(&(p_iter->second.chip->x3_chip)); + + std::vector<fapi::Target *> a_link_targets; + a_link_targets.push_back(&(p_iter->second.chip->a0_chip)); + a_link_targets.push_back(&(p_iter->second.chip->a1_chip)); + a_link_targets.push_back(&(p_iter->second.chip->a2_chip)); + + // process X-connected chips + ecmdDataBufferBase x_connected_chip_ids(PROC_FAB_SMP_NUM_CHIP_IDS); + for (std::vector<fapi::Target*>::iterator l = x_link_targets.begin(); + l != x_link_targets.end(); + l++) + { + bool link_is_enabled; + proc_fab_smp_node_id dest_node_id; + proc_fab_smp_chip_id dest_chip_id; + rc = proc_build_smp_query_link_state(p_iter->second, + (l - x_link_targets.begin()), + *l, + link_is_enabled, + dest_node_id, + dest_chip_id); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_process_chips: Error from proc_build_smp_query_link_state (X)"); + break; + } + + if (link_is_enabled) + { + rc_ecmd |= x_connected_chip_ids.writeBit( + (uint8_t) dest_chip_id, + ((((uint8_t) dest_node_id) == n_iter->first)?(1):(0))); + if (rc_ecmd) + { + FAPI_ERR("proc_build_smp_process_chips: Error 0x%x writing n%d:p%d X connected chip ID set data buffer", + rc_ecmd, n_iter->first, p_iter->first); + rc.setEcmdError(rc_ecmd); + break; + } + + FAPI_DBG("proc_build_smp_process_chips: n%d:p%d X%d -> n%d:p%d", + n_iter->first, p_iter->first, (l - x_link_targets.begin()), + dest_node_id, dest_chip_id); + } + } + if (!rc.ok()) + { + break; + } + + // process A-connected chips + ecmdDataBufferBase a_connected_node_ids(PROC_FAB_SMP_NUM_NODE_IDS); + for (std::vector<fapi::Target*>::iterator l = a_link_targets.begin(); + l != a_link_targets.end(); + l++) + { + bool link_is_enabled; + proc_fab_smp_node_id dest_node_id; + proc_fab_smp_chip_id dest_chip_id; + rc = proc_build_smp_query_link_state(p_iter->second, + (l - a_link_targets.begin()), + *l, + link_is_enabled, + dest_node_id, + dest_chip_id); + if (!rc.ok()) + { + FAPI_ERR("proc_build_smp_process_chips: Error from proc_build_smp_query_link_state (A)"); + break; + } + + if (link_is_enabled) + { + rc_ecmd |= a_connected_node_ids.writeBit( + (uint8_t) dest_node_id, + ((((uint8_t) dest_chip_id) == p_iter->first)?(1):(0))); + if (rc_ecmd) + { + FAPI_ERR("proc_build_smp_process_chips: Error 0x%x writing n%d:p%d A connected node ID set data buffer", + rc_ecmd, n_iter->first, p_iter->first); + rc.setEcmdError(rc_ecmd); + break; + } + + FAPI_DBG("proc_build_smp_process_chips: n%d:p%d A%d -> n%d:p%d", + n_iter->first, p_iter->first, (l - a_link_targets.begin()), + dest_node_id, dest_chip_id); + } + } + if (!rc.ok()) + { + break; + } + + // add IDs associated with current chip, to make direct set comparison easy + FAPI_DBG("proc_build_smp_process_chips: Checking connectivity for n%d:p%d", + n_iter->first, p_iter->first); + rc_ecmd |= a_connected_node_ids.setBit(n_iter->first); + rc_ecmd |= x_connected_chip_ids.setBit(p_iter->first); + if (rc_ecmd) + { + FAPI_ERR("proc_build_smp_process_chips: Error 0x%x writing n%d:p%d connected ID set data buffer (self)", + rc_ecmd, n_iter->first, p_iter->first); + rc.setEcmdError(rc_ecmd); + break; + } + + // compare ID sets, exit if they don't match + bool internode_set_match = (node_ids_in_system == a_connected_node_ids); + bool intranode_set_match = (chip_ids_in_node == x_connected_chip_ids); + if (!internode_set_match || + !intranode_set_match) + { + FAPI_ERR("proc_build_smp_process_chips: Invalid fabric topology detected!"); + if (!intranode_set_match) + { + FAPI_ERR("proc_build_smp_process_chips: Target %s is not fully connected (X) to all other chips in its node", + p_iter->second.chip->this_chip.toEcmdString()); + } + if (!internode_set_match) + { + FAPI_ERR("proc_build_smp_process_chips: Target %s is not fully connected (A) to all other nodes", + p_iter->second.chip->this_chip.toEcmdString()); + } + + const fapi::Target& TARGET = p_iter->second.chip->this_chip; + const bool& A_CONNECTIONS_OK = internode_set_match; + const ecmdDataBufferBase& A_CONNECTED_NODE_IDS = a_connected_node_ids; + const bool& X_CONNECTIONS_OK = intranode_set_match; + const ecmdDataBufferBase& X_CONNECTED_NODE_IDS = x_connected_chip_ids; + FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_INVALID_TOPOLOGY); + break; + } + } + if (!rc.ok()) + { + break; + } + } + if (!rc.ok()) + { + break; + } + } while(0); // mark function exit diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H index f7e24d68a..980df00f1 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp.H,v 1.13 2013/11/13 01:41:53 jmcgill Exp $ +// $Id: proc_build_smp.H,v 1.14 2014/02/23 21:41:06 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp.H,v $ //------------------------------------------------------------------------------ // *| @@ -57,8 +57,6 @@ // *! (switch A/B) // *! //------------------------------------------------------------------------------ -// *! TODO:: support for manufacturing AVP mode configurations -//------------------------------------------------------------------------------ #ifndef _PROC_BUILD_SMP_H_ #define _PROC_BUILD_SMP_H_ @@ -69,8 +67,8 @@ #include <vector> #include <map> #include <fapi.H> -#include "proc_fab_smp.H" -#include "p8_scom_addresses.H" +#include <proc_fab_smp.H> +#include <p8_scom_addresses.H> //------------------------------------------------------------------------------ @@ -120,6 +118,7 @@ struct proc_build_smp_proc_chip proc_fab_smp_node_id f1_node_id; }; + // structure to represent fabric connectivty & properites for a single chip // in the SMP topology struct proc_build_smp_chip @@ -158,6 +157,23 @@ struct proc_build_smp_node proc_fab_smp_node_id node_id; }; +// structure to encapsulate system epsilon configuration +struct proc_build_smp_eps_cfg +{ + // epsilon configuration inputs + bool gb_positive; + uint8_t gb_percentage; + proc_fab_smp_eps_table_type table_type; + // target epsilon values + uint32_t r_t0; // read, tier0 (np) + uint32_t r_t1; // read, tier1 (gp) + uint32_t r_t2; // read, tier2 (sp) + uint32_t r_f; // read, foreign (f) + uint32_t w_t2; // write, tier2 (sp) + uint32_t w_f; // write, foreign (f) + uint32_t p; // pre +}; + // core/nest frequency ratio cutpoints (epsilon) enum proc_build_smp_core_ratio { @@ -170,8 +186,6 @@ enum proc_build_smp_core_ratio }; // core floor/nest frequency ratio cutpoints (CPU delay) -const uint8_t PROC_BUILD_SMP_CPU_DELAY_NUM_SETPOINTS = 13; - enum proc_build_smp_cpu_delay { PROC_BUILD_SMP_CPU_DELAY_4800_2400 = 0, @@ -189,23 +203,6 @@ enum proc_build_smp_cpu_delay PROC_BUILD_SMP_CPU_DELAY_2400_2400 = 12 }; -// structure to encapsulate system epsilon configuration -struct proc_build_smp_eps_cfg -{ - // epsilon configuration inputs - bool gb_positive; - uint8_t gb_percentage; - proc_fab_smp_eps_table_type table_type; - // target epsilon values - uint32_t r_t0; // read, tier0 (np) - uint32_t r_t1; // read, tier1 (gp) - uint32_t r_t2; // read, tier2 (sp) - uint32_t r_f; // read, foreign (f) - uint32_t w_t2; // write, tier2 (sp) - uint32_t w_f; // write, foreign (f) - uint32_t p; // pre -}; - // structure to represent collection of nodes in SMP topology struct proc_build_smp_system { @@ -259,6 +256,9 @@ typedef fapi::ReturnCode // PB shadow register constant definition const uint8_t PROC_BUILD_SMP_NUM_SHADOWS = 3; +// core floor/nest frequency ratio cutpoints (CPU delay) +const uint8_t PROC_BUILD_SMP_CPU_DELAY_NUM_SETPOINTS = 13; + extern "C" { @@ -276,9 +276,19 @@ extern "C" // (SMP_ACTIVATE_PHASE1 = HBI, // SMP_ACTIVATE_PHASE2 = FSP) // returns: FAPI_RC_SUCCESS if SMP build operation is successful, +// FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of +// ADU atomic lock, +// RC_PROC_ADU_UTILS_INVALID_LOCK_OPERATION if an unsupported operation +// is specified, +// RC_PROC_ADU_UTILS_INVALID_LOCK_ATTEMPTS if invalid number of attempts +// is specified, +// RC_PROC_ADU_UTILS_INVALID_FBC_OP if invalid fabric operation +// parameters are specified, +// RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH if ADU status mismatches +// for switch operation, // RC_PROC_FAB_SMP_X_BUS_WIDTH_ATTR_ERR if attribute value is // invalid, -// RC_PROC_FAB_SMP_PUMP_TYPE_ATTR_ERR if attribute value is +// RC_PROC_FAB_SMP_PUMP_MODE_ATTR_ERR if attribute value is // invalid, // RC_PROC_FAB_SMP_MCS_INTERLEAVED_ATTR_ERR if attribute value is // invalid, @@ -288,6 +298,8 @@ extern "C" // invalid, // RC_PROC_BUILD_SMP_CORE_FLOOR_FREQ_RATIO_ERR if cache/nest frequency // ratio is unsupported, +// RC_PROC_BUILD_SMP_CORE_FREQ_RANGE_ERR if invalid relationship exists +// between ceiling/nominal/floor core frequency attributes, // RC_PROC_BUILD_SMP_CORE_CEILING_FREQ_RATIO_ERR if cache/nest frequency // ratio is unsupported, // RC_PROC_BUILD_SMP_CORE_FLOOR_RATIO_ERR if cache/nest frequency @@ -309,7 +321,7 @@ extern "C" // do not specify a new fabric system master, // RC_PROC_BUILD_SMP_MASTER_DESIGNATION_ERR if node/system master // error is detected based on chip state and input paramters, -// RC_PROC_BUILD_SMP_INVALID_OPERATION if an unsupported operation +// RC_PROC_BUILD_SMP_INVALID_OPERATION_ERR if an unsupported operation // is specified // RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if HP shadow registers are not // equivalent, @@ -329,6 +341,14 @@ extern "C" // is invalid, // RC_PROC_BUILD_SMP_X_CMD_RATE_ERR if calculated X link command rate // is invalid, +// RC_PROC_BUILD_SMP_AX_PARTIAL_GOOD_ERR if partial good attribute +// state does not allow for action on target, +// RC_PROC_BUILD_SMP_PCIE_PARTIAL_GOOD_ERR if partial good attribute +// state does not allow for action on target, +// RC_PROC_BUILD_SMP_LINK_TARGET_TYPE_ERR if link target type is +// unsupported, +// RC_PROC_BUILD_SMP_INVALID_TOPOLOGY if specified fabric topology +// is illegal, // else error //------------------------------------------------------------------------------ fapi::ReturnCode proc_build_smp( diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C index ad1080a6d..b5f8dd4dd 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_adu.C,v 1.8 2013/09/26 18:00:08 jmcgill Exp $ +// $Id: proc_build_smp_adu.C,v 1.9 2014/02/23 21:41:06 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_adu.C,v $ //------------------------------------------------------------------------------ // *| @@ -40,8 +40,60 @@ //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ -#include "proc_build_smp_adu.H" -#include "proc_adu_utils.H" +#include <proc_build_smp_adu.H> +#include <proc_adu_utils.H> + +//------------------------------------------------------------------------------ +// Constants +//------------------------------------------------------------------------------ + +const uint32_t PROC_BUILD_SMP_MAX_STATUS_POLLS = 5; + +const uint32_t PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS = 1; +const bool PROC_BUILD_SMP_PHASE1_ADU_PICK_LOCK = false; +const uint32_t PROC_BUILD_SMP_PHASE1_POST_QUIESCE_DELAY = 128; +const uint32_t PROC_BUILD_SMP_PHASE1_PRE_INIT_DELAY = 128; + +const uint32_t PROC_BUILD_SMP_PHASE2_ADU_LOCK_ATTEMPTS = 5; +const bool PROC_BUILD_SMP_PHASE2_ADU_PICK_LOCK = true; +const uint32_t PROC_BUILD_SMP_PHASE2_POST_QUIESCE_DELAY = 4096; +const uint32_t PROC_BUILD_SMP_PHASE2_PRE_INIT_DELAY = 512; + +// ADU pMISC Mode register field/bit definitions +const uint32_t ADU_PMISC_MODE_ENABLE_PB_SWITCH_AB_BIT = 30; +const uint32_t ADU_PMISC_MODE_ENABLE_PB_SWITCH_CD_BIT = 31; + +// FFDC logging on ADU switch fails +const uint8_t PROC_BUILD_SMP_FFDC_NUM_REGS = 11; +const uint32_t PROC_BUILD_SMP_FFDC_REGS[PROC_BUILD_SMP_FFDC_NUM_REGS] = +{ + PB_MODE_CENT_0x02010C4A, + PB_HP_MODE_NEXT_CENT_0x02010C4B, + PB_HP_MODE_CURR_CENT_0x02010C4C, + PB_HPX_MODE_NEXT_CENT_0x02010C4D, + PB_HPX_MODE_CURR_CENT_0x02010C4E, + X_GP0_0x04000000, + PB_X_MODE_0x04010C0A, + A_GP0_0x08000000, + ADU_IOS_LINK_EN_0x02020019, + PB_A_MODE_0x0801080A, + ADU_PMISC_MODE_0x0202000B +}; +enum proc_build_smp_ffdc_reg_index +{ + PB_MODE_CENT_DATA_INDEX = 0, + PB_HP_MODE_NEXT_CENT_DATA_INDEX = 1, + PB_HP_MODE_CURR_CENT_DATA_INDEX = 2, + PB_HPX_MODE_NEXT_CENT_DATA_INDEX = 3, + PB_HPX_MODE_CURR_CENT_DATA_INDEX = 4, + X_GP0_DATA_INDEX = 5, + PB_X_MODE_DATA_INDEX = 6, + A_GP0_DATA_INDEX = 7, + ADU_IOS_LINK_EN_DATA_INDEX = 8, + PB_A_MODE_DATA_INDEX = 9, + ADU_PMISC_MODE_DATA_INDEX = 10 +}; + extern "C" { @@ -85,12 +137,12 @@ fapi::ReturnCode proc_build_smp_adu_set_switch_action( i_switch_cd); rc_ecmd |= pmisc_mask.setBit( ADU_PMISC_MODE_ENABLE_PB_SWITCH_CD_BIT); - rc.setEcmdError(rc_ecmd); - if (!rc.ok()) + if (rc_ecmd) { FAPI_ERR("proc_build_smp_adu_set_switch_action: Error 0x%x setting up ADU pMisc Mode register data buffer", rc_ecmd); + rc.setEcmdError(rc_ecmd); break; } // write ADU pMisc Mode register content @@ -100,7 +152,7 @@ fapi::ReturnCode proc_build_smp_adu_set_switch_action( pmisc_mask); if (!rc.ok()) { - FAPI_ERR("proc_build_smp_adu_set_switch_action: fapiPutUnderMask error (ADU_PMISC_MODE_0x0202000B)"); + FAPI_ERR("proc_build_smp_adu_set_switch_action: fapiPutScomUnderMask error (ADU_PMISC_MODE_0x0202000B)"); break; } } while(0); @@ -120,10 +172,10 @@ fapi::ReturnCode proc_build_smp_adu_set_switch_action( // returns: FAPI_RC_SUCCESS if lock is successfully acquired, // FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of // ADU atomic lock, -// RC_PROC_ADU_UTILS_INVALID_ARGS if invalid number of lock attempts +// RC_PROC_ADU_UTILS_INVALID_LOCK_OPERATION if an unsupported operation +// is specified, +// RC_PROC_ADU_UTILS_INVALID_LOCK_ATTEMPTS if invalid number of attempts // is specified, -// RC_PROC_ADU_UTILS_INTERNAL_ERR if an unexpected internal -// logic error occurs, // else error //------------------------------------------------------------------------------ fapi::ReturnCode proc_build_smp_adu_acquire_lock( @@ -223,10 +275,10 @@ fapi::ReturnCode proc_build_smp_adu_reset( // returns: FAPI_RC_SUCCESS if lock is successfully released, // FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of // ADU atomic lock, -// RC_PROC_ADU_UTILS_INVALID_ARGS if invalid number of unlock attempts +// RC_PROC_ADU_UTILS_INVALID_LOCK_OPERATION if an unsupported operation +// is specified, +// RC_PROC_ADU_UTILS_INVALID_LOCK_ATTEMPTS if invalid number of attempts // is specified, -// RC_PROC_ADU_UTILS_INTERNAL_ERR if an unexpected internal -// logic error occurs, // else error //------------------------------------------------------------------------------ fapi::ReturnCode proc_build_smp_adu_release_lock( @@ -270,44 +322,35 @@ fapi::ReturnCode proc_build_smp_adu_release_lock( //------------------------------------------------------------------------------ // function: check ADU status matches expected state/value // NOTE: intended to be run while holding ADU lock -// parameters: i_target => P8 chip target -// i_read_not_write => desired operation (read=true, write=false) +// parameters: i_target => P8 chip target +// i_smp => structure encapsulating SMP topology +// i_dump_all_targets => dump FFDC for all targets in SMP? +// true=yes, false=no, only for i_target // returns: FAPI_RC_SUCCESS if status matches expected value, // RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH if status mismatches, // else error //------------------------------------------------------------------------------ fapi::ReturnCode proc_build_smp_adu_check_status( - const fapi::Target& i_target) + const fapi::Target& i_target, + proc_build_smp_system& i_smp, + const bool i_dump_all_targets) { fapi::ReturnCode rc; - proc_adu_utils_adu_status status_exp, status_act; + uint32_t rc_ecmd = 0; + proc_adu_utils_adu_status status; bool match = false; uint8_t num_polls = 0; FAPI_DBG("proc_build_smp_adu_check_status: Start"); do { - // build expected status structure - status_exp.busy = ADU_STATUS_BIT_CLEAR; - status_exp.wait_cmd_arbit = ADU_STATUS_BIT_CLEAR; - status_exp.addr_done = ADU_STATUS_BIT_SET; - status_exp.data_done = ADU_STATUS_BIT_CLEAR; - status_exp.wait_resp = ADU_STATUS_BIT_CLEAR; - status_exp.overrun_err = ADU_STATUS_BIT_CLEAR; - status_exp.autoinc_err = ADU_STATUS_BIT_CLEAR; - status_exp.command_err = ADU_STATUS_BIT_CLEAR; - status_exp.address_err = ADU_STATUS_BIT_CLEAR; - status_exp.command_hang_err = ADU_STATUS_BIT_CLEAR; - status_exp.data_hang_err = ADU_STATUS_BIT_CLEAR; - status_exp.pbinit_missing = ADU_STATUS_BIT_DONT_CARE; - // retreive actual status value while (num_polls < PROC_BUILD_SMP_MAX_STATUS_POLLS) { FAPI_DBG("proc_build_smp_adu_check_status: Calling library to read ADU status (poll %d)", num_polls+1); rc = proc_adu_utils_get_adu_status(i_target, - status_act); + status); if (!rc.ok()) { FAPI_ERR("proc_build_smp_adu_check_status: Error from proc_adu_utils_get_adu_status"); @@ -315,7 +358,7 @@ fapi::ReturnCode proc_build_smp_adu_check_status( } // status reported as busy, poll again - if (status_act.busy) + if (status.busy) { num_polls++; } @@ -332,62 +375,139 @@ fapi::ReturnCode proc_build_smp_adu_check_status( // check status bits versus expected pattern match = - (((status_exp.busy == ADU_STATUS_BIT_DONT_CARE) || - (status_exp.busy == status_act.busy)) && - ((status_exp.wait_cmd_arbit == ADU_STATUS_BIT_DONT_CARE) || - (status_exp.wait_cmd_arbit == status_act.wait_cmd_arbit)) && - ((status_exp.addr_done == ADU_STATUS_BIT_DONT_CARE) || - (status_exp.addr_done == status_act.addr_done)) && - ((status_exp.data_done == ADU_STATUS_BIT_DONT_CARE) || - (status_exp.data_done == status_act.data_done)) && - ((status_exp.wait_resp == ADU_STATUS_BIT_DONT_CARE) || - (status_exp.wait_resp == status_act.wait_resp)) && - ((status_exp.overrun_err == ADU_STATUS_BIT_DONT_CARE) || - (status_exp.overrun_err == status_act.overrun_err)) && - ((status_exp.autoinc_err == ADU_STATUS_BIT_DONT_CARE) || - (status_exp.autoinc_err == status_act.autoinc_err)) && - ((status_exp.command_err == ADU_STATUS_BIT_DONT_CARE) || - (status_exp.command_err == status_act.command_err)) && - ((status_exp.address_err == ADU_STATUS_BIT_DONT_CARE) || - (status_exp.address_err == status_act.address_err)) && - ((status_exp.command_hang_err == ADU_STATUS_BIT_DONT_CARE) || - (status_exp.command_hang_err == status_act.command_hang_err)) && - ((status_exp.data_hang_err == ADU_STATUS_BIT_DONT_CARE) || - (status_exp.data_hang_err == status_act.data_hang_err)) && - ((status_exp.pbinit_missing == ADU_STATUS_BIT_DONT_CARE) || - (status_exp.pbinit_missing == status_act.pbinit_missing))); + ((status.busy == ADU_STATUS_BIT_CLEAR) && + (status.wait_cmd_arbit == ADU_STATUS_BIT_CLEAR) && + (status.addr_done == ADU_STATUS_BIT_SET) && + (status.data_done == ADU_STATUS_BIT_CLEAR) && + (status.wait_resp == ADU_STATUS_BIT_CLEAR) && + (status.overrun_err == ADU_STATUS_BIT_CLEAR) && + (status.autoinc_err == ADU_STATUS_BIT_CLEAR) && + (status.command_err == ADU_STATUS_BIT_CLEAR) && + (status.address_err == ADU_STATUS_BIT_CLEAR) && + (status.command_hang_err == ADU_STATUS_BIT_CLEAR) && + (status.data_hang_err == ADU_STATUS_BIT_CLEAR)); if (!match) { FAPI_ERR("proc_adu_utils_check_adu_status: Status mismatch detected"); FAPI_ERR("proc_adu_utils_check_adu_status: ADU Status bits:"); FAPI_ERR("proc_adu_utils_check_adu_status: FBC_ALTD_BUSY = %d", - (status_act.busy == ADU_STATUS_BIT_SET)?(1):(0)); + (status.busy == ADU_STATUS_BIT_SET)?(1):(0)); FAPI_ERR("proc_adu_utils_check_adu_status: FBC_ALTD_WAIT_CMD_ARBIT = %d", - (status_act.wait_cmd_arbit == ADU_STATUS_BIT_SET)?(1):(0)); + (status.wait_cmd_arbit == ADU_STATUS_BIT_SET)?(1):(0)); FAPI_ERR("proc_adu_utils_check_adu_status: FBC_ALTD_ADDR_DONE = %d", - (status_act.addr_done == ADU_STATUS_BIT_SET)?(1):(0)); + (status.addr_done == ADU_STATUS_BIT_SET)?(1):(0)); FAPI_ERR("proc_adu_utils_check_adu_status: FBC_ALTD_DATA_DONE = %d", - (status_act.data_done == ADU_STATUS_BIT_SET)?(1):(0)); + (status.data_done == ADU_STATUS_BIT_SET)?(1):(0)); FAPI_ERR("proc_adu_utils_check_adu_status: FBC_ALTD_WAIT_RESP = %d", - (status_act.wait_resp == ADU_STATUS_BIT_SET)?(1):(0)); + (status.wait_resp == ADU_STATUS_BIT_SET)?(1):(0)); FAPI_ERR("proc_adu_utils_check_adu_status: ADU Error bits:"); FAPI_ERR("proc_adu_utils_check_adu_status: FBC_ALTD_OVERRUN_ERROR = %d", - (status_act.overrun_err == ADU_STATUS_BIT_SET)?(1):(0)); + (status.overrun_err == ADU_STATUS_BIT_SET)?(1):(0)); FAPI_ERR("proc_adu_utils_check_adu_status: FBC_ALTD_AUTOINC_ERROR = %d", - (status_act.autoinc_err == ADU_STATUS_BIT_SET)?(1):(0)); + (status.autoinc_err == ADU_STATUS_BIT_SET)?(1):(0)); FAPI_ERR("proc_adu_utils_check_adu_status: FBC_ALTD_COMMAND_ERROR = %d", - (status_act.command_err == ADU_STATUS_BIT_SET)?(1):(0)); + (status.command_err == ADU_STATUS_BIT_SET)?(1):(0)); FAPI_ERR("proc_adu_utils_check_adu_status: FBC_ALTD_ADDRESS_ERROR = %d", - (status_act.address_err == ADU_STATUS_BIT_SET)?(1):(0)); + (status.address_err == ADU_STATUS_BIT_SET)?(1):(0)); FAPI_ERR("proc_adu_utils_check_adu_status: FBC_ALTD_COMMAND_HANG_ERROR = %d", - (status_act.command_hang_err == ADU_STATUS_BIT_SET)?(1) + (status.command_hang_err == ADU_STATUS_BIT_SET)?(1) :(0)); FAPI_ERR("proc_adu_utils_check_adu_status: FBC_ALTD_DATA_HANG_ERROR = %d", - (status_act.data_hang_err == ADU_STATUS_BIT_SET)?(1):(0)); + (status.data_hang_err == ADU_STATUS_BIT_SET)?(1):(0)); FAPI_ERR("proc_adu_utils_check_adu_status: FBC_ALTD_PBINIT_MISSING_ERROR = %d", - (status_act.pbinit_missing == ADU_STATUS_BIT_SET)?(1):(0)); - const proc_adu_utils_adu_status & STATUS_DATA = status_act; - const uint8_t & NUM_POLLS = num_polls; + (status.pbinit_missing == ADU_STATUS_BIT_SET)?(1):(0)); + + // dump FFDC + // there is no clean way to represent the collection in XML (given an arbitrary number of chips), + // so collect manually and store into data buffers which can be post-processed from the error log + std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator n_iter; + std::map<proc_fab_smp_chip_id, proc_build_smp_chip>::iterator p_iter; + std::vector<fapi::Target*> targets_to_collect; + ecmdDataBufferBase scom_data(64); + ecmdDataBufferBase chip_ids; + ecmdDataBufferBase ffdc_reg_data[PROC_BUILD_SMP_FFDC_NUM_REGS]; + bool ffdc_scom_error = false; + + // determine set of chips to collect + for (n_iter = i_smp.nodes.begin(); + n_iter != i_smp.nodes.end(); + n_iter++) + { + for (p_iter = n_iter->second.chips.begin(); + p_iter != n_iter->second.chips.end(); + p_iter++) + { + if (i_dump_all_targets || + (p_iter->second.chip->this_chip == i_target)) + { + targets_to_collect.push_back(&(p_iter->second.chip->this_chip)); + } + } + } + + // size FFDC buffers + rc_ecmd |= chip_ids.setByteLength(targets_to_collect.size()); + for (uint8_t i = 0; i < PROC_BUILD_SMP_FFDC_NUM_REGS; i++) + { + rc_ecmd |= ffdc_reg_data[i].setDoubleWordLength(targets_to_collect.size()); + } + + // extract FFDC data + for (std::vector<fapi::Target*>::iterator t = targets_to_collect.begin(); + t != targets_to_collect.end(); + t++) + { + // log node/chip ID + for (n_iter = i_smp.nodes.begin(); + n_iter != i_smp.nodes.end(); + n_iter++) + { + for (p_iter = n_iter->second.chips.begin(); + p_iter != n_iter->second.chips.end(); + p_iter++) + { + if ((&(p_iter->second.chip->this_chip)) == *t) + { + uint8_t id = ((n_iter->first & 0x3) << 4) | + (p_iter->first & 0x3); + + rc_ecmd |= chip_ids.setByte(t - targets_to_collect.begin(), id); + } + } + } + + // collect SCOM data + for (uint8_t i = 0; i < PROC_BUILD_SMP_FFDC_NUM_REGS; i++) + { + rc = fapiGetScom(*(*t), PROC_BUILD_SMP_FFDC_REGS[i], scom_data); + if (!rc.ok()) + { + ffdc_scom_error = true; + } + rc_ecmd |= scom_data.extractPreserve( + ffdc_reg_data[i], + 0, 64, + 64*(t - targets_to_collect.begin())); + } + } + + const fapi::Target& TARGET = i_target; + const proc_adu_utils_adu_status& ADU_STATUS_DATA = status; + const uint8_t& ADU_NUM_POLLS = num_polls; + const uint8_t& NUM_CHIPS = targets_to_collect.size(); + const uint8_t& FFDC_VALID = !rc_ecmd && !ffdc_scom_error; + const ecmdDataBufferBase& CHIP_IDS = chip_ids; + const ecmdDataBufferBase& PB_MODE_CENT_DATA = ffdc_reg_data[0]; + const ecmdDataBufferBase& PB_HP_MODE_NEXT_CENT_DATA = ffdc_reg_data[1]; + const ecmdDataBufferBase& PB_HP_MODE_CURR_CENT_DATA = ffdc_reg_data[2]; + const ecmdDataBufferBase& PB_HPX_MODE_NEXT_CENT_DATA = ffdc_reg_data[3]; + const ecmdDataBufferBase& PB_HPX_MODE_CURR_CENT_DATA = ffdc_reg_data[4]; + const ecmdDataBufferBase& X_GP0_DATA = ffdc_reg_data[5]; + const ecmdDataBufferBase& PB_X_MODE_DATA = ffdc_reg_data[6]; + const ecmdDataBufferBase& A_GP0_DATA = ffdc_reg_data[7]; + const ecmdDataBufferBase& ADU_IOS_LINK_EN_DATA = ffdc_reg_data[8]; + const ecmdDataBufferBase& PB_A_MODE_DATA = ffdc_reg_data[9]; + const ecmdDataBufferBase& ADU_PMISC_MODE_DATA = ffdc_reg_data[10]; FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH); break; } @@ -400,7 +520,8 @@ fapi::ReturnCode proc_build_smp_adu_check_status( // NOTE: see comments above function prototype in header fapi::ReturnCode proc_build_smp_switch_cd( - proc_build_smp_chip& i_smp_chip) + proc_build_smp_chip& i_smp_chip, + proc_build_smp_system& i_smp) { fapi::ReturnCode rc; // ADU status/control information @@ -483,7 +604,7 @@ fapi::ReturnCode proc_build_smp_switch_cd( } // check status - rc = proc_build_smp_adu_check_status(i_smp_chip.chip->this_chip); + rc = proc_build_smp_adu_check_status(i_smp_chip.chip->this_chip, i_smp, false); if (!rc.ok()) { FAPI_ERR("proc_build_smp_switch_cd: Error from proc_build_smp_adu_check_status"); @@ -636,7 +757,10 @@ fapi::ReturnCode proc_build_smp_quiesce_pb( } // check status - rc = proc_build_smp_adu_check_status(p_iter->second.chip->this_chip); + rc = proc_build_smp_adu_check_status( + p_iter->second.chip->this_chip, + i_smp, + (i_op == SMP_ACTIVATE_PHASE2)); if (!rc.ok()) { FAPI_ERR("proc_build_smp_quiesce_pb: Error from proc_build_smp_adu_check_status"); @@ -820,7 +944,10 @@ fapi::ReturnCode proc_build_smp_switch_ab( } // check status - rc = proc_build_smp_adu_check_status(i_smp.nodes[i_smp.master_chip_curr_node_id].chips[i_smp.master_chip_curr_chip_id].chip->this_chip); + rc = proc_build_smp_adu_check_status( + i_smp.nodes[i_smp.master_chip_curr_node_id].chips[i_smp.master_chip_curr_chip_id].chip->this_chip, + i_smp, + true); if (!rc.ok()) { FAPI_ERR("proc_build_smp_switch_ab: Error from proc_build_smp_adu_check_status"); diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.H index b102f8213..f988d64c6 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.H +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_adu.H,v 1.4 2013/09/26 18:00:09 jmcgill Exp $ +// $Id: proc_build_smp_adu.H,v 1.5 2014/02/23 21:41:06 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_adu.H,v $ //------------------------------------------------------------------------------ // *| @@ -43,27 +43,7 @@ // Includes //------------------------------------------------------------------------------ #include <fapi.H> -#include "proc_build_smp.H" - -//------------------------------------------------------------------------------ -// Constants -//------------------------------------------------------------------------------ - -const uint32_t PROC_BUILD_SMP_MAX_STATUS_POLLS = 5; - -const uint32_t PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS = 1; -const bool PROC_BUILD_SMP_PHASE1_ADU_PICK_LOCK = false; -const uint32_t PROC_BUILD_SMP_PHASE1_POST_QUIESCE_DELAY = 128; -const uint32_t PROC_BUILD_SMP_PHASE1_PRE_INIT_DELAY = 128; - -const uint32_t PROC_BUILD_SMP_PHASE2_ADU_LOCK_ATTEMPTS = 5; -const bool PROC_BUILD_SMP_PHASE2_ADU_PICK_LOCK = true; -const uint32_t PROC_BUILD_SMP_PHASE2_POST_QUIESCE_DELAY = 4096; -const uint32_t PROC_BUILD_SMP_PHASE2_PRE_INIT_DELAY = 512; - -// ADU pMISC Mode register field/bit definitions -const uint32_t ADU_PMISC_MODE_ENABLE_PB_SWITCH_AB_BIT = 30; -const uint32_t ADU_PMISC_MODE_ENABLE_PB_SWITCH_CD_BIT = 31; +#include <proc_build_smp.H> extern "C" { @@ -74,19 +54,21 @@ extern "C" { //------------------------------------------------------------------------------ // function: perform fabric C/D configuration switch on a single chip // parameters: i_smp_chip => structure encapsulating chip +// i_smp => structure encapsulating SMP // returns: FAPI_RC_SUCCESS if fabric reconfiguration is successful, // FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of // ADU atomic lock, -// RC_PROC_ADU_UTILS_INVALID_ARGS if invalid parameters are detected -// by ADU library code, -// RC_PROC_ADU_UTILS_INTERNAL_ERR if an unexpected internal -// logic error occurs in ADU library code, +// RC_PROC_ADU_UTILS_INVALID_LOCK_OPERATION if an unsupported operation +// is specified, +// RC_PROC_ADU_UTILS_INVALID_LOCK_ATTEMPTS if invalid number of attempts +// is specified, // RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH if ADU status mismatches // for switch operation, // else error //------------------------------------------------------------------------------ fapi::ReturnCode proc_build_smp_switch_cd( - proc_build_smp_chip& i_smp_chip); + proc_build_smp_chip& i_smp_chip, + proc_build_smp_system& i_smp); //------------------------------------------------------------------------------ @@ -101,10 +83,10 @@ fapi::ReturnCode proc_build_smp_switch_cd( // returns: FAPI_RC_SUCCESS if fabric reconfiguration is successful, // FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of // ADU atomic lock, -// RC_PROC_ADU_UTILS_INVALID_ARGS if invalid parameters are detected -// by ADU library code, -// RC_PROC_ADU_UTILS_INTERNAL_ERR if an unexpected internal -// logic error occurs in ADU library code, +// RC_PROC_ADU_UTILS_INVALID_LOCK_OPERATION if an unsupported operation +// is specified, +// RC_PROC_ADU_UTILS_INVALID_LOCK_ATTEMPTS if invalid number of attempts +// is specified, // RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH if ADU status mismatches // for switch operation, // else error @@ -126,10 +108,10 @@ fapi::ReturnCode proc_build_smp_quiesce_pb( // returns: FAPI_RC_SUCCESS if fabric reconfiguration is successful, // FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of // ADU atomic lock, -// RC_PROC_ADU_UTILS_INVALID_ARGS if invalid parameters are detected -// by ADU library code, -// RC_PROC_ADU_UTILS_INTERNAL_ERR if an unexpected internal -// logic error occurs in ADU library code, +// RC_PROC_ADU_UTILS_INVALID_LOCK_OPERATION if an unsupported operation +// is specified, +// RC_PROC_ADU_UTILS_INVALID_LOCK_ATTEMPTS if invalid number of attempts +// is specified, // RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH if ADU status mismatches // for switch operation, // else error diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C index 2984fc0ae..3fb3577c8 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_epsilon.C,v 1.9 2013/11/13 01:46:55 jmcgill Exp $ +// $Id: proc_build_smp_epsilon.C,v 1.10 2014/02/23 21:41:06 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_epsilon.C,v $ //------------------------------------------------------------------------------ // *| @@ -39,12 +39,155 @@ //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ -#include "proc_build_smp_epsilon.H" +#include <proc_build_smp_epsilon.H> extern "C" { //------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +// +// table of base epsilon values +// + +const uint32_t PROC_BUILD_SMP_EPSILON_MIN_VALUE = 0x1; +const uint32_t PROC_BUILD_SMP_EPSILON_MAX_VALUE = 0xFFFFFFFF; + +// HE epsilon (4 chips per-group) +const uint32_t PROC_BUILD_SMP_EPSILON_R_T0_HE[] = { 6, 6, 7, 8, 9, 15 }; +const uint32_t PROC_BUILD_SMP_EPSILON_R_T1_HE[] = { 56, 58, 60, 62, 65, 84 }; +const uint32_t PROC_BUILD_SMP_EPSILON_R_T2_HE[] = { 102, 104, 105, 108, 111, 130 }; +const uint32_t PROC_BUILD_SMP_EPSILON_R_F_HE[] = { 66, 67, 69, 71, 75, 93 }; +const uint32_t PROC_BUILD_SMP_EPSILON_W_HE[] = { 46, 47, 47, 48, 50, 55 }; +const uint32_t PROC_BUILD_SMP_EPSILON_W_F_HE[] = { 37, 38, 39, 40, 40, 46 }; + +// LE epsilon (2 chips per-group) +const uint32_t PROC_BUILD_SMP_EPSILON_R_T0_LE[] = { 6, 6, 7, 8, 9, 15 }; +const uint32_t PROC_BUILD_SMP_EPSILON_R_T1_LE[] = { 47, 49, 50, 53, 56, 75 }; +const uint32_t PROC_BUILD_SMP_EPSILON_R_T2_LE[] = { 93, 95, 96, 99, 102, 120 }; +const uint32_t PROC_BUILD_SMP_EPSILON_R_F_LE[] = { 66, 67, 69, 71, 75, 93 }; +const uint32_t PROC_BUILD_SMP_EPSILON_W_LE[] = { 46, 47, 47, 48, 50, 55 }; +const uint32_t PROC_BUILD_SMP_EPSILON_W_F_LE[] = { 37, 38, 39, 40, 40, 46 }; + +// Stradale epsilon (1 chip per-group) +const uint32_t PROC_BUILD_SMP_EPSILON_R_T0_1S[] = { 6, 6, 7, 8, 9, 15 }; +const uint32_t PROC_BUILD_SMP_EPSILON_R_T1_1S[] = { 6, 6, 7, 8, 9, 15 }; +const uint32_t PROC_BUILD_SMP_EPSILON_R_T2_1S[] = { 63, 64, 65, 68, 72, 90 }; +const uint32_t PROC_BUILD_SMP_EPSILON_R_F_1S[] = { 66, 67, 69, 71, 75, 93 }; +const uint32_t PROC_BUILD_SMP_EPSILON_W_1S[] = { 14, 14, 15, 15, 16, 23 }; +const uint32_t PROC_BUILD_SMP_EPSILON_W_F_1S[] = { 37, 38, 39, 40, 40, 46 }; + + +// +// unit specific epsilon range constants +// + +enum proc_build_smp_epsilon_unit +{ + PROC_BUILD_SMP_EPSILON_UNIT_L2_R_T2, + PROC_BUILD_SMP_EPSILON_UNIT_L2_W_T2, + PROC_BUILD_SMP_EPSILON_UNIT_L2_R_T0, + PROC_BUILD_SMP_EPSILON_UNIT_L2_R_T1, + PROC_BUILD_SMP_EPSILON_UNIT_L3_R_T2, + PROC_BUILD_SMP_EPSILON_UNIT_L3_W_T2, + PROC_BUILD_SMP_EPSILON_UNIT_L3_R_T0, + PROC_BUILD_SMP_EPSILON_UNIT_L3_R_T1, + PROC_BUILD_SMP_EPSILON_UNIT_MCS_R_T0, + PROC_BUILD_SMP_EPSILON_UNIT_MCS_R_T1, + PROC_BUILD_SMP_EPSILON_UNIT_MCS_R_T2, + PROC_BUILD_SMP_EPSILON_UNIT_MCS_R_F, + PROC_BUILD_SMP_EPSILON_UNIT_NX_W_T2, + PROC_BUILD_SMP_EPSILON_UNIT_HCA_W_T2, + PROC_BUILD_SMP_EPSILON_UNIT_CAPP_R_T2, + PROC_BUILD_SMP_EPSILON_UNIT_CAPP_W_T2, + PROC_BUILD_SMP_EPSILON_UNIT_CAPP_R_T0, + PROC_BUILD_SMP_EPSILON_UNIT_CAPP_R_T1, + PROC_BUILD_SMP_EPSILON_UNIT_MCD_P +}; + +// L2 +const uint32_t PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T0 = 512; +const uint32_t PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T1 = 512; +const uint32_t PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T2 = 2048; +const uint32_t PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_W_T2 = 128; + +// L3 +const uint32_t PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T0 = 512; +const uint32_t PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T1 = 512; +const uint32_t PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T2 = 2048; +const uint32_t PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_W_T2 = 128; + +// MCS +const uint32_t PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T0 = 1016; +const uint32_t PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T1 = 1016; +const uint32_t PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T2 = 1016; +const uint32_t PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_F = 1016; + +const uint8_t PROC_BUILD_SMP_EPSILON_MCS_JITTER = 0x1; + +// NX +const uint32_t PROC_BUILD_SMP_EPSILON_NX_MAX_VALUE_W_T2 = 448; + +// HCA +const uint32_t PROC_BUILD_SMP_EPSILON_HCA_MAX_VALUE_W_T2 = 512; + +// CAPP +const uint32_t PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T0 = 512; +const uint32_t PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T1 = 512; +const uint32_t PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T2 = 512; +const uint32_t PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_W_T2 = 128; + +const uint32_t PROC_BUILD_SMP_EPSILON_CAPP_FORCE_T2 = 0x1; + +// MCD +const uint32_t PROC_BUILD_SMP_EPSILON_MCD_MAX_VALUE_P = 65520; + + +// +// unit specific register field/bit definition constants +// + +// MCS MCEPS register field/bit definitions +const uint32_t MCEPS_JITTER_EPSILON_START_BIT = 0; +const uint32_t MCEPS_JITTER_EPSILON_END_BIT = 7; +const uint32_t MCEPS_NODAL_EPSILON_START_BIT = 8; +const uint32_t MCEPS_NODAL_EPSILON_END_BIT = 15; +const uint32_t MCEPS_GROUP_EPSILON_START_BIT = 16; +const uint32_t MCEPS_GROUP_EPSILON_END_BIT = 23; +const uint32_t MCEPS_SYSTEM_EPSILON_START_BIT = 24; +const uint32_t MCEPS_SYSTEM_EPSILON_END_BIT = 31; +const uint32_t MCEPS_FOREIGN_EPSILON_START_BIT = 32; +const uint32_t MCEPS_FOREIGN_EPSILON_END_BIT = 39; + +// NX CQ Epsilon Scale register field/bit definitions +const uint32_t NX_CQ_EPSILON_SCALE_EPSILON_START_BIT = 0; +const uint32_t NX_CQ_EPSILON_SCALE_EPSILON_END_BIT = 5; + +// HCA Mode register field/bit definitions +const uint32_t HCA_MODE_EPSILON_START_BIT = 21; +const uint32_t HCA_MODE_EPSILON_END_BIT = 29; + +// CAPP CXA Snoop Control register field/bit definitions +const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER0_START_BIT = 3; +const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER0_END_BIT = 11; +const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER1_START_BIT = 15; +const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER1_END_BIT = 23; +const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER2_START_BIT = 25; +const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER2_END_BIT = 35; +const uint32_t CAPP_CXA_SNP_READ_EPSILON_MODE_BIT = 0; + +// CAPP APC Master PB Control register field/bit definitions +const uint32_t CAPP_APC_MASTER_CONTROL_EPSILON_START_BIT = 39; +const uint32_t CAPP_APC_MASTER_CONTROL_EPSILON_END_BIT = 45; + +// MCD Recovery Pre Epsilon Configuration register field/bit definitions +const uint32_t MCD_RECOVERY_PRE_EPS_CONFIG_EPSILON_START_BIT = 52; +const uint32_t MCD_RECOVERY_PRE_EPS_CONFIG_EPSILON_END_BIT = 63; + + +//------------------------------------------------------------------------------ // Function definitions //------------------------------------------------------------------------------ @@ -127,6 +270,7 @@ void proc_build_smp_guardband_epsilon( // underlying register storage // i_must_fit => raise error if true and target value // cannot be represented in underlying storage +// i_unit => unit enum for FFDC // o_does_fit => boolean indicating comparison result // returns: FAPI_RC_SUCCESS if value can be represented in HW storage (or // i_must_fit is false) @@ -137,6 +281,7 @@ fapi::ReturnCode proc_build_smp_check_epsilon( const uint32_t i_target_value, const uint32_t i_max_hw_value, const bool i_must_fit, + const proc_build_smp_epsilon_unit i_unit, bool& o_does_fit) { fapi::ReturnCode rc; @@ -154,6 +299,7 @@ fapi::ReturnCode proc_build_smp_check_epsilon( i_target_value, i_max_hw_value); const uint32_t& VALUE = i_target_value; const uint32_t& MAX_HW_VALUE = i_max_hw_value; + const proc_build_smp_epsilon_unit& UNIT = i_unit; FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR); break; } @@ -213,6 +359,7 @@ fapi::ReturnCode proc_build_smp_set_epsilons_l2( i_eps_cfg.r_t2, PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T2, true, + PROC_BUILD_SMP_EPSILON_UNIT_L2_R_T2, r_t2_fits); if (!rc.ok()) @@ -225,6 +372,7 @@ fapi::ReturnCode proc_build_smp_set_epsilons_l2( i_eps_cfg.w_t2, PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_W_T2, true, + PROC_BUILD_SMP_EPSILON_UNIT_L2_W_T2, w_t2_fits); if (!rc.ok()) @@ -240,11 +388,13 @@ fapi::ReturnCode proc_build_smp_set_epsilons_l2( i_eps_cfg.r_t0, PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T0, false, + PROC_BUILD_SMP_EPSILON_UNIT_L2_R_T0, r_t0_fits); (void) proc_build_smp_check_epsilon( i_eps_cfg.r_t1, PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T1, false, + PROC_BUILD_SMP_EPSILON_UNIT_L2_R_T1, r_t1_fits); // set attributes based on unit implementation @@ -387,6 +537,7 @@ fapi::ReturnCode proc_build_smp_set_epsilons_l3( i_eps_cfg.r_t2, PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T2, true, + PROC_BUILD_SMP_EPSILON_UNIT_L3_R_T2, r_t2_fits); if (!rc.ok()) @@ -399,6 +550,7 @@ fapi::ReturnCode proc_build_smp_set_epsilons_l3( i_eps_cfg.w_t2, PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_W_T2, true, + PROC_BUILD_SMP_EPSILON_UNIT_L3_W_T2, w_t2_fits); if (!rc.ok()) @@ -414,11 +566,13 @@ fapi::ReturnCode proc_build_smp_set_epsilons_l3( i_eps_cfg.r_t0, PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T0, false, + PROC_BUILD_SMP_EPSILON_UNIT_L3_R_T0, r_t0_fits); (void) proc_build_smp_check_epsilon( i_eps_cfg.r_t1, PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T1, false, + PROC_BUILD_SMP_EPSILON_UNIT_L3_R_T1, r_t1_fits); // set attributes based on unit implementation @@ -552,6 +706,7 @@ fapi::ReturnCode proc_build_smp_set_epsilons_mcs( i_eps_cfg.r_t0, PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T0, true, + PROC_BUILD_SMP_EPSILON_UNIT_MCS_R_T0, r_t0_fits); if (!rc.ok()) @@ -564,6 +719,7 @@ fapi::ReturnCode proc_build_smp_set_epsilons_mcs( i_eps_cfg.r_t1, PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T1, true, + PROC_BUILD_SMP_EPSILON_UNIT_MCS_R_T1, r_t1_fits); if (!rc.ok()) @@ -576,6 +732,7 @@ fapi::ReturnCode proc_build_smp_set_epsilons_mcs( i_eps_cfg.r_t2, PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T2, true, + PROC_BUILD_SMP_EPSILON_UNIT_MCS_R_T2, r_t2_fits); if (!rc.ok()) @@ -588,6 +745,7 @@ fapi::ReturnCode proc_build_smp_set_epsilons_mcs( i_eps_cfg.r_f, PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_F, true, + PROC_BUILD_SMP_EPSILON_UNIT_MCS_R_F, r_f_fits); if (!rc.ok()) @@ -705,6 +863,7 @@ fapi::ReturnCode proc_build_smp_set_epsilons_nx( i_eps_cfg.w_t2, PROC_BUILD_SMP_EPSILON_NX_MAX_VALUE_W_T2, true, + PROC_BUILD_SMP_EPSILON_UNIT_NX_W_T2, w_t2_fits); if (!rc.ok()) @@ -791,6 +950,7 @@ fapi::ReturnCode proc_build_smp_set_epsilons_hca( i_eps_cfg.w_t2, PROC_BUILD_SMP_EPSILON_HCA_MAX_VALUE_W_T2, true, + PROC_BUILD_SMP_EPSILON_UNIT_HCA_W_T2, w_t2_fits); if (!rc.ok()) @@ -881,6 +1041,7 @@ fapi::ReturnCode proc_build_smp_set_epsilons_capp( i_eps_cfg.r_t2, PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T2, true, + PROC_BUILD_SMP_EPSILON_UNIT_CAPP_R_T2, r_t2_fits); if (!rc.ok()) @@ -893,6 +1054,7 @@ fapi::ReturnCode proc_build_smp_set_epsilons_capp( i_eps_cfg.w_t2, PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_W_T2, true, + PROC_BUILD_SMP_EPSILON_UNIT_CAPP_W_T2, w_t2_fits); if (!rc.ok()) @@ -908,11 +1070,13 @@ fapi::ReturnCode proc_build_smp_set_epsilons_capp( i_eps_cfg.r_t0, PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T0, false, + PROC_BUILD_SMP_EPSILON_UNIT_CAPP_R_T0, r_t0_fits); (void) proc_build_smp_check_epsilon( i_eps_cfg.r_t1, PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T1, false, + PROC_BUILD_SMP_EPSILON_UNIT_CAPP_R_T1, r_t1_fits); // program write epsilon register based on unit implementation @@ -950,7 +1114,7 @@ fapi::ReturnCode proc_build_smp_set_epsilons_capp( // program read epsilon register based on unit implementation rc_ecmd = data.flushTo0(); - rc_ecmd = mask.flushTo0(); + rc_ecmd |= mask.flushTo0(); rc_ecmd |= data.insertFromRight( ((i_eps_cfg.r_t2 == PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T2)? @@ -1060,6 +1224,7 @@ fapi::ReturnCode proc_build_smp_set_epsilons_mcd( i_eps_cfg.p, PROC_BUILD_SMP_EPSILON_MCD_MAX_VALUE_P, true, + PROC_BUILD_SMP_EPSILON_UNIT_MCD_P, p_fits); if (!rc.ok()) @@ -1184,6 +1349,7 @@ fapi::ReturnCode proc_build_smp_calc_epsilons( break; default: FAPI_ERR("proc_build_smp_calc_epsilons: Invalid epsilon table type"); + const proc_fab_smp_eps_table_type& TABLE_TYPE = io_smp.eps_cfg.table_type; FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_EPSILON_INVALID_TABLE_ERR); break; } @@ -1289,6 +1455,7 @@ fapi::ReturnCode proc_build_smp_calc_epsilons( ((io_smp.eps_cfg.w_f > io_smp.eps_cfg.w_t2) && (io_smp.eps_cfg.table_type != PROC_FAB_SMP_EPSILON_TABLE_TYPE_1S))) { FAPI_ERR("proc_build_smp_calc_epsilons: Invalid relationship between base epsilon values"); + const proc_fab_smp_eps_table_type& TABLE_TYPE = io_smp.eps_cfg.table_type; FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_EPSILON_INVALID_TABLE_ERR); break; } diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.H index 00a3ae2e2..f79c8c764 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.H +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_epsilon.H,v 1.7 2013/11/13 01:49:53 jmcgill Exp $ +// $Id: proc_build_smp_epsilon.H,v 1.8 2014/02/23 21:41:06 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_epsilon.H,v $ //------------------------------------------------------------------------------ // *| @@ -41,128 +41,9 @@ //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ -#include "proc_build_smp.H" +#include <proc_build_smp.H> -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -// -// table of base epsilon values -// - -const uint32_t PROC_BUILD_SMP_EPSILON_MIN_VALUE = 0x1; -const uint32_t PROC_BUILD_SMP_EPSILON_MAX_VALUE = 0xFFFFFFFF; - -// HE epsilon (4 chips per-group) -const uint32_t PROC_BUILD_SMP_EPSILON_R_T0_HE[] = { 6, 6, 7, 8, 9, 15 }; -const uint32_t PROC_BUILD_SMP_EPSILON_R_T1_HE[] = { 56, 58, 60, 62, 65, 84 }; -const uint32_t PROC_BUILD_SMP_EPSILON_R_T2_HE[] = { 102, 104, 105, 108, 111, 130 }; -const uint32_t PROC_BUILD_SMP_EPSILON_R_F_HE[] = { 66, 67, 69, 71, 75, 93 }; -const uint32_t PROC_BUILD_SMP_EPSILON_W_HE[] = { 46, 47, 47, 48, 50, 55 }; -const uint32_t PROC_BUILD_SMP_EPSILON_W_F_HE[] = { 37, 38, 39, 40, 40, 46 }; - -// LE epsilon (2 chips per-group) -const uint32_t PROC_BUILD_SMP_EPSILON_R_T0_LE[] = { 6, 6, 7, 8, 9, 15 }; -const uint32_t PROC_BUILD_SMP_EPSILON_R_T1_LE[] = { 47, 49, 50, 53, 56, 75 }; -const uint32_t PROC_BUILD_SMP_EPSILON_R_T2_LE[] = { 93, 95, 96, 99, 102, 120 }; -const uint32_t PROC_BUILD_SMP_EPSILON_R_F_LE[] = { 66, 67, 69, 71, 75, 93 }; -const uint32_t PROC_BUILD_SMP_EPSILON_W_LE[] = { 46, 47, 47, 48, 50, 55 }; -const uint32_t PROC_BUILD_SMP_EPSILON_W_F_LE[] = { 37, 38, 39, 40, 40, 46 }; - -// Stradale epsilon (1 chip per-group) -const uint32_t PROC_BUILD_SMP_EPSILON_R_T0_1S[] = { 6, 6, 7, 8, 9, 15 }; -const uint32_t PROC_BUILD_SMP_EPSILON_R_T1_1S[] = { 6, 6, 7, 8, 9, 15 }; -const uint32_t PROC_BUILD_SMP_EPSILON_R_T2_1S[] = { 63, 64, 65, 68, 72, 90 }; -const uint32_t PROC_BUILD_SMP_EPSILON_R_F_1S[] = { 66, 67, 69, 71, 75, 93 }; -const uint32_t PROC_BUILD_SMP_EPSILON_W_1S[] = { 14, 14, 15, 15, 16, 23 }; -const uint32_t PROC_BUILD_SMP_EPSILON_W_F_1S[] = { 37, 38, 39, 40, 40, 46 }; - - -// -// unit specific epsilon range constants -// - -// L2 -const uint32_t PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T0 = 512; -const uint32_t PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T1 = 512; -const uint32_t PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T2 = 2048; -const uint32_t PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_W_T2 = 128; - -// L3 -const uint32_t PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T0 = 512; -const uint32_t PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T1 = 512; -const uint32_t PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T2 = 2048; -const uint32_t PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_W_T2 = 128; - -// MCS -const uint32_t PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T0 = 1016; -const uint32_t PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T1 = 1016; -const uint32_t PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T2 = 1016; -const uint32_t PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_F = 1016; - -const uint8_t PROC_BUILD_SMP_EPSILON_MCS_JITTER = 0x1; - -// NX -const uint32_t PROC_BUILD_SMP_EPSILON_NX_MAX_VALUE_W_T2 = 448; - -// HCA -const uint32_t PROC_BUILD_SMP_EPSILON_HCA_MAX_VALUE_W_T2 = 512; - -// CAPP -const uint32_t PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T0 = 512; -const uint32_t PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T1 = 512; -const uint32_t PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T2 = 512; -const uint32_t PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_W_T2 = 128; - -const uint32_t PROC_BUILD_SMP_EPSILON_CAPP_FORCE_T2 = 0x1; - -// MCD -const uint32_t PROC_BUILD_SMP_EPSILON_MCD_MAX_VALUE_P = 65520; - - -// -// unit specific register field/bit definition constants -// - -// MCS MCEPS register field/bit definitions -const uint32_t MCEPS_JITTER_EPSILON_START_BIT = 0; -const uint32_t MCEPS_JITTER_EPSILON_END_BIT = 7; -const uint32_t MCEPS_NODAL_EPSILON_START_BIT = 8; -const uint32_t MCEPS_NODAL_EPSILON_END_BIT = 15; -const uint32_t MCEPS_GROUP_EPSILON_START_BIT = 16; -const uint32_t MCEPS_GROUP_EPSILON_END_BIT = 23; -const uint32_t MCEPS_SYSTEM_EPSILON_START_BIT = 24; -const uint32_t MCEPS_SYSTEM_EPSILON_END_BIT = 31; -const uint32_t MCEPS_FOREIGN_EPSILON_START_BIT = 32; -const uint32_t MCEPS_FOREIGN_EPSILON_END_BIT = 39; - -// NX CQ Epsilon Scale register field/bit definitions -const uint32_t NX_CQ_EPSILON_SCALE_EPSILON_START_BIT = 0; -const uint32_t NX_CQ_EPSILON_SCALE_EPSILON_END_BIT = 5; - -// HCA Mode register field/bit definitions -const uint32_t HCA_MODE_EPSILON_START_BIT = 21; -const uint32_t HCA_MODE_EPSILON_END_BIT = 29; - -// CAPP CXA Snoop Control register field/bit definitions -const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER0_START_BIT = 3; -const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER0_END_BIT = 11; -const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER1_START_BIT = 15; -const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER1_END_BIT = 23; -const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER2_START_BIT = 25; -const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER2_END_BIT = 35; -const uint32_t CAPP_CXA_SNP_READ_EPSILON_MODE_BIT = 0; - -// CAPP APC Master PB Control register field/bit definitions -const uint32_t CAPP_APC_MASTER_CONTROL_EPSILON_START_BIT = 39; -const uint32_t CAPP_APC_MASTER_CONTROL_EPSILON_END_BIT = 45; - -// MCD Recovery Pre Epsilon Configuration register field/bit definitions -const uint32_t MCD_RECOVERY_PRE_EPS_CONFIG_EPSILON_START_BIT = 52; -const uint32_t MCD_RECOVERY_PRE_EPS_CONFIG_EPSILON_END_BIT = 63; - extern "C" { diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml index 4d8783a95..be4494a83 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2014 --> <!-- --> <!-- p1 --> <!-- --> @@ -20,92 +20,222 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_build_smp_errors.xml,v 1.7 2013/11/13 13:59:51 jmcgill Exp $ --> +<!-- $Id: proc_build_smp_errors.xml,v 1.9 2014/02/26 18:14:12 jmcgill Exp $ --> <!-- Error definitions for proc_build_smp --> <hwpErrors> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_BUILD_SMP_NODE_ADD_INTERNAL_ERR</rc> - <description>Internal Error. Error encountered adding node to SMP structure.</description> + <rc>RC_PROC_BUILD_SMP_CORE_FREQ_RANGE_ERR</rc> + <description>Invalid relationship between ceiling/nominal/floor core frequency attributes.</description> + <ffdc>FREQ_CORE_CEILING</ffdc> + <ffdc>FREQ_CORE_NOM</ffdc> + <ffdc>FREQ_CORE_FLOOR</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> + <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_BUILD_SMP_DUPLICATE_FABRIC_ID_ERR</rc> - <description>Multiple chips found with identifcal fabric node/chip ID attribute values.</description> - <ffdc>NODE_ID</ffdc> - <ffdc>CHIP_ID</ffdc> + <rc>RC_PROC_BUILD_SMP_CORE_FLOOR_FREQ_RATIO_ERR</rc> + <description>Unsupported core floor to PB frequency ratio.</description> + <ffdc>FREQ_PB</ffdc> + <ffdc>FREQ_CORE_FLOOR</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_BUILD_SMP_CORE_CEILING_FREQ_RATIO_ERR</rc> + <description>Unsupported core ceiling to PB frequency ratio.</description> + <ffdc>FREQ_PB</ffdc> + <ffdc>FREQ_CORE_CEILING</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> <hwpError> <rc>RC_PROC_BUILD_SMP_INVALID_OPERATION_ERR</rc> <description>Unsupported SMP build operation presented.</description> <ffdc>OP</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> + <!-- *********************************************************************** --> <hwpError> <rc>RC_PROC_BUILD_SMP_MASTER_DESIGNATION_ERR</rc> <description>Node or system master chip designation error.</description> + <ffdc>TARGET</ffdc> <ffdc>OP</ffdc> <ffdc>MASTER_CHIP_SYS_CURR</ffdc> <ffdc>MASTER_CHIP_NODE_CURR</ffdc> <ffdc>MASTER_CHIP_SYS_NEXT</ffdc> <ffdc>MASTER_CHIP_NODE_NEXT</ffdc> <ffdc>SYS_RECONFIG_MASTER_SET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_BUILD_SMP_NODE_ADD_INTERNAL_ERR</rc> + <description>Internal Error. Error encountered adding node to SMP structure.</description> + <ffdc>TARGET</ffdc> + <ffdc>NODE_ID</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_BUILD_SMP_DUPLICATE_FABRIC_ID_ERR</rc> + <description>Multiple chips found with identifcal fabric node/chip ID attribute values.</description> + <ffdc>TARGET1</ffdc> + <ffdc>TARGET2</ffdc> + <ffdc>NODE_ID</ffdc> + <ffdc>CHIP_ID</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> + <!-- *********************************************************************** --> <hwpError> <rc>RC_PROC_BUILD_SMP_NO_MASTER_SPECIFIED_ERR</rc> <description>Input parameters do not specify a new fabric system master.</description> <ffdc>OP</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH</rc> + <description>Status mismatch detected on ADU operation executed for SMP configuration.</description> + <ffdc>TARGET</ffdc> + <ffdc>ADU_STATUS_DATA</ffdc> + <ffdc>ADU_NUM_POLLS</ffdc> + <ffdc>FFDC_VALID</ffdc> + <ffdc>NUM_CHIPS</ffdc> + <ffdc>CHIP_IDS</ffdc> + <ffdc>PB_MODE_CENT_DATA</ffdc> + <ffdc>PB_HP_MODE_NEXT_CENT_DATA</ffdc> + <ffdc>PB_HP_MODE_CURR_CENT_DATA</ffdc> + <ffdc>PB_HPX_MODE_NEXT_CENT_DATA</ffdc> + <ffdc>PB_HPX_MODE_CURR_CENT_DATA</ffdc> + <ffdc>X_GP0_DATA</ffdc> + <ffdc>PB_X_MODE_DATA</ffdc> + <ffdc>A_GP0_DATA</ffdc> + <ffdc>ADU_IOS_LINK_EN_DATA</ffdc> + <ffdc>PB_A_MODE_DATA</ffdc> + <ffdc>ADU_PMISC_MODE_DATA</ffdc> + <callout> + <procedure>LVL_SUPPORT</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> <hwpError> <rc>RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR</rc> <description>Target epsilon value exceeds maximum value supported by HW capabilities.</description> <ffdc>VALUE</ffdc> <ffdc>MAX_HW_VALUE</ffdc> + <ffdc>UNIT</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> + <!-- *********************************************************************** --> <hwpError> <rc>RC_PROC_BUILD_SMP_EPSILON_INVALID_TABLE_ERR</rc> <description>Invalid epsilon table type or content detected.</description> + <ffdc>TABLE_TYPE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> + <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_BUILD_SMP_PACING_RATE_TABLE_ERR</rc> - <description>Command rate pacing table lookup error.</description> - </hwpError> - <hwpError> - <rc>RC_PROC_BUILD_SMP_CORE_FREQ_RANGE_ERR</rc> - <description>Invalid relationship between ceiling/nominal/floor core frequency attributes.</description> - <ffdc>CEILING</ffdc> - <ffdc>NOM</ffdc> - <ffdc>FLOOR</ffdc> + <rc>RC_PROC_BUILD_SMP_INVALID_AGGREGATE_CONFIG_ERR</rc> + <description>Invalid aggregate link configuration detected.</description> + <ffdc>TARGET</ffdc> + <ffdc>X_NOT_A</ffdc> + <ffdc>ALLOW_AGGREGATE</ffdc> + <ffdc>AGGREGATE_DEST_ID1</ffdc> + <ffdc>AGGREGATE_DEST_ID2</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> + <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_BUILD_SMP_CORE_FLOOR_FREQ_RATIO_ERR</rc> - <description>Unsupported core floor to PB frequency ratio.</description> + <rc>RC_PROC_BUILD_SMP_X_CMD_RATE_ERR</rc> + <description>Target link command rate value is out of range.</description> <ffdc>FREQ_PB</ffdc> - <ffdc>FREQ_CORE_FLOOR</ffdc> + <ffdc>FREQ_X</ffdc> + <ffdc>X_IS_8B</ffdc> + <ffdc>X_AGGREGATE</ffdc> + <ffdc>N</ffdc> + <ffdc>D</ffdc> + <ffdc>CMD_RATE</ffdc> + <ffdc>MIN_CMD_RATE</ffdc> + <ffdc>MAX_CMD_RATE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> + <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_BUILD_SMP_CORE_CEILING_FREQ_RATIO_ERR</rc> - <description>Unsupported core ceiling to PB frequency ratio.</description> + <rc>RC_PROC_BUILD_SMP_A_CMD_RATE_ERR</rc> + <description>Target link command rate value is out of range.</description> <ffdc>FREQ_PB</ffdc> - <ffdc>FREQ_CORE_CEILING</ffdc> - </hwpError> - <hwpError> - <rc>RC_PROC_BUILD_SMP_CORE_FLOOR_RATIO_ERR</rc> - <description>Unsupported core floor frequency enumerated value.</description> - <ffdc>CORE_FLOOR_RATIO</ffdc> - </hwpError> - <hwpError> - <rc>RC_PROC_BUILD_SMP_CORE_CEILING_RATIO_ERR</rc> - <description>Unsupported core ceiling frequency enumerated value.</description> - <ffdc>CORE_CEILING_RATIO</ffdc> - </hwpError> - <hwpError> - <rc>RC_PROC_BUILD_SMP_INVALID_GROUP_SIZE_ERR</rc> - <description>Invalid chips per group configuration detected.</description> - <ffdc>SIZE</ffdc> + <ffdc>FREQ_A</ffdc> + <ffdc>A_OW_PACK</ffdc> + <ffdc>A_OW_PACK_PRIORITY</ffdc> + <ffdc>A_AGGREGATE</ffdc> + <ffdc>N</ffdc> + <ffdc>D</ffdc> + <ffdc>CMD_RATE</ffdc> + <ffdc>MIN_CMD_RATE</ffdc> + <ffdc>MAX_CMD_RATE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> + <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_BUILD_SMP_INVALID_AGGREGATE_CONFIG_ERR</rc> - <description>Invalid aggregate link configuration detected.</description> + <rc>RC_PROC_BUILD_SMP_F_CMD_RATE_ERR</rc> + <description>Target link command rate value is out of range.</description> + <ffdc>FREQ_PB</ffdc> + <ffdc>FREQ_F</ffdc> + <ffdc>F_OW_PACK</ffdc> + <ffdc>F_OW_PACK_PRIORITY</ffdc> + <ffdc>F_AGGREGATE</ffdc> + <ffdc>N</ffdc> + <ffdc>D</ffdc> + <ffdc>CMD_RATE</ffdc> + <ffdc>MIN_CMD_RATE</ffdc> + <ffdc>MAX_CMD_RATE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> + <!-- *********************************************************************** --> <hwpError> <rc>RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR</rc> <description>Inconsistent state in hotplug (CURR) shadow copies.</description> @@ -113,38 +243,129 @@ <ffdc>ADDRESS1</ffdc> <ffdc>DATA0</ffdc> <ffdc>DATA1</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> + <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_BUILD_SMP_X_CMD_RATE_ERR</rc> - <description>Target link command rate value is out of range.</description> - <ffdc>CMD_RATE</ffdc> + <rc>RC_PROC_BUILD_SMP_AX_PARTIAL_GOOD_ERR</rc> + <description>A/X bus partial good attribute state does not allow for action on target.</description> + <ffdc>SOURCE_CHIP_TARGET</ffdc> + <ffdc>CHIPLET_ID</ffdc> + <ffdc>SOURCE_LINK_ID</ffdc> + <ffdc>REGION_ENABLED</ffdc> + <ffdc>REGIONS_TO_ENABLE</ffdc> + <ffdc>REGIONS_TO_ENABLE_VALID</ffdc> + <ffdc>DEST_LINK_TARGET</ffdc> + <callout> + <target>SOURCE_CHIP_TARGET</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <deconfigure> + <target>SOURCE_CHIP_TARGET</target> + </deconfigure> </hwpError> + <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_BUILD_SMP_A_CMD_RATE_ERR</rc> - <description>Target link command rate value is out of range.</description> - <ffdc>CMD_RATE</ffdc> + <rc>RC_PROC_BUILD_SMP_LINK_TARGET_TYPE_ERR</rc> + <description>Invalid destination link target type detected in input parameters.</description> + <ffdc>SOURCE_CHIP_TARGET</ffdc> + <ffdc>SOURCE_LINK_ID</ffdc> + <ffdc>DEST_LINK_TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> + <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_BUILD_SMP_F_CMD_RATE_ERR</rc> - <description>Target link command rate value is out of range.</description> - <ffdc>CMD_RATE</ffdc> + <rc>RC_PROC_BUILD_SMP_PCIE_PARTIAL_GOOD_ERR</rc> + <description>PCIE partial good attribute state does not allow for action on target.</description> + <ffdc>SOURCE_CHIP_TARGET</ffdc> + <ffdc>CHIPLET_ID</ffdc> + <ffdc>SOURCE_LINK_ID</ffdc> + <ffdc>REGION_ENABLED</ffdc> + <ffdc>REGIONS_TO_ENABLE</ffdc> + <ffdc>REGIONS_TO_ENABLE_VALID</ffdc> + <ffdc>DEST_NODE_ID</ffdc> + <callout> + <target>SOURCE_CHIP_TARGET</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <deconfigure> + <target>SOURCE_CHIP_TARGET</target> + </deconfigure> </hwpError> + <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH</rc> - <description>Status mismatch detected on ADU operation executed for SMP configuration.</description> - <ffdc>NUM_POLLS</ffdc> - <ffdc>STATUS_DATA</ffdc> + <rc>RC_PROC_BUILD_SMP_CORE_CEILING_RATIO_ERR</rc> + <description>Unsupported core ceiling frequency enumerated value.</description> + <ffdc>FREQ_PB</ffdc> + <ffdc>FREQ_CORE_CEILING</ffdc> + <ffdc>CORE_CEILING_RATIO</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_BUILD_SMP_CORE_FLOOR_RATIO_ERR</rc> + <description>Unsupported core floor frequency enumerated value.</description> + <ffdc>FREQ_PB</ffdc> + <ffdc>FREQ_CORE_FLOOR</ffdc> + <ffdc>CORE_FLOOR_RATIO</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> + <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_BUILD_SMP_X_PARTIAL_GOOD_ERR</rc> - <description>X bus partial good attribute state does not allow for action on target.</description> + <rc>RC_PROC_BUILD_SMP_INVALID_GROUP_SIZE_ERR</rc> + <description>Invalid chips per group configuration detected.</description> + <ffdc>TARGET</ffdc> + <ffdc>GROUP_SIZE</ffdc> + <ffdc>NODE_ID</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> + <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_BUILD_SMP_A_PARTIAL_GOOD_ERR</rc> - <description>A bus partial good attribute state does not allow for action on target.</description> + <rc>RC_PROC_BUILD_SMP_PACING_RATE_TABLE_ERR</rc> + <description>Command rate pacing table lookup error.</description> + <ffdc>TARGET</ffdc> + <ffdc>GROUP_SIZE</ffdc> + <ffdc>NODE_ID</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> + <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_BUILD_SMP_PCIE_PARTIAL_GOOD_ERR</rc> - <description>PCIE partial good attribute state does not allow for action on target.</description> + <rc>RC_PROC_BUILD_SMP_INVALID_TOPOLOGY</rc> + <description>Invalid fabric topology specified by input parameters.</description> + <ffdc>TARGET</ffdc> + <ffdc>A_CONNECTIONS_OK</ffdc> + <ffdc>A_CONNECTED_NODE_IDS</ffdc> + <ffdc>X_CONNECTIONS_OK</ffdc> + <ffdc>X_CONNECTED_NODE_IDS</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> </hwpErrors> diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C index fb198f0e5..852d301f5 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_fbc_ab.C,v 1.9 2013/10/24 19:59:08 jmcgill Exp $ +// $Id: proc_build_smp_fbc_ab.C,v 1.11 2014/02/26 18:12:57 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_ab.C,v $ //------------------------------------------------------------------------------ // *| @@ -39,18 +39,126 @@ //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ -#include "proc_build_smp_fbc_ab.H" -#include "proc_build_smp_epsilon.H" -#include "proc_build_smp_adu.H" +#include <proc_build_smp_fbc_ab.H> +#include <proc_build_smp_epsilon.H> +#include <proc_build_smp_adu.H> -extern "C" { +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +// PB Hotplug Mode register field/bit definitions +const uint32_t PB_HP_MODE_LINK_A_EN_BIT[PROC_FAB_SMP_NUM_A_LINKS] = { 1, 2, 3 }; +const uint32_t PB_HP_MODE_LINK_A_ADDR_DIS_BIT[PROC_FAB_SMP_NUM_A_LINKS] = { 4, 5, 6 }; +const uint32_t PB_HP_MODE_LINK_A_ID_START_BIT[PROC_FAB_SMP_NUM_A_LINKS] = { 7, 10, 13 }; +const uint32_t PB_HP_MODE_LINK_A_ID_END_BIT[PROC_FAB_SMP_NUM_A_LINKS] = { 9, 12, 15 }; + +const uint32_t PB_HP_MODE_PCIE_NOT_DSMP_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 38, 39 }; +const uint32_t PB_HP_MODE_LINK_F_MASTER_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 42, 43 }; +const uint32_t PB_HP_MODE_LINK_F_EN_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 44, 45 }; +const uint32_t PB_HP_MODE_LINK_F_ADDR_DIS_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 46, 47 }; +const uint32_t PB_HP_MODE_LINK_F_ID_START_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 48, 51 }; +const uint32_t PB_HP_MODE_LINK_F_ID_END_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 50, 53 }; + +const uint32_t PB_HP_MODE_A_AGGREGATE_BIT = 16; +const uint32_t PB_HP_MODE_TM_MASTER_BIT = 17; +const uint32_t PB_HP_MODE_CHG_RATE_SP_MASTER_BIT = 19; +const uint32_t PB_HP_MODE_PUMP_MODE_BIT = 20; +const uint32_t PB_HP_MODE_SINGLE_MC_BIT = 21; +const uint32_t PB_HP_MODE_DCACHE_CAPP_MODE_BIT = 22; +const uint32_t PB_HP_MODE_A_CMD_RATE_START_BIT = 24; +const uint32_t PB_HP_MODE_A_CMD_RATE_END_BIT = 31; +const uint32_t PB_HP_MODE_A_CMD_RATE_MIN_VALUE = 1; +const uint32_t PB_HP_MODE_A_CMD_RATE_MAX_VALUE = 0x7F; +const uint32_t PB_HP_MODE_A_GATHER_ENABLE_BIT = 32; +const uint32_t PB_HP_MODE_A_GATHER_DLY_CNT_START_BIT = 33; +const uint32_t PB_HP_MODE_A_GATHER_DLY_CNT_END_BIT = 37; +const uint32_t PB_HP_MODE_GATHER_ENABLE_BIT = 40; +const uint32_t PB_HP_MODE_F_AGGREGATE_BIT = 55; +const uint32_t PB_HP_MODE_F_CMD_RATE_START_BIT = 56; +const uint32_t PB_HP_MODE_F_CMD_RATE_END_BIT = 63; +const uint32_t PB_HP_MODE_F_CMD_RATE_MIN_VALUE = 1; +const uint32_t PB_HP_MODE_F_CMD_RATE_MAX_VALUE = 0x7F; + +const bool PB_HP_MODE_DCACHE_CAPP_EN = false; +const bool PB_HP_MODE_A_GATHER_ENABLE = true; +const uint8_t PB_HP_MODE_A_GATHER_DLY_CNT = 0x04; +const bool PB_HP_MODE_GATHER_ENABLE = true; + +const uint32_t PB_HP_MODE_NEXT_SHADOWS[PROC_BUILD_SMP_NUM_SHADOWS] = +{ + PB_HP_MODE_NEXT_WEST_0x02010C0B, + PB_HP_MODE_NEXT_CENT_0x02010C4B, + PB_HP_MODE_NEXT_EAST_0x02010C8B +}; +const uint32_t PB_HP_MODE_CURR_SHADOWS[PROC_BUILD_SMP_NUM_SHADOWS] = +{ + PB_HP_MODE_CURR_WEST_0x02010C0C, + PB_HP_MODE_CURR_CENT_0x02010C4C, + PB_HP_MODE_CURR_EAST_0x02010C8C +}; + +// PB Hotplug Extension Mode register field/bit definitions +const uint32_t PB_HPX_MODE_LINK_X_EN_BIT[PROC_FAB_SMP_NUM_X_LINKS] = { 0, 1, 2, 3 }; +const uint32_t PB_HPX_MODE_LINK_X_ADDR_DIS_BIT[PROC_FAB_SMP_NUM_X_LINKS] = { 5, 6, 7, 8 }; +const uint32_t PB_HPX_MODE_LINK_X_CHIPID_START_BIT[PROC_FAB_SMP_NUM_X_LINKS] = { 10, 13, 16, 19 }; +const uint32_t PB_HPX_MODE_LINK_X_CHIPID_END_BIT[PROC_FAB_SMP_NUM_X_LINKS] = { 12, 15, 18, 21 }; + +const uint32_t PB_HPX_MODE_X_AGGREGATE_BIT = 25; +const uint32_t PB_HPX_MODE_X_INDIRECT_EN_BIT = 26; +const uint32_t PB_HPX_MODE_X_GATHER_ENABLE_BIT = 32; +const uint32_t PB_HPX_MODE_X_GATHER_DLY_CNT_START_BIT = 33; +const uint32_t PB_HPX_MODE_X_GATHER_DLY_CNT_END_BIT = 37; +const uint32_t PB_HPX_MODE_X_ONNODE_12QUEUES_BIT = 38; +const uint32_t PB_HPX_MODE_X_CMD_RATE_START_BIT = 56; +const uint32_t PB_HPX_MODE_X_CMD_RATE_END_BIT = 63; +const uint32_t PB_HPX_MODE_X_CMD_RATE_MIN_VALUE = 1; +const uint32_t PB_HPX_MODE_X_CMD_RATE_MAX_VALUE = 0x7F; + +const bool PB_HPX_MODE_X_INDIRECT_EN = true; +const bool PB_HPX_MODE_X_GATHER_ENABLE = true; +const uint8_t PB_HPX_MODE_X_GATHER_DLY_CNT = 0x04; +const bool PB_HPX_MODE_X_ONNODE_12QUEUES = true; + +const uint32_t PB_HPX_MODE_NEXT_SHADOWS[PROC_BUILD_SMP_NUM_SHADOWS] = +{ + PB_HPX_MODE_NEXT_WEST_0x02010C0D, + PB_HPX_MODE_NEXT_CENT_0x02010C4D, + PB_HPX_MODE_NEXT_EAST_0x02010C8D +}; +const uint32_t PB_HPX_MODE_CURR_SHADOWS[PROC_BUILD_SMP_NUM_SHADOWS] = +{ + PB_HPX_MODE_CURR_WEST_0x02010C0E, + PB_HPX_MODE_CURR_CENT_0x02010C4E, + PB_HPX_MODE_CURR_EAST_0x02010C8E +}; + +// PB X Link Mode register field/bit definitions +const uint32_t PB_X_MODE_LINK_DELAY_START_BIT[PROC_FAB_SMP_NUM_X_LINKS] = { 24, 32, 40, 48 }; +const uint32_t PB_X_MODE_LINK_DELAY_END_BIT[PROC_FAB_SMP_NUM_X_LINKS] = { 31, 39, 47, 55 }; +// PB A Link Mode register field/bit definitions +const uint32_t PB_A_MODE_LINK_DELAY_START_BIT[PROC_FAB_SMP_NUM_A_LINKS] = { 40, 48, 56 }; +const uint32_t PB_A_MODE_LINK_DELAY_END_BIT[PROC_FAB_SMP_NUM_A_LINKS] = { 47, 55, 63 }; + +// PB A Link Framer Configuration register field/bit definitions +const uint32_t PB_A_FMR_CFG_OW_PACK_BIT = 24; +const uint32_t PB_A_FMR_CFG_OW_PACK_PRIORITY_BIT = 25; + +// PB IOF Link Mode register field/bit definitions +const uint32_t PB_IOF_MODE_LINK_DELAY_START_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 32, 48 }; +const uint32_t PB_IOF_MODE_LINK_DELAY_END_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 47, 63 }; + +// PB F Link Framer Configuration register field/bit definitions +const uint32_t PB_F_FMR_CFG_OW_PACK_BIT = 20; +const uint32_t PB_F_FMR_CFG_OW_PACK_PRIORITY_BIT = 21; + +extern "C" { //------------------------------------------------------------------------------ // Function definitions //------------------------------------------------------------------------------ - //------------------------------------------------------------------------------ // function: read PB A Link Framer Configuration register and determine // OW packing setup @@ -152,7 +260,7 @@ fapi::ReturnCode proc_build_smp_get_f_owpack_config( // i_link_en => per-link enable values // i_link_target => link endpoint targets // o_link_delay_local => array of link round trip delay values -// (measured by local chip) +// (measured by local chip) // o_link_delay_remote => array of link round trip delay values // (measured by remote chips) // o_link_number_remote => array of link numbers @@ -289,7 +397,128 @@ fapi::ReturnCode proc_build_smp_get_link_delays( } while(0); // mark function exit - FAPI_DBG("proc_build_smp_get_link_delays: Start"); + FAPI_DBG("proc_build_smp_get_link_delays: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: determine paramters of link/destination chip +// parameters: i_smp_chip => structure encapsulating SMP chip +// i_source_link_id => link identifier for FFDC +// i_dest_target => pointer to destination link endpoint target +// o_link_is_enabled => true=link enabled, false=link disabled +// o_dest_target_node_id => node ID of destination chip +// o_dest_target_chip_id => chip ID of destination chip +// returns: FAPI_RC_SUCCESS if output values are valid, +// RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is +// invalid, +// RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is +// invalid, +// RC_PROC_BUILD_SMP_AX_PARTIAL_GOOD_ERR if partial good attribute +// state does not allow for action on target, +// RC_PROC_BUILD_SMP_LINK_TARGET_TYPE_ERR if link target type is +// unsupported, +// else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_build_smp_query_link_state( + const proc_build_smp_chip& i_smp_chip, + const uint8_t i_source_link_id, + fapi::Target* i_dest_target, + bool& o_link_is_enabled, + proc_fab_smp_node_id& o_dest_target_node_id, + proc_fab_smp_chip_id& o_dest_target_chip_id) +{ + fapi::ReturnCode rc; + fapi::TargetType dest_target_type = i_dest_target->getType(); + bool src_link_region_pg = false; + uint8_t src_link_chiplet_id = 0xFF; + + FAPI_DBG("proc_build_smp_query_link_state: Start"); + + do + { + switch (dest_target_type) + { + case (fapi::TARGET_TYPE_NONE): + o_link_is_enabled = false; + o_dest_target_node_id = FBC_NODE_ID_0; + o_dest_target_chip_id = FBC_CHIP_ID_0; + break; + case (fapi::TARGET_TYPE_ABUS_ENDPOINT): + case (fapi::TARGET_TYPE_XBUS_ENDPOINT): + // destination target is valid, so mark link as enabled + o_link_is_enabled = true; + + // extract chip/node ID from destination chip + rc = proc_fab_smp_get_node_id_attr(i_dest_target, o_dest_target_node_id); + if (rc) + { + FAPI_ERR("proc_build_smp_query_link_state: Error from proc_fab_smp_get_node_id_attr"); + break; + } + + rc = proc_fab_smp_get_chip_id_attr(i_dest_target, o_dest_target_chip_id); + if (rc) + { + FAPI_ERR("proc_build_smp_query_link_state: Error from proc_fab_smp_get_chip_id_attr"); + break; + } + + // perform partial good attribute checking + // ABUS + if (dest_target_type == fapi::TARGET_TYPE_ABUS_ENDPOINT) + { + src_link_region_pg = i_smp_chip.a_enabled; + src_link_chiplet_id = 0x8; + } + // XBUS + else + { + src_link_region_pg = i_smp_chip.x_enabled; + src_link_chiplet_id = 0x4; + } + + // destination target is valid, but region on source chip containing + // connected link logic is not enabled, given state of partial good + // attributes + if (!src_link_region_pg) + { + // obtain VPD partial good attribute for FFDC + uint64_t src_link_region_pg_attr[32]; + rc = FAPI_ATTR_GET(ATTR_CHIP_REGIONS_TO_ENABLE, + &(i_smp_chip.chip->this_chip), + src_link_region_pg_attr); + + FAPI_ERR("proc_build_smp_query_link_state: Partial good attribute error (chiplet ID = 0x%02X)", + src_link_chiplet_id); + const fapi::Target& SOURCE_CHIP_TARGET = i_smp_chip.chip->this_chip; + const uint8_t& CHIPLET_ID = src_link_chiplet_id; + const uint8_t& SOURCE_LINK_ID = i_source_link_id; + const bool& REGION_ENABLED = src_link_region_pg; + const uint64_t& REGIONS_TO_ENABLE = src_link_region_pg_attr[src_link_chiplet_id]; + const bool& REGIONS_TO_ENABLE_VALID = rc.ok(); + const fapi::Target& DEST_LINK_TARGET = *(i_dest_target); + FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_AX_PARTIAL_GOOD_ERR); + break; + } + break; + default: + FAPI_ERR("proc_build_smp_query_link_state: Unsupported destination link target type!"); + const fapi::Target& SOURCE_CHIP_TARGET = i_smp_chip.chip->this_chip; + const uint8_t& SOURCE_LINK_ID = i_source_link_id; + const fapi::Target& DEST_LINK_TARGET = *(i_dest_target); + FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_LINK_TARGET_TYPE_ERR); + break; + } + if (!rc.ok()) + { + break; + } + + } while(0); + + FAPI_DBG("proc_build_smp_query_link_state: End"); return rc; } @@ -373,7 +602,21 @@ fapi::ReturnCode proc_build_smp_calc_link_setup( // currently procedure does not support aggregate F links if (!i_allow_aggregate || o_link_aggregate) { + uint8_t first_id = 0; + for (first_id = 0; first_id < id; first_id++) + { + if (id_active_count[first_id] > 1) + { + break; + } + } + FAPI_ERR("proc_build_smp_calc_link_setup: Invalid aggregate link configuration"); + const fapi::Target& TARGET = i_smp_chip.chip->this_chip; + const bool& X_NOT_A = i_x_not_a; + const bool& ALLOW_AGGREGATE = i_allow_aggregate; + const uint8_t& AGGREGATE_DEST_ID1 = first_id; + const uint8_t& AGGREGATE_DEST_ID2 = id; FAPI_SET_HWP_ERROR( rc, RC_PROC_BUILD_SMP_INVALID_AGGREGATE_CONFIG_ERR); @@ -550,7 +793,15 @@ fapi::ReturnCode proc_build_smp_calc_x_cmd_rate( (cmd_rate > PB_HPX_MODE_X_CMD_RATE_MAX_VALUE)) { FAPI_ERR("proc_build_smp_calc_x_cmd_rate: X link command rate is out of range"); - const uint32_t & CMD_RATE = cmd_rate; + const uint32_t& FREQ_PB = i_freq_pb; + const uint32_t& FREQ_X = i_freq_x; + const bool& X_IS_8B = i_x_is_8B; + const bool& X_AGGREGATE = i_x_aggregate; + const uint32_t& N = n; + const uint32_t& D = d; + const uint32_t& CMD_RATE = cmd_rate; + const uint32_t& MIN_CMD_RATE = PB_HPX_MODE_X_CMD_RATE_MIN_VALUE; + const uint32_t& MAX_CMD_RATE = PB_HPX_MODE_X_CMD_RATE_MAX_VALUE; FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_X_CMD_RATE_ERR); break; @@ -615,7 +866,16 @@ fapi::ReturnCode proc_build_smp_calc_a_cmd_rate( (cmd_rate > PB_HP_MODE_A_CMD_RATE_MAX_VALUE)) { FAPI_ERR("proc_build_smp_calc_a_cmd_rate: A link command rate is out of range"); - const uint32_t & CMD_RATE = cmd_rate; + const uint32_t& FREQ_PB = i_freq_pb; + const uint32_t& FREQ_A = i_freq_a; + const bool& A_OW_PACK = i_a_ow_pack; + const bool& A_OW_PACK_PRIORITY = i_a_ow_pack_priority; + const bool& A_AGGREGATE = i_a_aggregate; + const uint32_t& N = n; + const uint32_t& D = d; + const uint32_t& CMD_RATE = cmd_rate; + const uint32_t& MIN_CMD_RATE = PB_HP_MODE_A_CMD_RATE_MIN_VALUE; + const uint32_t& MAX_CMD_RATE = PB_HP_MODE_A_CMD_RATE_MAX_VALUE; FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_A_CMD_RATE_ERR); break; @@ -625,7 +885,7 @@ fapi::ReturnCode proc_build_smp_calc_a_cmd_rate( o_a_cmd_rate = (uint8_t) cmd_rate; // mark function exit - FAPI_DBG("proc_build_smp_calc_a_cmd_rate: Start"); + FAPI_DBG("proc_build_smp_calc_a_cmd_rate: End"); return rc; } @@ -655,7 +915,7 @@ fapi::ReturnCode proc_build_smp_calc_f_cmd_rate( uint32_t n_ow_pack = 0; uint32_t cmd_rate; - // mark function exit + // mark function entry FAPI_DBG("proc_build_smp_calc_f_cmd_rate: Start"); do @@ -683,7 +943,16 @@ fapi::ReturnCode proc_build_smp_calc_f_cmd_rate( (cmd_rate > PB_HP_MODE_F_CMD_RATE_MAX_VALUE)) { FAPI_ERR("proc_build_smp_calc_f_cmd_rate: F link command rate is out of range"); - const uint32_t & CMD_RATE = cmd_rate; + const uint32_t& FREQ_PB = i_freq_pb; + const uint32_t& FREQ_F = i_freq_f; + const bool& F_OW_PACK = i_f_ow_pack; + const bool& F_OW_PACK_PRIORITY = i_f_ow_pack_priority; + const bool& F_AGGREGATE = i_f_aggregate; + const uint32_t& N = n; + const uint32_t& D = d; + const uint32_t& CMD_RATE = cmd_rate; + const uint32_t& MIN_CMD_RATE = PB_HP_MODE_F_CMD_RATE_MIN_VALUE; + const uint32_t& MAX_CMD_RATE = PB_HP_MODE_F_CMD_RATE_MAX_VALUE; FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_F_CMD_RATE_ERR); break; @@ -774,6 +1043,7 @@ fapi::ReturnCode proc_build_smp_get_hotplug_curr_reg( ecmdDataBufferBase& o_data) { fapi::ReturnCode rc; + uint32_t rc_ecmd = 0; ecmdDataBufferBase data(64); // mark function entry @@ -817,7 +1087,14 @@ fapi::ReturnCode proc_build_smp_get_hotplug_curr_reg( } // set output (will be used to compare with next HW read) - data.copy(o_data); + rc_ecmd |= data.copy(o_data); + if (rc_ecmd) + { + FAPI_ERR("proc_build_smp_get_hotplug_curr_reg: Error 0x%x copying register data buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } } // mark function exit @@ -827,49 +1104,52 @@ fapi::ReturnCode proc_build_smp_get_hotplug_curr_reg( //------------------------------------------------------------------------------ -// function: reset (copy CURR->NEXT) PB Hotplug Mode register -// parameters: i_smp_chip => structure encapsulating SMP chip +// function: reset (copy CURR->NEXT) PB Hotplug Mode/Mode Extension register +// parameters: i_smp_chip => structure encapsulating SMP chip +// i_hp_not_hpx => choose HP/HPX register set (true=HP, +// false=HPX) // returns: FAPI_RC_SUCCESS if register programming is successful, // RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if shadow registers are not // equivalent, // else error //------------------------------------------------------------------------------ -fapi::ReturnCode proc_build_smp_reset_pb_hp_mode( - const proc_build_smp_chip& i_smp_chip) +fapi::ReturnCode proc_build_smp_reset_hotplug_next_reg( + const proc_build_smp_chip& i_smp_chip, + const bool i_hp_not_hpx) { fapi::ReturnCode rc; ecmdDataBufferBase data(64); // mark function entry - FAPI_DBG("proc_build_smp_reset_pb_hp_mode: Start"); + FAPI_DBG("proc_build_smp_reset_hotplug_next_reg: Start"); do { // read CURR state rc = proc_build_smp_get_hotplug_curr_reg(i_smp_chip, - true, + i_hp_not_hpx, data); if (!rc.ok()) { - FAPI_ERR("proc_build_smp_reset_pb_hp_mode: proc_build_smp_get_hotplug_curr_reg"); + FAPI_ERR("proc_build_smp_reset_hotplug_next_reg: proc_build_smp_get_hotplug_curr_reg"); break; } // write NEXT state rc = proc_build_smp_set_hotplug_reg(i_smp_chip, false, - true, + i_hp_not_hpx, data); if (!rc.ok()) { - FAPI_ERR("proc_build_smp_reset_pb_hp_mode: proc_build_smp_set_hotplug_reg"); + FAPI_ERR("proc_build_smp_reset_hotplug_next_reg: proc_build_smp_set_hotplug_reg"); break; } } while(0); // mark function exit - FAPI_DBG("proc_build_smp_reset_pb_hp_mode: End"); + FAPI_DBG("proc_build_smp_reset_hotplug_next_reg: End"); return rc; } @@ -889,6 +1169,12 @@ fapi::ReturnCode proc_build_smp_reset_pb_hp_mode( // is invalid, // RC_PROC_BUILD_SMP_F_CMD_RATE_ERR if calculated F link command rate // is invalid, +// RC_PROC_BUILD_SMP_AX_PARTIAL_GOOD_ERR if partial good attribute +// state does not allow for action on target, +// RC_PROC_BUILD_SMP_PCIE_PARTIAL_GOOD_ERR if partial good attribute +// state does not allow for action on target, +// RC_PROC_BUILD_SMP_LINK_TARGET_TYPE_ERR if link target type is +// unsupported, // else error //------------------------------------------------------------------------------ fapi::ReturnCode proc_build_smp_set_pb_hp_mode( @@ -935,26 +1221,20 @@ fapi::ReturnCode proc_build_smp_set_pb_hp_mode( a_target[2] = &(i_smp_chip.chip->a2_chip); for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_A_LINKS; l++) { - // determine link enable - a_en[l] = (a_target[l]->getType() != fapi::TARGET_TYPE_NONE); - if (a_en[l] && !i_smp_chip.a_enabled) + // determine link enable/ID + proc_fab_smp_node_id dest_node_id; + proc_fab_smp_chip_id dest_chip_id; + rc = proc_build_smp_query_link_state(i_smp_chip, + l, + a_target[l], + a_en[l], + dest_node_id, + dest_chip_id); + if (!rc.ok()) { - FAPI_ERR("proc_build_smp_set_pb_hp_mode: Partial good attribute error (A)"); - FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_A_PARTIAL_GOOD_ERR); + FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_query_link_state"); break; } - - // determine link ID - proc_fab_smp_node_id dest_node_id = FBC_NODE_ID_0; - if (a_en[l]) - { - rc = proc_fab_smp_get_node_id_attr(a_target[l], dest_node_id); - if (rc) - { - FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_fab_smp_get_node_id_attr"); - break; - } - } a_id[l] = (uint8_t) dest_node_id; } if (rc) @@ -975,7 +1255,21 @@ fapi::ReturnCode proc_build_smp_set_pb_hp_mode( { if (f_en[l] && !i_smp_chip.pcie_enabled) { + // obtain partial good attribute for FFDC + uint8_t src_link_chiplet_id = 0x9; + uint64_t src_link_region_pg_attr[32]; + rc = FAPI_ATTR_GET(ATTR_CHIP_REGIONS_TO_ENABLE, + &(i_smp_chip.chip->this_chip), + src_link_region_pg_attr); + FAPI_ERR("proc_build_smp_set_pb_hp_mode: Partial good attribute error (PCIE)"); + const fapi::Target& SOURCE_CHIP_TARGET = i_smp_chip.chip->this_chip; + const uint8_t& CHIPLET_ID = src_link_chiplet_id; + const uint8_t& SOURCE_LINK_ID = l; + const bool& REGION_ENABLED = i_smp_chip.pcie_enabled; + const uint64_t& REGIONS_TO_ENABLE = src_link_region_pg_attr[src_link_chiplet_id]; + const bool& REGIONS_TO_ENABLE_VALID = rc.ok(); + const uint8_t& DEST_NODE_ID = f_id[l]; FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_PCIE_PARTIAL_GOOD_ERR); break; } @@ -1229,53 +1523,6 @@ fapi::ReturnCode proc_build_smp_set_pb_hp_mode( //------------------------------------------------------------------------------ -// function: reset (copy CURR->NEXT) PB Hotplug Extension Mode register -// parameters: i_smp_chip => structure encapsulating SMP chip -// returns: FAPI_RC_SUCCESS if register programming is successful, -// RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if shadow registers are not -// equivalent, -// else error -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_build_smp_reset_pb_hpx_mode( - const proc_build_smp_chip& i_smp_chip) -{ - fapi::ReturnCode rc; - ecmdDataBufferBase data(64); - - // mark function entry - FAPI_DBG("proc_build_smp_reset_pb_hpx_mode: Start"); - - do - { - // read CURR state - rc = proc_build_smp_get_hotplug_curr_reg(i_smp_chip, - false, - data); - if (!rc.ok()) - { - FAPI_ERR("proc_build_smp_reset_pb_hpx_mode: proc_build_smp_get_hotplug_curr_reg"); - break; - } - - // write NEXT state - rc = proc_build_smp_set_hotplug_reg(i_smp_chip, - false, - false, - data); - if (!rc.ok()) - { - FAPI_ERR("proc_build_smp_reset_pb_hpx_mode: proc_build_smp_set_hotplug_reg"); - break; - } - } while(0); - - // mark function exit - FAPI_DBG("proc_build_smp_reset_pb_hpx_mode: End"); - return rc; -} - - -//------------------------------------------------------------------------------ // function: program PB Hotplug Extension Mode register // parameters: i_smp_chip => structure encapsulating SMP chip // i_smp => structure encapsulating SMP topology @@ -1288,6 +1535,10 @@ fapi::ReturnCode proc_build_smp_reset_pb_hpx_mode( // specifies invalid aggregate link setup, // RC_PROC_BUILD_SMP_X_CMD_RATE_ERR if calculated X link command rate // is invalid, +// RC_PROC_BUILD_SMP_AX_PARTIAL_GOOD_ERR if partial good attribute +// state does not allow for action on target, +// RC_PROC_BUILD_SMP_LINK_TARGET_TYPE_ERR if link target type is +// unsupported, // else error //------------------------------------------------------------------------------ fapi::ReturnCode proc_build_smp_set_pb_hpx_mode( @@ -1324,26 +1575,20 @@ fapi::ReturnCode proc_build_smp_set_pb_hpx_mode( x_target[3] = &(i_smp_chip.chip->x3_chip); for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_X_LINKS; l++) { - // determine link enable - x_en[l] = (x_target[l]->getType() != fapi::TARGET_TYPE_NONE); - if (x_en[l] && !i_smp_chip.x_enabled) + // determine link enable/ID + proc_fab_smp_node_id dest_node_id; + proc_fab_smp_chip_id dest_chip_id; + rc = proc_build_smp_query_link_state(i_smp_chip, + l, + x_target[l], + x_en[l], + dest_node_id, + dest_chip_id); + if (!rc.ok()) { - FAPI_ERR("proc_build_smp_set_pb_hpx_mode: Partial good attribute error (X)"); - FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_X_PARTIAL_GOOD_ERR); + FAPI_ERR("proc_build_smp_set_pb_hpx_mode: Error from proc_build_smp_query_link_state"); break; } - - // determine link ID - proc_fab_smp_chip_id dest_chip_id = FBC_CHIP_ID_0; - if (x_en[l]) - { - rc = proc_fab_smp_get_chip_id_attr(x_target[l], dest_chip_id); - if (rc) - { - FAPI_ERR("proc_build_smp_set_pb_hpx_mode: Error from proc_fab_smp_get_chip_id_attr"); - break; - } - } x_id[l] = (uint8_t) dest_chip_id; } if (rc) @@ -1558,14 +1803,14 @@ fapi::ReturnCode proc_build_smp_set_fbc_ab( (p_iter != n_iter->second.chips.end()) && (rc.ok()); p_iter++) { - rc = proc_build_smp_reset_pb_hp_mode(p_iter->second); + rc = proc_build_smp_reset_hotplug_next_reg(p_iter->second, true); if (!rc.ok()) { FAPI_ERR("proc_build_smp_set_fbc_ab: Error from proc_build_smp_reset_pb_hp_mode"); break; } - rc = proc_build_smp_reset_pb_hpx_mode(p_iter->second); + rc = proc_build_smp_reset_hotplug_next_reg(p_iter->second, false); if (!rc.ok()) { FAPI_ERR("proc_build_smp_set_fbc_ab: Error from proc_build_smp_reset_pb_hpx_mode"); diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.H index 0959343ef..389da1c34 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.H +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_fbc_ab.H,v 1.2 2012/09/05 03:12:18 jmcgill Exp $ +// $Id: proc_build_smp_fbc_ab.H,v 1.3 2014/02/23 21:41:07 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_ab.H,v $ //------------------------------------------------------------------------------ // *| @@ -41,12 +41,8 @@ //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ -#include "proc_build_smp.H" -#include "p8_scom_addresses.H" - -//------------------------------------------------------------------------------ -// Structure definitions -//------------------------------------------------------------------------------ +#include <proc_build_smp.H> +#include <p8_scom_addresses.H> //------------------------------------------------------------------------------ @@ -54,112 +50,8 @@ //------------------------------------------------------------------------------ // PB Hotplug Mode register field/bit definitions -const uint32_t PB_HP_MODE_LINK_A_EN_BIT[PROC_FAB_SMP_NUM_A_LINKS] = { 1, 2, 3 }; -const uint32_t PB_HP_MODE_LINK_A_ADDR_DIS_BIT[PROC_FAB_SMP_NUM_A_LINKS] = { 4, 5, 6 }; -const uint32_t PB_HP_MODE_LINK_A_ID_START_BIT[PROC_FAB_SMP_NUM_A_LINKS] = { 7, 10, 13 }; -const uint32_t PB_HP_MODE_LINK_A_ID_END_BIT[PROC_FAB_SMP_NUM_A_LINKS] = { 9, 12, 15 }; - -const uint32_t PB_HP_MODE_PCIE_NOT_DSMP_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 38, 39 }; -const uint32_t PB_HP_MODE_LINK_F_MASTER_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 42, 43 }; -const uint32_t PB_HP_MODE_LINK_F_EN_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 44, 45 }; -const uint32_t PB_HP_MODE_LINK_F_ADDR_DIS_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 46, 47 }; -const uint32_t PB_HP_MODE_LINK_F_ID_START_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 48, 51 }; -const uint32_t PB_HP_MODE_LINK_F_ID_END_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 50, 53 }; - const uint32_t PB_HP_MODE_MASTER_CHIP_BIT = 0; -const uint32_t PB_HP_MODE_A_AGGREGATE_BIT = 16; -const uint32_t PB_HP_MODE_TM_MASTER_BIT = 17; const uint32_t PB_HP_MODE_CHG_RATE_GP_MASTER_BIT = 18; -const uint32_t PB_HP_MODE_CHG_RATE_SP_MASTER_BIT = 19; -const uint32_t PB_HP_MODE_PUMP_MODE_BIT = 20; -const uint32_t PB_HP_MODE_SINGLE_MC_BIT = 21; -const uint32_t PB_HP_MODE_DCACHE_CAPP_MODE_BIT = 22; -const uint32_t PB_HP_MODE_A_CMD_RATE_START_BIT = 24; -const uint32_t PB_HP_MODE_A_CMD_RATE_END_BIT = 31; -const uint32_t PB_HP_MODE_A_CMD_RATE_MIN_VALUE = 1; -const uint32_t PB_HP_MODE_A_CMD_RATE_MAX_VALUE = 0x7F; -const uint32_t PB_HP_MODE_A_GATHER_ENABLE_BIT = 32; -const uint32_t PB_HP_MODE_A_GATHER_DLY_CNT_START_BIT = 33; -const uint32_t PB_HP_MODE_A_GATHER_DLY_CNT_END_BIT = 37; -const uint32_t PB_HP_MODE_GATHER_ENABLE_BIT = 40; -const uint32_t PB_HP_MODE_F_AGGREGATE_BIT = 55; -const uint32_t PB_HP_MODE_F_CMD_RATE_START_BIT = 56; -const uint32_t PB_HP_MODE_F_CMD_RATE_END_BIT = 63; -const uint32_t PB_HP_MODE_F_CMD_RATE_MIN_VALUE = 1; -const uint32_t PB_HP_MODE_F_CMD_RATE_MAX_VALUE = 0x7F; - -const bool PB_HP_MODE_DCACHE_CAPP_EN = false; -const bool PB_HP_MODE_A_GATHER_ENABLE = true; -const uint8_t PB_HP_MODE_A_GATHER_DLY_CNT = 0x04; -const bool PB_HP_MODE_GATHER_ENABLE = true; - -const uint32_t PB_HP_MODE_NEXT_SHADOWS[PROC_BUILD_SMP_NUM_SHADOWS] = -{ - PB_HP_MODE_NEXT_WEST_0x02010C0B, - PB_HP_MODE_NEXT_CENT_0x02010C4B, - PB_HP_MODE_NEXT_EAST_0x02010C8B -}; -const uint32_t PB_HP_MODE_CURR_SHADOWS[PROC_BUILD_SMP_NUM_SHADOWS] = -{ - PB_HP_MODE_CURR_WEST_0x02010C0C, - PB_HP_MODE_CURR_CENT_0x02010C4C, - PB_HP_MODE_CURR_EAST_0x02010C8C -}; - -// PB Hotplug Extension Mode register field/bit definitions -const uint32_t PB_HPX_MODE_LINK_X_EN_BIT[PROC_FAB_SMP_NUM_X_LINKS] = { 0, 1, 2, 3 }; -const uint32_t PB_HPX_MODE_LINK_X_ADDR_DIS_BIT[PROC_FAB_SMP_NUM_X_LINKS] = { 5, 6, 7, 8 }; -const uint32_t PB_HPX_MODE_LINK_X_CHIPID_START_BIT[PROC_FAB_SMP_NUM_X_LINKS] = { 10, 13, 16, 19 }; -const uint32_t PB_HPX_MODE_LINK_X_CHIPID_END_BIT[PROC_FAB_SMP_NUM_X_LINKS] = { 12, 15, 18, 21 }; - -const uint32_t PB_HPX_MODE_X_AGGREGATE_BIT = 25; -const uint32_t PB_HPX_MODE_X_INDIRECT_EN_BIT = 26; -const uint32_t PB_HPX_MODE_X_GATHER_ENABLE_BIT = 32; -const uint32_t PB_HPX_MODE_X_GATHER_DLY_CNT_START_BIT = 33; -const uint32_t PB_HPX_MODE_X_GATHER_DLY_CNT_END_BIT = 37; -const uint32_t PB_HPX_MODE_X_ONNODE_12QUEUES_BIT = 38; -const uint32_t PB_HPX_MODE_X_CMD_RATE_START_BIT = 56; -const uint32_t PB_HPX_MODE_X_CMD_RATE_END_BIT = 63; -const uint32_t PB_HPX_MODE_X_CMD_RATE_MIN_VALUE = 1; -const uint32_t PB_HPX_MODE_X_CMD_RATE_MAX_VALUE = 0x7F; - -const bool PB_HPX_MODE_X_INDIRECT_EN = true; -const bool PB_HPX_MODE_X_GATHER_ENABLE = true; -const uint8_t PB_HPX_MODE_X_GATHER_DLY_CNT = 0x04; -const bool PB_HPX_MODE_X_ONNODE_12QUEUES = true; - -const uint32_t PB_HPX_MODE_NEXT_SHADOWS[PROC_BUILD_SMP_NUM_SHADOWS] = -{ - PB_HPX_MODE_NEXT_WEST_0x02010C0D, - PB_HPX_MODE_NEXT_CENT_0x02010C4D, - PB_HPX_MODE_NEXT_EAST_0x02010C8D -}; -const uint32_t PB_HPX_MODE_CURR_SHADOWS[PROC_BUILD_SMP_NUM_SHADOWS] = -{ - PB_HPX_MODE_CURR_WEST_0x02010C0E, - PB_HPX_MODE_CURR_CENT_0x02010C4E, - PB_HPX_MODE_CURR_EAST_0x02010C8E -}; - -// PB X Link Mode register field/bit definitions -const uint32_t PB_X_MODE_LINK_DELAY_START_BIT[PROC_FAB_SMP_NUM_X_LINKS] = { 24, 32, 40, 48 }; -const uint32_t PB_X_MODE_LINK_DELAY_END_BIT[PROC_FAB_SMP_NUM_X_LINKS] = { 31, 39, 47, 55 }; - -// PB A Link Mode register field/bit definitions -const uint32_t PB_A_MODE_LINK_DELAY_START_BIT[PROC_FAB_SMP_NUM_A_LINKS] = { 40, 48, 56 }; -const uint32_t PB_A_MODE_LINK_DELAY_END_BIT[PROC_FAB_SMP_NUM_A_LINKS] = { 47, 55, 63 }; - -// PB A Link Framer Configuration register field/bit definitions -const uint32_t PB_A_FMR_CFG_OW_PACK_BIT = 24; -const uint32_t PB_A_FMR_CFG_OW_PACK_PRIORITY_BIT = 25; - -// PB IOF Link Mode register field/bit definitions -const uint32_t PB_IOF_MODE_LINK_DELAY_START_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 32, 48 }; -const uint32_t PB_IOF_MODE_LINK_DELAY_END_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 47, 63 }; - -// PB F Link Framer Configuration register field/bit definitions -const uint32_t PB_F_FMR_CFG_OW_PACK_BIT = 20; -const uint32_t PB_F_FMR_CFG_OW_PACK_PRIORITY_BIT = 21; extern "C" { @@ -169,6 +61,34 @@ extern "C" //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ +// function: determine paramters of link/destination chip +// parameters: i_smp_chip => structure encapsulating SMP chip +// i_source_link_id => link identifier for FFDC +// i_dest_target => pointer to destination link endpoint target +// o_link_is_enabled => true=link enabled, false=link disabled +// o_dest_target_node_id => node ID of destination chip +// o_dest_target_chip_id => chip ID of destination chip +// returns: FAPI_RC_SUCCESS if output values are valid, +// RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is +// invalid, +// RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is +// invalid, +// RC_PROC_BUILD_SMP_AX_PARTIAL_GOOD_ERR if partial good attribute +// state does not allow for action on target, +// RC_PROC_BUILD_SMP_LINK_TARGET_TYPE_ERR if link target type is +// unsupported, +// else error +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_build_smp_query_link_state( + const proc_build_smp_chip& i_smp_chip, + const uint8_t i_source_link_id, + fapi::Target* i_dest_target, + bool& o_link_is_enabled, + proc_fab_smp_node_id& o_dest_target_node_id, + proc_fab_smp_chip_id& o_dest_target_chip_id); + + +//------------------------------------------------------------------------------ // function: utility function to read set of PB CURR hotplug registers // parameters: i_smp_chip => structure encapsulating SMP chip // i_hp_not_hpx => choose HP/HPX register set (true=HP, @@ -192,6 +112,16 @@ fapi::ReturnCode proc_build_smp_get_hotplug_curr_reg( // i_op => enumerated type representing SMP build phase // returns: FAPI_RC_SUCCESS if register reads are successful and all shadow // registers are equivalent, +// FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of +// ADU atomic lock, +// RC_PROC_ADU_UTILS_INVALID_LOCK_OPERATION if an unsupported operation +// is specified, +// RC_PROC_ADU_UTILS_INVALID_LOCK_ATTEMPTS if invalid number of attempts +// is specified, +// RC_PROC_ADU_UTILS_INVALID_FBC_OP if invalid fabric operation +// parameters are specified, +// RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH if ADU status mismatches +// for switch operation, // RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is // invalid, // RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is @@ -206,6 +136,14 @@ fapi::ReturnCode proc_build_smp_get_hotplug_curr_reg( // is invalid, // RC_PROC_BUILD_SMP_X_CMD_RATE_ERR if calculated X link command rate // is invalid, +// RC_PROC_BUILD_SMP_AX_PARTIAL_GOOD_ERR if partial good attribute +// state does not allow for action on target, +// RC_PROC_BUILD_SMP_PCIE_PARTIAL_GOOD_ERR if partial good attribute +// state does not allow for action on target, +// RC_PROC_BUILD_SMP_LINK_TARGET_TYPE_ERR if link target type is +// unsupported, +// RC_PROC_BUILD_SMP_INVALID_TOPOLOGY if specified fabric topology +// is illegal, // else error //------------------------------------------------------------------------------ fapi::ReturnCode proc_build_smp_set_fbc_ab( diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C index 67e76d127..bb004df12 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_fbc_cd.C,v 1.14 2014/01/18 18:31:03 jmcgill Exp $ +// $Id: proc_build_smp_fbc_cd.C,v 1.15 2014/02/23 21:41:07 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_cd.C,v $ //------------------------------------------------------------------------------ // *| @@ -39,11 +39,500 @@ //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ -#include "proc_build_smp_fbc_cd.H" -#include "proc_build_smp_adu.H" +#include <proc_build_smp_fbc_cd.H> +#include <proc_build_smp_adu.H> extern "C" { + +//------------------------------------------------------------------------------ +// Structure definitions +//------------------------------------------------------------------------------ + +// structure encapsulating serial configuration load programming +struct proc_build_smp_sconfig_def +{ + uint8_t select; // ID/select for chain + uint8_t length; // number of bits to load + bool use_slow_clock; // use 16:1 slow clock? (EX) + bool use_shadow[PROC_BUILD_SMP_NUM_SHADOWS]; // define which shadows to set +}; + + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +// +// PB Serial Configuration Load register field/bit definitions +// + +// hang level constants +const uint8_t PB_SCONFIG_NUM_HANG_LEVELS = 7; + +// CPU ratio constants +const uint8_t PB_SCONFIG_NUM_CPU_RATIOS = 4; + + +const uint32_t PB_SCONFIG_LOAD[PROC_BUILD_SMP_NUM_SHADOWS] = +{ + PB_SCONFIG_LOAD_WEST_0x02010C16, + PB_SCONFIG_LOAD_CENT_0x02010C6D, + PB_SCONFIG_LOAD_EAST_0x02010C96 +}; + +const uint32_t PB_SCONFIG_LOAD_START_BIT = 0; +const uint32_t PB_SCONFIG_LOAD_SLOW_BIT = 1; +const uint32_t PB_SCONFIG_SHIFT_COUNT_START_BIT = 2; +const uint32_t PB_SCONFIG_SHIFT_COUNT_END_BIT = 7; +const uint32_t PB_SCONFIG_SELECT_START_BIT = 8; +const uint32_t PB_SCONFIG_SELECT_END_BIT = 11; +const uint32_t PB_SCONFIG_SHIFT_DATA_START_BIT = 12; +const uint32_t PB_SCONFIG_SHIFT_DATA_END_BIT = 63; + + +// +// PBH_CMD_SNOOPER (center, chain #4) field/bit definitions +// + +const proc_build_smp_sconfig_def PB_SCONFIG_C4_DEF = { 0x4, 50, false, { false, true, false} }; + +const uint32_t PB_SCONFIG_C4_GP_LO_RTY_THRESHOLD_START_BIT = 14; +const uint32_t PB_SCONFIG_C4_GP_LO_RTY_THRESHOLD_END_BIT = 23; +const uint32_t PB_SCONFIG_C4_GP_HI_RTY_THRESHOLD_START_BIT = 24; +const uint32_t PB_SCONFIG_C4_GP_HI_RTY_THRESHOLD_END_BIT = 33; +const uint32_t PB_SCONFIG_C4_RGP_LO_RTY_THRESHOLD_START_BIT = 34; +const uint32_t PB_SCONFIG_C4_RGP_LO_RTY_THRESHOLD_END_BIT = 43; +const uint32_t PB_SCONFIG_C4_RGP_HI_RTY_THRESHOLD_START_BIT = 44; +const uint32_t PB_SCONFIG_C4_RGP_HI_RTY_THRESHOLD_END_BIT = 53; +const uint32_t PB_SCONFIG_C4_SP_LO_RTY_THRESHOLD_START_BIT = 54; +const uint32_t PB_SCONFIG_C4_SP_LO_RTY_THRESHOLD_END_BIT = 63; + +const uint32_t PB_SCONFIG_C4_GP_LO_RTY_THRESHOLD = 0x7; +const uint32_t PB_SCONFIG_C4_GP_HI_RTY_THRESHOLD = 0x5; +const uint32_t PB_SCONFIG_C4_RGP_LO_RTY_THRESHOLD = 0x5; +const uint32_t PB_SCONFIG_C4_RGP_HI_RTY_THRESHOLD = 0x4; +const uint32_t PB_SCONFIG_C4_SP_LO_RTY_THRESHOLD = 0x5; + + +// +// PBH_CMD_SNOOPER (center, chain #5) field/bit definitions +// + +const proc_build_smp_sconfig_def PB_SCONFIG_C5_DEF = { 0x5, 46, false, { false, true, false} }; + +const uint32_t PB_SCONFIG_C5_SP_HI_RTY_THRESHOLD_START_BIT = 18; +const uint32_t PB_SCONFIG_C5_SP_HI_RTY_THRESHOLD_END_BIT = 27; +const uint32_t PB_SCONFIG_C5_GP_CRESP_SAMPLE_TIME_START_BIT = 28; +const uint32_t PB_SCONFIG_C5_GP_CRESP_SAMPLE_TIME_END_BIT = 39; +const uint32_t PB_SCONFIG_C5_RGP_CRESP_SAMPLE_TIME_START_BIT = 40; +const uint32_t PB_SCONFIG_C5_RGP_CRESP_SAMPLE_TIME_END_BIT = 51; +const uint32_t PB_SCONFIG_C5_SP_CRESP_SAMPLE_TIME_START_BIT = 52; +const uint32_t PB_SCONFIG_C5_SP_CRESP_SAMPLE_TIME_END_BIT = 63; + +const uint32_t PB_SCONFIG_C5_SP_HI_RTY_THRESHOLD = 0x4; +const uint32_t PB_SCONFIG_C5_GP_CRESP_SAMPLE_TIME = 321; +const uint32_t PB_SCONFIG_C5_RGP_CRESP_SAMPLE_TIME = 539; +const uint32_t PB_SCONFIG_C5_SP_CRESP_SAMPLE_TIME = 781; + + +// +// PBH_CMD_SNOOPER (center, chain #6) field/bit definitions +// + +const proc_build_smp_sconfig_def PB_SCONFIG_C6_DEF = { 0x6, 42, false, { false, true, false} }; + +const uint32_t PB_SCONFIG_C6_GP_REQ_SAMPLE_TIME_START_BIT = 22; +const uint32_t PB_SCONFIG_C6_GP_REQ_SAMPLE_TIME_END_BIT = 33; +const uint32_t PB_SCONFIG_C6_SP_REQ_SAMPLE_TIME_START_BIT = 34; +const uint32_t PB_SCONFIG_C6_SP_REQ_SAMPLE_TIME_END_BIT = 45; +const uint32_t PB_SCONFIG_C6_GP_LO_JUMP_START_BIT = 46; +const uint32_t PB_SCONFIG_C6_GP_LO_JUMP_END_BIT = 48; +const uint32_t PB_SCONFIG_C6_GP_HI_JUMP_START_BIT = 49; +const uint32_t PB_SCONFIG_C6_GP_HI_JUMP_END_BIT = 51; +const uint32_t PB_SCONFIG_C6_SP_LO_JUMP_START_BIT = 52; +const uint32_t PB_SCONFIG_C6_SP_LO_JUMP_END_BIT = 54; +const uint32_t PB_SCONFIG_C6_SP_HI_JUMP_START_BIT = 55; +const uint32_t PB_SCONFIG_C6_SP_HI_JUMP_END_BIT = 57; +const uint32_t PB_SCONFIG_C6_RGP_LO_JUMP_START_BIT = 58; +const uint32_t PB_SCONFIG_C6_RGP_LO_JUMP_END_BIT = 60; +const uint32_t PB_SCONFIG_C6_RGP_HI_JUMP_START_BIT = 61; +const uint32_t PB_SCONFIG_C6_RGP_HI_JUMP_END_BIT = 63; + +const uint32_t PB_SCONFIG_C6_GP_REQ_SAMPLE_TIME = 1024; +const uint32_t PB_SCONFIG_C6_SP_REQ_SAMPLE_TIME = 1024; +const uint32_t PB_SCONFIG_C6_GP_LO_JUMP = 0x2; +const uint32_t PB_SCONFIG_C6_GP_HI_JUMP = 0x2; +const uint32_t PB_SCONFIG_C6_SP_LO_JUMP = 0x2; +const uint32_t PB_SCONFIG_C6_SP_HI_JUMP = 0x2; +const uint32_t PB_SCONFIG_C6_RGP_LO_JUMP = 0x2; +const uint32_t PB_SCONFIG_C6_RGP_HI_JUMP = 0x2; + + +// +// PBH_CMD_SNOOPER (center, chain #7) field/bit definitions +// + +const proc_build_smp_sconfig_def PB_SCONFIG_C7_DEF = { 0x7, 36, false, { false, true, false } }; + +const uint32_t PB_SCONFIG_C7_HANG_CMD_RATE_START_BIT[PB_SCONFIG_NUM_HANG_LEVELS] = { 28, 33, 38, 43, 48, 53, 58 }; +const uint32_t PB_SCONFIG_C7_HANG_CMD_RATE_END_BIT[PB_SCONFIG_NUM_HANG_LEVELS] = { 32, 37, 42, 47, 52, 57, 62 }; +const uint32_t PB_SCONFIG_C7_SLOW_GO_RATE_BIT = 63; + +// PB_CFG_HANG0_CMD_RATE = 0x00 = 127/128 +// PB_CFG_HANG1_CMD_RATE = 0x06 = 1/2 +// PB_CFG_HANG2_CMD_RATE = 0x0D = 1/512 +// PB_CFG_HANG3_CMD_RATE = 0x00 = 127/128 +// PB_CFG_HANG4_CMD_RATE = 0x1E = 1/4096 (toad mode) +// PB_CFG_HANG5_CMD_RATE = 0x19 = 1/8 (toad mode) +// PB_CFG_HANG6_CMD_RATE = 0x00 = 127/128 +const uint8_t PB_SCONFIG_C7_HANG_CMD_RATE[PB_SCONFIG_NUM_HANG_LEVELS] = { 0x00, 0x06, 0x0D, 0x00, 0x1E, 0x19, 0x00 }; +const bool PB_SCONFIG_C7_SLOW_GO_RATE = true; + + +// +// PBH_CMD_SNOOPER (center, chain #8) field/bit definitions +// + +const proc_build_smp_sconfig_def PB_SCONFIG_C8_DEF_VER1 = { 0x8, 37, false, { false, true, false } }; +const proc_build_smp_sconfig_def PB_SCONFIG_C8_DEF_VER2 = { 0x8, 39, false, { false, true, false } }; +const proc_build_smp_sconfig_def PB_SCONFIG_C8_DEF_VER3 = { 0x8, 43, false, { false, true, false } }; + +const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT_VER1[PB_SCONFIG_NUM_HANG_LEVELS] = { 27, 31, 35, 39, 43, 47, 51 }; +const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT_VER1[PB_SCONFIG_NUM_HANG_LEVELS] = { 30, 34, 38, 42, 46, 50, 54 }; +const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT_VER1 = 55; +const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT_VER1 = 57; +const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT_VER1 = 58; +const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT_VER1 = 63; + +const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT_VER2[PB_SCONFIG_NUM_HANG_LEVELS] = { 25, 29, 33, 37, 41, 45, 49 }; +const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT_VER2[PB_SCONFIG_NUM_HANG_LEVELS] = { 28, 32, 36, 40, 44, 48, 52 }; +const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT_VER2 = 53; +const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT_VER2 = 55; +const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT_VER2 = 56; +const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT_VER2 = 61; +const uint32_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT_VER2 = 62; +const uint32_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT_VER2 = 63; + +const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT_VER3[PB_SCONFIG_NUM_HANG_LEVELS] = { 21, 25, 29, 33, 37, 41, 45 }; +const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT_VER3[PB_SCONFIG_NUM_HANG_LEVELS] = { 24, 28, 32, 36, 40, 44, 48 }; +const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT_VER3 = 49; +const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT_VER3 = 51; +const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT_VER3 = 52; +const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT_VER3 = 57; +const uint32_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT_VER3 = 58; +const uint32_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT_VER3 = 59; +const uint32_t PB_SCONFIG_C8_RTY_PERCENTAGE_START_BIT_VER3 = 60; +const uint32_t PB_SCONFIG_C8_RTY_PERCENTAGE_END_BIT_VER3 = 62; +const uint32_t PB_SCONFIG_C8_INCLUDE_LPC_RTY_BIT_VER3 = 63; + +const uint8_t PB_SCONFIG_C8_HANG_CMD_RATE[PB_SCONFIG_NUM_HANG_LEVELS] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; +const uint8_t PB_SCONFIG_C8_CPO_JUMP_LEVEL = 0x7; +const uint8_t PB_SCONFIG_C8_CPO_RTY_LEVEL = 0x4; + +const uint8_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF = 0x2; // backoff_1k + +const uint8_t PB_SCONFIG_C8_RTY_PERCENTAGE = 0x0; // 000 +const uint8_t PB_SCONFIG_C8_INCLUDE_LPC_RTY = 0x0; // off + +// +// PBH_CMD_CENTRAL_ARB (center, chain #9) field/bit definitions +// + +const proc_build_smp_sconfig_def PB_SCONFIG_C9_DEF = { 0x9, 44, false, { false, true, false } }; + +const uint32_t PB_SCONFIG_C9_CP_STARVE_LIMIT_START_BIT = 20; +const uint32_t PB_SCONFIG_C9_CP_STARVE_LIMIT_END_BIT = 27; +const uint32_t PB_SCONFIG_C9_GP_STARVE_LIMIT_START_BIT = 28; +const uint32_t PB_SCONFIG_C9_GP_STARVE_LIMIT_END_BIT = 35; +const uint32_t PB_SCONFIG_C9_RGP_STARVE_LIMIT_START_BIT = 36; +const uint32_t PB_SCONFIG_C9_RGP_STARVE_LIMIT_END_BIT = 43; +const uint32_t PB_SCONFIG_C9_SP_STARVE_LIMIT_START_BIT = 44; +const uint32_t PB_SCONFIG_C9_SP_STARVE_LIMIT_END_BIT = 51; +const uint32_t PB_SCONFIG_C9_FP_STARVE_LIMIT_START_BIT = 52; +const uint32_t PB_SCONFIG_C9_FP_STARVE_LIMIT_END_BIT = 59; +const uint32_t PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_START_BIT = 60; +const uint32_t PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_END_BIT = 61; +const uint32_t PB_SCONFIG_C9_UX_LOCAL_ARB_MODE_START_BIT = 62; +const uint32_t PB_SCONFIG_C9_UX_LOCAL_ARB_MODE_END_BIT = 63; + +const uint8_t PB_SCONFIG_C9_CP_STARVE_LIMIT = 0x10; +const uint8_t PB_SCONFIG_C9_GP_STARVE_LIMIT = 0x10; +const uint8_t PB_SCONFIG_C9_RGP_STARVE_LIMIT = 0x10; +const uint8_t PB_SCONFIG_C9_SP_STARVE_LIMIT = 0x10; +const uint8_t PB_SCONFIG_C9_FP_STARVE_LIMIT = 0x10; +const uint8_t PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_LFSR = 0x0; // LFSR_ONLY +const uint8_t PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_RR = 0x1; // RR_ONLY +const uint8_t PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_LFSR_ON_STARVATION_ELSE_RR = 0x2; // LFSR_ON_STARVATION_ELSE_RR +const uint8_t PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_RR_ON_STARVATION_ELSE_LFSR = 0x3; // RR_ON_STARVATION_ELSE_LFSR +const uint8_t PB_SCONFIG_C9_UX_LOCAL_ARB_MODE = 0x2; // LFSR_ON_STARVATION_ELSE_RR + + +// +// PBH_CMD_CENTRAL_ARB (center, chain #10) field/bit definitions +// + +const proc_build_smp_sconfig_def PB_SCONFIG_C10_DEF_VER1 = { 0xA, 20, false, { false, true, false } }; +const proc_build_smp_sconfig_def PB_SCONFIG_C10_DEF_VER2 = { 0xA, 23, false, { false, true, false } }; + +const uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT_VER1[PB_SCONFIG_NUM_CPU_RATIOS] = { 59, 54, 49, 44 }; +const uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT_VER1[PB_SCONFIG_NUM_CPU_RATIOS] = { 63, 58, 53, 48 }; + +const uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT_VER2[PB_SCONFIG_NUM_CPU_RATIOS] = { 56, 51, 46, 41 }; +const uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT_VER2[PB_SCONFIG_NUM_CPU_RATIOS] = { 60, 55, 50, 45 }; +const uint32_t PB_SCONFIG_C10_DAT_X_LINK_HOLDOFF_ENABLE_BIT_VER2 = 61; +const uint32_t PB_SCONFIG_C10_DAT_A_LINK_HOLDOFF_ENABLE_BIT_VER2 = 62; +const uint32_t PB_SCONFIG_C10_DAT_LINK_HOLDOFF_MULTIPLIER_BIT_VER2 = 63; + +const uint8_t PB_SCONFIG_C10_CMD_CPU_RATIO_TABLE[PROC_BUILD_SMP_CPU_DELAY_NUM_SETPOINTS] = { 15, 14, 13, 12, 11, 11, 10, 10, 9, 9, 8, 8, 7 }; + +const uint8_t PB_SCONFIG_C10_CMD_CPU_RATIO_QUARTER = 3; +const uint8_t PB_SCONFIG_C10_CMD_CPU_RATIO_HALF = 7; +const uint8_t PB_SCONFIG_C10_DAT_X_LINK_HOLDOFF_ENABLE = 0x0; // disable +const uint8_t PB_SCONFIG_C10_DAT_A_LINK_HOLDOFF_ENABLE = 0x0; // disable +const uint8_t PB_SCONFIG_C10_DAT_LINK_HOLDOFF_MULTIPLIER = 0x0; // x2 + + +// +// PBH_RSP_CRESP_ARB (center, chain #11) field/bit definitions +// + +const proc_build_smp_sconfig_def PB_SCONFIG_C11_DEF = { 0xB, 20, false, { false, true, false } }; + +const uint32_t PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[PB_SCONFIG_NUM_CPU_RATIOS] = { 59, 54, 49, 44 }; +const uint32_t PB_SCONFIG_C11_RSP_CPU_RATIO_END_BIT[PB_SCONFIG_NUM_CPU_RATIOS] = { 63, 58, 53, 48 }; + +const uint8_t PB_SCONFIG_C11_RSP_CPU_RATIO_TABLE[PROC_BUILD_SMP_CPU_DELAY_NUM_SETPOINTS] = { 16, 15, 14, 13, 12, 12, 11, 11, 10, 10, 9, 9, 8 }; + +const uint8_t PB_SCONFIG_C11_RSP_CPU_RATIO_QUARTER = 4; +const uint8_t PB_SCONFIG_C11_RSP_CPU_RATIO_HALF = 8; + +// +// PBH_PBIEX_EH (east/west, chain #0) field/bit definitions +// + +const proc_build_smp_sconfig_def PB_SCONFIG_WE0_DEF = { 0x0, 52, false, { true, false, true } }; + +const uint32_t PB_SCONFIG_WE0_CMD_C2I_DONE_LAUNCH_START_BIT = 12; +const uint32_t PB_SCONFIG_WE0_CMD_C2I_DONE_LAUNCH_END_BIT = 14; +const uint32_t PB_SCONFIG_WE0_CMD_C2I_LATE_RD_MODE_BIT = 15; +const uint32_t PB_SCONFIG_WE0_CMD_C2I_DELAY_SP_RD_START_BIT = 16; +const uint32_t PB_SCONFIG_WE0_CMD_C2I_DELAY_SP_RD_END_BIT = 17; +const uint32_t PB_SCONFIG_WE0_CMD_C2I_SPARE_MODE_BIT = 18; +const uint32_t PB_SCONFIG_WE0_PRSP_C2I_DONE_LAUNCH_BIT = 19; +const uint32_t PB_SCONFIG_WE0_PRSP_C2I_HW070772_DIS_BIT = 20; +const uint32_t PB_SCONFIG_WE0_PRSP_C2I_NOP_MODE_START_BIT = 21; +const uint32_t PB_SCONFIG_WE0_PRSP_C2I_NOP_MODE_END_BIT = 22; +const uint32_t PB_SCONFIG_WE0_PRSP_C2I_SPARE_MODE_BIT = 23; +const uint32_t PB_SCONFIG_WE0_CRSP_I2C_DVAL_LAUNCH_START_BIT = 24; +const uint32_t PB_SCONFIG_WE0_CRSP_I2C_DVAL_LAUNCH_END_BIT = 25; +const uint32_t PB_SCONFIG_WE0_CRSP_I2C_HSHAKE_BIT = 26; +const uint32_t PB_SCONFIG_WE0_CRSP_I2C_SPARE_MODE_BIT = 27; +const uint32_t PB_SCONFIG_WE0_DATA_I2C_DVAL_LAUNCH_START_BIT = 28; +const uint32_t PB_SCONFIG_WE0_DATA_I2C_DVAL_LAUNCH_END_BIT = 29; +const uint32_t PB_SCONFIG_WE0_DATA_I2C_SPARE_MODE_BIT = 30; +const uint32_t PB_SCONFIG_WE0_DATA_I2C_FORCE_FA_ALLOC_BIT = 31; +const uint32_t PB_SCONFIG_WE0_DATA_C2I_DONE_LAUNCH_START_BIT = 32; +const uint32_t PB_SCONFIG_WE0_DATA_C2I_DONE_LAUNCH_END_BIT = 33; +const uint32_t PB_SCONFIG_WE0_DATA_C2I_INITIAL_REQ_DLY_START_BIT = 34; +const uint32_t PB_SCONFIG_WE0_DATA_C2I_INITIAL_REQ_DLY_END_BIT = 36; +const uint32_t PB_SCONFIG_WE0_DATA_C2I_DCTR_LAUNCH_START_BIT = 37; +const uint32_t PB_SCONFIG_WE0_DATA_C2I_DCTR_LAUNCH_END_BIT = 38; +const uint32_t PB_SCONFIG_WE0_DATA_C2I_OUTSTANDING_REQ_COUNT_BIT = 39; +const uint32_t PB_SCONFIG_WE0_DATA_C2I_REQ_ID_ASSIGNMENT_MODE_BIT = 40; +const uint32_t PB_SCONFIG_WE0_DATA_C2I_ALLOW_FRAGMENTATION_BIT = 41; +const uint32_t PB_SCONFIG_WE0_DATA_C2I_SERIAL_DREQ_ID_BIT = 42; +const uint32_t PB_SCONFIG_WE0_DATA_C2I_SPARE_MODE_BIT = 43; +const uint32_t PB_SCONFIG_WE0_RCMD_I2C_DVAL_LAUNCH_START_BIT = 44; +const uint32_t PB_SCONFIG_WE0_RCMD_I2C_DVAL_LAUNCH_END_BIT = 45; +const uint32_t PB_SCONFIG_WE0_RCMD_I2C_HSHAKE_BIT = 46; +const uint32_t PB_SCONFIG_WE0_RCMD_I2C_SPARE_MODE_BIT = 47; +const uint32_t PB_SCONFIG_WE0_FP_I2C_DVAL_LAUNCH_START_BIT = 48; +const uint32_t PB_SCONFIG_WE0_FP_I2C_DVAL_LAUNCH_END_BIT = 49; +const uint32_t PB_SCONFIG_WE0_FP_I2C_HSHAKE_BIT = 50; +const uint32_t PB_SCONFIG_WE0_FP_I2C_SPARE_MODE_BIT = 51; +const uint32_t PB_SCONFIG_WE0_FP_C2I_DONE_LAUNCH_BIT = 52; +const uint32_t PB_SCONFIG_WE0_FP_C2I_SPARE_MODE_BIT = 53; +const uint32_t PB_SCONFIG_WE0_CPU_DELAY_FULL_START_BIT = 54; +const uint32_t PB_SCONFIG_WE0_CPU_DELAY_FULL_END_BIT = 58; +const uint32_t PB_SCONFIG_WE0_CPU_DELAY_NOM_START_BIT = 59; +const uint32_t PB_SCONFIG_WE0_CPU_DELAY_NOM_END_BIT = 63; + +const bool PB_SCONFIG_WE0_CMD_C2I_LATE_RD_MODE = true; // on +const uint8_t PB_SCONFIG_WE0_CMD_C2I_DELAY_SP_RD = 0x0; // rc_p1 +const bool PB_SCONFIG_WE0_CMD_C2I_SPARE_MODE = false; // spare +const uint8_t PB_SCONFIG_WE0_PRSP_C2I_DONE_LAUNCH = 0x0; // rc_p1 +const bool PB_SCONFIG_WE0_PRSP_C2I_HW070772_DIS = true; // on +const uint8_t PB_SCONFIG_WE0_PRSP_C2I_NOP_MODE = 0x0; // 16c +const bool PB_SCONFIG_WE0_PRSP_C2I_SPARE_MODE = false; // spare +const bool PB_SCONFIG_WE0_CRSP_I2C_HSHAKE = false; // off +const bool PB_SCONFIG_WE0_CRSP_I2C_SPARE_MODE = false; // spare +const bool PB_SCONFIG_WE0_DATA_I2C_SPARE_MODE = false; // spare +const bool PB_SCONFIG_WE0_DATA_I2C_FORCE_FA_ALLOC = false; // off +const uint8_t PB_SCONFIG_WE0_DATA_C2I_INITIAL_REQ_DLY = 0x7; // 7c +const bool PB_SCONFIG_WE0_DATA_C2I_OUTSTANDING_REQ_COUNT = false; // 8 +const bool PB_SCONFIG_WE0_DATA_C2I_REQ_ID_ASSIGNMENT_MODE = false; // FA +const bool PB_SCONFIG_WE0_DATA_C2I_ALLOW_FRAGMENTATION = true; // on +const bool PB_SCONFIG_WE0_DATA_C2I_SERIAL_DREQ_ID = true; // on +const bool PB_SCONFIG_WE0_DATA_C2I_SPARE_MODE = false; // spare +const bool PB_SCONFIG_WE0_RCMD_I2C_HSHAKE = false; // off +const bool PB_SCONFIG_WE0_RCMD_I2C_SPARE_MODE = false; // spare +const uint8_t PB_SCONFIG_WE0_FP_I2C_DVAL_LAUNCH = 0x0; // wc_p1 +const uint8_t PB_SCONFIG_WE0_FP_I2C_HSHAKE = false; // off +const bool PB_SCONFIG_WE0_FP_I2C_SPARE_MODE = false; // spare +const uint8_t PB_SCONFIG_WE0_FP_C2I_DONE_LAUNCH = 0x0; // rc_p1 +const bool PB_SCONFIG_WE0_FP_C2I_SPARE_MODE = false; // spare + +const uint8_t PB_SCONFIG_WE0_CPU_DELAY_TABLE[PROC_BUILD_SMP_CPU_DELAY_NUM_SETPOINTS] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 }; + + +// +// PBH_PBIEX_EX (east/west, chain #1) field/bit definitions +// + +const proc_build_smp_sconfig_def PB_SCONFIG_WE1_DEF = { 0x1, 38, true, { true, false, true } }; + +const uint32_t PB_SCONFIG_WE1_CMD_C2I_DVAL_LAUNCH_START_BIT = 26; +const uint32_t PB_SCONFIG_WE1_CMD_C2I_DVAL_LAUNCH_END_BIT = 27; +const uint32_t PB_SCONFIG_WE1_CMD_C2I_EARLY_REQ_MODE_BIT = 28; +const uint32_t PB_SCONFIG_WE1_CMD_C2I_SPARE_BIT = 29; +const uint32_t PB_SCONFIG_WE1_CMD_C2I_SPARE_MODE_BIT = 30; +const uint32_t PB_SCONFIG_WE1_PRSP_C2I_DVAL_LAUNCH_START_BIT = 31; +const uint32_t PB_SCONFIG_WE1_PRSP_C2I_DVAL_LAUNCH_END_BIT = 32; +const uint32_t PB_SCONFIG_WE1_PRSP_C2I_HSHAKE_BIT = 33; +const uint32_t PB_SCONFIG_WE1_PRSP_C2I_SPARE_MODE_BIT = 34; +const uint32_t PB_SCONFIG_WE1_CRSP_I2C_DONE_LAUNCH_BIT = 35; +const uint32_t PB_SCONFIG_WE1_CRSP_I2C_PTY_RD_CAPTURE_START_BIT = 36; +const uint32_t PB_SCONFIG_WE1_CRSP_I2C_PTY_RD_CAPTURE_END_BIT = 37; +const uint32_t PB_SCONFIG_WE1_CRSP_I2C_SPARE_MODE_BIT = 38; +const uint32_t PB_SCONFIG_WE1_DATA_I2C_DONE_LAUNCH_START_BIT = 39; +const uint32_t PB_SCONFIG_WE1_DATA_I2C_DONE_LAUNCH_END_BIT = 40; +const uint32_t PB_SCONFIG_WE1_DATA_I2C_DCTR_LAUNCH_START_BIT = 41; +const uint32_t PB_SCONFIG_WE1_DATA_I2C_DCTR_LAUNCH_END_BIT = 42; +const uint32_t PB_SCONFIG_WE1_DATA_I2C_SPARE_MODE_BIT = 43; +const uint32_t PB_SCONFIG_WE1_DATA_C2I_DVAL_LAUNCH_START_BIT = 44; +const uint32_t PB_SCONFIG_WE1_DATA_C2I_DVAL_LAUNCH_END_BIT = 45; +const uint32_t PB_SCONFIG_WE1_DATA_C2I_DREQ_LAUNCH_START_BIT = 46; +const uint32_t PB_SCONFIG_WE1_DATA_C2I_DREQ_LAUNCH_END_BIT = 47; +const uint32_t PB_SCONFIG_WE1_DATA_C2I_SPARE_MODE_BIT = 48; +const uint32_t PB_SCONFIG_WE1_RCMD_I2C_DONE_LAUNCH_BIT = 49; +const uint32_t PB_SCONFIG_WE1_RCMD_I2C_L3_NOT_USE_DCBFL_BIT = 50; +const uint32_t PB_SCONFIG_WE1_RCMD_I2C_PTY_RD_CAPTURE_START_BIT = 51; +const uint32_t PB_SCONFIG_WE1_RCMD_I2C_PTY_RD_CAPTURE_END_BIT = 52; +const uint32_t PB_SCONFIG_WE1_RCMD_I2C_PTY_INJECT_BIT = 53; +const uint32_t PB_SCONFIG_WE1_RCMD_I2C_SPARE_MODE_BIT = 54; +const uint32_t PB_SCONFIG_WE1_FP_I2C_DONE_LAUNCH_BIT = 55; +const uint32_t PB_SCONFIG_WE1_FP_I2C_SPARE_BIT = 56; +const uint32_t PB_SCONFIG_WE1_FP_I2C_PTY_RD_CAPTURE_START_BIT = 57; +const uint32_t PB_SCONFIG_WE1_FP_I2C_PTY_RD_CAPTURE_END_BIT = 58; +const uint32_t PB_SCONFIG_WE1_FP_I2C_SPARE_MODE_BIT = 59; +const uint32_t PB_SCONFIG_WE1_FP_C2I_DVAL_LAUNCH_START_BIT = 60; +const uint32_t PB_SCONFIG_WE1_FP_C2I_DVAL_LAUNCH_END_BIT = 61; +const uint32_t PB_SCONFIG_WE1_FP_C2I_HSHAKE_BIT = 62; +const uint32_t PB_SCONFIG_WE1_FP_C2I_SPARE_MODE_BIT = 63; + +const bool PB_SCONFIG_WE1_CMD_C2I_EARLY_REQ_MODE = false; // off +const bool PB_SCONFIG_WE1_CMD_C2I_SPARE = false; // spare +const bool PB_SCONFIG_WE1_CMD_C2I_SPARE_MODE = false; // spare +const uint8_t PB_SCONFIG_WE1_PRSP_C2I_DVAL_LAUNCH = 0x0; // rc_p1 +const bool PB_SCONFIG_WE1_PRSP_C2I_HSHAKE = false; // off +const bool PB_SCONFIG_WE1_PRSP_C2I_SPARE_MODE = false; // spare +const bool PB_SCONFIG_WE1_CRSP_I2C_SPARE_MODE = false; // spare +const bool PB_SCONFIG_WE1_DATA_I2C_SPARE_MODE = false; // spare +const uint8_t PB_SCONFIG_WE1_DATA_C2I_DREQ_LAUNCH = 0x0; // rc_d3 +const bool PB_SCONFIG_WE1_DATA_C2I_SPARE_MODE = false; // off +const bool PB_SCONFIG_WE1_RCMD_I2C_L3_NOT_USE_DCBFL = false; // off +const bool PB_SCONFIG_WE1_RCMD_I2C_PTY_INJECT = false; // off +const bool PB_SCONFIG_WE1_RCMD_I2C_SPARE_MODE = false; // off +const bool PB_SCONFIG_WE1_FP_I2C_DONE_LAUNCH = false; // rc_p1 +const bool PB_SCONFIG_WE1_FP_I2C_SPARE = false; // spare +const uint8_t PB_SCONFIG_WE1_FP_I2C_PTY_RD_CAPTURE = 0x0; // rc +const bool PB_SCONFIG_WE1_FP_I2C_SPARE_MODE = false; // off +const uint8_t PB_SCONFIG_WE1_FP_C2I_DVAL_LAUNCH = 0x0; // wc_p1 +const bool PB_SCONFIG_WE1_FP_C2I_HSHAKE = false; // off +const bool PB_SCONFIG_WE1_FP_C2I_SPARE_MODE = false; // spare + + +// +// PBH_DAT_ARB_EM (east/west, chain #5) field/bit definitions +// + +const proc_build_smp_sconfig_def PB_SCONFIG_WE5_DEF_VER1 = { 0x5, 51, false, { true, false, true } }; +const proc_build_smp_sconfig_def PB_SCONFIG_WE5_DEF_VER2 = { 0x5, 52, false, { true, false, true } }; + +const uint32_t PB_SCONFIG_WE5_LOCK_ON_LINKS_BIT_VER1 = 13; +const uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1 = 14; +const uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1 = 17; +const uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1 = 18; +const uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1 = 21; +const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1 = 22; +const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1 = 25; +const uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1 = 26; +const uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1 = 29; +const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT_VER1 = 30; +const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_END_BIT_VER1 = 33; +const uint32_t PB_SCONFIG_WE5_PASSTHRU_ENABLE_BIT_VER1 = 34; +const uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT_VER1 = 35; +const uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_END_BIT_VER1 = 42; +const uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT_VER1 = 43; +const uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_END_BIT_VER1 = 50; +const uint32_t PB_SCONFIG_WE5_A_TOK_INIT_START_BIT_VER1 = 51; +const uint32_t PB_SCONFIG_WE5_A_TOK_INIT_END_BIT_VER1 = 54; +const uint32_t PB_SCONFIG_WE5_F_TOK_INIT_START_BIT_VER1 = 55; +const uint32_t PB_SCONFIG_WE5_F_TOK_INIT_END_BIT_VER1 = 58; +const uint32_t PB_SCONFIG_WE5_EM_FP_ENABLE_BIT_VER1 = 59; +const uint32_t PB_SCONFIG_WE5_SPARE_START_BIT_VER1 = 60; +const uint32_t PB_SCONFIG_WE5_SPARE_END_BIT_VER1 = 61; +const uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT_VER1 = 62; +const uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_END_BIT_VER1 = 63; + +const uint32_t PB_SCONFIG_WE5_LOCK_ON_LINKS_BIT_VER2 = 12; +const uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2 = 13; +const uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2 = 16; +const uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2 = 17; +const uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2 = 20; +const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2 = 21; +const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2 = 24; +const uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2 = 25; +const uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2 = 28; +const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT_VER2 = 29; +const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_END_BIT_VER2 = 32; +const uint32_t PB_SCONFIG_WE5_PASSTHRU_ENABLE_BIT_VER2 = 33; +const uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT_VER2 = 34; +const uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_END_BIT_VER2 = 41; +const uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT_VER2 = 42; +const uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_END_BIT_VER2 = 49; +const uint32_t PB_SCONFIG_WE5_A_TOK_INIT_START_BIT_VER2 = 50; +const uint32_t PB_SCONFIG_WE5_A_TOK_INIT_END_BIT_VER2 = 53; +const uint32_t PB_SCONFIG_WE5_F_TOK_INIT_START_BIT_VER2 = 54; +const uint32_t PB_SCONFIG_WE5_F_TOK_INIT_END_BIT_VER2 = 57; +const uint32_t PB_SCONFIG_WE5_EM_FP_ENABLE_BIT_VER2 = 58; +const uint32_t PB_SCONFIG_WE5_SPARE_START_BIT_VER2 = 59; +const uint32_t PB_SCONFIG_WE5_SPARE_END_BIT_VER2 = 59; +const uint32_t PB_SCONFIG_WE5_A_IND_THRESHOLD_BIT_VER2 = 60; +const uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT_VER2 = 61; +const uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_END_BIT_VER2 = 62; +const uint32_t PB_SCONFIG_WE5_X_OFF_SEL_BIT_VER2 = 63; + +const bool PB_SCONFIG_WE5_LOCK_ON_LINKS = true; // lock +const uint8_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD = 0x4; // cnt_4 +const uint8_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD = 0x4; // cnt_4 +const uint8_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD = 0x4; // cnt_4 +const uint8_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD = 0x0; // cnt_0 +const uint8_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD = 0x0; // cnt_0 +const bool PB_SCONFIG_WE5_PASSTHRU_ENABLE = true; // enable +const uint8_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY = 0xFE; // cnt_7to1 +const uint8_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY = 0xFE; // cnt_7to1 +const uint8_t PB_SCONFIG_WE5_A_TOK_INIT = 0x8; // cnt_8 +const uint8_t PB_SCONFIG_WE5_F_TOK_INIT = 0x4; // cnt_4 +const bool PB_SCONFIG_WE5_EM_FP_ENABLE = true; // enable +const uint8_t PB_SCONFIG_WE5_SPARE = 0x0; // spare +const uint8_t PB_SCONFIG_WE5_MEM_STV_PRIORITY = 0x2; // stv + +const uint8_t PB_SCONFIG_WE5_A_IND_THRESHOLD = 0x0; // gt4 +const uint8_t PB_SCONFIG_WE5_X_OFF_SEL = 0x0; // disable + + //------------------------------------------------------------------------------ // Function definitions //------------------------------------------------------------------------------ @@ -977,9 +1466,11 @@ fapi::ReturnCode proc_build_smp_set_sconfig_we0( case PROC_BUILD_SMP_CORE_RATIO_2_8: break; default: - FAPI_ERR("proc_build_smp_set_sconfig_we0: Unsupported core floor frequency ratio enum (%d)", - i_smp.core_floor_ratio); - const uint32_t& CORE_CEILING_RATIO = i_smp.core_floor_ratio; + FAPI_ERR("proc_build_smp_set_sconfig_we0: Unsupported core ceiling frequency ratio enum (%d)", + i_smp.core_ceiling_ratio); + const uint32_t& FREQ_PB = i_smp.freq_pb; + const uint32_t& FREQ_CORE_CEILING = i_smp.freq_core_ceiling; + const uint32_t& CORE_CEILING_RATIO = i_smp.core_ceiling_ratio; FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_CORE_CEILING_RATIO_ERR); break; @@ -1267,6 +1758,8 @@ fapi::ReturnCode proc_build_smp_set_sconfig_we1( default: FAPI_ERR("proc_build_smp_set_sconfig_we1: Unsupported core floor frequency ratio enum (%d)", i_smp.core_floor_ratio); + const uint32_t& FREQ_PB = i_smp.freq_pb; + const uint32_t& FREQ_CORE_FLOOR = i_smp.freq_core_floor; const uint32_t& CORE_FLOOR_RATIO = i_smp.core_floor_ratio; FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_CORE_FLOOR_RATIO_ERR); @@ -1859,7 +2352,7 @@ fapi::ReturnCode proc_build_smp_set_fbc_cd( } // issue single switch CD to force all updates to occur - rc = proc_build_smp_switch_cd(p_iter->second); + rc = proc_build_smp_switch_cd(p_iter->second, i_smp); if (!rc.ok()) { FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_switch_cd"); diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H index 69fec2e11..f0c023739 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_fbc_cd.H,v 1.16 2014/01/18 18:31:12 jmcgill Exp $ +// $Id: proc_build_smp_fbc_cd.H,v 1.17 2014/02/23 21:41:07 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_cd.H,v $ //------------------------------------------------------------------------------ // *| @@ -41,492 +41,8 @@ //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ -#include "proc_build_smp.H" -#include "p8_scom_addresses.H" - -//------------------------------------------------------------------------------ -// Structure definitions -//------------------------------------------------------------------------------ - -// structure encapsulating serial configuration load programming -struct proc_build_smp_sconfig_def -{ - uint8_t select; // ID/select for chain - uint8_t length; // number of bits to load - bool use_slow_clock; // use 16:1 slow clock? (EX) - bool use_shadow[PROC_BUILD_SMP_NUM_SHADOWS]; // define which shadows to set -}; - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -// -// PB Serial Configuration Load register field/bit definitions -// - -// hang level constants -const uint8_t PB_SCONFIG_NUM_HANG_LEVELS = 7; - -// CPU ratio constants -const uint8_t PB_SCONFIG_NUM_CPU_RATIOS = 4; - - -const uint32_t PB_SCONFIG_LOAD[PROC_BUILD_SMP_NUM_SHADOWS] = -{ - PB_SCONFIG_LOAD_WEST_0x02010C16, - PB_SCONFIG_LOAD_CENT_0x02010C6D, - PB_SCONFIG_LOAD_EAST_0x02010C96 -}; - -const uint32_t PB_SCONFIG_LOAD_START_BIT = 0; -const uint32_t PB_SCONFIG_LOAD_SLOW_BIT = 1; -const uint32_t PB_SCONFIG_SHIFT_COUNT_START_BIT = 2; -const uint32_t PB_SCONFIG_SHIFT_COUNT_END_BIT = 7; -const uint32_t PB_SCONFIG_SELECT_START_BIT = 8; -const uint32_t PB_SCONFIG_SELECT_END_BIT = 11; -const uint32_t PB_SCONFIG_SHIFT_DATA_START_BIT = 12; -const uint32_t PB_SCONFIG_SHIFT_DATA_END_BIT = 63; - - -// -// PBH_CMD_SNOOPER (center, chain #4) field/bit definitions -// - -const proc_build_smp_sconfig_def PB_SCONFIG_C4_DEF = { 0x4, 50, false, { false, true, false} }; - -const uint32_t PB_SCONFIG_C4_GP_LO_RTY_THRESHOLD_START_BIT = 14; -const uint32_t PB_SCONFIG_C4_GP_LO_RTY_THRESHOLD_END_BIT = 23; -const uint32_t PB_SCONFIG_C4_GP_HI_RTY_THRESHOLD_START_BIT = 24; -const uint32_t PB_SCONFIG_C4_GP_HI_RTY_THRESHOLD_END_BIT = 33; -const uint32_t PB_SCONFIG_C4_RGP_LO_RTY_THRESHOLD_START_BIT = 34; -const uint32_t PB_SCONFIG_C4_RGP_LO_RTY_THRESHOLD_END_BIT = 43; -const uint32_t PB_SCONFIG_C4_RGP_HI_RTY_THRESHOLD_START_BIT = 44; -const uint32_t PB_SCONFIG_C4_RGP_HI_RTY_THRESHOLD_END_BIT = 53; -const uint32_t PB_SCONFIG_C4_SP_LO_RTY_THRESHOLD_START_BIT = 54; -const uint32_t PB_SCONFIG_C4_SP_LO_RTY_THRESHOLD_END_BIT = 63; - -const uint32_t PB_SCONFIG_C4_GP_LO_RTY_THRESHOLD = 0x7; -const uint32_t PB_SCONFIG_C4_GP_HI_RTY_THRESHOLD = 0x5; -const uint32_t PB_SCONFIG_C4_RGP_LO_RTY_THRESHOLD = 0x5; -const uint32_t PB_SCONFIG_C4_RGP_HI_RTY_THRESHOLD = 0x4; -const uint32_t PB_SCONFIG_C4_SP_LO_RTY_THRESHOLD = 0x5; - - -// -// PBH_CMD_SNOOPER (center, chain #5) field/bit definitions -// - -const proc_build_smp_sconfig_def PB_SCONFIG_C5_DEF = { 0x5, 46, false, { false, true, false} }; - -const uint32_t PB_SCONFIG_C5_SP_HI_RTY_THRESHOLD_START_BIT = 18; -const uint32_t PB_SCONFIG_C5_SP_HI_RTY_THRESHOLD_END_BIT = 27; -const uint32_t PB_SCONFIG_C5_GP_CRESP_SAMPLE_TIME_START_BIT = 28; -const uint32_t PB_SCONFIG_C5_GP_CRESP_SAMPLE_TIME_END_BIT = 39; -const uint32_t PB_SCONFIG_C5_RGP_CRESP_SAMPLE_TIME_START_BIT = 40; -const uint32_t PB_SCONFIG_C5_RGP_CRESP_SAMPLE_TIME_END_BIT = 51; -const uint32_t PB_SCONFIG_C5_SP_CRESP_SAMPLE_TIME_START_BIT = 52; -const uint32_t PB_SCONFIG_C5_SP_CRESP_SAMPLE_TIME_END_BIT = 63; - -const uint32_t PB_SCONFIG_C5_SP_HI_RTY_THRESHOLD = 0x4; -const uint32_t PB_SCONFIG_C5_GP_CRESP_SAMPLE_TIME = 321; -const uint32_t PB_SCONFIG_C5_RGP_CRESP_SAMPLE_TIME = 539; -const uint32_t PB_SCONFIG_C5_SP_CRESP_SAMPLE_TIME = 781; - - -// -// PBH_CMD_SNOOPER (center, chain #6) field/bit definitions -// - -const proc_build_smp_sconfig_def PB_SCONFIG_C6_DEF = { 0x6, 42, false, { false, true, false} }; - -const uint32_t PB_SCONFIG_C6_GP_REQ_SAMPLE_TIME_START_BIT = 22; -const uint32_t PB_SCONFIG_C6_GP_REQ_SAMPLE_TIME_END_BIT = 33; -const uint32_t PB_SCONFIG_C6_SP_REQ_SAMPLE_TIME_START_BIT = 34; -const uint32_t PB_SCONFIG_C6_SP_REQ_SAMPLE_TIME_END_BIT = 45; -const uint32_t PB_SCONFIG_C6_GP_LO_JUMP_START_BIT = 46; -const uint32_t PB_SCONFIG_C6_GP_LO_JUMP_END_BIT = 48; -const uint32_t PB_SCONFIG_C6_GP_HI_JUMP_START_BIT = 49; -const uint32_t PB_SCONFIG_C6_GP_HI_JUMP_END_BIT = 51; -const uint32_t PB_SCONFIG_C6_SP_LO_JUMP_START_BIT = 52; -const uint32_t PB_SCONFIG_C6_SP_LO_JUMP_END_BIT = 54; -const uint32_t PB_SCONFIG_C6_SP_HI_JUMP_START_BIT = 55; -const uint32_t PB_SCONFIG_C6_SP_HI_JUMP_END_BIT = 57; -const uint32_t PB_SCONFIG_C6_RGP_LO_JUMP_START_BIT = 58; -const uint32_t PB_SCONFIG_C6_RGP_LO_JUMP_END_BIT = 60; -const uint32_t PB_SCONFIG_C6_RGP_HI_JUMP_START_BIT = 61; -const uint32_t PB_SCONFIG_C6_RGP_HI_JUMP_END_BIT = 63; - -const uint32_t PB_SCONFIG_C6_GP_REQ_SAMPLE_TIME = 1024; -const uint32_t PB_SCONFIG_C6_SP_REQ_SAMPLE_TIME = 1024; -const uint32_t PB_SCONFIG_C6_GP_LO_JUMP = 0x2; -const uint32_t PB_SCONFIG_C6_GP_HI_JUMP = 0x2; -const uint32_t PB_SCONFIG_C6_SP_LO_JUMP = 0x2; -const uint32_t PB_SCONFIG_C6_SP_HI_JUMP = 0x2; -const uint32_t PB_SCONFIG_C6_RGP_LO_JUMP = 0x2; -const uint32_t PB_SCONFIG_C6_RGP_HI_JUMP = 0x2; - - -// -// PBH_CMD_SNOOPER (center, chain #7) field/bit definitions -// - -const proc_build_smp_sconfig_def PB_SCONFIG_C7_DEF = { 0x7, 36, false, { false, true, false } }; - -const uint32_t PB_SCONFIG_C7_HANG_CMD_RATE_START_BIT[PB_SCONFIG_NUM_HANG_LEVELS] = { 28, 33, 38, 43, 48, 53, 58 }; -const uint32_t PB_SCONFIG_C7_HANG_CMD_RATE_END_BIT[PB_SCONFIG_NUM_HANG_LEVELS] = { 32, 37, 42, 47, 52, 57, 62 }; -const uint32_t PB_SCONFIG_C7_SLOW_GO_RATE_BIT = 63; - -// PB_CFG_HANG0_CMD_RATE = 0x00 = 127/128 -// PB_CFG_HANG1_CMD_RATE = 0x06 = 1/2 -// PB_CFG_HANG2_CMD_RATE = 0x0D = 1/512 -// PB_CFG_HANG3_CMD_RATE = 0x00 = 127/128 -// PB_CFG_HANG4_CMD_RATE = 0x1E = 1/4096 (toad mode) -// PB_CFG_HANG5_CMD_RATE = 0x19 = 1/8 (toad mode) -// PB_CFG_HANG6_CMD_RATE = 0x00 = 127/128 -const uint8_t PB_SCONFIG_C7_HANG_CMD_RATE[PB_SCONFIG_NUM_HANG_LEVELS] = { 0x00, 0x06, 0x0D, 0x00, 0x1E, 0x19, 0x00 }; -const bool PB_SCONFIG_C7_SLOW_GO_RATE = true; - - -// -// PBH_CMD_SNOOPER (center, chain #8) field/bit definitions -// - -const proc_build_smp_sconfig_def PB_SCONFIG_C8_DEF_VER1 = { 0x8, 37, false, { false, true, false } }; -const proc_build_smp_sconfig_def PB_SCONFIG_C8_DEF_VER2 = { 0x8, 39, false, { false, true, false } }; -const proc_build_smp_sconfig_def PB_SCONFIG_C8_DEF_VER3 = { 0x8, 43, false, { false, true, false } }; - -const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT_VER1[PB_SCONFIG_NUM_HANG_LEVELS] = { 27, 31, 35, 39, 43, 47, 51 }; -const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT_VER1[PB_SCONFIG_NUM_HANG_LEVELS] = { 30, 34, 38, 42, 46, 50, 54 }; -const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT_VER1 = 55; -const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT_VER1 = 57; -const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT_VER1 = 58; -const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT_VER1 = 63; - -const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT_VER2[PB_SCONFIG_NUM_HANG_LEVELS] = { 25, 29, 33, 37, 41, 45, 49 }; -const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT_VER2[PB_SCONFIG_NUM_HANG_LEVELS] = { 28, 32, 36, 40, 44, 48, 52 }; -const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT_VER2 = 53; -const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT_VER2 = 55; -const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT_VER2 = 56; -const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT_VER2 = 61; -const uint32_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT_VER2 = 62; -const uint32_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT_VER2 = 63; - -const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT_VER3[PB_SCONFIG_NUM_HANG_LEVELS] = { 21, 25, 29, 33, 37, 41, 45 }; -const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT_VER3[PB_SCONFIG_NUM_HANG_LEVELS] = { 24, 28, 32, 36, 40, 44, 48 }; -const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT_VER3 = 49; -const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT_VER3 = 51; -const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT_VER3 = 52; -const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT_VER3 = 57; -const uint32_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT_VER3 = 58; -const uint32_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT_VER3 = 59; -const uint32_t PB_SCONFIG_C8_RTY_PERCENTAGE_START_BIT_VER3 = 60; -const uint32_t PB_SCONFIG_C8_RTY_PERCENTAGE_END_BIT_VER3 = 62; -const uint32_t PB_SCONFIG_C8_INCLUDE_LPC_RTY_BIT_VER3 = 63; - -const uint8_t PB_SCONFIG_C8_HANG_CMD_RATE[PB_SCONFIG_NUM_HANG_LEVELS] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -const uint8_t PB_SCONFIG_C8_CPO_JUMP_LEVEL = 0x7; -const uint8_t PB_SCONFIG_C8_CPO_RTY_LEVEL = 0x4; - -const uint8_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF = 0x2; // backoff_1k - -const uint8_t PB_SCONFIG_C8_RTY_PERCENTAGE = 0x0; // 000 -const uint8_t PB_SCONFIG_C8_INCLUDE_LPC_RTY = 0x0; // off - -// -// PBH_CMD_CENTRAL_ARB (center, chain #9) field/bit definitions -// - -const proc_build_smp_sconfig_def PB_SCONFIG_C9_DEF = { 0x9, 44, false, { false, true, false } }; - -const uint32_t PB_SCONFIG_C9_CP_STARVE_LIMIT_START_BIT = 20; -const uint32_t PB_SCONFIG_C9_CP_STARVE_LIMIT_END_BIT = 27; -const uint32_t PB_SCONFIG_C9_GP_STARVE_LIMIT_START_BIT = 28; -const uint32_t PB_SCONFIG_C9_GP_STARVE_LIMIT_END_BIT = 35; -const uint32_t PB_SCONFIG_C9_RGP_STARVE_LIMIT_START_BIT = 36; -const uint32_t PB_SCONFIG_C9_RGP_STARVE_LIMIT_END_BIT = 43; -const uint32_t PB_SCONFIG_C9_SP_STARVE_LIMIT_START_BIT = 44; -const uint32_t PB_SCONFIG_C9_SP_STARVE_LIMIT_END_BIT = 51; -const uint32_t PB_SCONFIG_C9_FP_STARVE_LIMIT_START_BIT = 52; -const uint32_t PB_SCONFIG_C9_FP_STARVE_LIMIT_END_BIT = 59; -const uint32_t PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_START_BIT = 60; -const uint32_t PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_END_BIT = 61; -const uint32_t PB_SCONFIG_C9_UX_LOCAL_ARB_MODE_START_BIT = 62; -const uint32_t PB_SCONFIG_C9_UX_LOCAL_ARB_MODE_END_BIT = 63; - -const uint8_t PB_SCONFIG_C9_CP_STARVE_LIMIT = 0x10; -const uint8_t PB_SCONFIG_C9_GP_STARVE_LIMIT = 0x10; -const uint8_t PB_SCONFIG_C9_RGP_STARVE_LIMIT = 0x10; -const uint8_t PB_SCONFIG_C9_SP_STARVE_LIMIT = 0x10; -const uint8_t PB_SCONFIG_C9_FP_STARVE_LIMIT = 0x10; -const uint8_t PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_LFSR = 0x0; // LFSR_ONLY -const uint8_t PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_RR = 0x1; // RR_ONLY -const uint8_t PB_SCONFIG_C9_UX_LOCAL_ARB_MODE = 0x2; // LFSR_ON_STARVATION_ELSE_RR - - -// -// PBH_CMD_CENTRAL_ARB (center, chain #10) field/bit definitions -// - -const proc_build_smp_sconfig_def PB_SCONFIG_C10_DEF_VER1 = { 0xA, 20, false, { false, true, false } }; -const proc_build_smp_sconfig_def PB_SCONFIG_C10_DEF_VER2 = { 0xA, 23, false, { false, true, false } }; - -const uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT_VER1[PB_SCONFIG_NUM_CPU_RATIOS] = { 59, 54, 49, 44 }; -const uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT_VER1[PB_SCONFIG_NUM_CPU_RATIOS] = { 63, 58, 53, 48 }; - -const uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT_VER2[PB_SCONFIG_NUM_CPU_RATIOS] = { 56, 51, 46, 41 }; -const uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT_VER2[PB_SCONFIG_NUM_CPU_RATIOS] = { 60, 55, 50, 45 }; -const uint32_t PB_SCONFIG_C10_DAT_X_LINK_HOLDOFF_ENABLE_BIT_VER2 = 61; -const uint32_t PB_SCONFIG_C10_DAT_A_LINK_HOLDOFF_ENABLE_BIT_VER2 = 62; -const uint32_t PB_SCONFIG_C10_DAT_LINK_HOLDOFF_MULTIPLIER_BIT_VER2 = 63; - -const uint8_t PB_SCONFIG_C10_CMD_CPU_RATIO_TABLE[PROC_BUILD_SMP_CPU_DELAY_NUM_SETPOINTS] = { 15, 14, 13, 12, 11, 11, 10, 10, 9, 9, 8, 8, 7 }; - -const uint8_t PB_SCONFIG_C10_CMD_CPU_RATIO_QUARTER = 3; -const uint8_t PB_SCONFIG_C10_CMD_CPU_RATIO_HALF = 7; -const uint8_t PB_SCONFIG_C10_DAT_X_LINK_HOLDOFF_ENABLE = 0x0; // disable -const uint8_t PB_SCONFIG_C10_DAT_A_LINK_HOLDOFF_ENABLE = 0x0; // disable -const uint8_t PB_SCONFIG_C10_DAT_LINK_HOLDOFF_MULTIPLIER = 0x0; // x2 - - -// -// PBH_RSP_CRESP_ARB (center, chain #11) field/bit definitions -// - -const proc_build_smp_sconfig_def PB_SCONFIG_C11_DEF = { 0xB, 20, false, { false, true, false } }; - -const uint32_t PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[PB_SCONFIG_NUM_CPU_RATIOS] = { 59, 54, 49, 44 }; -const uint32_t PB_SCONFIG_C11_RSP_CPU_RATIO_END_BIT[PB_SCONFIG_NUM_CPU_RATIOS] = { 63, 58, 53, 48 }; - -const uint8_t PB_SCONFIG_C11_RSP_CPU_RATIO_TABLE[PROC_BUILD_SMP_CPU_DELAY_NUM_SETPOINTS] = { 16, 15, 14, 13, 12, 12, 11, 11, 10, 10, 9, 9, 8 }; - -const uint8_t PB_SCONFIG_C11_RSP_CPU_RATIO_QUARTER = 4; -const uint8_t PB_SCONFIG_C11_RSP_CPU_RATIO_HALF = 8; - -// -// PBH_PBIEX_EH (east/west, chain #0) field/bit definitions -// - -const proc_build_smp_sconfig_def PB_SCONFIG_WE0_DEF = { 0x0, 52, false, { true, false, true } }; - -const uint32_t PB_SCONFIG_WE0_CMD_C2I_DONE_LAUNCH_START_BIT = 12; -const uint32_t PB_SCONFIG_WE0_CMD_C2I_DONE_LAUNCH_END_BIT = 14; -const uint32_t PB_SCONFIG_WE0_CMD_C2I_LATE_RD_MODE_BIT = 15; -const uint32_t PB_SCONFIG_WE0_CMD_C2I_DELAY_SP_RD_START_BIT = 16; -const uint32_t PB_SCONFIG_WE0_CMD_C2I_DELAY_SP_RD_END_BIT = 17; -const uint32_t PB_SCONFIG_WE0_CMD_C2I_SPARE_MODE_BIT = 18; -const uint32_t PB_SCONFIG_WE0_PRSP_C2I_DONE_LAUNCH_BIT = 19; -const uint32_t PB_SCONFIG_WE0_PRSP_C2I_HW070772_DIS_BIT = 20; -const uint32_t PB_SCONFIG_WE0_PRSP_C2I_NOP_MODE_START_BIT = 21; -const uint32_t PB_SCONFIG_WE0_PRSP_C2I_NOP_MODE_END_BIT = 22; -const uint32_t PB_SCONFIG_WE0_PRSP_C2I_SPARE_MODE_BIT = 23; -const uint32_t PB_SCONFIG_WE0_CRSP_I2C_DVAL_LAUNCH_START_BIT = 24; -const uint32_t PB_SCONFIG_WE0_CRSP_I2C_DVAL_LAUNCH_END_BIT = 25; -const uint32_t PB_SCONFIG_WE0_CRSP_I2C_HSHAKE_BIT = 26; -const uint32_t PB_SCONFIG_WE0_CRSP_I2C_SPARE_MODE_BIT = 27; -const uint32_t PB_SCONFIG_WE0_DATA_I2C_DVAL_LAUNCH_START_BIT = 28; -const uint32_t PB_SCONFIG_WE0_DATA_I2C_DVAL_LAUNCH_END_BIT = 29; -const uint32_t PB_SCONFIG_WE0_DATA_I2C_SPARE_MODE_BIT = 30; -const uint32_t PB_SCONFIG_WE0_DATA_I2C_FORCE_FA_ALLOC_BIT = 31; -const uint32_t PB_SCONFIG_WE0_DATA_C2I_DONE_LAUNCH_START_BIT = 32; -const uint32_t PB_SCONFIG_WE0_DATA_C2I_DONE_LAUNCH_END_BIT = 33; -const uint32_t PB_SCONFIG_WE0_DATA_C2I_INITIAL_REQ_DLY_START_BIT = 34; -const uint32_t PB_SCONFIG_WE0_DATA_C2I_INITIAL_REQ_DLY_END_BIT = 36; -const uint32_t PB_SCONFIG_WE0_DATA_C2I_DCTR_LAUNCH_START_BIT = 37; -const uint32_t PB_SCONFIG_WE0_DATA_C2I_DCTR_LAUNCH_END_BIT = 38; -const uint32_t PB_SCONFIG_WE0_DATA_C2I_OUTSTANDING_REQ_COUNT_BIT = 39; -const uint32_t PB_SCONFIG_WE0_DATA_C2I_REQ_ID_ASSIGNMENT_MODE_BIT = 40; -const uint32_t PB_SCONFIG_WE0_DATA_C2I_ALLOW_FRAGMENTATION_BIT = 41; -const uint32_t PB_SCONFIG_WE0_DATA_C2I_SERIAL_DREQ_ID_BIT = 42; -const uint32_t PB_SCONFIG_WE0_DATA_C2I_SPARE_MODE_BIT = 43; -const uint32_t PB_SCONFIG_WE0_RCMD_I2C_DVAL_LAUNCH_START_BIT = 44; -const uint32_t PB_SCONFIG_WE0_RCMD_I2C_DVAL_LAUNCH_END_BIT = 45; -const uint32_t PB_SCONFIG_WE0_RCMD_I2C_HSHAKE_BIT = 46; -const uint32_t PB_SCONFIG_WE0_RCMD_I2C_SPARE_MODE_BIT = 47; -const uint32_t PB_SCONFIG_WE0_FP_I2C_DVAL_LAUNCH_START_BIT = 48; -const uint32_t PB_SCONFIG_WE0_FP_I2C_DVAL_LAUNCH_END_BIT = 49; -const uint32_t PB_SCONFIG_WE0_FP_I2C_HSHAKE_BIT = 50; -const uint32_t PB_SCONFIG_WE0_FP_I2C_SPARE_MODE_BIT = 51; -const uint32_t PB_SCONFIG_WE0_FP_C2I_DONE_LAUNCH_BIT = 52; -const uint32_t PB_SCONFIG_WE0_FP_C2I_SPARE_MODE_BIT = 53; -const uint32_t PB_SCONFIG_WE0_CPU_DELAY_FULL_START_BIT = 54; -const uint32_t PB_SCONFIG_WE0_CPU_DELAY_FULL_END_BIT = 58; -const uint32_t PB_SCONFIG_WE0_CPU_DELAY_NOM_START_BIT = 59; -const uint32_t PB_SCONFIG_WE0_CPU_DELAY_NOM_END_BIT = 63; - -const bool PB_SCONFIG_WE0_CMD_C2I_LATE_RD_MODE = true; // on -const uint8_t PB_SCONFIG_WE0_CMD_C2I_DELAY_SP_RD = 0x0; // rc_p1 -const bool PB_SCONFIG_WE0_CMD_C2I_SPARE_MODE = false; // spare -const uint8_t PB_SCONFIG_WE0_PRSP_C2I_DONE_LAUNCH = 0x0; // rc_p1 -const bool PB_SCONFIG_WE0_PRSP_C2I_HW070772_DIS = true; // on -const uint8_t PB_SCONFIG_WE0_PRSP_C2I_NOP_MODE = 0x0; // 16c -const bool PB_SCONFIG_WE0_PRSP_C2I_SPARE_MODE = false; // spare -const bool PB_SCONFIG_WE0_CRSP_I2C_HSHAKE = false; // off -const bool PB_SCONFIG_WE0_CRSP_I2C_SPARE_MODE = false; // spare -const bool PB_SCONFIG_WE0_DATA_I2C_SPARE_MODE = false; // spare -const bool PB_SCONFIG_WE0_DATA_I2C_FORCE_FA_ALLOC = false; // off -const uint8_t PB_SCONFIG_WE0_DATA_C2I_INITIAL_REQ_DLY = 0x7; // 7c -const bool PB_SCONFIG_WE0_DATA_C2I_OUTSTANDING_REQ_COUNT = false; // 8 -const bool PB_SCONFIG_WE0_DATA_C2I_REQ_ID_ASSIGNMENT_MODE = false; // FA -const bool PB_SCONFIG_WE0_DATA_C2I_ALLOW_FRAGMENTATION = true; // on -const bool PB_SCONFIG_WE0_DATA_C2I_SERIAL_DREQ_ID = true; // on -const bool PB_SCONFIG_WE0_DATA_C2I_SPARE_MODE = false; // spare -const bool PB_SCONFIG_WE0_RCMD_I2C_HSHAKE = false; // off -const bool PB_SCONFIG_WE0_RCMD_I2C_SPARE_MODE = false; // spare -const uint8_t PB_SCONFIG_WE0_FP_I2C_DVAL_LAUNCH = 0x0; // wc_p1 -const uint8_t PB_SCONFIG_WE0_FP_I2C_HSHAKE = false; // off -const bool PB_SCONFIG_WE0_FP_I2C_SPARE_MODE = false; // spare -const uint8_t PB_SCONFIG_WE0_FP_C2I_DONE_LAUNCH = 0x0; // rc_p1 -const bool PB_SCONFIG_WE0_FP_C2I_SPARE_MODE = false; // spare - -const uint8_t PB_SCONFIG_WE0_CPU_DELAY_TABLE[PROC_BUILD_SMP_CPU_DELAY_NUM_SETPOINTS] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 }; - - -// -// PBH_PBIEX_EX (east/west, chain #1) field/bit definitions -// - -const proc_build_smp_sconfig_def PB_SCONFIG_WE1_DEF = { 0x1, 38, true, { true, false, true } }; - -const uint32_t PB_SCONFIG_WE1_CMD_C2I_DVAL_LAUNCH_START_BIT = 26; -const uint32_t PB_SCONFIG_WE1_CMD_C2I_DVAL_LAUNCH_END_BIT = 27; -const uint32_t PB_SCONFIG_WE1_CMD_C2I_EARLY_REQ_MODE_BIT = 28; -const uint32_t PB_SCONFIG_WE1_CMD_C2I_SPARE_BIT = 29; -const uint32_t PB_SCONFIG_WE1_CMD_C2I_SPARE_MODE_BIT = 30; -const uint32_t PB_SCONFIG_WE1_PRSP_C2I_DVAL_LAUNCH_START_BIT = 31; -const uint32_t PB_SCONFIG_WE1_PRSP_C2I_DVAL_LAUNCH_END_BIT = 32; -const uint32_t PB_SCONFIG_WE1_PRSP_C2I_HSHAKE_BIT = 33; -const uint32_t PB_SCONFIG_WE1_PRSP_C2I_SPARE_MODE_BIT = 34; -const uint32_t PB_SCONFIG_WE1_CRSP_I2C_DONE_LAUNCH_BIT = 35; -const uint32_t PB_SCONFIG_WE1_CRSP_I2C_PTY_RD_CAPTURE_START_BIT = 36; -const uint32_t PB_SCONFIG_WE1_CRSP_I2C_PTY_RD_CAPTURE_END_BIT = 37; -const uint32_t PB_SCONFIG_WE1_CRSP_I2C_SPARE_MODE_BIT = 38; -const uint32_t PB_SCONFIG_WE1_DATA_I2C_DONE_LAUNCH_START_BIT = 39; -const uint32_t PB_SCONFIG_WE1_DATA_I2C_DONE_LAUNCH_END_BIT = 40; -const uint32_t PB_SCONFIG_WE1_DATA_I2C_DCTR_LAUNCH_START_BIT = 41; -const uint32_t PB_SCONFIG_WE1_DATA_I2C_DCTR_LAUNCH_END_BIT = 42; -const uint32_t PB_SCONFIG_WE1_DATA_I2C_SPARE_MODE_BIT = 43; -const uint32_t PB_SCONFIG_WE1_DATA_C2I_DVAL_LAUNCH_START_BIT = 44; -const uint32_t PB_SCONFIG_WE1_DATA_C2I_DVAL_LAUNCH_END_BIT = 45; -const uint32_t PB_SCONFIG_WE1_DATA_C2I_DREQ_LAUNCH_START_BIT = 46; -const uint32_t PB_SCONFIG_WE1_DATA_C2I_DREQ_LAUNCH_END_BIT = 47; -const uint32_t PB_SCONFIG_WE1_DATA_C2I_SPARE_MODE_BIT = 48; -const uint32_t PB_SCONFIG_WE1_RCMD_I2C_DONE_LAUNCH_BIT = 49; -const uint32_t PB_SCONFIG_WE1_RCMD_I2C_L3_NOT_USE_DCBFL_BIT = 50; -const uint32_t PB_SCONFIG_WE1_RCMD_I2C_PTY_RD_CAPTURE_START_BIT = 51; -const uint32_t PB_SCONFIG_WE1_RCMD_I2C_PTY_RD_CAPTURE_END_BIT = 52; -const uint32_t PB_SCONFIG_WE1_RCMD_I2C_PTY_INJECT_BIT = 53; -const uint32_t PB_SCONFIG_WE1_RCMD_I2C_SPARE_MODE_BIT = 54; -const uint32_t PB_SCONFIG_WE1_FP_I2C_DONE_LAUNCH_BIT = 55; -const uint32_t PB_SCONFIG_WE1_FP_I2C_SPARE_BIT = 56; -const uint32_t PB_SCONFIG_WE1_FP_I2C_PTY_RD_CAPTURE_START_BIT = 57; -const uint32_t PB_SCONFIG_WE1_FP_I2C_PTY_RD_CAPTURE_END_BIT = 58; -const uint32_t PB_SCONFIG_WE1_FP_I2C_SPARE_MODE_BIT = 59; -const uint32_t PB_SCONFIG_WE1_FP_C2I_DVAL_LAUNCH_START_BIT = 60; -const uint32_t PB_SCONFIG_WE1_FP_C2I_DVAL_LAUNCH_END_BIT = 61; -const uint32_t PB_SCONFIG_WE1_FP_C2I_HSHAKE_BIT = 62; -const uint32_t PB_SCONFIG_WE1_FP_C2I_SPARE_MODE_BIT = 63; - -const bool PB_SCONFIG_WE1_CMD_C2I_EARLY_REQ_MODE = false; // off -const bool PB_SCONFIG_WE1_CMD_C2I_SPARE = false; // spare -const bool PB_SCONFIG_WE1_CMD_C2I_SPARE_MODE = false; // spare -const uint8_t PB_SCONFIG_WE1_PRSP_C2I_DVAL_LAUNCH = 0x0; // rc_p1 -const bool PB_SCONFIG_WE1_PRSP_C2I_HSHAKE = false; // off -const bool PB_SCONFIG_WE1_PRSP_C2I_SPARE_MODE = false; // spare -const bool PB_SCONFIG_WE1_CRSP_I2C_SPARE_MODE = false; // spare -const bool PB_SCONFIG_WE1_DATA_I2C_SPARE_MODE = false; // spare -const uint8_t PB_SCONFIG_WE1_DATA_C2I_DREQ_LAUNCH = 0x0; // rc_d3 -const bool PB_SCONFIG_WE1_DATA_C2I_SPARE_MODE = false; // off -const bool PB_SCONFIG_WE1_RCMD_I2C_L3_NOT_USE_DCBFL = false; // off -const bool PB_SCONFIG_WE1_RCMD_I2C_PTY_INJECT = false; // off -const bool PB_SCONFIG_WE1_RCMD_I2C_SPARE_MODE = false; // off -const bool PB_SCONFIG_WE1_FP_I2C_DONE_LAUNCH = false; // rc_p1 -const bool PB_SCONFIG_WE1_FP_I2C_SPARE = false; // spare -const uint8_t PB_SCONFIG_WE1_FP_I2C_PTY_RD_CAPTURE = 0x0; // rc -const bool PB_SCONFIG_WE1_FP_I2C_SPARE_MODE = false; // off -const uint8_t PB_SCONFIG_WE1_FP_C2I_DVAL_LAUNCH = 0x0; // wc_p1 -const bool PB_SCONFIG_WE1_FP_C2I_HSHAKE = false; // off -const bool PB_SCONFIG_WE1_FP_C2I_SPARE_MODE = false; // spare - - -// -// PBH_DAT_ARB_EM (east/west, chain #5) field/bit definitions -// - -const proc_build_smp_sconfig_def PB_SCONFIG_WE5_DEF_VER1 = { 0x5, 51, false, { true, false, true } }; -const proc_build_smp_sconfig_def PB_SCONFIG_WE5_DEF_VER2 = { 0x5, 52, false, { true, false, true } }; - -const uint32_t PB_SCONFIG_WE5_LOCK_ON_LINKS_BIT_VER1 = 13; -const uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1 = 14; -const uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1 = 17; -const uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1 = 18; -const uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1 = 21; -const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1 = 22; -const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1 = 25; -const uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1 = 26; -const uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1 = 29; -const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT_VER1 = 30; -const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_END_BIT_VER1 = 33; -const uint32_t PB_SCONFIG_WE5_PASSTHRU_ENABLE_BIT_VER1 = 34; -const uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT_VER1 = 35; -const uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_END_BIT_VER1 = 42; -const uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT_VER1 = 43; -const uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_END_BIT_VER1 = 50; -const uint32_t PB_SCONFIG_WE5_A_TOK_INIT_START_BIT_VER1 = 51; -const uint32_t PB_SCONFIG_WE5_A_TOK_INIT_END_BIT_VER1 = 54; -const uint32_t PB_SCONFIG_WE5_F_TOK_INIT_START_BIT_VER1 = 55; -const uint32_t PB_SCONFIG_WE5_F_TOK_INIT_END_BIT_VER1 = 58; -const uint32_t PB_SCONFIG_WE5_EM_FP_ENABLE_BIT_VER1 = 59; -const uint32_t PB_SCONFIG_WE5_SPARE_START_BIT_VER1 = 60; -const uint32_t PB_SCONFIG_WE5_SPARE_END_BIT_VER1 = 61; -const uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT_VER1 = 62; -const uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_END_BIT_VER1 = 63; - -const uint32_t PB_SCONFIG_WE5_LOCK_ON_LINKS_BIT_VER2 = 12; -const uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2 = 13; -const uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2 = 16; -const uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2 = 17; -const uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2 = 20; -const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2 = 21; -const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2 = 24; -const uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2 = 25; -const uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2 = 28; -const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT_VER2 = 29; -const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_END_BIT_VER2 = 32; -const uint32_t PB_SCONFIG_WE5_PASSTHRU_ENABLE_BIT_VER2 = 33; -const uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT_VER2 = 34; -const uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_END_BIT_VER2 = 41; -const uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT_VER2 = 42; -const uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_END_BIT_VER2 = 49; -const uint32_t PB_SCONFIG_WE5_A_TOK_INIT_START_BIT_VER2 = 50; -const uint32_t PB_SCONFIG_WE5_A_TOK_INIT_END_BIT_VER2 = 53; -const uint32_t PB_SCONFIG_WE5_F_TOK_INIT_START_BIT_VER2 = 54; -const uint32_t PB_SCONFIG_WE5_F_TOK_INIT_END_BIT_VER2 = 57; -const uint32_t PB_SCONFIG_WE5_EM_FP_ENABLE_BIT_VER2 = 58; -const uint32_t PB_SCONFIG_WE5_SPARE_START_BIT_VER2 = 59; -const uint32_t PB_SCONFIG_WE5_SPARE_END_BIT_VER2 = 59; -const uint32_t PB_SCONFIG_WE5_A_IND_THRESHOLD_BIT_VER2 = 60; -const uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT_VER2 = 61; -const uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_END_BIT_VER2 = 62; -const uint32_t PB_SCONFIG_WE5_X_OFF_SEL_BIT_VER2 = 63; - -const bool PB_SCONFIG_WE5_LOCK_ON_LINKS = true; // lock -const uint8_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD = 0x4; // cnt_4 -const uint8_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD = 0x4; // cnt_4 -const uint8_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD = 0x4; // cnt_4 -const uint8_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD = 0x0; // cnt_0 -const uint8_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD = 0x0; // cnt_0 -const bool PB_SCONFIG_WE5_PASSTHRU_ENABLE = true; // enable -const uint8_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY = 0xFE; // cnt_7to1 -const uint8_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY = 0xFE; // cnt_7to1 -const uint8_t PB_SCONFIG_WE5_A_TOK_INIT = 0x8; // cnt_8 -const uint8_t PB_SCONFIG_WE5_F_TOK_INIT = 0x4; // cnt_4 -const bool PB_SCONFIG_WE5_EM_FP_ENABLE = true; // enable -const uint8_t PB_SCONFIG_WE5_SPARE = 0x0; // spare -const uint8_t PB_SCONFIG_WE5_MEM_STV_PRIORITY = 0x2; // stv - -const uint8_t PB_SCONFIG_WE5_A_IND_THRESHOLD = 0x0; // gt4 -const uint8_t PB_SCONFIG_WE5_X_OFF_SEL = 0x0; // disable +#include <proc_build_smp.H> +#include <p8_scom_addresses.H> extern "C" { @@ -541,6 +57,16 @@ extern "C" // parameters: i_smp => structure encapsulating SMP topology // returns: FAPI_RC_SUCCESS if register reads are successful and all shadow // registers are equivalent, +// FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of +// ADU atomic lock, +// RC_PROC_ADU_UTILS_INVALID_LOCK_OPERATION if an unsupported operation +// is specified, +// RC_PROC_ADU_UTILS_INVALID_LOCK_ATTEMPTS if invalid number of attempts +// is specified, +// RC_PROC_ADU_UTILS_INVALID_FBC_OP if invalid fabric operation +// parameters are specified, +// RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH if ADU status mismatches +// for switch operation, // RC_PROC_BUILD_SMP_CORE_FLOOR_RATIO_ERR if cache/nest frequency // ratio is unsupported, // RC_PROC_BUILD_SMP_CORE_CEILING_RATIO_ERR if cache/nest frequency diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.C index eb8c33392..9662fe015 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.C +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_fbc_nohp.C,v 1.5 2013/01/21 03:11:34 jmcgill Exp $ +// $Id: proc_build_smp_fbc_nohp.C,v 1.6 2014/02/23 21:41:07 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_nohp.C,v $ //------------------------------------------------------------------------------ // *| @@ -39,12 +39,151 @@ //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ -#include "proc_build_smp_fbc_nohp.H" +#include <proc_build_smp_fbc_nohp.H> + + +//------------------------------------------------------------------------------ +// Structure definitions +//------------------------------------------------------------------------------ + +// enumerate chips per group configurations +enum proc_build_smp_chips_per_group { + PROC_BUILD_SMP_1CPG = 0x0, + PROC_BUILD_SMP_2CPG = 0x1, + PROC_BUILD_SMP_4CPG = 0x2 +}; //------------------------------------------------------------------------------ // Constant definitions //------------------------------------------------------------------------------ + +// +// PB Mode register field/bit definitions +// + +const uint32_t PB_MODE_CHIP_IS_SYSTEM_BIT = 4; + +const uint32_t PB_MODE_SHADOWS[PROC_BUILD_SMP_NUM_SHADOWS] = +{ + PB_MODE_WEST_0x02010C0A, + PB_MODE_CENT_0x02010C4A, + PB_MODE_EAST_0x02010C8A +}; + + +// +// Group/Remote Group/System Command Pacing Rate register field/bit definitions +// + +const uint8_t PROC_BUILD_SMP_DP_LEVELS = 8; + +const uint8_t PB_GP_CMD_RATE_DP_LO_1CPG[PROC_BUILD_SMP_DP_LEVELS] = { 1, 2, 3, 4, 5, 6, 7, 8 }; +const uint8_t PB_GP_CMD_RATE_DP_HI_1CPG[PROC_BUILD_SMP_DP_LEVELS] = { 2, 4, 6, 8, 8, 8, 8, 8 }; +const uint8_t PB_RGP_CMD_RATE_DP_LO_1CPG[PROC_BUILD_SMP_DP_LEVELS] = { 9, 9, 9, 9, 10, 10, 11, 12 }; +const uint8_t PB_RGP_CMD_RATE_DP_HI_1CPG[PROC_BUILD_SMP_DP_LEVELS] = { 9, 10, 11, 12, 13, 14, 15, 16 }; +const uint8_t PB_SP_CMD_RATE_DP_LO_1CPG[PROC_BUILD_SMP_DP_LEVELS] = { 9, 10, 11, 12, 13, 14, 15, 16 }; +const uint8_t PB_SP_CMD_RATE_DP_HI_1CPG[PROC_BUILD_SMP_DP_LEVELS] = { 12, 13, 14, 16, 18, 20, 22, 24 }; + +const uint8_t PB_GP_CMD_RATE_DP_LO_2CPG[PROC_BUILD_SMP_DP_LEVELS] = { 3, 4, 5, 6, 7, 8, 10, 16 }; +const uint8_t PB_GP_CMD_RATE_DP_HI_2CPG[PROC_BUILD_SMP_DP_LEVELS] = { 4, 5, 6, 7, 8, 10, 12, 16 }; +const uint8_t PB_RGP_CMD_RATE_DP_LO_2CPG[PROC_BUILD_SMP_DP_LEVELS] = { 9, 10, 11, 12, 13, 14, 16, 32 }; +const uint8_t PB_RGP_CMD_RATE_DP_HI_2CPG[PROC_BUILD_SMP_DP_LEVELS] = { 12, 13, 14, 15, 16, 20, 32, 32 }; +const uint8_t PB_SP_CMD_RATE_DP_LO_2CPG[PROC_BUILD_SMP_DP_LEVELS] = { 12, 13, 14, 15, 16, 20, 32, 64 }; +const uint8_t PB_SP_CMD_RATE_DP_HI_2CPG[PROC_BUILD_SMP_DP_LEVELS] = { 20, 22, 24, 26, 32, 40, 64, 64 }; + +const uint8_t PB_GP_CMD_RATE_DP_LO_4CPG[PROC_BUILD_SMP_DP_LEVELS] = { 3, 4, 5, 6, 8, 10, 16, 32 }; +const uint8_t PB_GP_CMD_RATE_DP_HI_4CPG[PROC_BUILD_SMP_DP_LEVELS] = { 4, 6, 8, 12, 16, 20, 32, 32 }; +const uint8_t PB_RGP_CMD_RATE_DP_LO_4CPG[PROC_BUILD_SMP_DP_LEVELS] = { 9, 10, 11, 12, 16, 20, 32, 64 }; +const uint8_t PB_RGP_CMD_RATE_DP_HI_4CPG[PROC_BUILD_SMP_DP_LEVELS] = { 12, 14, 16, 24, 32, 40, 64, 64 }; +const uint8_t PB_SP_CMD_RATE_DP_LO_4CPG[PROC_BUILD_SMP_DP_LEVELS] = { 12, 14, 16, 24, 32, 40, 64, 128 }; +const uint8_t PB_SP_CMD_RATE_DP_HI_4CPG[PROC_BUILD_SMP_DP_LEVELS] = { 20, 24, 32, 48, 64, 80, 128, 128 }; + +const uint32_t PB_SCOPE_COMMAND_PACING_LVL_START_BIT[PROC_BUILD_SMP_DP_LEVELS] = { 0, 8, 16, 24, 32, 40, 48, 56 }; +const uint32_t PB_SCOPE_COMMAND_PACING_LVL_END_BIT[PROC_BUILD_SMP_DP_LEVELS] = { 7, 15, 23, 31, 39, 47, 55, 63 }; + + +// define set of group scope command pacing rate settings +struct proc_build_smp_gp_low_pacing_table +{ + static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map() + { + std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m; + m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_GP_CMD_RATE_DP_LO_1CPG)); + m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_GP_CMD_RATE_DP_LO_2CPG)); + m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_GP_CMD_RATE_DP_LO_4CPG)); + return m; + } + static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map; +}; + +struct proc_build_smp_gp_high_pacing_table +{ + static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map() + { + std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m; + m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_GP_CMD_RATE_DP_HI_1CPG)); + m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_GP_CMD_RATE_DP_HI_2CPG)); + m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_GP_CMD_RATE_DP_HI_4CPG)); + return m; + } + static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map; +}; + +struct proc_build_smp_sp_low_pacing_table +{ + static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map() + { + std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m; + m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_SP_CMD_RATE_DP_LO_1CPG)); + m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_SP_CMD_RATE_DP_LO_2CPG)); + m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_SP_CMD_RATE_DP_LO_4CPG)); + return m; + } + static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map; +}; + +struct proc_build_smp_sp_high_pacing_table +{ + static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map() + { + std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m; + m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_SP_CMD_RATE_DP_HI_1CPG)); + m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_SP_CMD_RATE_DP_HI_2CPG)); + m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_SP_CMD_RATE_DP_HI_4CPG)); + return m; + } + static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map; +}; + +struct proc_build_smp_rgp_low_pacing_table +{ + static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map() + { + std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m; + m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_RGP_CMD_RATE_DP_LO_1CPG)); + m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_RGP_CMD_RATE_DP_LO_2CPG)); + m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_RGP_CMD_RATE_DP_LO_4CPG)); + return m; + } + static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map; +}; + +struct proc_build_smp_rgp_high_pacing_table +{ + static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map() + { + std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m; + m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_RGP_CMD_RATE_DP_HI_1CPG)); + m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_RGP_CMD_RATE_DP_HI_2CPG)); + m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_RGP_CMD_RATE_DP_HI_4CPG)); + return m; + } + static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map; +}; + + + const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> proc_build_smp_gp_low_pacing_table::xlate_map = proc_build_smp_gp_low_pacing_table::create_map(); @@ -64,6 +203,54 @@ const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> proc_build_s proc_build_smp_rgp_high_pacing_table::create_map(); +// +// X Link Mode register field/bit definitions +// + +const uint32_t PB_X_MODE_TRACE_ENABLE_BIT = 4; +const uint32_t PB_X_MODE_TRACE_SELECT_START_BIT = 5; +const uint32_t PB_X_MODE_TRACE_SELECT_END_BIT = 7; + + +// +// A Link Trace register field/bit definitions +// + +const uint32_t PB_A_TRACE_A0_OUT_SEL0_START_BIT = 0; +const uint32_t PB_A_TRACE_A0_OUT_SEL0_END_BIT = 1; +const uint32_t PB_A_TRACE_A0_OUT_SEL1_START_BIT = 2; +const uint32_t PB_A_TRACE_A0_OUT_SEL1_END_BIT = 3; +const uint32_t PB_A_TRACE_A0_OUT_SEL2_START_BIT = 4; +const uint32_t PB_A_TRACE_A0_OUT_SEL2_END_BIT = 5; +const uint32_t PB_A_TRACE_A1_OUT_SEL0_START_BIT = 6; +const uint32_t PB_A_TRACE_A1_OUT_SEL0_END_BIT = 7; +const uint32_t PB_A_TRACE_A1_OUT_SEL1_START_BIT = 8; +const uint32_t PB_A_TRACE_A1_OUT_SEL1_END_BIT = 9; +const uint32_t PB_A_TRACE_A1_OUT_SEL2_START_BIT = 10; +const uint32_t PB_A_TRACE_A1_OUT_SEL2_END_BIT = 11; +const uint32_t PB_A_TRACE_A2_OUT_SEL0_START_BIT = 12; +const uint32_t PB_A_TRACE_A2_OUT_SEL0_END_BIT = 13; +const uint32_t PB_A_TRACE_A2_OUT_SEL1_START_BIT = 14; +const uint32_t PB_A_TRACE_A2_OUT_SEL1_END_BIT = 15; +const uint32_t PB_A_TRACE_A2_OUT_SEL2_START_BIT = 16; +const uint32_t PB_A_TRACE_A2_OUT_SEL2_END_BIT = 17; + +// +// F Link Trace register field/bit definitions +// + +const uint32_t PB_F_TRACE_F0_OUT_SEL0_START_BIT = 0; +const uint32_t PB_F_TRACE_F0_OUT_SEL0_END_BIT = 3; +const uint32_t PB_F_TRACE_F0_OUT_SEL1_START_BIT = 8; +const uint32_t PB_F_TRACE_F0_OUT_SEL1_END_BIT = 11; +const uint32_t PB_F_TRACE_F1_OUT_SEL0_START_BIT = 16; +const uint32_t PB_F_TRACE_F1_OUT_SEL0_END_BIT = 19; +const uint32_t PB_F_TRACE_F1_OUT_SEL1_START_BIT = 24; +const uint32_t PB_F_TRACE_F1_OUT_SEL1_END_BIT = 27; +const uint32_t PB_F_TRACE_F0_OBS_SEL = 32; +const uint32_t PB_F_TRACE_F1_OBS_SEL = 33; + + extern "C" { //------------------------------------------------------------------------------ @@ -109,7 +296,9 @@ fapi::ReturnCode proc_build_smp_calc_chips_per_group( default: FAPI_ERR("proc_build_smp_calc_chips_per_group: Unsupported group size (=%d)", chips_per_group_exact); - const uint8_t& SIZE = chips_per_group_exact; + const fapi::Target& TARGET = i_smp_chip.chip->this_chip; + const uint8_t& GROUP_SIZE = chips_per_group_exact; + const proc_fab_smp_node_id & NODE_ID = i_smp_chip.node_id; FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_INVALID_GROUP_SIZE_ERR); break; } @@ -155,6 +344,9 @@ fapi::ReturnCode proc_build_smp_set_pacing_rate( if (m == i_map_table.end()) { FAPI_ERR("proc_build_smp_set_pacing_rate: Pacing rate map table lookup failed"); + const fapi::Target& TARGET = i_smp_chip.chip->this_chip; + const proc_build_smp_chips_per_group& GROUP_SIZE = i_chips_per_group; + const proc_fab_smp_node_id& NODE_ID = i_smp_chip.node_id; FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_PACING_RATE_TABLE_ERR); break; } diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.H index 29545ae2e..927578c7e 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.H +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_fbc_nohp.H,v 1.2 2012/09/05 03:13:18 jmcgill Exp $ +// $Id: proc_build_smp_fbc_nohp.H,v 1.3 2014/02/23 21:41:07 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_nohp.H,v $ //------------------------------------------------------------------------------ // *| @@ -41,195 +41,8 @@ //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ -#include "proc_build_smp.H" -#include "p8_scom_addresses.H" - -//------------------------------------------------------------------------------ -// Structure definitions -//------------------------------------------------------------------------------ - -// enumerate chips per group configurations -enum proc_build_smp_chips_per_group { - PROC_BUILD_SMP_1CPG = 0x0, - PROC_BUILD_SMP_2CPG = 0x1, - PROC_BUILD_SMP_4CPG = 0x2 -}; - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -// -// PB Mode register field/bit definitions -// - -const uint32_t PB_MODE_CHIP_IS_SYSTEM_BIT = 4; - -const uint32_t PB_MODE_SHADOWS[PROC_BUILD_SMP_NUM_SHADOWS] = -{ - PB_MODE_WEST_0x02010C0A, - PB_MODE_CENT_0x02010C4A, - PB_MODE_EAST_0x02010C8A -}; - - -// -// Group/Remote Group/System Command Pacing Rate register field/bit definitions -// - -const uint8_t PROC_BUILD_SMP_DP_LEVELS = 8; - -const uint8_t PB_GP_CMD_RATE_DP_LO_1CPG[PROC_BUILD_SMP_DP_LEVELS] = { 1, 2, 3, 4, 5, 6, 7, 8 }; -const uint8_t PB_GP_CMD_RATE_DP_HI_1CPG[PROC_BUILD_SMP_DP_LEVELS] = { 2, 4, 6, 8, 8, 8, 8, 8 }; -const uint8_t PB_RGP_CMD_RATE_DP_LO_1CPG[PROC_BUILD_SMP_DP_LEVELS] = { 9, 9, 9, 9, 10, 10, 11, 12 }; -const uint8_t PB_RGP_CMD_RATE_DP_HI_1CPG[PROC_BUILD_SMP_DP_LEVELS] = { 9, 10, 11, 12, 13, 14, 15, 16 }; -const uint8_t PB_SP_CMD_RATE_DP_LO_1CPG[PROC_BUILD_SMP_DP_LEVELS] = { 9, 10, 11, 12, 13, 14, 15, 16 }; -const uint8_t PB_SP_CMD_RATE_DP_HI_1CPG[PROC_BUILD_SMP_DP_LEVELS] = { 12, 13, 14, 16, 18, 20, 22, 24 }; - -const uint8_t PB_GP_CMD_RATE_DP_LO_2CPG[PROC_BUILD_SMP_DP_LEVELS] = { 3, 4, 5, 6, 7, 8, 10, 16 }; -const uint8_t PB_GP_CMD_RATE_DP_HI_2CPG[PROC_BUILD_SMP_DP_LEVELS] = { 4, 5, 6, 7, 8, 10, 12, 16 }; -const uint8_t PB_RGP_CMD_RATE_DP_LO_2CPG[PROC_BUILD_SMP_DP_LEVELS] = { 9, 10, 11, 12, 13, 14, 16, 32 }; -const uint8_t PB_RGP_CMD_RATE_DP_HI_2CPG[PROC_BUILD_SMP_DP_LEVELS] = { 12, 13, 14, 15, 16, 20, 32, 32 }; -const uint8_t PB_SP_CMD_RATE_DP_LO_2CPG[PROC_BUILD_SMP_DP_LEVELS] = { 12, 13, 14, 15, 16, 20, 32, 64 }; -const uint8_t PB_SP_CMD_RATE_DP_HI_2CPG[PROC_BUILD_SMP_DP_LEVELS] = { 20, 22, 24, 26, 32, 40, 64, 64 }; - -const uint8_t PB_GP_CMD_RATE_DP_LO_4CPG[PROC_BUILD_SMP_DP_LEVELS] = { 3, 4, 5, 6, 8, 10, 16, 32 }; -const uint8_t PB_GP_CMD_RATE_DP_HI_4CPG[PROC_BUILD_SMP_DP_LEVELS] = { 4, 6, 8, 12, 16, 20, 32, 32 }; -const uint8_t PB_RGP_CMD_RATE_DP_LO_4CPG[PROC_BUILD_SMP_DP_LEVELS] = { 9, 10, 11, 12, 16, 20, 32, 64 }; -const uint8_t PB_RGP_CMD_RATE_DP_HI_4CPG[PROC_BUILD_SMP_DP_LEVELS] = { 12, 14, 16, 24, 32, 40, 64, 64 }; -const uint8_t PB_SP_CMD_RATE_DP_LO_4CPG[PROC_BUILD_SMP_DP_LEVELS] = { 12, 14, 16, 24, 32, 40, 64, 128 }; -const uint8_t PB_SP_CMD_RATE_DP_HI_4CPG[PROC_BUILD_SMP_DP_LEVELS] = { 20, 24, 32, 48, 64, 80, 128, 128 }; - -const uint32_t PB_SCOPE_COMMAND_PACING_LVL_START_BIT[PROC_BUILD_SMP_DP_LEVELS] = { 0, 8, 16, 24, 32, 40, 48, 56 }; -const uint32_t PB_SCOPE_COMMAND_PACING_LVL_END_BIT[PROC_BUILD_SMP_DP_LEVELS] = { 7, 15, 23, 31, 39, 47, 55, 63 }; - - -// define set of group scope command pacing rate settings -struct proc_build_smp_gp_low_pacing_table -{ - static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map() - { - std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m; - m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_GP_CMD_RATE_DP_LO_1CPG)); - m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_GP_CMD_RATE_DP_LO_2CPG)); - m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_GP_CMD_RATE_DP_LO_4CPG)); - return m; - } - static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map; -}; - -struct proc_build_smp_gp_high_pacing_table -{ - static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map() - { - std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m; - m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_GP_CMD_RATE_DP_HI_1CPG)); - m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_GP_CMD_RATE_DP_HI_2CPG)); - m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_GP_CMD_RATE_DP_HI_4CPG)); - return m; - } - static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map; -}; - -struct proc_build_smp_sp_low_pacing_table -{ - static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map() - { - std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m; - m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_SP_CMD_RATE_DP_LO_1CPG)); - m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_SP_CMD_RATE_DP_LO_2CPG)); - m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_SP_CMD_RATE_DP_LO_4CPG)); - return m; - } - static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map; -}; - -struct proc_build_smp_sp_high_pacing_table -{ - static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map() - { - std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m; - m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_SP_CMD_RATE_DP_HI_1CPG)); - m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_SP_CMD_RATE_DP_HI_2CPG)); - m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_SP_CMD_RATE_DP_HI_4CPG)); - return m; - } - static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map; -}; - -struct proc_build_smp_rgp_low_pacing_table -{ - static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map() - { - std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m; - m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_RGP_CMD_RATE_DP_LO_1CPG)); - m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_RGP_CMD_RATE_DP_LO_2CPG)); - m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_RGP_CMD_RATE_DP_LO_4CPG)); - return m; - } - static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map; -}; - -struct proc_build_smp_rgp_high_pacing_table -{ - static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map() - { - std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m; - m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_RGP_CMD_RATE_DP_HI_1CPG)); - m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_RGP_CMD_RATE_DP_HI_2CPG)); - m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_RGP_CMD_RATE_DP_HI_4CPG)); - return m; - } - static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map; -}; - - -// -// X Link Mode register field/bit definitions -// - -const uint32_t PB_X_MODE_TRACE_ENABLE_BIT = 4; -const uint32_t PB_X_MODE_TRACE_SELECT_START_BIT = 5; -const uint32_t PB_X_MODE_TRACE_SELECT_END_BIT = 7; - - -// -// A Link Trace register field/bit definitions -// - -const uint32_t PB_A_TRACE_A0_OUT_SEL0_START_BIT = 0; -const uint32_t PB_A_TRACE_A0_OUT_SEL0_END_BIT = 1; -const uint32_t PB_A_TRACE_A0_OUT_SEL1_START_BIT = 2; -const uint32_t PB_A_TRACE_A0_OUT_SEL1_END_BIT = 3; -const uint32_t PB_A_TRACE_A0_OUT_SEL2_START_BIT = 4; -const uint32_t PB_A_TRACE_A0_OUT_SEL2_END_BIT = 5; -const uint32_t PB_A_TRACE_A1_OUT_SEL0_START_BIT = 6; -const uint32_t PB_A_TRACE_A1_OUT_SEL0_END_BIT = 7; -const uint32_t PB_A_TRACE_A1_OUT_SEL1_START_BIT = 8; -const uint32_t PB_A_TRACE_A1_OUT_SEL1_END_BIT = 9; -const uint32_t PB_A_TRACE_A1_OUT_SEL2_START_BIT = 10; -const uint32_t PB_A_TRACE_A1_OUT_SEL2_END_BIT = 11; -const uint32_t PB_A_TRACE_A2_OUT_SEL0_START_BIT = 12; -const uint32_t PB_A_TRACE_A2_OUT_SEL0_END_BIT = 13; -const uint32_t PB_A_TRACE_A2_OUT_SEL1_START_BIT = 14; -const uint32_t PB_A_TRACE_A2_OUT_SEL1_END_BIT = 15; -const uint32_t PB_A_TRACE_A2_OUT_SEL2_START_BIT = 16; -const uint32_t PB_A_TRACE_A2_OUT_SEL2_END_BIT = 17; - -// -// F Link Trace register field/bit definitions -// - -const uint32_t PB_F_TRACE_F0_OUT_SEL0_START_BIT = 0; -const uint32_t PB_F_TRACE_F0_OUT_SEL0_END_BIT = 3; -const uint32_t PB_F_TRACE_F0_OUT_SEL1_START_BIT = 8; -const uint32_t PB_F_TRACE_F0_OUT_SEL1_END_BIT = 11; -const uint32_t PB_F_TRACE_F1_OUT_SEL0_START_BIT = 16; -const uint32_t PB_F_TRACE_F1_OUT_SEL0_END_BIT = 19; -const uint32_t PB_F_TRACE_F1_OUT_SEL1_START_BIT = 24; -const uint32_t PB_F_TRACE_F1_OUT_SEL1_END_BIT = 27; -const uint32_t PB_F_TRACE_F0_OBS_SEL = 32; -const uint32_t PB_F_TRACE_F1_OBS_SEL = 33; +#include <proc_build_smp.H> +#include <p8_scom_addresses.H> extern "C" |
