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| author | Christian Geddes <crgeddes@us.ibm.com> | 2018-08-21 15:15:25 -0500 |
|---|---|---|
| committer | William G. Hoffa <wghoffa@us.ibm.com> | 2018-09-05 07:50:51 -0500 |
| commit | e82098f4237a0f0fd6c00dc206b581d4d0d0156f (patch) | |
| tree | 7c6d995113491360f4414e9826d1ee05abca24f6 /src/usr/hwas/test | |
| parent | 2c8610bff34febfdfeb97fba484a75983141a8b3 (diff) | |
| download | talos-hostboot-e82098f4237a0f0fd6c00dc206b581d4d0d0156f.tar.gz talos-hostboot-e82098f4237a0f0fd6c00dc206b581d4d0d0156f.zip | |
Update PG detection for new Axone memory targets
Add support for presence detection of new OMI, OMIC, and MCC targets.
Detection is done by looking at the MC01, and MC23 PG data.
Change-Id: I2706bb28f64df653546ce22451e690507be09d8e
RTC: 197541
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64966
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/usr/hwas/test')
| -rw-r--r-- | src/usr/hwas/test/hwas1test.H | 230 |
1 files changed, 230 insertions, 0 deletions
diff --git a/src/usr/hwas/test/hwas1test.H b/src/usr/hwas/test/hwas1test.H index fa9cbb3ab..10f0f366c 100644 --- a/src/usr/hwas/test/hwas1test.H +++ b/src/usr/hwas/test/hwas1test.H @@ -1648,6 +1648,236 @@ public: } break; + case TYPE_OMI: + { + TS_INFO( "testHWASisDescFunctional: " + "OMI%d is not functional", l_chipUnit); + + size_t indexMC = l_chipUnit / 8; + size_t mcPgIndex = indexMC ? VPD_CP00_PG_MC23_INDEX : VPD_CP00_PG_MC01_INDEX; + + if (indexMC) + { + pgData[VPD_CP00_PG_N1_INDEX] |= + (uint16_t)VPD_CP00_PG_N1_MCS23; + } + else + { + pgData[VPD_CP00_PG_N3_INDEX] |= + (uint16_t)VPD_CP00_PG_N3_MCS01; + } + + if (isDescFunctional(pDesc, pgData)) + { + TS_FAIL("testHWASisDescFunctional>" + "functional = 0x%x, should be false, " + "N1/N3 for OMI%d = 0x%04x.", + isDescFunctional(pDesc, pgData), + l_chipUnit, + indexMC + ? pgData[VPD_CP00_PG_N1_INDEX] + : pgData[VPD_CP00_PG_N3_INDEX]); + } + + if (indexMC) + { + pgData[VPD_CP00_PG_N1_INDEX] = + (uint16_t)VPD_CP00_PG_N1_GOOD; + } + else + { + pgData[VPD_CP00_PG_N3_INDEX] = + (uint16_t)VPD_CP00_PG_N3_GOOD; + } + + for (l_mask = 0x8000; + l_mask > 0; + l_mask >>= 1) + { + if (pgData[mcPgIndex] & l_mask) + { + // Turn off a bit that should be on + pgData[mcPgIndex] &= ~l_mask; + } + else + { + // Turn on a bit that should be off + pgData[mcPgIndex] |= l_mask; + } + + if (isDescFunctional(pDesc, pgData)) + { + TS_FAIL("testHWASisDescFunctional>" + "functional = 0x%x, should be false, " + "MC%s for OMI%d = 0x%04x, " + "mask = 0x%04x.", + isDescFunctional(pDesc, pgData), + indexMC ? "01" : "23", + l_chipUnit, + pgData[mcPgIndex], + l_mask); + } + + // Restore the "all good" data + pgData[mcPgIndex] = (uint16_t)VPD_CP00_PG_MCxx_GOOD; + } + + break; + } + + case TYPE_OMIC: + { + TS_INFO( "testHWASisDescFunctional: " + "OMIC%d is not functional", l_chipUnit); + + size_t indexMC = l_chipUnit / 3; + size_t mcPgIndex = indexMC ? VPD_CP00_PG_MC23_INDEX : VPD_CP00_PG_MC01_INDEX; + + if (indexMC) + { + pgData[VPD_CP00_PG_N1_INDEX] |= + (uint16_t)VPD_CP00_PG_N1_MCS23; + } + else + { + pgData[VPD_CP00_PG_N3_INDEX] |= + (uint16_t)VPD_CP00_PG_N3_MCS01; + } + + if (isDescFunctional(pDesc, pgData)) + { + TS_FAIL("testHWASisDescFunctional>" + "functional = 0x%x, should be false, " + "N1/N3 for OMIC%d = 0x%04x.", + isDescFunctional(pDesc, pgData), + l_chipUnit, + indexMC + ? pgData[VPD_CP00_PG_N1_INDEX] + : pgData[VPD_CP00_PG_N3_INDEX]); + } + + if (indexMC) + { + pgData[VPD_CP00_PG_N1_INDEX] = + (uint16_t)VPD_CP00_PG_N1_GOOD; + } + else + { + pgData[VPD_CP00_PG_N3_INDEX] = + (uint16_t)VPD_CP00_PG_N3_GOOD; + } + + for (l_mask = 0x8000; + l_mask > 0; + l_mask >>= 1) + { + if (pgData[mcPgIndex] & l_mask) + { + // Turn off a bit that should be on + pgData[mcPgIndex] &= ~l_mask; + } + else + { + // Turn on a bit that should be off + pgData[mcPgIndex] |= l_mask; + } + + if (isDescFunctional(pDesc, pgData)) + { + TS_FAIL("testHWASisDescFunctional>" + "functional = 0x%x, should be false, " + "MC%s for OMIC%d = 0x%04x, " + "mask = 0x%04x.", + isDescFunctional(pDesc, pgData), + indexMC ? "01" : "23", + l_chipUnit, + pgData[mcPgIndex], + l_mask); + } + + // Restore the "all good" data + pgData[mcPgIndex] = (uint16_t)VPD_CP00_PG_MCxx_GOOD; + } + + break; + } + + case TYPE_MCC: + { + TS_INFO( "testHWASisDescFunctional: " + "MCC%d is not functional", l_chipUnit); + + size_t indexMC = l_chipUnit / 4; + size_t mcPgIndex = indexMC ? VPD_CP00_PG_MC23_INDEX : VPD_CP00_PG_MC01_INDEX; + + if (indexMC) + { + pgData[VPD_CP00_PG_N1_INDEX] |= + (uint16_t)VPD_CP00_PG_N1_MCS23; + } + else + { + pgData[VPD_CP00_PG_N3_INDEX] |= + (uint16_t)VPD_CP00_PG_N3_MCS01; + } + + if (isDescFunctional(pDesc, pgData)) + { + TS_FAIL("testHWASisDescFunctional>" + "functional = 0x%x, should be false, " + "N1/N3 for MCC%d = 0x%04x.", + isDescFunctional(pDesc, pgData), + l_chipUnit, + indexMC + ? pgData[VPD_CP00_PG_N1_INDEX] + : pgData[VPD_CP00_PG_N3_INDEX]); + } + + if (indexMC) + { + pgData[VPD_CP00_PG_N1_INDEX] = + (uint16_t)VPD_CP00_PG_N1_GOOD; + } + else + { + pgData[VPD_CP00_PG_N3_INDEX] = + (uint16_t)VPD_CP00_PG_N3_GOOD; + } + + for (l_mask = 0x8000; + l_mask > 0; + l_mask >>= 1) + { + if (pgData[mcPgIndex] & l_mask) + { + // Turn off a bit that should be on + pgData[mcPgIndex] &= ~l_mask; + } + else + { + // Turn on a bit that should be off + pgData[mcPgIndex] |= l_mask; + } + + if (isDescFunctional(pDesc, pgData)) + { + TS_FAIL("testHWASisDescFunctional>" + "functional = 0x%x, should be false, " + "MC%s for MCC%d = 0x%04x, " + "mask = 0x%04x.", + isDescFunctional(pDesc, pgData), + indexMC ? "01" : "23", + l_chipUnit, + pgData[mcPgIndex], + l_mask); + } + + // Restore the "all good" data + pgData[mcPgIndex] = (uint16_t)VPD_CP00_PG_MCxx_GOOD; + } + break; + } + case TYPE_OBUS_BRICK: { |
