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| author | Lateef Quraishi <lateef@us.ibm.com> | 2016-07-21 13:27:17 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-07-30 19:11:45 -0400 |
| commit | 5df2675372b378275cfe7e3b83d3663fed2fd21a (patch) | |
| tree | 9a8f33625b8e00542158f825969664f1c63bb458 /src/usr/fapi2/test/fapi2TestUtils.H | |
| parent | dec28fb2f89a231ae8a7e954e3d387fb878a8b27 (diff) | |
| download | talos-hostboot-5df2675372b378275cfe7e3b83d3663fed2fd21a.tar.gz talos-hostboot-5df2675372b378275cfe7e3b83d3663fed2fd21a.zip | |
Add getChipletNumber to Target Class
Chiplet Ids are as follows:
- EQ 0-5 Ids: 0x10 - 0x15
- EX 0-11 Ids: 0x10, 0x10, 0x11, 0x11, --- (parent's id)
- Cores 0-23 Ids: 0x20 - 0x37
- Pervasive Id: 0x01
- Xbus Id: 0x06
- Mcbist 0-1 Ids: 0x07 - 0x08
- Mcs 0-3 Ids: 0x07, 0x07, 0x08, 0x08 (parent's id)
- Mca 0-3 Ids: 0x07, 0x07, 0x07, 0x07 (parent's id)
- Mca 4-7 Ids: 0x08, 0x08, 0x08, 0x08 (parent's id)
- Obus0 Id: 0x09
- Obus3 Id: 0x0C
Change-Id: I89be032654c191b8930fac07a1b64061e381fe14
RTC: 156120
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27339
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr/fapi2/test/fapi2TestUtils.H')
| -rw-r--r-- | src/usr/fapi2/test/fapi2TestUtils.H | 28 |
1 files changed, 22 insertions, 6 deletions
diff --git a/src/usr/fapi2/test/fapi2TestUtils.H b/src/usr/fapi2/test/fapi2TestUtils.H index 21ba562d7..ccc90146d 100644 --- a/src/usr/fapi2/test/fapi2TestUtils.H +++ b/src/usr/fapi2/test/fapi2TestUtils.H @@ -33,15 +33,31 @@ #ifndef FAPI2TESTUTILS_H_ #define FAPI2TESTUTILS_H_ -#define EQ_PER_PROC 6 -#define EX_PER_EQ 2 -#define CORE_PER_EX 2 -#define MCS_PER_PROC 4 -#define MCA_PER_MCS 2 -#define MCBIST_PER_PROC 2 +#define EQ_PER_PROC 6 +#define EX_PER_EQ 2 +#define CORE_PER_EX 2 +#define MCS_PER_PROC 4 +#define MCA_PER_MCS 2 +#define MCBIST_PER_PROC 2 +#define MCS_PER_MCBIST 2 +#define PERV_PER_PROC 43 +#define XBUS_PER_PROC 1 +#define OBUS_PER_PROC 2 #define SIMULATED_GOOD_CORES 4 +// non-core and non-cache chiplet ids +#define START_PERV_CHIPLET_NUM 0x01 +#define START_XBUS_CHIPLET_NUM 0x06 +#define START_MCBIST_CHIPLET_NUM 0x07 +#define START_OBUS_CHIPLET_NUM 0x09 + +// All Cache Chiplets +#define START_EQ_CHIPLET_NUM 0x10 + +// All Core Chiplets +#define START_CORE_CHIPLET_NUM 0x20 + #include <fapi2.H> namespace fapi2 |
