diff options
author | Brian Stegmiller <bjs@us.ibm.com> | 2017-03-21 16:26:49 -0500 |
---|---|---|
committer | Zane C. Shelley <zshelle@us.ibm.com> | 2017-06-16 17:14:08 -0400 |
commit | 87824e36613d0f1a18ac2873012c7cc0ce98cc01 (patch) | |
tree | 6cb36e9886d4c4ab50b44612b57eb32e04bb5523 /src/usr/diag | |
parent | 44d178b6d050d9491e35360d5f3867e23c8ee895 (diff) | |
download | talos-hostboot-87824e36613d0f1a18ac2873012c7cc0ce98cc01.tar.gz talos-hostboot-87824e36613d0f1a18ac2873012c7cc0ce98cc01.zip |
PRDF: Update HOMER FIR data and read pnor
Change-Id: If8101569dfcaf25d3b9dfb493cc88e1bfab6f703
RTC: 161588
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38286
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41762
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/usr/diag')
-rw-r--r-- | src/usr/diag/prdf/common/plat/p9/p9_capp.rule | 37 | ||||
-rw-r--r-- | src/usr/diag/prdf/common/plat/p9/p9_ec.rule | 180 | ||||
-rw-r--r-- | src/usr/diag/prdf/common/plat/p9/p9_ex.rule | 68 | ||||
-rw-r--r-- | src/usr/diag/prdf/common/plat/p9/p9_mcs.rule | 52 | ||||
-rw-r--r-- | src/usr/diag/prdf/common/plat/p9/p9_nimbus.rule | 206 | ||||
-rw-r--r-- | src/usr/diag/prdf/common/plat/p9/p9_obus.rule | 16 | ||||
-rw-r--r-- | src/usr/diag/prdf/common/plat/p9/p9_phb.rule | 11 | ||||
-rw-r--r-- | src/usr/diag/prdf/common/plat/p9/p9_xbus.rule | 17 | ||||
-rw-r--r-- | src/usr/diag/prdf/occ_firdata/firDataConst_common.h | 94 | ||||
-rw-r--r-- | src/usr/diag/prdf/occ_firdata/homerData_common.h | 233 | ||||
-rw-r--r-- | src/usr/diag/prdf/occ_firdata/pnorData_common.h | 63 | ||||
-rw-r--r-- | src/usr/diag/prdf/occ_firdata/prdfReadPnorFirData.C | 56 | ||||
-rw-r--r-- | src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C | 1573 | ||||
-rw-r--r-- | src/usr/diag/prdf/test/prdfTest_WriteHomerFir.H | 146 |
14 files changed, 1969 insertions, 783 deletions
diff --git a/src/usr/diag/prdf/common/plat/p9/p9_capp.rule b/src/usr/diag/prdf/common/plat/p9/p9_capp.rule index 3b8c00b5a..5ad05ecff 100644 --- a/src/usr/diag/prdf/common/plat/p9/p9_capp.rule +++ b/src/usr/diag/prdf/common/plat/p9/p9_capp.rule @@ -79,6 +79,43 @@ chip p9_capp capture req nonzero("CXAFIR"); }; + ############################################################################ + # P9 CAPP target HDCT additions (open power chkstop analysis) + ############################################################################ + register SNOOP_ERR_RPT + { + name "P9 CAPP target Snoop Error Report"; + scomaddr 0x0201080a; + capture group default; + }; + + register APC_CERR + { + name "P9 CAPP target APC CERR"; + scomaddr 0x0201080b; + capture group default; + }; + + register XPT_ERR_RPT + { + name "P9 CAPP target XPT Error Report"; + scomaddr 0x0201080c; + capture group default; + }; + + register TLBI_ERR_RPT + { + name "P9 CAPP target TLBI Error Report"; + scomaddr 0x0201080d; + capture group default; + }; + + register CAPP_ERRSTAT_CTRL_REG + { + name "P9 CAPP target ErrorStatus and Ctrl Reg"; + scomaddr 0x0201080e; + capture group default; + }; # Include registers not defined by the xml .include "p9_capp_regs.rule"; diff --git a/src/usr/diag/prdf/common/plat/p9/p9_ec.rule b/src/usr/diag/prdf/common/plat/p9/p9_ec.rule index cd616a455..78942e0bb 100644 --- a/src/usr/diag/prdf/common/plat/p9/p9_ec.rule +++ b/src/usr/diag/prdf/common/plat/p9/p9_ec.rule @@ -163,6 +163,186 @@ chip p9_ec capture group default; }; + ############################################################################ + # P9 EC target HOMER Enable Reg + ############################################################################ + + register HOMER_ENABLE + { + name "P9 EC target HOMER ENABLE"; + capture group default; + scomaddr 0x20010a96; + }; + + ############################################################################ + # P9 EC target Spec Att Reason + ############################################################################ + + register SPEC_ATTN_REASON + { + name "P9 EC target SPEC ATTN REASON"; + scomaddr 0x20010a99; + capture group default; + }; + + register SPEC_ATTN_REASON_MASK + { + name "P9 EC target SPEC ATTN REASON MASK"; + scomaddr 0x20010a9a; + capture group default; + }; + + ############################################################################ + # P9 EC target CERR Holdout Regs + ############################################################################ + + register SPR_CORE_ERR_HOLDOUT + { + name "P9 EC target SPR CORE ERR HOLDOUT"; + scomaddr 0x20010ab5; + capture group default; + }; + + register PMU_ERR_HOLDOUT + { + name "P9 EC target PMU ERR HOLDOUT"; + scomaddr 0x20010ab6; + capture group default; + }; + + register TFAC_ERR_HOLDOUT + { + name "P9 EC target TFAC ERR HOLDOUT"; + scomaddr 0x20010ab7; + capture group default; + }; + + register SPR_COMMON_ERR_HOLDOUT + { + name "P9 EC target SPR COMMON ERR HOLDOUT"; + scomaddr 0x20010ab8; + capture group default; + }; + + register IFU_ERR_HOLDOUT0 + { + name "P9 EC target IFU ERR HOLDOUT 0"; + scomaddr 0x20010c00; + capture group default; + }; + + register IFU_ERR_HOLDOUT1 + { + name "P9 EC target IFU ERR HOLDOUT 1"; + scomaddr 0x20010c01; + capture group default; + }; + + register IFU_ERR_HOLDOUT2 + { + name "P9 EC target IFU ERR HOLDOUT 2"; + scomaddr 0x20010c02; + capture group default; + }; + + register IFU_ERR_HOLDOUT3 + { + name "P9 EC target IFU ERR HOLDOUT 3"; + scomaddr 0x20010c03; + capture group default; + }; + + register ISU_ERR_HOLDOUT0 + { + name "P9 EC target ISU ERR HOLDOUT 0"; + scomaddr 0x20010c40; + capture group default; + }; + + register ISU_ERR_HOLDOUT1 + { + name "P9 EC target ISU ERR HOLDOUT 1"; + scomaddr 0x20010c41; + capture group default; + }; + + register ISU_ERR_HOLDOUT2 + { + name "P9 EC target ISU ERR HOLDOUT 2"; + scomaddr 0x20010c42; + capture group default; + }; + + register ISU_ERR_HOLDOUT3 + { + name "P9 EC target ISU ERR HOLDOUT 3"; + scomaddr 0x20010c43; + capture group default; + }; + + register ISU_ERR_HOLDOUT4 + { + name "P9 EC target ISU ERR HOLDOUT 4"; + scomaddr 0x20010c44; + capture group default; + }; + + register ISU_ERR_HOLDOUT5 + { + name "P9 EC target ISU ERR HOLDOUT 5"; + scomaddr 0x20010c45; + capture group default; + }; + + register LSU_ERR_HOLDOUT0 + { + name "P9 EC target LSU ERR HOLDOUT 0"; + scomaddr 0x20010c80; + capture group default; + }; + + register LSU_ERR_HOLDOUT1 + { + name "P9 EC target LSU ERR HOLDOUT 1"; + scomaddr 0x20010c81; + capture group default; + }; + + register LSU_ERR_HOLDOUT2 + { + name "P9 EC target LSU ERR HOLDOUT 2"; + scomaddr 0x20010c82; + capture group default; + }; + + register LSU_ERR_HOLDOUT3 + { + name "P9 EC target LSU ERR HOLDOUT 3"; + scomaddr 0x20010c83; + capture group default; + }; + + register FIR_ERR_HOLDOUT + { + name "P9 EC target FIR ERR HOLDOUT"; + scomaddr 0x20010a51; + capture group default; + }; + + register THREAD_CTRL_ERR_HOLDOUT + { + name "P9 EC target THREAD CTRL ERR HOLDOUT"; + scomaddr 0x20010a03; + capture group default; + }; + + register PPM_STOP_STATE_HISTORY + { + name "P9 EC target PPM STOP STATE HISTORY"; + scomaddr 0x200f0110; + capture group default; + }; + # Include registers not defined by the xml .include "p9_ec_regs.rule"; diff --git a/src/usr/diag/prdf/common/plat/p9/p9_ex.rule b/src/usr/diag/prdf/common/plat/p9/p9_ex.rule index 45876f7f1..7e5daf08d 100644 --- a/src/usr/diag/prdf/common/plat/p9/p9_ex.rule +++ b/src/usr/diag/prdf/common/plat/p9/p9_ex.rule @@ -190,6 +190,74 @@ chip p9_ex }; + ############################################################################ + # P9 EX target ERROR REPORTING REGS + ############################################################################ + + register ERR_REPORT_REG0 + { + name "P9 EX target ERR REPORT REG0"; + scomaddr 0x10010812; + capture group default; + }; + + register ERR_REPORT_REG1 + { + name "P9 EX target ERR REPORT REG1"; + scomaddr 0x10010813; + capture group default; + }; + + register NCU_ERROR_REPORT_REG + { + name "P9 EX target NCU ERROR REPORT REG"; + scomaddr 0x1001100e; + capture group default; + }; + + register L3_PRD_PURGE_REG + { + name "P9 EX target L3 PRD PURGE REG"; + scomaddr 0x1001180e; + capture group default; + }; + + register L3_ERR_REPORT0 + { + name "P9 EX target L3 ERR REPORT 0"; + scomaddr 0x10011810; + capture group default; + }; + + register L3_ERR_REPORT1 + { + name "P9 EX target L3 ERR REPORT 1"; + scomaddr 0x10011817; + capture group default; + }; + + register L3_EDRAM_ERRSTAT_REG0 + { + name "P9 EX target L3 EDRAM ERRSTAT REG 0"; + scomaddr 0x10011819; + capture group default; + }; + + register L3_EDRAM_ERRSTAT_REG1 + { + name "P9 EX target L3 EDRAM ERRSTAT REG 1"; + scomaddr 0x1001181a; + capture group default; + }; + + register L3_EDRAM_BANK_FAIL + { + name "P9 EX target L3 EDRAM BANK FAIL"; + scomaddr 0x1001181b; + capture group default; + }; + + # Include registers not defined by the xml .include "p9_ex_regs.rule"; diff --git a/src/usr/diag/prdf/common/plat/p9/p9_mcs.rule b/src/usr/diag/prdf/common/plat/p9/p9_mcs.rule index 982976225..a5d379fbd 100644 --- a/src/usr/diag/prdf/common/plat/p9/p9_mcs.rule +++ b/src/usr/diag/prdf/common/plat/p9/p9_mcs.rule @@ -79,6 +79,58 @@ chip p9_mcs capture req nonzero("MCFIR"); }; + ############################################################################ + # P9 MCS target HDCT additions (open power chkstop analysis) + ############################################################################ + register MC_ERR_REPORT2 + { + name "P9 MCS target MC ERR REPORT2"; + scomaddr 0x0501081a; + capture group default; + }; + + register MC_ERR_REPORT0 + { + name "P9 MCS target MC ERR REPORT0"; + scomaddr 0x0501081e; + capture group default; + }; + + register MC_ERR_REPORT1 + { + name "P9 MCS target MC ERR REPORT1"; + scomaddr 0x0501081f; + capture group default; + }; + + register MEMCFG_REG + { + name "P9 MCS target MEMCFG REG"; + scomaddr 0x0501080a; + capture group default; + }; + + register MCFGPA + { + name "P9 MCS target MCFGPA"; + scomaddr 0x0501080b; + capture group default; + }; + + register MCFGPM + { + name "P9 MCS target MCFGPM"; + scomaddr 0x0501080c; + capture group default; + }; + + register MCFGPMA + { + name "P9 MCS target MCFGPMA"; + scomaddr 0x0501080d; + capture group default; + }; + # Include registers not defined by the xml .include "p9_mcs_regs.rule"; diff --git a/src/usr/diag/prdf/common/plat/p9/p9_nimbus.rule b/src/usr/diag/prdf/common/plat/p9/p9_nimbus.rule index 15435c5d8..5baa56c83 100644 --- a/src/usr/diag/prdf/common/plat/p9/p9_nimbus.rule +++ b/src/usr/diag/prdf/common/plat/p9/p9_nimbus.rule @@ -1560,6 +1560,212 @@ chip p9_nimbus capture group PciChipletFir2; }; + ############################################################################ + # P9 PROC target HDCT additions (open power chkstop analysis) + ############################################################################ + + register OCC_ERROR_REPORT_REG + { + name "OCC ERROR REPORT REG"; + scomaddr 0x0101080a; + capture group default; + }; + + register PB_ERROR_REPORT + { + name "PB ERROR REPORT REG"; + scomaddr 0x020110a1; + capture group default; + }; + + register PB_PTY_ERROR_REPORT + { + name "PB PTY ERROR REPORT REG"; + scomaddr 0x020110a2; + capture group default; + }; + + register DMA_CERR_0 + { + name "DMA CERR 0"; + scomaddr 0x02011057; + capture group default; + }; + + register DMA_CERR_1 + { + name "DMA CERR 1"; + scomaddr 0x02011058; + capture group default; + }; + + register PB_CENT_CR_ERROR + { + name "PB CENT CR ERROR"; + scomaddr 0x05011c2c; + capture group default; + }; + + register PBA_ERR_REPORT_0 + { + name "PBA ERROR REPORT 0"; + scomaddr 0x0501284c; + capture group default; + }; + + register PBA_ERR_REPORT_1 + { + name "PBA ERROR REPORT 1"; + scomaddr 0x0501284d; + capture group default; + }; + + register PBA_ERR_REPORT_2 + { + name "PBA ERROR REPORT 2"; + scomaddr 0x0501284e; + capture group default; + }; + + register PB_PTY_ERR_REPORT + { + name "PB PTY ERROR REPORT"; + scomaddr 0x05012C22; + capture group default; + }; + + register TOD_SLAVE_PATH_CTRL + { + name "TOD SLAVE PATH CTRL"; + scomaddr 0x00040005; + capture group default; + }; + + register TOD_INTERNAL_PATH_CTRL + { + name "TOD INTERNAL PATH CTRL"; + scomaddr 0x00040006; + capture group default; + }; + + register TOD_CONFIG_CTRL + { + name "TOD Prim Sec Config Control"; + scomaddr 0x00040007; + capture group default; + }; + + register TOD_PSS_MSS_STATUS + { + name "TOD PSS MSS Status Reg"; + scomaddr 0x00040008; + capture group default; + }; + + register TOD_MASTER_PATH_STATUS + { + name "TOD Master Path Status Reg"; + scomaddr 0x00040009; + capture group default; + }; + + register TOD_MASTER_PATH0_STEP_STEERING + { + name "TOD Master Path0 Step Steering"; + scomaddr 0x0004000E; + capture group default; + }; + + register TOD_MASTER_PATH1_STEP_STEERING + { + name "TOD Master Path1 Step Steering"; + scomaddr 0x0004000F; + capture group default; + }; + + register TOD_TRACE_DATASET_1 + { + name "TOD Trace Dataset 1"; + scomaddr 0x0004001D; + capture group default; + }; + + register TOD_TRACE_DATASET_2 + { + name "TOD Trace Dataset 2"; + scomaddr 0x0004001E; + capture group default; + }; + + register TOD_TRACE_DATASET_3 + { + name "TOD Trace Dataset 3"; + scomaddr 0x0004001F; + capture group default; + }; + + register OSC_ERROR_HOLD + { + name "OSC ERROR HOLD"; + scomaddr 0x01020019; + capture group default; + }; + + register OSC_ERROR_MASK + { + name "OSC ERROR MASK"; + scomaddr 0x0102001A; + capture group default; + }; + + register OSC_ERROR_MODE + { + name "OSC ERROR MODE"; + scomaddr 0x0102001B; + capture group default; + }; + + register TOD_FSM_REGISTER + { + name "TOD FSM Register"; + scomaddr 0x00040024; + capture group default; + }; + + register TOD_TX_TTYPE_CTRL_REG + { + name "TOD TX TType Ctrl reg"; + scomaddr 0x00040027; + capture group default; + }; + + register TOD_RX_TTYPE_CTRL_REG + { + name "TOD RX TType Ctrl reg"; + scomaddr 0x00040029; + capture group default; + }; + + register TOD_ERROR_INTERRUPTS + { + name "TOD Error and Interrupts"; + scomaddr 0x00040030; + capture group default; + }; + + register TOD_CERR_REPORT + { + name "TOD CERR Report"; + scomaddr 0x00040032; + capture group default; + }; + + register TOD_ROUTE_ERRORS_TO_CORE + { + name "TOD Route Errors to Core"; + scomaddr 0x00040033; + capture group default; + }; # Include registers not defined by the xml .include "p9_nimbus_regs.rule"; diff --git a/src/usr/diag/prdf/common/plat/p9/p9_obus.rule b/src/usr/diag/prdf/common/plat/p9/p9_obus.rule index d086c1bba..d6767c995 100644 --- a/src/usr/diag/prdf/common/plat/p9/p9_obus.rule +++ b/src/usr/diag/prdf/common/plat/p9/p9_obus.rule @@ -230,6 +230,22 @@ chip p9_obus capture req nonzero("OBPPEFIR"); }; + ############################################################################ + # P9 OBUS target HDCT additions (open power chkstop analysis) + ############################################################################ + register PBOLL_LINK0_ERRSTAT + { + name "P9 OBUS target PB OLL Link0 ErrStatus"; + scomaddr 0x09010816; + capture group default; + }; + + register PBOLL_LINK1_ERRSTAT + { + name "P9 OBUS target PB OLL Link1 ErrStatus"; + scomaddr 0x09010817; + capture group default; + }; # Include registers not defined by the xml .include "p9_obus_regs.rule"; diff --git a/src/usr/diag/prdf/common/plat/p9/p9_phb.rule b/src/usr/diag/prdf/common/plat/p9/p9_phb.rule index 857448617..656665ad7 100644 --- a/src/usr/diag/prdf/common/plat/p9/p9_phb.rule +++ b/src/usr/diag/prdf/common/plat/p9/p9_phb.rule @@ -151,6 +151,17 @@ chip p9_phb capture req nonzero("ETUFIR"); }; + ############################################################################ + # P9 PHB target CERR Report Hold Reg + ############################################################################ + + register PBAIB_CERR + { + name "P9 PHB target PBAIB CERR Report Reg"; + scomaddr 0x0d01084b; + capture group default; + }; + # Include registers not defined by the xml .include "p9_phb_regs.rule"; diff --git a/src/usr/diag/prdf/common/plat/p9/p9_xbus.rule b/src/usr/diag/prdf/common/plat/p9/p9_xbus.rule index 2ace7c3d3..dc35e2c31 100644 --- a/src/usr/diag/prdf/common/plat/p9/p9_xbus.rule +++ b/src/usr/diag/prdf/common/plat/p9/p9_xbus.rule @@ -115,6 +115,23 @@ chip p9_xbus capture req nonzero("IOELFIR"); }; + ############################################################################ + # P9 XBUS target HDCT additions (open power chkstop analysis) + ############################################################################ + register PBELL_LINK0_ERRSTAT + { + name "P9 XBUS target PB ELL Link0 ErrStatus"; + scomaddr 0x06011816; + capture group default; + }; + + register PBELL_LINK1_ERRSTAT + { + name "P9 XBUS target PB ELL Link1 ErrStatus"; + scomaddr 0x06011817; + capture group default; + }; + # Include registers not defined by the xml .include "p9_xbus_regs.rule"; diff --git a/src/usr/diag/prdf/occ_firdata/firDataConst_common.h b/src/usr/diag/prdf/occ_firdata/firDataConst_common.h index 3b8f9bb71..d9e870309 100644 --- a/src/usr/diag/prdf/occ_firdata/firDataConst_common.h +++ b/src/usr/diag/prdf/occ_firdata/firDataConst_common.h @@ -33,29 +33,79 @@ #include <stdint.h> /** Target types for all supported targets. */ +/** NOTE: These are used to build the register list in HOMER data */ +/** and also to create the exiting chiplet masks. Hence, */ +/** the numbers assigned here have to match the sequence */ +/** of chiplets in HOMER_ChipNimbus_t, HOMER_ChipCumulus_t, etc. */ typedef enum { /* NOTE: These will be used as array indexes. */ - FIRST_TRGT = 0, - PROC = FIRST_TRGT, - EX, - MCS, - MEMB, - MBA, - MAX_TRGTS, + TRGT_FIRST = 0, + + /** Common Nimbus/Cumulus types */ + TRGT_PROC = TRGT_FIRST, + TRGT_CAPP, + TRGT_XBUS, + TRGT_OBUS, + TRGT_PEC, + TRGT_PHB, + TRGT_EQ, + TRGT_EX, + TRGT_EC, + + /* Nimbus only */ + TRGT_MCBIST, + TRGT_MCS, + TRGT_MCA, + + /* Cumulus only */ + /* NOTE: Nimbus and Cumulus cannot be used at the same time. So we can have + * These array indexes overlap to save space. */ + TRGT_MC = TRGT_MCBIST, + TRGT_MI, + TRGT_DMI, + + /* Centaur only */ + TRGT_MEMBUF, + TRGT_MBA, + + /* EC level handling -- special case for NIMBUS */ + TRGT_PROC_NIMBUS_10, + TRGT_PROC_NIMBUS_20, + + TRGT_MAX, } TrgtType_t; /** Boundary/position ranges for each target type. */ typedef enum { - MAX_PROC_PER_NODE = 8, - MAX_EX_PER_PROC = 16, - MAX_MCS_PER_PROC = 8, - MAX_MEMB_PER_PROC = MAX_MCS_PER_PROC, - MAX_MEMB_PER_NODE = MAX_MEMB_PER_PROC * MAX_PROC_PER_NODE, - MAX_MBA_PER_MEMB = 2, - MAX_MBA_PER_PROC = MAX_MEMB_PER_PROC * MAX_MBA_PER_MEMB, + /* Common Nimbus/Cumulus */ + MAX_PROC_PER_NODE = 8, + MAX_CAPP_PER_PROC = 2, + MAX_XBUS_PER_PROC = 3, /* Nimbus 1 and 2, Cumulus 0, 1, and 2 */ + MAX_OBUS_PER_PROC = 4, /* Nimbus 0 and 3, Cumulus 0, 1, 2, and 3 */ + MAX_PEC_PER_PROC = 3, + MAX_PHB_PER_PROC = 6, + MAX_EQ_PER_PROC = 6, + MAX_EX_PER_PROC = 12, + MAX_EC_PER_PROC = 24, + + /** Nimbus only */ + MAX_MCBIST_PER_PROC = 2, + MAX_MCS_PER_PROC = 4, + MAX_MCA_PER_PROC = 8, + + /** Cumulus only */ + MAX_MC_PER_PROC = 2, + MAX_MI_PER_PROC = 4, + MAX_DMI_PER_PROC = 8, + + /** Centaur only */ + MAX_MEMBUF_PER_PROC = 8, + MAX_MEMBUF_PER_NODE = MAX_MEMBUF_PER_PROC * MAX_PROC_PER_NODE, + MAX_MBA_PER_MEMBUF = 2, + MAX_MBA_PER_PROC = MAX_MEMBUF_PER_PROC * MAX_MBA_PER_MEMBUF, } TrgtPos_t; @@ -63,13 +113,15 @@ typedef enum typedef enum { /* NOTE: These will be used as array indexes. */ - FIRST_REG = 0, - GLBL = FIRST_REG, - FIR, - REG, - IDFIR, - IDREG, - MAX_REGS, + REG_FIRST = 0, + + REG_GLBL = REG_FIRST, /* 32-bit addresses, 64-bit value */ + REG_FIR, /* 32-bit addresses, 64-bit value */ + REG_REG, /* 32-bit addresses, 64-bit value */ + REG_IDFIR, /* 64-bit addresses, 32-bit value */ + REG_IDREG, /* 64-bit addresses, 32-bit value */ + + REG_MAX, } RegType_t; diff --git a/src/usr/diag/prdf/occ_firdata/homerData_common.h b/src/usr/diag/prdf/occ_firdata/homerData_common.h index e43d7ecfb..c470ce6dc 100644 --- a/src/usr/diag/prdf/occ_firdata/homerData_common.h +++ b/src/usr/diag/prdf/occ_firdata/homerData_common.h @@ -38,26 +38,22 @@ * in the event of a system checkstop. The data will be stored in the following * format: * - * - HOMER_Data_t struct - This has all of the information characterizing what - * hardware is configured and how many addresses are in each register - * list. See the struct definition below. + * - HOMER_Data_t struct - This contains PNOR information, IPL state, number of + * configured chips, and number of register addresses per target type per + * register type. * - * - Rgister address lists - These lists vary in size depending on the number - * of register addresses needed in each list. The list counts are - * stored in HOMER_Data_t::counts. All lists for each target type will - * be stored in the following order: - * - PROC lists - * - EX lists - * - MCS lists - * - MEMB lists - * - MBA lists - * Each target type will have a set of lists that will be stored in the - * following order: - * - Global FIRs 32-bit addresses - * - FIRs 32-bit addresses - * - Registers 32-bit addresses - * - Indirect-SCOM FIRs 64-bit addresses - * - Indirect-SCOM registers 64-bit addresses + * - For each configured chip, the following format will be used: + * - HOMER_Chip_t struct - containing FSI base address, chip type, and chip + * position. + * - Immediately following will be a chip struct that is specific to the + * chip type stored in the preceding struct. These vary in size and + * structure depending on the chip type. + * + * - Register address lists - These lists vary in size depending on the number + * of register addresses needed in each list. The list counts are stored in + * HOMER_Data_t::regCounts. Order of the lists must match the array indexes + * HOMER_Data_t::regCounts, which are specified in TrgtType_t and + * RegType_t. * * Note that FIRs and indirect-SCOM FIRs characterize a set of registers to * capture. In addition to capturing the FIR (or ID FIR), the OCC will need to @@ -77,7 +73,8 @@ typedef enum { - HOMER_FIR1 = 0x46495231, /** FIR data version 1 ("FIR1" in ascii) */ + HOMER_FIR1 = 0x46495231, /** FIR data version 1 ("FIR1" in ascii) P8 */ + HOMER_FIR2 = 0x46495232, /** FIR data version 1 ("FIR2" in ascii) P9 */ } HOMER_Version_t; @@ -97,45 +94,13 @@ typedef struct __attribute__((packed)) { uint32_t header; /** Magic number to indicate valid data and version */ - uint16_t iplState : 1; /** See enum IplState_t */ - uint16_t reserved : 15; - - uint8_t masterProc; /** The position of the master PROC */ - - /** Bitwise mask to indicate which PROCs are configured (max 8). The mask - * bit position is consistant with PROC ATTR_POSITION attribute. */ - uint8_t procMask; - - /** Bitwise masks to indicate which EXs are configured (16 per PROC). The - * array index is the associated PROC position. The mask bit position is - * consistant with the EX's ATTR_CHIP_UNIT attribute. */ - uint16_t exMasks[MAX_PROC_PER_NODE]; + uint8_t chipCount; /** Number of configured chips per node */ - /** Bitwise masks to indicate which MCSs are configured (8 per PROC). The - * array index is the associated PROC position. The mask bit position is - * consistant with the MCS's ATTR_CHIP_UNIT attribute. */ - uint8_t mcsMasks[MAX_PROC_PER_NODE]; - - /** Bitwise masks to indicate which MEMBs are configured (8 per PROC). The - * array index is the associated PROC position. The mask bit position is - * consistant with the ATTR_CHIP_UNIT attribute of the connected MCS. */ - uint8_t membMasks[MAX_PROC_PER_NODE]; - - /** Bitwise masks to indicate which MBAs are configured (16 per PROC). The - * array index is the associated PROC position. The mask bit position is - * calculated as: - * (MEMB position * MAX_MBA_PER_MEMB) + MBA's ATTR_CHIP_UNIT attribute - */ - uint16_t mbaMasks[MAX_PROC_PER_NODE]; + uint8_t iplState : 1; /** See IplState_t. */ + uint8_t reserved : 7; /** Contains number of registers per type for each target type. */ - uint8_t counts[MAX_TRGTS][MAX_REGS]; - - /** FSI base address for each PROC chip. */ - uint32_t procFsiBaseAddr[MAX_PROC_PER_NODE]; - - /** FSI base address for each MEMB chip. */ - uint32_t membFsiBaseAddr[MAX_PROC_PER_NODE][MAX_MEMB_PER_PROC]; + uint8_t regCounts[TRGT_MAX][REG_MAX]; /** Information regarding the PNOR location and size. */ HOMER_PnorInfo_t pnorInfo; @@ -145,29 +110,143 @@ typedef struct __attribute__((packed)) /** @return An initialized HOMER_Data_t struct. */ static inline HOMER_Data_t HOMER_getData() { - HOMER_PnorInfo_t p; - HOMER_Data_t d; - - p.pnorOffset = 0; - p.pnorSize = 0; - p.mmioOffset = 0; - p.norWorkarounds = 0; - - d.header = HOMER_FIR1; - d.reserved = 0; - d.masterProc = 0; - d.procMask = 0; - d.pnorInfo = p; - - memset( d.exMasks, 0x00, sizeof(d.exMasks) ); - memset( d.mcsMasks, 0x00, sizeof(d.mcsMasks) ); - memset( d.membMasks, 0x00, sizeof(d.membMasks) ); - memset( d.mbaMasks, 0x00, sizeof(d.mbaMasks) ); - memset( d.counts, 0x00, sizeof(d.counts) ); - memset( d.procFsiBaseAddr, 0xff, sizeof(d.procFsiBaseAddr) ); - memset( d.membFsiBaseAddr, 0xff, sizeof(d.membFsiBaseAddr) ); + HOMER_Data_t d; memset( &d, 0x00, sizeof(d) ); /* init to zero */ + + d.header = HOMER_FIR2; return d; } +/*----------------------------------------------------------------------------*/ + +/** Supported chip types. */ +typedef enum +{ + HOMER_CHIP_NIMBUS, /** P9 Nimbus processor chip */ + HOMER_CHIP_CUMULUS, /** P9 Cumulus processor chip */ + HOMER_CHIP_CENTAUR, /** Centaur memory buffer chip */ + +} HOMER_ChipType_t; + +/** Information for each configured chip. */ +typedef struct __attribute__((packed)) +{ + uint32_t fsiBaseAddr; /** FSI base address for the chip. */ + + uint16_t chipType : 4; /** Chip type (see HOMER_ChipType_t) */ + uint16_t chipPos : 6; /** Chip position relative to the node. */ + uint16_t reserved : 6; + +} HOMER_Chip_t; + +/** @return An initialized HOMER_Chip_t struct. */ +static inline HOMER_Chip_t HOMER_getChip( HOMER_ChipType_t i_type ) +{ + HOMER_Chip_t c; memset( &c, 0x00, sizeof(c) ); /* init to zero */ + + c.fsiBaseAddr = 0xffffffff; + c.chipType = i_type; + + return c; +} + +/*----------------------------------------------------------------------------*/ + +/** Information specific to a P9 Nimbus processor chip. */ +typedef struct __attribute__((packed)) +{ + uint32_t isMaster : 1; /** 1 if this is the master PROC, 0 otherwise */ + uint32_t xbusMask : 3; /** Mask of configured XBUS units (0-2) */ + uint32_t obusMask : 4; /** Mask of configured OBUS units (0-3) */ + uint32_t ecMask : 24; /** Mask of configured EC units (0-23) */ + + uint32_t eqMask : 6; /** Mask of configured EQ units (0-5) */ + uint32_t exMask : 12; /** Mask of configured EX units (0-11) */ + uint32_t mcbistMask : 2; /** Mask of configured MCBIST units (0-1) */ + uint32_t mcsMask : 4; /** Mask of configured MCS units (0-3) */ + uint32_t mcaMask : 8; /** Mask of configured MCA units (0-7) */ + + uint16_t cappMask : 2; /** Mask of configured CAPP units (0-1) */ + uint16_t pecMask : 3; /** Mask of configured PEC units (0-2) */ + uint16_t phbMask : 6; /** Mask of configured PHB units (0-5) */ + uint16_t reserved : 5; + +} HOMER_ChipNimbus_t; + +/** @return An initialized HOMER_ChipNimbus_t struct. */ +static inline HOMER_ChipNimbus_t HOMER_initChipNimbus() +{ + HOMER_ChipNimbus_t c; memset( &c, 0x00, sizeof(c) ); /* init to zero */ + + return c; +} + +/*----------------------------------------------------------------------------*/ + +/** Information specific to a P9 Cumulus processor chip. */ +typedef struct __attribute__((packed)) +{ + uint32_t isMaster : 1; /** 1 if this is the master PROC, 0 otherwise */ + uint32_t xbusMask : 3; /** Mask of configured XBUS units (0-2) */ + uint32_t obusMask : 4; /** Mask of configured OBUS units (0-3) */ + uint32_t ecMask : 24; /** Mask of configured EC units (0-23) */ + + uint32_t eqMask : 6; /** Mask of configured EQ units (0-5) */ + uint32_t exMask : 12; /** Mask of configured EX units (0-11) */ + uint32_t mcMask : 2; /** Mask of configured MC units (0-1) */ + uint32_t miMask : 4; /** Mask of configured MI units (0-3) */ + uint32_t dmiMask : 8; /** Mask of configured DMI units (0-7) */ + + uint16_t cappMask : 2; /** Mask of configured CAPP units (0-1) */ + uint16_t pecMask : 3; /** Mask of configured PEC units (0-2) */ + uint16_t phbMask : 6; /** Mask of configured PHB units (0-5) */ + uint16_t reserved : 5; + +} HOMER_ChipCumulus_t; + +/** @return An initialized HOMER_ChipCumulus_t struct. */ +static inline HOMER_ChipCumulus_t HOMER_initChipCumulus() +{ + HOMER_ChipCumulus_t c; memset( &c, 0x00, sizeof(c) ); /* init to zero */ + + return c; +} + +/*----------------------------------------------------------------------------*/ + +/** Information specific to a Centaur memory buffer chip. */ +typedef struct __attribute__((packed)) +{ + uint8_t mbaMask : 2; /** Mask of configured MBA units (0-1) */ + uint8_t reserved : 6; + +} HOMER_ChipCentaur_t; + +/** @return An initialized HOMER_ChipCentaur_t struct. */ +static inline HOMER_ChipCentaur_t HOMER_initChipCentaur() +{ + HOMER_ChipCentaur_t c; memset( &c, 0x00, sizeof(c) ); /* init to zero */ + + return c; +} + +/** @brief Chip information inserted into HOMER data section after header + * + * There is basically an array of these after the initial HOMER + * section (HOMER_Data_t). The register info then follows. + */ +typedef struct __attribute__((packed)) +{ + HOMER_Chip_t hChipType; + + union + { + HOMER_ChipNimbus_t hChipN; + HOMER_ChipCumulus_t hChipC; + HOMER_ChipCentaur_t hChipM; + }; + +} HOMER_ChipInfo_t; + + #endif /* __homerData_common_h */ diff --git a/src/usr/diag/prdf/occ_firdata/pnorData_common.h b/src/usr/diag/prdf/occ_firdata/pnorData_common.h index eab98e541..1174a72e7 100644 --- a/src/usr/diag/prdf/occ_firdata/pnorData_common.h +++ b/src/usr/diag/prdf/occ_firdata/pnorData_common.h @@ -31,6 +31,7 @@ * because OCC strictly uses C. */ #include <firDataConst_common.h> +#include <string.h> /** This file is used to define the format of the register data captured by the * OCC and stored in PNOR. The data will be stored in the following format: @@ -53,12 +54,9 @@ * - Each target type may have associated global registers. If none exist, * simply capture all registers for that type. However, if they do exist * and the values of ALL the global registers are zero, skip capturing - * the associated targets using the following rules: - * - For a PROC, skip this PROC and all associated EXs, and MCSs. - * - For an EX, skip this EX. - * - For an MCS, skip this MCS. - * - For a MEMB, skip this MEMB and all associated MBAs. - * - For an MBA, skip this MBA. + * the associated registers of the target and any subsequent targets on + * the affinity path. Example, + * - For a MCBIST, skip this MCBIST and all associated MCSs, and MCAs. * - If for some reason we run out of space in the PNOR, do not SCOM any * more registers, set the 'full' bit in the PNOR_Data_t struct, and * write all data successfully captured to PNOR. @@ -66,7 +64,8 @@ typedef enum { - PNOR_FIR1 = 0x46495231, /** FIR data version 1 ("FIR1" in ascii) */ + PNOR_FIR1 = 0x46495231, /** FIR data version 1 ("FIR1" in ascii) P8 */ + PNOR_FIR2 = 0x46495232, /** FIR data version 2 ("FIR2" in ascii) P9 */ } PNOR_Version_t; @@ -75,21 +74,19 @@ typedef struct __attribute__((packed)) { uint32_t header; /** Magic number to indicate valid data and version */ - uint32_t trgts : 8; /** Number of targets with register data */ - uint32_t full : 1; /** 1 if PNOR data is full and data may be missing*/ - uint32_t iplState : 1; /** See enum IplState_t */ - uint32_t reserved : 22; + uint16_t trgts : 12; /** Number of targets with register data */ + uint16_t full : 1; /** 1 if PNOR data is full and data incomplete */ + uint16_t iplState : 1; /** See enum IplState_t */ + uint16_t reserved : 2; } PNOR_Data_t; /** @return An initialized PNOR_Data_t struct. */ static inline PNOR_Data_t PNOR_getData() { - PNOR_Data_t d; - d.header = PNOR_FIR1; - d.trgts = 0; - d.full = 0; - d.reserved = 0; + PNOR_Data_t d; memset( &d, 0x00, sizeof(d) ); /* init to zero */ + + d.header = PNOR_FIR2; return d; }; @@ -99,37 +96,37 @@ typedef enum { PNOR_Trgt_MAX_REGS_PER_TRGT = 511, /* Currently expect 266 on the PROC */ PNOR_Trgt_MAX_ID_REGS_PER_TRGT = 15, /* Currently expect 9 on the MBA */ - PNOR_Trgt_MAX_SCOM_ERRORS = 511, /* Should be plenty */ + PNOR_Trgt_MAX_SCOM_ERRORS = 255, /* Should be plenty */ } PNOR_Trgt_RegLimits_t; /** Information for each target with SCOM data. */ typedef struct __attribute__((packed)) { - uint32_t type : 3; /** Target type. See enum TrgtType_t */ - uint32_t procPos : 3; /** The processor position (0-7) */ - uint32_t unitPos : 4; /** Unit position relative to the processor (0-15) */ + uint32_t chipPos : 6; /** Parent chip position relative to the node */ + uint32_t unitPos : 5; /** Unit position relative to the parent chip */ uint32_t regs : 9; /** Number of normal registers */ uint32_t idRegs : 4; /** Number of indirect-SCOM registers */ - uint32_t scomErrs : 9; /** Number of SCOM errors detected */ + uint32_t scomErrs : 8; /** Number of SCOM errors detected */ + + uint8_t trgtType : 6; /** Target type. See enum TrgtType_t */ + uint8_t reserved : 2; } PNOR_Trgt_t; -/** @param i_type Target type. See enum TrgtType_t. - * @param i_procPos The processor position. - * @param i_procUnitPos Unit position relative to the processor. +/** @param i_trgtType Target type. See enum TrgtType_t. + * @param i_chipPos Parent chip position relative to the node. + * @param i_unitPos Unit position relative to the parent chip. * @return An initialized PNOR_Data_t struct. */ -static inline PNOR_Trgt_t PNOR_getTrgt( uint32_t i_type, uint32_t i_procPos, - uint32_t i_procUnitPos ) +static inline PNOR_Trgt_t PNOR_getTrgt( uint32_t i_trgtType, uint32_t i_chipPos, + uint32_t i_unitPos ) { - PNOR_Trgt_t t; - t.type = i_type; - t.procPos = i_procPos; - t.unitPos = i_procUnitPos; - t.regs = 0; - t.idRegs = 0; - t.scomErrs = 0; + PNOR_Trgt_t t; memset( &t, 0x00, sizeof(t) ); /* init to zero */ + + t.trgtType = i_trgtType; + t.chipPos = i_chipPos; + t.unitPos = i_unitPos; return t; }; diff --git a/src/usr/diag/prdf/occ_firdata/prdfReadPnorFirData.C b/src/usr/diag/prdf/occ_firdata/prdfReadPnorFirData.C index c57a9fbaf..92d9d8be6 100644 --- a/src/usr/diag/prdf/occ_firdata/prdfReadPnorFirData.C +++ b/src/usr/diag/prdf/occ_firdata/prdfReadPnorFirData.C @@ -86,13 +86,24 @@ TargetHandle_t getTargetHandle( PNOR_Trgt_t * i_pTrgt ) { // Get the target type. TYPE type = TYPE_LAST_IN_RANGE; - switch ( i_pTrgt->type ) + switch ( i_pTrgt->trgtType ) { - case PROC: type = TYPE_PROC; break; - case EX: type = TYPE_EX; break; - case MCS: type = TYPE_MCS; break; - case MEMB: type = TYPE_MEMBUF; break; - case MBA: type = TYPE_MBA; break; + // TODO RTC 173614: story for CUMULUS for mc mi dmi types + case TRGT_PROC: type = TYPE_PROC; break; + case TRGT_XBUS: type = TYPE_XBUS ; break; + case TRGT_OBUS: type = TYPE_OBUS ; break; + case TRGT_EC: type = TYPE_CORE ; break; + case TRGT_EQ: type = TYPE_EQ ; break; + case TRGT_EX: type = TYPE_EX; break; + case TRGT_MCBIST: type = TYPE_MCBIST; break; + case TRGT_MCS: type = TYPE_MCS; break; + case TRGT_MCA: type = TYPE_MCA ; break; + case TRGT_CAPP: type = TYPE_CAPP; break; + case TRGT_PEC: type = TYPE_PEC; break; + case TRGT_PHB: type = TYPE_PHB; break; + + case TRGT_MEMBUF: type = TYPE_MEMBUF; break; + case TRGT_MBA: type = TYPE_MBA; break; } if ( TYPE_LAST_IN_RANGE == type ) break; @@ -102,37 +113,50 @@ TargetHandle_t getTargetHandle( PNOR_Trgt_t * i_pTrgt ) for ( TargetHandleList::iterator i = procList.begin(); i != procList.end(); ++i ) { - if ( i_pTrgt->procPos == getTargetPosition(*i) ) + if ( i_pTrgt->chipPos == getTargetPosition(*i) ) { procTrgt = *i; break; } } + if ( NULL == procTrgt ) break; if ( TYPE_PROC == type ) { o_trgt = procTrgt; // nothing more to do. } - else if ( TYPE_EX == type || TYPE_MCS == type || TYPE_MEMBUF == type ) + else if ( TYPE_MEMBUF == type ) { - // Get the connected child - o_trgt = getConnectedChild( procTrgt, type, i_pTrgt->unitPos ); + // Get the Centaur target + TargetHandleList membList = getFunctionalTargetList( TYPE_MEMBUF ); + + for ( TargetHandleList::iterator l_mb = membList.begin(); + l_mb != membList.end(); ++l_mb ) + { + if ( i_pTrgt->chipPos == getTargetPosition(*l_mb) ) + { + o_trgt = *l_mb; + break; + } + } } else if ( TYPE_MBA == type ) { - uint32_t membPos = i_pTrgt->unitPos / MAX_MBA_PER_MEMBUF; - uint32_t mbaPos = i_pTrgt->unitPos % MAX_MBA_PER_MEMBUF; - // Get the connected MEMBUF TargetHandle_t membTrgt = getConnectedChild( procTrgt, TYPE_MEMBUF, - membPos ); + i_pTrgt->chipPos ); if ( NULL != membTrgt ) { // Get the connected MBA - o_trgt = getConnectedChild( membTrgt, type, mbaPos ); + o_trgt = getConnectedChild( membTrgt, type, i_pTrgt->unitPos ); } } + else + { + // Get the connected child + o_trgt = getConnectedChild( procTrgt, type, i_pTrgt->unitPos ); + } } while (0); @@ -195,7 +219,7 @@ errlHndl_t readPnorFirData( bool & o_validData, PnorTrgtMap & o_trgtMap, if ( full ) break; // Check the header for valid data. - if ( PNOR_FIR1 != data->header ) + if ( PNOR_FIR2 != data->header ) { break; // nothing to analyze } diff --git a/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C b/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C index f1caa2573..f7f9bcd80 100644 --- a/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C +++ b/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C @@ -45,460 +45,620 @@ using namespace PlatServices; // Register lists //------------------------------------------------------------------------------ + // TODO RTC 124849: Auto-generate this list from rule code. +// although HDCT plays a role +// currently have a mix from HDCT, P8->P9 manual conversion +// and some other chiplet attn regs -static uint32_t proc_glbl[] = -{ - 0x570F001C, // GLOBAL_CS_FIR - 0x570F001B, // GLOBAL_RE_FIR -}; -static uint32_t proc_common_fir[] = -{ - 0x01010800, // OCCFIR - 0x01010840, // PMCFIR - 0x01010c00, // PBAMFIR - 0x0104000a, // TP_LFIR - 0x02010840, // PBAFIR - 0x02010900, // PSIHBFIR - 0x02010940, // ENHCAFIR - 0x02010980, // EHHCAFIR - 0x020109c0, // ICPFIR - 0x02010c00, // PBWESTFIR - 0x02010c40, // PBCENTFIR - 0x02010c80, // PBEASTFIR - 0x02011A00, // IOMCFIR_0 - 0x02011E00, // IOMCFIR_1 - 0x02012000, // PCINESTFIR_0 - 0x02012400, // PCINESTFIR_1 - 0x02012800, // PCINESTFIR_2 - 0x02013000, // NXCXAFIR - 0x02013080, // NXCQFIR - 0x02013100, // NXDMAENGFIR - 0x02013400, // MCDFIR - 0x0204000a, // PB_LFIR - 0x04010c00, // PBENFIR - 0x04011000, // IOXFIR_0 - 0x04011400, // IOXFIR_1 - 0x04011800, // IOXFIR_3 - 0x04011C00, // IOXFIR_2 - 0x0404000a, // XBUS_LFIR - 0x09011400, // IOPCIFIR_0 - 0x09011840, // IOPCIFIR_1 - 0x0904000a, // PCIE_LFIR -}; - -static uint32_t proc_murano_venice_fir[] = -{ - 0x08010800, // PBESFIR - 0x08010c00, // IOAFIR - 0x0804000a, // ABUS_LFIR - 0x09010800, // PBFFIR -}; +// For creating chiplet exist bit masks +typedef std::map<TrgtPos_t, uint32_t> typeMaskMap_t; +typedef std::map<TARGETING::TYPE, typeMaskMap_t> typeMaxMap_t; -static uint32_t proc_naples_fir[] = -{ - 0x02012c00, // PCINESTFIR_3 - 0x02013180, // NXCXAFIR_1 - 0x0804000a, // NVLFIR - 0x08010c00, // IONVFIR_0 - 0x08010c40, // IONVFIR_1 - 0x08013d80, // NPUFIR - 0x09011c40, // IOPCIFIR_3 -}; - -static uint32_t proc_common_reg[] = -{ - // Global FIRs - 0x570F001A, // GLOBAL_SPA (for FFDC only) - //0x51040001, // GLOBALUNITXSTPFIR (not even accessible during IPL) - - // For ATTN - 0x01020013, // IPOLL reg - 0x02000001, // GP1 reg - - // Chiplet FIRs - 0x01040000, // TP_CHIPLET_CS_FIR - 0x01040001, // TP_CHIPLET_RE_FIR - 0x01040002, // TP_CHIPLET_FIR_MASK - 0x01040004, // TP_CHIPLET_SPA (for FFDC only) - 0x01040007, // TP_CHIPLET_SPA_MASK (for FFDC only) - 0x02040000, // PB_CHIPLET_CS_FIR - 0x02040001, // PB_CHIPLET_RE_FIR - 0x02040002, // PB_CHIPLET_FIR_MASK - 0x02040004, // PB_CHIPLET_SPA (for FFDC only) - 0x02040007, // PB_CHIPLET_SPA_MASK (for FFDC only) - 0x04040000, // XBUS_CHIPLET_CS_FIR - 0x04040001, // XBUS_CHIPLET_RE_FIR - 0x04040002, // XBUS_CHIPLET_FIR_MASK - 0x08040000, // ABUS_CHIPLET_CS_FIR - 0x08040001, // ABUS_CHIPLET_RE_FIR - 0x08040002, // ABUS_CHIPLET_FIR_MASK - 0x09040000, // PCIE_CHIPLET_CS_FIR - 0x09040001, // PCIE_CHIPLET_RE_FIR - 0x09040002, // PCIE_CHIPLET_FIR_MASK - 0x09040004, // PCIE_CHIPLET_SPA (for FFDC only) - 0x09040007, // PCIE_CHIPLET_SPA_MASK (for FFDC only) - - // FIRs for FFDC only - 0x02010c6e, // PBEXTFIR - 0x020130c0, // NXASFIR - 0x020130c3, // NXASFIR_MASK - 0x04012400, // PSIXBUSFIR - 0x09012000, // PCICLOCKFIR_0 - 0x09012400, // PCICLOCKFIR_1 - 0x09012800, // PCICLOCKFIR_2 - - // PLL registers - //0x00050019, // PCIE_OSC_SWITCH - disabled due to SW324506 - 0x01020019, // OSCERR - - // TOD registers - 0x00040000, // TOD_MPCR - 0x00040001, // TOD_PCRP0 - 0x00040002, // TOD_PCRP1 - 0x00040003, // TOD_SCRP0 - 0x00040004, // TOD_SCRP1 - 0x00040005, // TOD_SPCR - 0x00040006, // TOD_IPCR - 0x00040007, // TOD_PSMSCR - 0x00040008, // TOD_STATUSREGISTER - 0x00040009, // TOD_MPSR - 0x0004000A, // TOD_SPSR - 0x00040010, // TOD_CCR - 0x0004001D, // TOD_TRACEDATA_SET_1 - 0x0004001E, // TOD_TRACEDATA_SET_2 - 0x0004001F, // TOD_TRACEDATA_SET_3 - 0x00040024, // TOD_FSM - 0x00040027, // TOD_TX_TTYPE - 0x00040029, // TOD_RX_TTYPE - 0x00040030, // TOD_ERRORREGISTER - 0x00040032, // TOD_ERRORMASK - 0x00040033, // TOD_ERRORACTION - - // c_err_rpt and extra FFDC registers - 0x00062002, // PMC_PSTATE_MONITOR_AND_CTRL_REG - 0x00062008, // GLOBAL_ACTUAL_VOLTAGE_REG - 0x00062046, // PMC_SPIV_STATUS_REG - 0x00062056, // PMC_O2S_STATUS_REG - 0x00062058, // PMC_O2S_WDATA_REG - 0x00062059, // PMC_O2S_RDATA_REG - 0x0101080A, // OCCFIR_ERROR_REPORT - 0x0201084C, // PBAFIR_ERROR_REPORT_0 - 0x0201084D, // PBAFIR_ERROR_REPORT_1 - 0x0201084E, // PBAFIR_ERROR_REPORT_2 - 0x02010c6c, // PB_CENT_CR_ERROR - 0x0201201C, // PCINESTFIR0_ERROR_REPORT_0 - 0x0201201D, // PCINESTFIR0_ERROR_REPORT_1 - 0x0201201E, // PCINESTFIR0_ERROR_REPORT_2 - 0x0201241C, // PCINESTFIR1_ERROR_REPORT_0 - 0x0201241D, // PCINESTFIR1_ERROR_REPORT_1 - 0x0201241E, // PCINESTFIR1_ERROR_REPORT_2 - 0x0201281C, // PCINESTFIR2_ERROR_REPORT_0 - 0x0201281D, // PCINESTFIR2_ERROR_REPORT_1 - 0x0201281E, // PCINESTFIR2_ERROR_REPORT_2 - 0x0201300A, // NXCXAFIR_SNP_ERROR_REPORT - 0x0201300B, // NXCXAFIR_APC1_ERROR_REPORT - 0x0201300C, // NXCXAFIR_XPT_ERROR_REPORT - 0x0201300D, // NXCXAFIR_TLBI_ERROR_REPORT - 0x02013057, // NXDMAENG_ERROR_REPORT_0 - 0x02013058, // NXDMAENG_ERROR_REPORT_1 - 0x020130A2, // NXCQFIR_ERROR_REPORT_0 - 0x020130A3, // NXCQFIR_ERROR_REPORT_1 - 0x020130EB, // NXASFIR_IN_ERROR_HOLD_REPORT - 0x020130FF, // NXASFIR_ERROR_HOLD_REPORT - //0x0201314E, // NXASFIR_EG_ERROR_HOLD_REPORT (Murano DD1.0 only) - 0x0201314F, // NXASFIR_CE_HOLD_REPORT - 0x02013419, // MCDFIR_ERROR_REPORT - 0x020F001E, // PB_CONFIG_REG - 0x020F001F, // PB_ERROR_REG - 0x0901200A, // PCI_ETU_RESET_0 - 0x0901240A, // PCI_ETU_RESET_1 - 0x0901280A, // PCI_ETU_RESET_2 - 0x090F001E, // PCI_CONFIG_REG - 0x090F001F, // PCI_ERROR_REG -}; - -static uint32_t proc_murano_venice_reg[] = -{ - // c_err_rpt and extra FFDC registers - 0x0901083A, // PBFIR_IOF0_ERROR_REPORT - 0x0901083B, // PBFIR_IOF1_ERROR_REPORT - 0x080F001E, // ABUS_CONFIG_REG - 0x080F001F, // ABUS_ERROR_REG -}; - -static uint32_t proc_naples_reg[] = -{ - // FIRs for FFDC only - 0x09012c00, // PCICLOCKFIR_3 - - // c_err_rpt and extra FFDC registers - 0x02012c1C, // PCINESTFIR3_ERROR_REPORT_0 - 0x02012c1D, // PCINESTFIR3_ERROR_REPORT_1 - 0x02012c1E, // PCINESTFIR3_ERROR_REPORT_2 - 0x0201318A, // NXCXAFIR_SNP_ERROR_REPORT - 0x0201318B, // NXCXAFIR_APC1_ERROR_REPORT - 0x0201318C, // NXCXAFIR_XPT_ERROR_REPORT - 0x0201318D, // NXCXAFIR_TLBI_ERROR_REPORT - 0x09012C0A, // PCI_ETU_RESET_3 -}; - -static uint32_t ex_glbl[] = -{ - 0x10040000, // EX_CHIPLET_CS_FIR - 0x10040001, // EX_CHIPLET_RE_FIR -}; +// For Creating list of registers +typedef std::vector<uint64_t> AddrList_t; +typedef std::map<RegType_t, AddrList_t> RegMap_t; +typedef std::map<TrgtType_t, RegMap_t> TrgtMap_t; -static uint32_t ex_fir[] = -{ - 0x10010800, // L3FIR - 0x10010c00, // NCUFIR - 0x10012800, // L2FIR - 0x1004000a, // EX_LFIR -}; -static uint32_t ex_reg[] = -{ - // Chiplet FIRs - 0x10040002, // EX_CHIPLET_FIR_MASK - 0x10040004, // EX_CHIPLET_SPA (for FFDC only) - - // The COREFIR needs to be captured differently because recoverable errors - // are reported through the WOF, not the FIR. - 0x10013100, // COREFIR - 0x10013103, // COREFIR_MASK - 0x10013106, // COREFIR_ACT0 - 0x10013107, // COREFIR_ACT1 - 0x10013108, // COREFIR_WOF - - // FIRs for FFDC only - 0x10013007, // SPATTN_0 - 0x10013017, // SPATTN_1 - 0x10013027, // SPATTN_2 - 0x10013037, // SPATTN_3 - 0x10013047, // SPATTN_4 - 0x10013057, // SPATTN_5 - 0x10013067, // SPATTN_6 - 0x10013077, // SPATTN_7 - - // c_err_rpt and extra FFDC registers - 0x10010810, // L3FIR_RD0_ERROR_REPORT - 0x10010817, // L3FIR_RD1_ERROR_REPORT - 0x10010C0C, // NCUFIR_ERROR_REPORT - 0x10012815, // L2FIR_ERROR_REPORT_0 - 0x10012816, // L2FIR_ERROR_REPORT_1 - 0x1001300D, // PCNE_REG0_HOLD_OUT - 0x1001301D, // PCNE_REG1_HOLD_OUT - 0x1001302D, // PCNE_REG2_HOLD_OUT - 0x1001303D, // PCNE_REG3_HOLD_OUT - 0x1001304D, // PCNE_REG4_HOLD_OUT - 0x1001305D, // PCNE_REG5_HOLD_OUT - 0x1001306D, // PCNE_REG6_HOLD_OUT - 0x1001307D, // PCNE_REG7_HOLD_OUT - 0x1001329B, // COREHMEER - 0x100132A9, // PCNW_REG0_HOLD_OUT - 0x100132AA, // PCNW_REG1_HOLD_OUT - 0x100132CB, // PCS_REG0_HOLD_OUT - 0x100132D5, // PCS_REG1_HOLD_OUT - 0x10013300, // FXU_REG0_HOLD_OUT - 0x10013301, // FXU_REG1_HOLD_OUT - 0x10013302, // FXU_REG2_HOLD_OUT - 0x10013303, // FXU_REG3_HOLD_OUT - 0x10013304, // FXU_REG4_HOLD_OUT - 0x10013340, // ISU_REG0_ISU_HOLD_OUT - 0x10013341, // ISU_REG1_ISU_HOLD_OUT - 0x10013342, // ISU_REG2_ISU_HOLD_OUT - 0x10013343, // ISU_REG3_ISU_HOLD_OUT - 0x10013344, // ISU_REG4_ISU_HOLD_OUT - 0x10013345, // ISU_REG5_ISU_HOLD_OUT - 0x10013346, // ISU_REG6_ISU_HOLD_OUT - 0x10013347, // ISU_REG7_ISU_HOLD_OUT - 0x10013348, // ISU_REG8_ISU_HOLD_OUT_ERRPT - 0x10013349, // ISU_REG9_ISU_HOLD_OUT - 0x10013381, // IFU_REG0_HOLD_OUT - 0x10013382, // IFU_REG1_HOLD_OUT - 0x10013383, // IFU_REG2_HOLD_OUT - 0x10013384, // IFU_REG3_HOLD_OUT - 0x10013385, // IFU_REG4_HOLD_OUT - 0x100133C0, // LSU_REG0_HOLD_OUT - 0x100133C1, // LSU_REG1_HOLD_OUT - 0x100133C2, // LSU_REG2_HOLD_OUT - 0x100133C3, // LSU_REG3_HOLD_OUT - 0x100133C4, // LSU_REG4_HOLD_OUT - 0x100133C5, // LSU_REG5_HOLD_OUT - 0x100133C6, // LSU_REG6_HOLD_OUT - 0x100133C7, // LSU_REG7_HOLD_OUT - 0x100133C8, // LSU_REG8_HOLD_OUT - 0x100133C9, // LSU_REG9_HOLD_OUT - 0x100133CA, // LSU_REG10_HOLD_OUT - 0x100133CB, // LSU_REG11_HOLD_OUT - 0x100133CC, // LSU_REG12_HOLD_OUT - 0x100133CD, // LSU_REG13_HOLD_OUT - 0x100133CE, // LSU_REG14_HOLD_OUT - 0x100133CF, // LSU_REG15_HOLD_OUT - 0x100F001E, // EX_CONFIG_REG - 0x100F001F, // EX_ERROR_REG - 0x100F0151, // EX_FREQ_CTRL_REG - 0x100F0153, // EX_POWER_MGMT_STATUS_REG - 0x100F0159, // EX_POWER_MGMT_CTRL_REG - 0x100F0161, // EX_DPLL_STATUS_REG -}; - -static uint32_t mcs_fir[] = +/** + * @fn void initChipMasks( typeMaxMap_t & io_typeMap ) + * + * @brief Fills in the SCOM addresses we need for all targets + * and for all register types. + */ +void initChipMasks( typeMaxMap_t & io_typeMap, + const HOMER_ChipType_t i_procType ) { - 0x02011840, // MCIFIR -}; + // Creates and Inits the 'exist bit masks' we need + // for each chiplet type. The mask is a bit sensitive + // field with each '1' bit indicating that chiplet + // is present. + io_typeMap[TYPE_CAPP][TrgtPos_t::MAX_CAPP_PER_PROC] = 0; + io_typeMap[TYPE_XBUS][TrgtPos_t::MAX_XBUS_PER_PROC] = 0; + io_typeMap[TYPE_OBUS][TrgtPos_t::MAX_OBUS_PER_PROC] = 0; + io_typeMap[TYPE_PEC][TrgtPos_t::MAX_PEC_PER_PROC] = 0; + io_typeMap[TYPE_PHB][TrgtPos_t::MAX_PHB_PER_PROC] = 0; + io_typeMap[TYPE_EQ][TrgtPos_t::MAX_EQ_PER_PROC] = 0; + io_typeMap[TYPE_EX][TrgtPos_t::MAX_EX_PER_PROC] = 0; + io_typeMap[TYPE_CORE][TrgtPos_t::MAX_EC_PER_PROC] = 0; + + + // A few types differ based on processor type + if (HOMER_CHIP_CUMULUS == i_procType) + { + // TODO RTC 173614: for CUMULUS + // Add when these targeting types are available + // io_typeMap[TYPE_MC][TrgtPos_t::MAX_MC_PER_PROC] = 0; + // io_typeMap[TYPE_MI][TrgtPos_t::MAX_MI_PER_PROC] = 0; + // io_typeMap[TYPE_DMI][TrgtPos_t::MAX_DMI_PER_PROC] = 0; + } + else + { + // NIMBUS processor + io_typeMap[TYPE_MCBIST][TrgtPos_t::MAX_MCBIST_PER_PROC] = 0; + io_typeMap[TYPE_MCS][TrgtPos_t::MAX_MCS_PER_PROC] = 0; + io_typeMap[TYPE_MCA][TrgtPos_t::MAX_MCA_PER_PROC] = 0; + } // else NIMBUS -static uint32_t mcs_reg[] = -{ - // WOF register explicitly needed for analysis - 0x02011848, // MCIFIR_WOF - // c_err_rpt and extra FFDC registers - 0x0201181E, // MCERPT0 - 0x0201184E, // MCIERPT0 - 0x02011800, // MCFGP - 0x0201181C, // MCHWFM -}; + return; +} // end createChipMasks -static uint32_t memb_glbl[] = -{ - 0x570F001C, // GLOBAL_CS_FIR - 0x570F001B, // GLOBAL_RE_FIR -}; -static uint32_t memb_fir[] = -{ - 0x0104000a, // TP_LFIR - 0x02010400, // DMIFIR - 0x02010800, // MBIFIR - 0x02011400, // MBSFIR - 0x02011440, // MBA0_MBSECCFIR - 0x02011480, // MBA1_MBSECCFIR - 0x020115c0, // SCACFIR - 0x02011600, // MBA0_MCBISTFIR - 0x02011700, // MBA1_MCBISTFIR - 0x0204000a, // NEST_LFIR - 0x0304000a, // MEM_LFIR -}; - -static uint32_t memb_reg[] = +/** + * @fn void getAddresses( TrgtMap_t & io_targMap ) + * + * @brief Fills in the SCOM addresses we need for all targets + * and for all register types. + */ +void getAddresses( TrgtMap_t & io_targMap ) { - // Global FIRs - 0x570F001A, // GLOBAL_SPA (for FFDC only) - - // Chiplet FIRs - 0x01040000, // TP_CHIPLET_CS_FIR - 0x01040001, // TP_CHIPLET_RE_FIR - 0x01040002, // TP_CHIPLET_FIR_MASK - 0x02040000, // NEST_CHIPLET_CS_FIR - 0x02040001, // NEST_CHIPLET_RE_FIR - 0x02040002, // NEST_CHIPLET_FIR_MASK - 0x03040000, // MEM_CHIPLET_CS_FIR - 0x03040001, // MEM_CHIPLET_RE_FIR - 0x03040002, // MEM_CHIPLET_FIR_MASK - 0x03040004, // MEM_CHIPLET_SPA (for FFDC only) - 0x03040007, // MEM_CHIPLET_SPA_MASK (for FFDC only) - - // FIRs for FFDC only - 0x02010880, // NESTFBISTFIR - 0x0201141e, // MBSSECUREFIR - - // c_err_rpt and extra FFDC registers - 0x01030009, // TP_ERROR_STATUS - 0x0201080F, // MBIERPT - 0x0201140A, // MBSXCR - 0x0201140B, // MBA0_MBAXCR - 0x0201140C, // MBA1_MBAXCR - 0x02011413, // MBSCERR1 - 0x02011416, // MBCELOG - 0x0201142C, // MBSCERR2 - 0x02011466, // MBA0_MBSECCERRPT_0 - 0x02011467, // MBA0_MBSECCERRPT_1 - 0x020114A6, // MBA1_MBSECCERRPT_0 - 0x020114A7, // MBA1_MBSECCERRPT_1 - 0x020115D4, // SENSORCACHEERRPT - 0x0201168f, // MBA0_MBXERRSTAT - 0x0201178f, // MBA1_MBXERRSTAT - 0x02030009, // NEST_ERROR_STATUS - 0x03030009, // MEM_ERROR_STATUS - - // ECC address registers (will be used in analysis). - 0x0201165f, // MBA0_MBSEVR - 0x02011660, // MBA0_MBNCER - 0x02011661, // MBA0_MBRCER - 0x02011662, // MBA0_MBMPER - 0x02011663, // MBA0_MBUER - 0x0201175f, // MBA1_MBSEVR - 0x02011760, // MBA1_MBNCER - 0x02011761, // MBA1_MBRCER - 0x02011762, // MBA1_MBMPER - 0x02011763, // MBA1_MBUER - - // Other ECC registers (won't be used in analysis, but could be useful FFDC) - 0x02011653, // MBA0_MBSEC0 - 0x02011654, // MBA0_MBSEC1 - 0x02011655, // MBA0_MBSTR - 0x02011656, // MBA0_MBSSYMEC0 - 0x02011657, // MBA0_MBSSYMEC1 - 0x02011658, // MBA0_MBSSYMEC2 - 0x02011659, // MBA0_MBSSYMEC3 - 0x0201165a, // MBA0_MBSSYMEC4 - 0x0201165b, // MBA0_MBSSYMEC5 - 0x0201165c, // MBA0_MBSSYMEC6 - 0x0201165d, // MBA0_MBSSYMEC7 - 0x0201165e, // MBA0_MBSSYMEC8 - 0x02011753, // MBA1_MBSEC0 - 0x02011754, // MBA1_MBSEC1 - 0x02011755, // MBA1_MBSTR - 0x02011756, // MBA1_MBSSYMEC0 - 0x02011757, // MBA1_MBSSYMEC1 - 0x02011758, // MBA1_MBSSYMEC2 - 0x02011759, // MBA1_MBSSYMEC3 - 0x0201175a, // MBA1_MBSSYMEC4 - 0x0201175b, // MBA1_MBSSYMEC5 - 0x0201175c, // MBA1_MBSSYMEC6 - 0x0201175d, // MBA1_MBSSYMEC7 - 0x0201175e, // MBA1_MBSSYMEC8 -}; - -static uint32_t mba_fir[] = -{ - 0x03010600, // MBAFIR - 0x03010400, // MBACALFIR -}; -static uint32_t mba_reg[] = -{ - 0x0301041b, // MBASECUREFIR - 0x03010611, // MBASPA (for FFDC only) - 0x03010614, // MBASPA_MASK (for FFDC only) - - 0x0301041A, // MBA_ERR_REPORT - 0x030106E7, // MBA_MCBERRPTQ - - // Scrub registers (won't be used in analysis, but could be useful FFDC) - 0x0301060A, // MBMCT - 0x0301060C, // MBMSR - 0x0301060D, // MBMACA - 0x0301060E, // MBMEA - 0x0301060F, // MBASCTL - 0x03010610, // MBAECTL -}; - -static uint64_t mba_id_fir[] = -{ - 0x800200900301143Fll, // MBADDRPHYFIR -}; + io_targMap[TRGT_PROC][REG_GLBL] = + { + 0x500F001C, // GLOBAL_CS_FIR + 0x500F001B, // GLOBAL_RE_FIR + 0x50040018, // GLOBAL_UNIT_CS_FIR + 0x50040009, // GLOBAL_HOST_ATTN_FIR + }; + + io_targMap[TRGT_PHB][REG_FIR] = + { + 0x04010C40, // PCINESTFIR_0 = PHBNFIR + 0x0D010908, // ETU FIR register + 0x0D010840, // PCIFIR 0 + }; + + io_targMap[TRGT_PHB][REG_REG] = + { + 0x0D01084B, // PBAIB CERR Report Hold Reg + }; + + io_targMap[TRGT_CAPP][REG_FIR] = + { + 0x02010800, // NXCXAFIR (CAPP0) - 0x04010800 for CAPP1 + }; + + io_targMap[TRGT_CAPP][REG_REG] = + { + 0x0201080a, // Snoop Error Report Reg + 0x0201080b, // APC CERR Hold + 0x0201080c, // XPT Error Report + 0x0201080d, // TLBI Error Report + 0x0201080e, // Capp Error Status and Ctrl Reg + }; + + io_targMap[TRGT_XBUS][REG_GLBL] = + { + 0x06040000, // XBUS_CHIPLET_CS_FIR + 0x06040001, // XBUS_CHIPLET_RE_FIR + }; + + io_targMap[TRGT_XBUS][REG_FIR] = + { + 0x0604000a, // XBUS_LFIR + 0x06010840, // XBPPEFIR + 0x06010c00, // IOXBFIR + 0x06011800, // IOELFIR + }; + + io_targMap[TRGT_XBUS][REG_REG] = + { + 0x06011816, // PB ELL Link0 ErrStatus + 0x06011817, // PB ELL Link1 ErrStatus + }; + + io_targMap[TRGT_OBUS][REG_GLBL] = + { + 0x09040000, // OB_CHIPLET_CS_FIR + 0x09040001, // OB_CHIPLET_RE_FIR + }; + + io_targMap[TRGT_OBUS][REG_FIR] = + { + 0x0904000a, // OB LFIR + 0x09010800, // IOOLFIR + 0x09010C00, // IOOBFIR + 0x09011040, // OBPPEFIR + }; + + io_targMap[TRGT_OBUS][REG_REG] = + { + 0x09040002, // OB_CHIPLET_FIR_MASK + 0x09040018, // unitCS + 0x09040019, // unitCS mask + 0x09010816, // PB OLL Link0 ErrStatus + 0x09010817, // PB OLL Link1 ErrStatus + }; + + io_targMap[TRGT_PEC][REG_FIR] = + { + 0x0D010C00, // IOPCIFIR_0 + 0x0D04000a, // PCIE_LFIR + }; + + io_targMap[TRGT_PEC][REG_REG] = + { + 0x0D0F001E, // PCI_CONFIG_REG + 0x0D0F001F, // PCI_ERROR_REG + }; + + io_targMap[TRGT_MCS][REG_FIR] = + { + 0x05010800, // MCIFIR + }; + + io_targMap[TRGT_MCS][REG_REG] = + { + 0x0501081a, // MC Error Report 2 + 0x0501081e, // MC Error Report 0 + 0x0501081f, // MC Error Report 1 + + 0x0501080a, // Primary MemCfg Reg + 0x0501080b, // MCFGPA + 0x0501080c, // MCFGPM + 0x0501080d, // MCFGPMA + }; + + io_targMap[TRGT_MCBIST][REG_FIR] = + { + 0x07012300, // MCBISTFIR + }; + + io_targMap[TRGT_MCA][REG_FIR] = + { + 0x07010900, // MCACALFIR + 0x07010A00, // MCAECCFIR + 0x07011000, // DDRPHYFIR + }; + + io_targMap[TRGT_MCBIST][REG_REG] = + { + 0x07040000, // MC_CHIPLET_CS_FIR + 0x07040001, // MC_CHIPLET_RE_FIR + 0x07040002, // MC_CHIPLET_FIR_MASK + 0x07040018, // unitCS + 0x07040019, // unitCS mask + 0x07040009, // hostAttn + 0x0704001A, // hostAttn mask + + // AUE/IAUE analysis + 0x0701236D, // MCB0_MBUER + 0x0701236E, // MCB0_MBAUER + 0x07012372, // MCB1_MBUER + 0x07012373, // MCB1_MBAUER + 0x07012377, // MCB2_MBUER + 0x07012378, // MCB2_MBAUER + 0x0701237C, // MCB3_MBUER + 0x0701237D, // MCB3_MBAUER + 0x070123D7 // MCBMCAT + }; + + io_targMap[TRGT_EQ][REG_GLBL] = + { + 0x10040000, // CACHE_CHIPLET_CS_FIR + 0x10040001, // CACHE_CHIPLET_RE_FIR + }; + + io_targMap[TRGT_EQ][REG_REG] = + { + 0x10040002, // CACHE_CHIPLET_FIR_MASK + }; + + + io_targMap[TRGT_PROC][REG_FIR] = + { + 0x05011440, // NPU FIR1 + 0x01010800, // OCCFIR + 0x050129C0, // PBAMFIR + 0x0104000a, // TP_LFIR + + 0x05012840, // PBAFIR + 0x05012900, // PSIHBFIR + 0x05012940, // ENHCAFIR + + 0x05011800, // PBWESTFIR + 0x05011C00, // PBCENTFIR + 0x05012000, // PBEASTFIR + + 0x02011080, // NXCQFIR - PBI CQ FIR Register + 0x02011100, // NXDMAENGFIR + 0x03011000, // MCDFIR + 0x03011400, // MCDFIR + 0x03011800, // VASFIR - Nimbus addition + 0x0204000a, // PB_LFIR + 0x0304000a, // N1_LFIR - Nimbus addition + 0x0404000a, // N2_LFIR - Nimbus addition + 0x0504000a, // N3_LFIR - Nimbus addition + 0x05013400, // PBENFIR + + 0x05013800, // PBESFIR + 0x04011800, // PSI NEST FIR + 0x05012400, // PBPPEFIR + 0x05012C00, // NMMUCQFIR + 0x05012C40, // NMMUFIR + 0x05013030, // INTCQFIR + }; + + io_targMap[TRGT_PROC][REG_REG] = + { + // Global FIRs + 0x500F001A, // GLOBAL_SPA (for FFDC only) + 0x500F0040, // NET CTRL 0 - chiplet enable + //0x51040001, // GLOBALUNITXSTPFIR (not even accessible during IPL) + + // Chiplet FIRs + 0x01040000, // TP_CHIPLET_CS_FIR + 0x01040001, // TP_CHIPLET_RE_FIR + 0x01040002, // TP_CHIPLET_FIR_MASK + + 0x0101080a, // OCC Error Report Reg + + // Skipping SPEC attn regs for chiplets (xxx40004 xxx40007) + + 0x02040000, // N0_CHIPLET_CS_FIR + 0x02040001, // N0_CHIPLET_RE_FIR + 0x02040002, // N0_CHIPLET_FIR_MASK + + 0x03040000, // N1_CHIPLET_CS_FIR + 0x03040001, // N1_CHIPLET_RE_FIR + 0x03040002, // N1_CHIPLET_FIR_MASK + + 0x04040000, // N2_CHIPLET_CS_FIR + 0x04040001, // N2_CHIPLET_RE_FIR + 0x04040002, // N2_CHIPLET_FIR_MASK + + 0x05040000, // N3_CHIPLET_CS_FIR + 0x05040001, // N3_CHIPLET_RE_FIR + 0x05040002, // N3_CHIPLET_FIR_MASK + + 0x06040002, // XBUS_CHIPLET_FIR_MASK + + 0x0D040000, // PCIE_CHIPLET_CS_FIR + 0x0D040001, // PCIE_CHIPLET_RE_FIR + 0x0D040002, // PCIE_CHIPLET_FIR_MASK + 0x0E040000, // PCIE_CHIPLET_CS_FIR + 0x0E040001, // PCIE_CHIPLET_RE_FIR + 0x0E040002, // PCIE_CHIPLET_FIR_MASK + 0x0F040000, // PCIE_CHIPLET_CS_FIR + 0x0F040001, // PCIE_CHIPLET_RE_FIR + 0x0F040002, // PCIE_CHIPLET_FIR_MASK + + // FIRs for FFDC only + 0x05011C2E, // PBEXTFIR + 0x050129C0, // PBAMFIR + 0x050129C3, // PBAMFIR MASK + + // UnitCS and HostAttn Chiplet regs + 0x02040018, // unitCS + 0x02040019, // unitCS mask + 0x03040018, // unitCS + 0x03040019, // unitCS mask + 0x03040009, // hostAttn + 0x0304001A, // hostAttn mask + 0x04040018, // unitCS + 0x04040019, // unitCS mask + 0x05040018, // unitCs + 0x05040019, // unitCS mask + 0x05040009, // hostAttn + 0x0504001A, // hostAttn mask + 0x06040018, // unitCS + 0x06040019, // unitCS mask + + 0x020110a1, // PB Error Report + 0x020110a2, // PB Pty Error Report + 0x02011057, // DMA CERR 0 + 0x02011058, // DMA CERR 1 + 0x05011c2c, // PB Cent CR ERROR + 0x0501284c, // PBA Err Report0 + 0x0501284d, // PBA Err Report1 + 0x0501284e, // PBA Err Report2 + 0x05012C22, // PB Pty Error Report + + // TOD registers + 0x00040000, // TOD: master paths control reg + 0x00040001, // TOD: primary config p0 + 0x00040002, // TOD: primary config p1 + 0x00040003, // TOD: secondary config p0 + 0x00040004, // TOD: secondary config p1 + + 0x00040005, // TOD: Slave path ctrl reg + 0x00040006, // TOD: Internal path ctrl reg + + 0x00040007, // TOD: primary/secondary config ctrl + + 0x00040008, // TOD: PSS MSS Status Reg + 0x00040009, // TOD: Master Path Status Reg + + 0x0004000A, // TOD: slave path status + + 0x0004000E, // TOD: Master Path0 Step Steering + 0x0004000F, // TOD: Master Path1 Step Steering + + 0x0004000D, // TOD: timer register + 0x00040010, // TOD: chip control register + 0x00040011, // TOD: TX TTYPE-0 triggering register + + 0x0004001D, // TOD: Trace dataset 1 + 0x0004001E, // TOD: Trace dataset 2 + 0x0004001F, // TOD: Trace dataset 3 + + 0x01020019, // OSC Error Hold + 0x0102001A, // OSC Error Mask + 0x0102001B, // OSC Error Mode + + 0x00040024, // TOD:FSM Register + 0x00040027, // TOD: TX TType Ctrl reg + 0x00040029, // TOD: RX TType Ctrl reg + 0x00040030, // TOD: Error and Interrupts + 0x00040032, // TOD: C_Err_Rpt + 0x00040033, // TOD: Route Errors to Core/FIR + + // Other HDCT items + 0x00050001, // CBS Ctrl/Status reg + 0x00018000, // EFUSE part 0 + 0x00018001, // EFUSE part 1 + 0x00018002, // EFUSE part 2 + 0x00010008, // Mode reg to enable features + 0x00030008, // chiplet clk state + }; + + io_targMap[TRGT_EC][REG_GLBL] = + { + 0x20040000, // EC_CHIPLET_CS_FIR + 0x20040001, // EC_CHIPLET_RE_FIR + }; + + io_targMap[TRGT_EC][REG_FIR] = + { + 0x20010A40, // COREFIR + 0x2004000A, // EC_LFIR + }; + + io_targMap[TRGT_EC][REG_REG] = + { + 0x20040002, // EX_CHIPLET_FIR_MASK + 0x20010A48, // COREFIR_WOF + + 0x20010A96, // COREHMEER + 0x20010A99, // SPATTN + 0x20010A9A, // SPATTN MASK + + // CERR Holdout regs + 0x20010AB5, // SPR Core Error Report Hold Out Reg + 0x20010AB6, // PMU Error Report Hold Out Register + 0x20010AB7, // TFAC Error Report Hold Out Register + 0x20010AB8, // SPR Common Error Report Hold Out Register + + 0x20010C00, // IFU Error Report Hold Out 0 Register + 0x20010C01, // IFU Error Report Hold Out 1 Register + 0x20010C02, // IFU Error Report Hold Out 2 Register + 0x20010C03, // IFU Error Report Hold Out 3 Register + + 0x20010C40, // ISU error report hold_out register 0 + 0x20010C41, // ISU error report hold_out register 1 + 0x20010C42, // ISU error report hold_out register 2 + 0x20010C43, // ISU error report hold_out register 3 + 0x20010C44, // ISU error report hold_out register 4 + 0x20010C45, // ISU error report hold_out register 5 + + 0x20010C80, // LSU error report hold_out register 0 + 0x20010C81, // LSU error report hold_out register 1 + 0x20010C82, // LSU error report hold_out register 2 + 0x20010C83, // LSU error report hold_out register 3 + + 0x20010A51, // FIR/RECOV Error Report Hold Out Register + 0x20010A03, // Thread Control Error Report Hold Out Register + + 0x200F0110, //PPM STOP_STATE_HIST_SRC_REG + }; + + io_targMap[TRGT_EX][REG_FIR] = + { + 0x10011800, // L3FIR + 0x10011000, // NCUFIR + 0x10010800, // L2FIR + 0x10012000, // CMEFIR + }; + + io_targMap[TRGT_EX][REG_REG] = + { + 0x10010812, // ERROR REPORT REGISTER0 + 0x10010813, // ERROR REPORT REGISTER1 + 0x1001100E, // NCU error rpt register + + 0x1001180E, // L3 PRD Purge Register + 0x10011810, // L3 Error Report Reg 0 + 0x10011817, // L3 Error Report Reg 1 + 0x10011819, // L3 eDRAM RD Err Stat Reg0 + 0x1001181A, // L3 eDRAM RD Err Stat Reg1 + 0x1001181B, // L3 Edram Bank Fail + }; + + + // These are all Centaur addresses below + // (Should match P8 except for global broadcast FIRs) + io_targMap[TRGT_MEMBUF][REG_GLBL] = + { + 0x500F001C, // GLOBAL_CS_FIR + 0x500F001B, // GLOBAL_RE_FIR + }; + + io_targMap[TRGT_MEMBUF][REG_FIR] = + { + 0x0104000a, // TP_LFIR + 0x02010400, // DMIFIR + 0x02010800, // MBIFIR + 0x02011400, // MBSFIR + 0x02011440, // MBA0_MBSECCFIR + 0x02011480, // MBA1_MBSECCFIR + 0x020115c0, // SCACFIR + 0x02011600, // MBA0_MCBISTFIR + 0x02011700, // MBA1_MCBISTFIR + 0x0204000a, // NEST_LFIR + 0x0304000a, // MEM_LFIR + }; + + io_targMap[TRGT_MEMBUF][REG_REG] = + { + // Global FIRs + 0x500F001A, // GLOBAL_SPA (for FFDC only) + + // Chiplet FIRs + 0x01040000, // TP_CHIPLET_CS_FIR + 0x01040001, // TP_CHIPLET_RE_FIR + 0x01040002, // TP_CHIPLET_FIR_MASK + 0x02040000, // NEST_CHIPLET_CS_FIR + 0x02040001, // NEST_CHIPLET_RE_FIR + 0x02040002, // NEST_CHIPLET_FIR_MASK + + 0x03040000, // MEM_CHIPLET_CS_FIR + 0x03040001, // MEM_CHIPLET_RE_FIR + 0x03040002, // MEM_CHIPLET_FIR_MASK + 0x03040004, // MEM_CHIPLET_SPA (for FFDC only) + 0x03040007, // MEM_CHIPLET_SPA_MASK (for FFDC only) + + // FIRs for FFDC only + 0x02010880, // NESTFBISTFIR + 0x0201141e, // MBSSECUREFIR + + // c_err_rpt and extra FFDC registers + 0x01030009, // TP_ERROR_STATUS + 0x0201080F, // MBIERPT + 0x0201140A, // MBSXCR + 0x0201140B, // MBA0_MBAXCR + 0x0201140C, // MBA1_MBAXCR + 0x02011413, // MBSCERR1 + 0x02011416, // MBCELOG + 0x0201142C, // MBSCERR2 + 0x02011466, // MBA0_MBSECCERRPT_0 + 0x02011467, // MBA0_MBSECCERRPT_1 + 0x020114A6, // MBA1_MBSECCERRPT_0 + 0x020114A7, // MBA1_MBSECCERRPT_1 + 0x020115D4, // SENSORCACHEERRPT + 0x0201168f, // MBA0_MBXERRSTAT + 0x0201178f, // MBA1_MBXERRSTAT + 0x02030009, // NEST_ERROR_STATUS + 0x03030009, // MEM_ERROR_STATUS + 0x020115D4, // SensorCache ERR report + + // ECC address registers (will be used in analysis). + 0x0201165f, // MBA0_MBSEVR + 0x02011660, // MBA0_MBNCER + 0x02011661, // MBA0_MBRCER + 0x02011662, // MBA0_MBMPER + 0x02011663, // MBA0_MBUER + 0x0201175f, // MBA1_MBSEVR + 0x02011760, // MBA1_MBNCER + 0x02011761, // MBA1_MBRCER + 0x02011762, // MBA1_MBMPER + 0x02011763, // MBA1_MBUER + + // Other ECC regs (won't be used in analysis, but could be useful FFDC) + 0x02011653, // MBA0_MBSEC0 + 0x02011654, // MBA0_MBSEC1 + 0x02011655, // MBA0_MBSTR + 0x02011656, // MBA0_MBSSYMEC0 + 0x02011657, // MBA0_MBSSYMEC1 + 0x02011658, // MBA0_MBSSYMEC2 + 0x02011659, // MBA0_MBSSYMEC3 + 0x0201165a, // MBA0_MBSSYMEC4 + 0x0201165b, // MBA0_MBSSYMEC5 + 0x0201165c, // MBA0_MBSSYMEC6 + 0x0201165d, // MBA0_MBSSYMEC7 + 0x0201165e, // MBA0_MBSSYMEC8 + 0x02011753, // MBA1_MBSEC0 + 0x02011754, // MBA1_MBSEC1 + 0x02011755, // MBA1_MBSTR + 0x02011756, // MBA1_MBSSYMEC0 + 0x02011757, // MBA1_MBSSYMEC1 + 0x02011758, // MBA1_MBSSYMEC2 + 0x02011759, // MBA1_MBSSYMEC3 + 0x0201175a, // MBA1_MBSSYMEC4 + 0x0201175b, // MBA1_MBSSYMEC5 + 0x0201175c, // MBA1_MBSSYMEC6 + 0x0201175d, // MBA1_MBSSYMEC7 + 0x0201175e, // MBA1_MBSSYMEC8 + + // Others from HDCT + 0x00010000, // EFUSE part0 + 0x00010001, // EFUSE part1 + 0x000F001A, // Int reg + }; + + io_targMap[TRGT_MBA][REG_FIR] = + { + 0x03010600, // MBAFIR + 0x03010400, // MBACALFIR + }; + + io_targMap[TRGT_MBA][REG_REG] = + { + 0x0301041B, // MBASECUREFIR + 0x03010611, // MBASPA (for FFDC only) + 0x03010614, // MBASPA_MASK (for FFDC only) + + 0x0301041A, // MBA_ERR_REPORT + 0x030106E7, // MBA_MCBERRPTQ + + // Scrub registers (won't be used in analysis, but could be useful FFDC) + 0x0301060A, // MBMCT + 0x0301060C, // MBMSR + 0x0301060D, // MBMACA + 0x0301060E, // MBMEA + 0x0301060F, // MBASCTL + 0x03010610, // MBAECTL + }; + + io_targMap[TRGT_MBA][REG_IDFIR] = + { + 0x800200900301143Fll, // MBADDRPHYFIR + }; + + io_targMap[TRGT_MBA][REG_IDREG] = + { + 0x8000D0060301143Fll, // DDRPHY_APB_FIR_ERR0_P0 + 0x8000D0070301143Fll, // DDRPHY_APB_FIR_ERR1_P0 + 0x8001D0060301143Fll, // DDRPHY_APB_FIR_ERR0_P1 + 0x8001D0070301143Fll, // DDRPHY_APB_FIR_ERR1_P1 + }; + + // EC level handling will be done with + // different target types. + io_targMap[TRGT_PROC_NIMBUS_10][REG_FIR] = + { + 0x05011400, // NPU FIR0 (differs on DD level) + }; + + io_targMap[TRGT_PROC_NIMBUS_20][REG_FIR] = + { + 0x05013C00, // NPU FIR0 (differs on DD level) + }; + +} // end getAddresses -static uint64_t mba_id_reg[] = -{ - 0x8000D0060301143Fll, // DDRPHY_APB_FIR_ERR0_P0 - 0x8000D0070301143Fll, // DDRPHY_APB_FIR_ERR1_P0 - 0x8001D0060301143Fll, // DDRPHY_APB_FIR_ERR0_P1 - 0x8001D0070301143Fll, // DDRPHY_APB_FIR_ERR1_P1 -}; //------------------------------------------------------------------------------ @@ -545,8 +705,8 @@ errlHndl_t getPnorInfo( HOMER_Data_t & o_data ) } //------------------------------------------------------------------------------ - -errlHndl_t getHwConfig( HOMER_Data_t & o_data, const HwInitialized_t i_curHw ) +errlHndl_t getHwConfig( std::vector<HOMER_ChipInfo_t> &io_chipInfVector, + const HwInitialized_t i_curHw ) { #define FUNC "[PRDF::getHwConfig] " @@ -559,153 +719,245 @@ errlHndl_t getHwConfig( HOMER_Data_t & o_data, const HwInitialized_t i_curHw ) //---------------------------------------------------------------------- // Get the master PROC position. - TargetHandle_t masterProc = getMasterProc(); - if ( NULL == masterProc ) - { - PRDF_ERR( FUNC "master PROC is NULL" ); + TARGETING::TargetHandle_t masterProc = getMasterProc(); + PRDF_ASSERT( NULL != masterProc ); - /*@ - * @errortype - * @reasoncode PRDF_NULL_VALUE_RETURNED - * @severity ERRL_SEV_UNRECOVERABLE - * @moduleid PRDF_CS_FIRDATA_WRITE - * @userdata1 0 - * @userdata2 0 - * @devdesc NULL system target. - */ - errl = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, - PRDF_CS_FIRDATA_WRITE, - PRDF_NULL_VALUE_RETURNED, 0, 0 ); - break; - } + // Should be able to build up at least one chip structure + FSI::FsiLinkInfo_t fsiInfo; + HOMER_ChipInfo_t l_chipItem; + HOMER_ChipType_t l_procModelType; + + l_procModelType = (MODEL_CUMULUS == getChipModel(masterProc)) ? + HOMER_CHIP_CUMULUS : HOMER_CHIP_NIMBUS; - o_data.masterProc = getTargetPosition( masterProc ); - // Iterate the list functional PROCs. + // Iterate the list of functional PROCs. TargetHandleList procList = getFunctionalTargetList( TYPE_PROC ); for ( TargetHandleList::iterator procIt = procList.begin(); procIt != procList.end(); ++procIt ) { + // Init chiplet masks + memset( &(l_chipItem.hChipN), 0x00, sizeof(l_chipItem.hChipN) ); + + // Determine which processor uint32_t procPos = getTargetPosition(*procIt); PRDF_ASSERT( procPos < MAX_PROC_PER_NODE ); - o_data.procMask |= 0x80 >> procPos; - // Get the PROC FSI address. - FSI::FsiLinkInfo_t fsiInfo; FSI::getFsiLinkInfo( *procIt, fsiInfo ); - o_data.procFsiBaseAddr[procPos] = fsiInfo.baseAddr; - // Iterate the connected EXs. - TargetHandleList exList = getConnected( *procIt, TYPE_EX ); - for ( TargetHandleList::iterator exIt = exList.begin(); - exIt != exList.end(); ++exIt ) - { - uint32_t exPos = getTargetPosition( *exIt ); - PRDF_ASSERT( exPos < MAX_EX_PER_PROC ); + // Fill in our HOMER chip info + l_chipItem.hChipType = HOMER_getChip(l_procModelType); + l_chipItem.hChipType.chipPos = procPos; + l_chipItem.hChipType.fsiBaseAddr = fsiInfo.baseAddr; + + // is this the MASTER processor ? + l_chipItem.hChipN.isMaster = (*procIt == masterProc) ? 1 : 0; + + std::map<TARGETING::TYPE, typeMaskMap_t>::const_iterator typePosIt; + std::map<TrgtPos_t, uint32_t>::const_iterator maskIt; + + typeMaxMap_t l_typeMaxMap; - o_data.exMasks[procPos] |= 0x8000 >> exPos; - } + // Init chiplet exist bit maps + initChipMasks(l_typeMaxMap, l_procModelType); + // Loop thru all chiplet types and fill in the + // exist bit maps. + for ( typePosIt=l_typeMaxMap.begin(); + (typePosIt != l_typeMaxMap.end()); + typePosIt++ ) + { + for ( maskIt=typePosIt->second.begin(); + (maskIt != typePosIt->second.end()); maskIt++ ) + { + TargetHandleList chipletList = getConnected(*procIt, + typePosIt->first); + + for ( TargetHandleList::iterator chipIt=chipletList.begin(); + chipIt != chipletList.end(); ++chipIt ) + { + uint32_t chipPos = getTargetPosition( *chipIt ); + PRDF_ASSERT( chipPos < maskIt->first ); + + // If right justified, it fits bit fields well + l_typeMaxMap[typePosIt->first][ maskIt->first] |= + 0x00000001 << (maskIt->first - chipPos - 1); + + } // end for on chiplet list + + } // end for loop on mask + + } // end for loop on type + + // Need to move the 32 bit chiplet mask into the HOMER defined masks + // (take all the processor ones to start) + l_chipItem.hChipN.xbusMask = + l_typeMaxMap[TYPE_XBUS][TrgtPos_t::MAX_XBUS_PER_PROC]; + l_chipItem.hChipN.obusMask = + l_typeMaxMap[TYPE_OBUS][TrgtPos_t::MAX_OBUS_PER_PROC]; + l_chipItem.hChipN.ecMask = + l_typeMaxMap[TYPE_CORE][TrgtPos_t::MAX_EC_PER_PROC]; + l_chipItem.hChipN.eqMask = + l_typeMaxMap[TYPE_EQ][TrgtPos_t::MAX_EQ_PER_PROC]; + l_chipItem.hChipN.exMask = + l_typeMaxMap[TYPE_EX][TrgtPos_t::MAX_EX_PER_PROC]; + + l_chipItem.hChipN.cappMask = + l_typeMaxMap[TYPE_CAPP][TrgtPos_t::MAX_CAPP_PER_PROC]; + l_chipItem.hChipN.pecMask = + l_typeMaxMap[TYPE_PEC][TrgtPos_t::MAX_PEC_PER_PROC]; + l_chipItem.hChipN.phbMask = + l_typeMaxMap[TYPE_PHB][TrgtPos_t::MAX_PHB_PER_PROC]; + + // Are we suppose to include memory ? if (ALL_PROC_MEM_MASTER_CORE == i_curHw || ALL_HARDWARE == i_curHw) { - // Iterate the connected MCSs. - TargetHandleList mcsList = getConnected( *procIt, TYPE_MCS ); - for ( TargetHandleList::iterator mcsIt = mcsList.begin(); - mcsIt != mcsList.end(); ++mcsIt ) + // We already have the MCBIST, MCS and MCA masks + // so just save them now into HOMER defined masks.. + + // Handle proc type + if (HOMER_CHIP_NIMBUS == l_procModelType) { - uint32_t mcsPos = getTargetPosition( *mcsIt ); - PRDF_ASSERT( mcsPos < MAX_MCS_PER_PROC ); + l_chipItem.hChipN.mcbistMask = + l_typeMaxMap[TYPE_MCBIST][TrgtPos_t::MAX_MCBIST_PER_PROC]; + l_chipItem.hChipN.mcsMask = + l_typeMaxMap[TYPE_MCS][TrgtPos_t::MAX_MCS_PER_PROC]; + l_chipItem.hChipN.mcaMask = + l_typeMaxMap[TYPE_MCA][TrgtPos_t::MAX_MCA_PER_PROC]; + } // end nimbus proc + else + { // Assuming CUMULUS here + // TODO RTC 173614: for CUMULUS + // Add when these targeting types are available + // l_chipItem.hChipC.mcMask = + // l_typeMaxMap[TYPE_MC][TrgtPos_t::MAX_MC_PER_PROC]; + // l_chipItem.hChipC.miMask = + // l_typeMaxMap[TYPE_MI][TrgtPos_t::MAX_MI_PER_PROC]; + // l_chipItem.hChipC.dmiMask = + // l_typeMaxMap[TYPE_DMI][TrgtPos_t::MAX_DMI_PER_PROC]; + } // end cumulus proc + + } // if all hw or memory included + + // save the PROC info we collected + io_chipInfVector.push_back(l_chipItem); + + } // for on processor chips + + + // Are we suppose to include memory -- then check Centaurs + if (ALL_PROC_MEM_MASTER_CORE == i_curHw || ALL_HARDWARE == i_curHw) + { + // Iterate the connected MEMBUFs. + TargetHandleList membList = getFunctionalTargetList( TYPE_MEMBUF ); + for ( TargetHandleList::iterator membIt = membList.begin(); + membIt != membList.end(); ++membIt ) + { + uint32_t membPos = getTargetPosition(*membIt); + PRDF_ASSERT( membPos < MAX_MEMBUF_PER_NODE ); + + // Get the MEMBUF FSI address. + getFsiLinkInfo( *membIt, fsiInfo ); + + // Fill in our HOMER chip info + l_chipItem.hChipType = HOMER_getChip(HOMER_CHIP_CENTAUR); + l_chipItem.hChipType.chipPos = membPos; + l_chipItem.hChipType.fsiBaseAddr = fsiInfo.baseAddr; + + // Init MBA chiplet masks + uint32_t l_mbaMask = 0; + memset( &(l_chipItem.hChipM), + 0x00, + sizeof(l_chipItem.hChipM) ); + + // Iterate the connected MBAs. + TargetHandleList mbaList = getConnected(*membIt, TYPE_MBA ); + for ( TargetHandleList::iterator mbaIt = mbaList.begin(); + mbaIt != mbaList.end(); ++mbaIt ) + { + uint32_t mbaPos = getTargetPosition(*mbaIt); + PRDF_ASSERT( mbaPos < MAX_MBA_PER_MEMBUF ); - o_data.mcsMasks[procPos] |= 0x80 >> mcsPos; + l_mbaMask |= 0x00000001 << (MAX_MBA_PER_MEMBUF - mbaPos -1); } - // Iterate the connected MEMBUFs. - TargetHandleList membList = getConnected(*procIt, TYPE_MEMBUF ); - for ( TargetHandleList::iterator membIt = membList.begin(); - membIt != membList.end(); ++membIt ) - { - uint32_t membPos = getMemChnl(*membIt); // relative to proc - PRDF_ASSERT( membPos < MAX_MEMB_PER_PROC ); + // save the MBA chiplets in HOMER format + l_chipItem.hChipM.mbaMask = l_mbaMask; - o_data.membMasks[procPos] |= 0x80 >> membPos; + // save the Centaur chip in our structure + io_chipInfVector.push_back(l_chipItem); - // Get the MEMBUF FSI address. - getFsiLinkInfo( *membIt, fsiInfo ); - o_data.membFsiBaseAddr[procPos][membPos] = fsiInfo.baseAddr; + } // for on MEMBUF - // Iterate the connected MBAs. - TargetHandleList mbaList = getConnected(*membIt, TYPE_MBA ); - for ( TargetHandleList::iterator mbaIt = mbaList.begin(); - mbaIt != mbaList.end(); ++mbaIt ) - { - uint32_t mbaPos = getTargetPosition(*mbaIt); - uint32_t shift = membPos * MAX_MBA_PER_MEMBUF + mbaPos; - PRDF_ASSERT( shift < MAX_MBA_PER_PROC ); + } // end if including memory -- centaur and mba - o_data.mbaMasks[procPos] |= 0x8000 >> shift; - } - } - } - } } while (0); return errl; #undef FUNC -} +} // end getHwConfig //------------------------------------------------------------------------------ errlHndl_t writeData( uint8_t * i_hBuf, size_t i_hBufSize, - const HwInitialized_t i_curHw, HOMER_Data_t & o_data ) + const HwInitialized_t i_curHw, + std::vector<HOMER_ChipInfo_t> &i_chipVector, + HOMER_Data_t &io_homerData ) { #define FUNC "[PRDF::writeData] " errlHndl_t errl = NULL; + TrgtMap_t l_targMap; do { - // Check Processor type - bool isNaples = false; - TargetHandleList list = getFunctionalTargetList( TYPE_PROC ); - if ((list.size() > 0) && (MODEL_NAPLES == getChipModel(list[0]))) - isNaples = true; - - // Get the ultimate buffer size. - size_t s[MAX_TRGTS][MAX_REGS]; - memset( s, 0x00, sizeof(s) ); - size_t sz_hBuf = 0; - size_t sz_data = sizeof(o_data); sz_hBuf += sz_data; - s[PROC][GLBL] = sizeof(proc_glbl); sz_hBuf += s[PROC][GLBL]; + // Grab size of all the registers being collected + size_t sz_data = sizeof(io_homerData); + sz_hBuf += sz_data; - s[PROC][FIR] = sizeof(proc_common_fir) + ( isNaples ? - sizeof(proc_naples_fir) : sizeof(proc_murano_venice_fir) ); - sz_hBuf += s[PROC][FIR]; - s[PROC][REG] = sizeof(proc_common_reg) + ( isNaples ? - sizeof(proc_naples_reg) : sizeof(proc_murano_venice_reg) ); - sz_hBuf += s[PROC][REG]; + // Add register counts to the data. + const size_t u32 = sizeof(uint32_t); + const size_t u64 = sizeof(uint64_t); + // initialize SCOM addresses for all targets & regs + getAddresses(l_targMap); - s[EX][GLBL] = sizeof(ex_glbl); sz_hBuf += s[EX][GLBL]; - s[EX][FIR] = sizeof(ex_fir); sz_hBuf += s[EX][FIR]; - s[EX][REG] = sizeof(ex_reg); sz_hBuf += s[EX][REG]; - if ((ALL_PROC_MEM_MASTER_CORE == i_curHw) || (ALL_HARDWARE == i_curHw)) + // loop thru targets + for ( auto & t : l_targMap ) { - s[MCS][FIR] = sizeof(mcs_fir); sz_hBuf += s[MCS][FIR]; - s[MCS][REG] = sizeof(mcs_reg); sz_hBuf += s[MCS][REG]; - s[MEMB][GLBL] = sizeof(memb_glbl); sz_hBuf += s[MEMB][GLBL]; - s[MEMB][FIR] = sizeof(memb_fir); sz_hBuf += s[MEMB][FIR]; - s[MEMB][REG] = sizeof(memb_reg); sz_hBuf += s[MEMB][REG]; - s[MBA][FIR] = sizeof(mba_fir); sz_hBuf += s[MBA][FIR]; - s[MBA][REG] = sizeof(mba_reg); sz_hBuf += s[MBA][REG]; - s[MBA][IDFIR] = sizeof(mba_id_fir); sz_hBuf += s[MBA][IDFIR]; - s[MBA][IDREG] = sizeof(mba_id_reg); sz_hBuf += s[MBA][IDREG]; - } + // loop thru register types + for ( auto & r : t.second ) + { + // TODO RTC 173614: + // For CUMULUS Add memory targets + + // Want all proc chiplets but only include + // memory when asked for + if ( (ALL_PROC_MEM_MASTER_CORE == i_curHw) || + (ALL_HARDWARE == i_curHw) || + ( (TRGT_MCBIST != t.first) && + (TRGT_MCS != t.first) && + (TRGT_MCA != t.first) && + (TRGT_MEMBUF != t.first) && + (TRGT_MBA != t.first) + ) + ) + { + // save the number of regs for target/regType + io_homerData.regCounts[t.first][r.first] = + r.second.size(); + } // end if need this target included + + } // end for on regTypes + + } // end for on Targets + // Verify data will fit in HOMER. if ( i_hBufSize < sz_hBuf ) @@ -731,71 +983,181 @@ errlHndl_t writeData( uint8_t * i_hBuf, size_t i_hBufSize, break; } - // Add register counts to the data. - const size_t u32 = sizeof(uint32_t); - const size_t u64 = sizeof(uint64_t); - - for ( uint32_t c = FIRST_TRGT; c < MAX_TRGTS; c++ ) - { - o_data.counts[c][GLBL] = s[c][GLBL] / u32; - o_data.counts[c][FIR] = s[c][FIR] / u32; - o_data.counts[c][REG] = s[c][REG] / u32; - o_data.counts[c][IDFIR] = s[c][IDFIR] / u64; - o_data.counts[c][IDREG] = s[c][IDREG] / u64; - } // Add everything to the buffer. uint32_t idx = 0; - uint32_t * notCommon = NULL; //Pointer to array of chip-specific regs - uint32_t notCommonSize = 0; //Size of chip model specific array - - memcpy( &i_hBuf[idx], &o_data, sz_data ); idx += sz_data; - memcpy( &i_hBuf[idx], proc_glbl, s[PROC][GLBL] ); idx += s[PROC][GLBL]; - memcpy( &i_hBuf[idx], proc_common_fir, sizeof(proc_common_fir) ); - idx += sizeof(proc_common_fir); - notCommon = isNaples ? proc_naples_fir : proc_murano_venice_fir; - notCommonSize = - isNaples ? sizeof(proc_naples_fir) : sizeof(proc_murano_venice_fir); - memcpy( &i_hBuf[idx], notCommon, notCommonSize ); idx += notCommonSize; - memcpy( &i_hBuf[idx], proc_common_reg, sizeof(proc_common_reg) ); - idx += sizeof(proc_common_reg); - notCommon = isNaples ? proc_naples_reg : proc_murano_venice_reg ; - notCommonSize = - isNaples ? sizeof(proc_naples_reg) : sizeof(proc_murano_venice_reg); - memcpy( &i_hBuf[idx], notCommon, notCommonSize ); idx += notCommonSize; - memcpy( &i_hBuf[idx], ex_glbl, s[EX][GLBL] ); idx += s[EX][GLBL]; - memcpy( &i_hBuf[idx], ex_fir, s[EX][FIR] ); idx += s[EX][FIR]; - memcpy( &i_hBuf[idx], ex_reg, s[EX][REG] ); idx += s[EX][REG]; - - if ((ALL_PROC_MEM_MASTER_CORE == i_curHw) || (ALL_HARDWARE == i_curHw)) + + // Fill in the header & number of chips + io_homerData.header = HOMER_FIR2; + io_homerData.chipCount = i_chipVector.size(); + // Fill the input buffer with chipcount, regcount, pnor info + memcpy( &i_hBuf[idx], &io_homerData, sz_data ); idx += sz_data; + + // We want a list of chips next + if (0 != io_homerData.chipCount) { - memcpy( &i_hBuf[idx], mcs_fir, s[MCS][FIR] ); - idx += s[MCS][FIR]; - memcpy( &i_hBuf[idx], mcs_reg, s[MCS][REG] ); - idx += s[MCS][REG]; - memcpy( &i_hBuf[idx], memb_glbl, s[MEMB][GLBL] ); - idx += s[MEMB][GLBL]; - memcpy( &i_hBuf[idx], memb_fir, s[MEMB][FIR] ); - idx += s[MEMB][FIR]; - memcpy( &i_hBuf[idx], memb_reg, s[MEMB][REG] ); - idx += s[MEMB][REG]; - memcpy( &i_hBuf[idx], mba_fir, s[MBA][FIR] ); - idx += s[MBA][FIR]; - memcpy( &i_hBuf[idx], mba_reg, s[MBA][REG] ); - idx += s[MBA][REG]; - memcpy( &i_hBuf[idx], mba_id_fir, s[MBA][IDFIR] ); - idx += s[MBA][IDFIR]; - memcpy( &i_hBuf[idx], mba_id_reg, s[MBA][IDREG] ); - idx += s[MBA][IDREG]; - } + // Roll thru the chips we have + std::vector<HOMER_ChipInfo_t>::iterator l_chipItr; + uint32_t l_chipTypeSize = sizeof(HOMER_Chip_t); - }while(0); + for ( l_chipItr = i_chipVector.begin(); + (l_chipItr < i_chipVector.end()); + l_chipItr++ ) + { + // place the CHIP information + memcpy( &i_hBuf[idx], &(l_chipItr->hChipType), + l_chipTypeSize ); idx += l_chipTypeSize; + + // place the configured chiplet information + if (HOMER_CHIP_CENTAUR != l_chipItr->hChipType.chipType) + { + // Cumulus and Nimbus are the same size area + memcpy( &i_hBuf[idx], &(l_chipItr->hChipN), + sizeof(HOMER_ChipNimbus_t) ); + + idx += sizeof(HOMER_ChipNimbus_t); + } // end if PROC (not-centaur) + else + { + // Centaur is smaller area than PROC chips + memcpy( &i_hBuf[idx], &(l_chipItr->hChipM), + sizeof(HOMER_ChipCentaur_t) ); + + idx += sizeof(HOMER_ChipCentaur_t); + } // end else CENTAUR chip + + } // end for loop on chip vector + + } // end if chipCount non-zero + + + // loop thru targets + for ( auto & t : l_targMap ) + { + // TODO RTC 173614: story for CUMULUS when we know the regs for sure + // TRGT_MC TRGT_MI TRGT_DMI -- probably NOOP now + if ( (ALL_PROC_MEM_MASTER_CORE == i_curHw) || + (ALL_HARDWARE == i_curHw) || + ( (TRGT_MCBIST != t.first) && + (TRGT_MCS != t.first) && + (TRGT_MCA != t.first) && + (TRGT_MEMBUF != t.first) && + (TRGT_MBA != t.first) + ) + ) + { + // loop thru register types + for ( auto & r : t.second ) + { + // loop thru SCOM addresses for reg type + for ( auto & rAddr : r.second ) + { + if ( (REG_IDFIR == r.first) || + (REG_IDREG == r.first) + ) + { + memcpy( &i_hBuf[idx], + &rAddr, + u64 ); + + idx += u64; + } + else + { + uint32_t tempAddr = (uint32_t)rAddr; + memcpy( &i_hBuf[idx], + &tempAddr, + u32 ); + + idx += u32; + } + + } // end for on register addresses + + } // end for on regs + + } // end if we need this target + + } // end for on targets + + } while(0); return errl; #undef FUNC } +#if 1 +// TODO RTC 173623: Remove when done with initial testing +// Traces the information built into the vector +void dumpInfoVector( std::vector<HOMER_ChipInfo_t> &i_chipVector ) +{ + PRDF_ERR("HOMER: Number of elements:%d", i_chipVector.size() ); + std::vector<HOMER_ChipInfo_t>::iterator l_chipItr; + + for ( l_chipItr = i_chipVector.begin(); + (l_chipItr < i_chipVector.end()); + l_chipItr++ ) + { + PRDF_ERR("HOMER: ChipPosition:%d", l_chipItr->hChipType.chipPos); + PRDF_ERR("HOMER: FSI Addr:%X", l_chipItr->hChipType.fsiBaseAddr); + + switch (l_chipItr->hChipType.chipType) + { + case HOMER_CHIP_NIMBUS: + PRDF_ERR("HOMER: NIMBUS chip"); + + PRDF_ERR(" isMaster:%X", l_chipItr->hChipN.isMaster ); + PRDF_ERR(" xbusMask:%X", l_chipItr->hChipN.xbusMask ); + PRDF_ERR(" obusMask:%X", l_chipItr->hChipN.obusMask ); + PRDF_ERR(" ecMask:%X", l_chipItr->hChipN.ecMask ); + PRDF_ERR(" eqMask:%X", l_chipItr->hChipN.eqMask ); + PRDF_ERR(" exMask:%X", l_chipItr->hChipN.exMask ); + PRDF_ERR(" mcbistMask:%X", l_chipItr->hChipN.mcbistMask ); + PRDF_ERR(" mcsMask:%X", l_chipItr->hChipN.mcsMask ); + PRDF_ERR(" mcaMask:%X", l_chipItr->hChipN.mcaMask ); + PRDF_ERR(" cappMask:%X", l_chipItr->hChipN.cappMask ); + PRDF_ERR(" pecMask:%X", l_chipItr->hChipN.pecMask ); + PRDF_ERR(" phbMask:%X", l_chipItr->hChipN.phbMask ); + break; + + case HOMER_CHIP_CUMULUS: + PRDF_ERR("HOMER: CUMULUS chip"); + + PRDF_ERR(" isMaster:%X", l_chipItr->hChipC.isMaster ); + PRDF_ERR(" xbusMask:%X", l_chipItr->hChipC.xbusMask ); + PRDF_ERR(" obusMask:%X", l_chipItr->hChipC.obusMask ); + PRDF_ERR(" ecMask:%X", l_chipItr->hChipC.ecMask ); + PRDF_ERR(" eqMask:%X", l_chipItr->hChipC.eqMask ); + PRDF_ERR(" exMask:%X", l_chipItr->hChipC.exMask ); + PRDF_ERR(" mcMask:%X", l_chipItr->hChipC.mcMask ); + PRDF_ERR(" miMask:%X", l_chipItr->hChipC.miMask ); + PRDF_ERR(" dmiMask:%X", l_chipItr->hChipC.dmiMask ); + PRDF_ERR(" cappMask:%X", l_chipItr->hChipC.cappMask ); + PRDF_ERR(" pecMask:%X", l_chipItr->hChipC.pecMask ); + PRDF_ERR(" phbMask:%X", l_chipItr->hChipC.phbMask ); + break; + + case HOMER_CHIP_CENTAUR: + PRDF_ERR("HOMER: CENTAUR chip"); + + PRDF_ERR(" mbaMask:%X", l_chipItr->hChipM.mbaMask ); + break; + + default: + PRDF_ERR("HOMER: Unknown Chip:%d", + l_chipItr->hChipType.chipType ); + break; + + } // end switch + + } // end for printing out things + +} // end dumpInfoVector +#endif // 1 for temporary debug + + + //------------------------------------------------------------------------------ errlHndl_t writeHomerFirData( uint8_t * i_hBuf, size_t i_hBufSize, @@ -807,22 +1169,32 @@ errlHndl_t writeHomerFirData( uint8_t * i_hBuf, size_t i_hBufSize, do { - HOMER_Data_t data = HOMER_getData(); // Initializes data + HOMER_Data_t l_homerData = HOMER_getData(); // Initializes data // Set flag indicating if IPL or runtime situation. - data.iplState = (ALL_HARDWARE == i_curHw) + l_homerData.iplState = (ALL_HARDWARE == i_curHw) ? FIRDATA_STATE_RUNTIME : FIRDATA_STATE_IPL; // Get the PNOR information - errl = getPnorInfo( data ); + errl = getPnorInfo( l_homerData ); if ( NULL != errl ) { PRDF_ERR( FUNC "getPnorInfo() failed" ); break; } + // Hardware present gets pushed into this vector + // (one element per chip) + std::vector<HOMER_ChipInfo_t> l_chipInfVector; + // Get the hardware configuration - errl = getHwConfig( data, i_curHw ); + errl = getHwConfig( l_chipInfVector, i_curHw ); + +#if 1 + // TODO RTC 173623: Remove when done with initial testing + dumpInfoVector(l_chipInfVector); +#endif + if ( NULL != errl ) { PRDF_ERR( FUNC "getHwConfig() failed" ); @@ -830,7 +1202,9 @@ errlHndl_t writeHomerFirData( uint8_t * i_hBuf, size_t i_hBufSize, } // Write the HOMER data - errl = writeData( i_hBuf, i_hBufSize, i_curHw, data ); + errl = writeData( i_hBuf, i_hBufSize, i_curHw, + l_chipInfVector, l_homerData ); + if ( NULL != errl ) { PRDF_ERR( FUNC "writeData() failed" ); @@ -851,4 +1225,3 @@ errlHndl_t writeHomerFirData( uint8_t * i_hBuf, size_t i_hBufSize, } }; // end namespace PRDF - diff --git a/src/usr/diag/prdf/test/prdfTest_WriteHomerFir.H b/src/usr/diag/prdf/test/prdfTest_WriteHomerFir.H index 0e92a38e3..bbd642bcb 100644 --- a/src/usr/diag/prdf/test/prdfTest_WriteHomerFir.H +++ b/src/usr/diag/prdf/test/prdfTest_WriteHomerFir.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -53,9 +53,13 @@ namespace PRDF { // these functions from prdfWriteHomerFirData.C are needed for the // fakeWriteHomerFirData() function -errlHndl_t getHwConfig( HOMER_Data_t & o_data, const HwInitialized_t i_curHw ); +errlHndl_t getHwConfig( std::vector<HOMER_ChipInfo_t> &io_chipInfVector, + const HwInitialized_t i_curHw ); + errlHndl_t writeData( uint8_t * i_hBuf, size_t i_hBufSize, - const HwInitialized_t i_curHw, HOMER_Data_t & o_data ); + const HwInitialized_t i_curHw, + std::vector<HOMER_ChipInfo_t> &i_chipVector, + HOMER_Data_t &io_homerData ); }; class WriteHomerFir: public CxxTest::TestSuite @@ -90,7 +94,8 @@ private: fakeGetPnorInfo( data ); // Get the hardware configuration - errl = getHwConfig( data, i_curHw ); + std::vector<HOMER_ChipInfo_t> l_chipInfVector; + errl = getHwConfig( l_chipInfVector, i_curHw ); if ( NULL != errl ) { TS_FAIL("getHwConfig() failed"); @@ -98,7 +103,9 @@ private: } // Write the HOMER data - errl = writeData( i_hBuf, i_hBufSize, i_curHw, data ); + errl = writeData( i_hBuf, i_hBufSize, i_curHw, + l_chipInfVector, data ); + if ( NULL != errl ) { TS_FAIL("writeData() failed"); @@ -118,41 +125,108 @@ private: //------------------------------------------------------------------------------ // check if data exists in HOMER when it should not - void checkHomerData(HOMER_Data_t d, const PRDF::HwInitialized_t i_curHw) + void checkHomerData(HOMER_Data_t *d, const PRDF::HwInitialized_t i_curHw) { using namespace PRDF; if (MASTER_PROC_CORE == i_curHw || ALL_PROC_MASTER_CORE == i_curHw) { - // check if mcs, membuf, or mba data is available - for (uint32_t i = 0; i < PRDF::MAX_PROC_PER_NODE; i++) + // Should have at least one processor chip + if (0 == d->chipCount) { - // mcs - if (d.mcsMasks[i] != 0) - { - TS_FAIL("ERROR: MCS should not be available. " - "(MCS: 0x%02x)", d.mcsMasks[i]); - break; - } - - // membuf - if (d.membMasks[i] != 0) - { - TS_FAIL("ERROR: MEMBUF should not be available. " - "(MEMBUF: 0x%02x)", d.membMasks[i]); - break; - } + TS_FAIL("ERROR: ChipCount is zero in HOMER data"); + } // end if no chips + else + { + uint8_t *l_bytePtr = (reinterpret_cast<uint8_t *>(d)) + + sizeof(HOMER_Data_t); + HOMER_Chip_t *l_chipPtr = NULL; - // mba - if (d.mbaMasks[i] != 0) + // Have a chip or more to look thru + for ( uint32_t l_chipNum=0; + (l_chipNum < d->chipCount); l_chipNum++ ) { - TS_FAIL("ERROR: MBA should not be available. " - "(MBA: 0x%02x)", d.mbaMasks[i]); - break; - } - } - } - } + l_chipPtr = reinterpret_cast<HOMER_Chip_t *>(l_bytePtr); + l_bytePtr += sizeof(HOMER_Chip_t); + + /* 'Existing chiplet area' can vary in size */ + if (HOMER_CHIP_NIMBUS == l_chipPtr->chipType) + { + HOMER_ChipNimbus_t *l_nimPtr = + reinterpret_cast<HOMER_ChipNimbus_t *>(l_bytePtr); + + // MCBIST + if (l_nimPtr->mcbistMask != 0) + { + TS_FAIL("ERROR: MCBIST should not be available. " + "(MCBIST: 0x%x)", l_nimPtr->mcbistMask); + break; + } + + // MCS + if (l_nimPtr->mcsMask != 0) + { + TS_FAIL("ERROR: MCS should not be available. " + "(MCS: 0x%x)", l_nimPtr->mcsMask); + break; + } + + // MCA + if (l_nimPtr->mcaMask != 0) + { + TS_FAIL("ERROR: MCA should not be available. " + "(MCA: 0x%x)", l_nimPtr->mcaMask); + break; + } + + // prepare for next chip (if any) + l_bytePtr += sizeof(HOMER_ChipNimbus_t); + } + else if (HOMER_CHIP_CUMULUS == l_chipPtr->chipType) + { + HOMER_ChipCumulus_t *l_cumPtr = + reinterpret_cast<HOMER_ChipCumulus_t *>(l_bytePtr); + + // MC + if (l_cumPtr->mcMask != 0) + { + TS_FAIL("ERROR: MC should not be available. " + "(MC: 0x%x)", l_cumPtr->mcMask); + break; + } + + // MCS + if (l_cumPtr->miMask != 0) + { + TS_FAIL("ERROR: MI should not be available. " + "(MI: 0x%x)", l_cumPtr->miMask); + break; + } + + // MCA + if (l_cumPtr->dmiMask != 0) + { + TS_FAIL("ERROR: DMI should not be available. " + "(DMI: 0x%x)", l_cumPtr->dmiMask); + break; + } + + // prepare for next chip (if any) + l_bytePtr += sizeof(HOMER_ChipCumulus_t); + } + else if (HOMER_CHIP_CENTAUR == l_chipPtr->chipType) + { + TS_FAIL("ERROR: MEMBUF should not be available "); + break; + } + + } // end for loop thru chips + + } // end else we have a chip or 2 + + } // end if proc related + + } // end function checkHomerData //------------------------------------------------------------------------------ @@ -183,7 +257,7 @@ public: } HOMER_Data_t * d = reinterpret_cast<HOMER_Data_t *>(hBuf); - checkHomerData(*d, MASTER_PROC_CORE); + checkHomerData(d, MASTER_PROC_CORE); TS_TRACE("- Write Homer Test 1 - Master Proc Core - End-"); } @@ -205,7 +279,7 @@ public: } HOMER_Data_t * d = reinterpret_cast<HOMER_Data_t *>(hBuf); - checkHomerData(*d, ALL_PROC_MASTER_CORE); + checkHomerData(d, ALL_PROC_MASTER_CORE); TS_TRACE("- Write Homer Test 2 - All Proc Master Core - End-"); @@ -228,7 +302,7 @@ public: } HOMER_Data_t * d = reinterpret_cast<HOMER_Data_t *>(hBuf); - checkHomerData(*d, ALL_PROC_MEM_MASTER_CORE); + checkHomerData(d, ALL_PROC_MEM_MASTER_CORE); TS_TRACE("- Write Homer Test 3 - All Proc Mem Master Core - End-"); @@ -251,7 +325,7 @@ public: } HOMER_Data_t * d = reinterpret_cast<HOMER_Data_t *>(hBuf); - checkHomerData(*d, ALL_HARDWARE); + checkHomerData(d, ALL_HARDWARE); TS_TRACE("- Write Homer Test 4 - All Hardware - End-"); |