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authorBenjamin Weisenbeck <bweisenb@us.ibm.com>2018-08-29 14:47:59 -0500
committerZane C. Shelley <zshelle@us.ibm.com>2018-08-31 21:03:56 -0500
commit6c30bcf8975825c394a6eb6f687535a9c52c74e8 (patch)
tree22e0587b362abc43c47c333bce3d22456c8ae360 /src/usr/diag
parent501844c893e5bb4b094e8427879334093a6db54f (diff)
downloadtalos-hostboot-6c30bcf8975825c394a6eb6f687535a9c52c74e8.tar.gz
talos-hostboot-6c30bcf8975825c394a6eb6f687535a9c52c74e8.zip
PRD: Handle chips with different MF clock sources
Change-Id: I00cff187de8377efc67297934905695ff3ab84cb CQ: SW443788 Backport: release-fips921 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65504 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65572 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/usr/diag')
-rw-r--r--src/usr/diag/prdf/common/plat/p9/prdfP9PllDomain.C82
1 files changed, 79 insertions, 3 deletions
diff --git a/src/usr/diag/prdf/common/plat/p9/prdfP9PllDomain.C b/src/usr/diag/prdf/common/plat/p9/prdfP9PllDomain.C
index f85eafebb..f8cb6582b 100644
--- a/src/usr/diag/prdf/common/plat/p9/prdfP9PllDomain.C
+++ b/src/usr/diag/prdf/common/plat/p9/prdfP9PllDomain.C
@@ -123,6 +123,74 @@ bool PllDomain::Query(ATTENTION_TYPE attentionType)
//------------------------------------------------------------------------------
+void mfClockResolution( STEP_CODE_DATA_STRUCT &io_sc,
+ std::vector<ExtensibleChip *> i_chipList )
+{
+ for ( auto chip : i_chipList )
+ {
+ bool bothClocksFailed = false;
+ TargetHandle_t chipTgt = chip->GetChipHandle();
+
+ SCAN_COMM_REGISTER_CLASS *oscSw = chip->getRegister("OSC_SW_SENSE");
+ uint32_t l_rc = oscSw->Read();
+ if ( SUCCESS == l_rc )
+ {
+ const uint32_t OSC_0_OK = 28;
+ const uint32_t OSC_1_OK = 29;
+ if ( !(oscSw->IsBitSet(OSC_0_OK) || oscSw->IsBitSet(OSC_1_OK) ) )
+ {
+ bothClocksFailed = true;
+
+ // Callout both PCI Clocks
+ #ifndef __HOSTBOOT_MODULE
+ TargetHandle_t pciOsc =
+ getClockId( chipTgt, TYPE_OSCPCICLK, 0 );
+ if (pciOsc)
+ io_sc.service_data->SetCallout( pciOsc );
+
+ pciOsc = getClockId( chipTgt, TYPE_OSCPCICLK, 1 );
+ if (pciOsc)
+ io_sc.service_data->SetCallout( pciOsc );
+
+ #else
+ io_sc.service_data->SetCallout( PRDcallout(chipTgt,
+ PRDcalloutData::TYPE_PCICLK0));
+ io_sc.service_data->SetCallout( PRDcallout(chipTgt,
+ PRDcalloutData::TYPE_PCICLK1));
+ #endif
+ }
+ }
+ else
+ {
+ PRDF_ERR( "ClockResolution::Resolve "
+ "Read() failed on OSC_SW_SENSE huid 0x%08X", chipTgt );
+ }
+
+ if ( !bothClocksFailed )
+ {
+ TargetHandle_t l_ptargetClock =
+ PlatServices::getActiveRefClk(chipTgt, TYPE_OSCPCICLK);
+
+ // Callout this chip if nothing else.
+ if(NULL == l_ptargetClock)
+ {
+ l_ptargetClock = chipTgt;
+ }
+
+ // callout the clock source
+ // HB does not have the osc target modeled
+ // so we need to use the proc target with
+ // osc clock type to call out
+ #ifndef __HOSTBOOT_MODULE
+ io_sc.service_data->SetCallout(l_ptargetClock);
+ #else
+ io_sc.service_data->SetCallout( PRDcallout(l_ptargetClock,
+ PRDcalloutData::TYPE_PCICLK));
+ #endif
+ }
+ }
+}
+
int32_t PllDomain::Analyze(STEP_CODE_DATA_STRUCT & serviceData,
ATTENTION_TYPE attentionType)
{
@@ -227,10 +295,18 @@ int32_t PllDomain::Analyze(STEP_CODE_DATA_STRUCT & serviceData,
}
// always suspect the clock source
- closeClockSource.Resolve(serviceData);
- if(&closeClockSource != &farClockSource)
+ if (GetId() == CLOCK_DOMAIN_IO)
+ {
+ mfClockResolution(serviceData, failoverList);
+ mfClockResolution(serviceData, pllUnlockList);
+ }
+ else
{
- farClockSource.Resolve(serviceData);
+ closeClockSource.Resolve(serviceData);
+ if(&closeClockSource != &farClockSource)
+ {
+ farClockSource.Resolve(serviceData);
+ }
}
if (pllUnlockList.size() > 0)
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