summaryrefslogtreecommitdiffstats
path: root/src/usr/diag
diff options
context:
space:
mode:
authorPrem Shanker Jha <premjha2@in.ibm.com>2014-11-18 00:32:33 -0600
committerA. Patrick Williams III <iawillia@us.ibm.com>2015-01-16 16:01:15 -0600
commit10a7acedb2b79673f997f849e7b344a6c2c78771 (patch)
tree980f171921b310a61f9b08f79bd3aa5418d192b9 /src/usr/diag
parent97cf5a436ee27a3e66f66fa781953db8e8cbe943 (diff)
downloadtalos-hostboot-10a7acedb2b79673f997f849e7b344a6c2c78771.tar.gz
talos-hostboot-10a7acedb2b79673f997f849e7b344a6c2c78771.zip
PRD: Added documentation in code for L4CE handling.
Change-Id: If64e57d98f1652a907e7556ab89ffcfc4477c571 RTC: 112474 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/14544 Tested-by: Jenkins Server Reviewed-by: Christopher T. Phan <cphan@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Bilicon Patil <bilpatil@in.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com> Reviewed-by: Zane Shelley <zshelle@us.ibm.com> Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/15206
Diffstat (limited to 'src/usr/diag')
-rwxr-xr-xsrc/usr/diag/prdf/common/plat/pegasus/prdfCenMembuf.C18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMembuf.C b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMembuf.C
index 4283a48ce..b68d6a416 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMembuf.C
+++ b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMembuf.C
@@ -1209,6 +1209,24 @@ int32_t CaptureL4CacheErr( ExtensibleChip * i_mbChip,
// NOTE: FW should write on MBCELOG so that HW can capture
// address for next L4 CE error.
+ // NOTE: Line delete feature for L4 cache may not be available during
+ // P8. But if it is incorporated in P8, we need to make sure following
+ // should be the order of events:
+ // 1. Capture group of registers associated with group L4CacheErr
+ // 2. do L4 line delete.
+ // 3. clear register MBCELOG
+
+ // If we clear register MBCELOG before doing line delete, it is possible
+ // that hardware procedures shall run into erroneous scenarios. One
+ // probable order of events from PRDF's perspective which can cause
+ // this is below:
+ // 1. Receives an attention due to failure at cache address X.
+ // 2. captures all relevant register including MBCELOG.
+ // 3. cleares MBCELOG - i.e. failed address info is lost. HW populates
+ // this register with another L4 CE address say Y.
+ // 4. requestes HWP for line delete operation on address X but it
+ // actually deletes Y. It's because MBCELOG now contains address Y.
+
SCAN_COMM_REGISTER_CLASS * mbcelogReg =
i_mbChip->getRegister("MBCELOG");
mbcelogReg->clearAllBits();
OpenPOWER on IntegriCloud