PRD: rule and action file support for Explorer

Change-Id: I76253f19997b82cdcd667399b8b30d340170084a
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69104
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com>
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69307
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>

2 files changed, 1633 insertions, 0 deletions

diff --git a/src/usr/diag/prdf/common/plat/explorer/explorer_ocmb.rule b/src/usr/diag/prdf/common/plat/explorer/explorer_ocmb.rule
new file mode 100644
index 000000000..7fefa6a2c
--- /dev/null
+++ b/src/usr/diag/prdf/common/plat/explorer/explorer_ocmb.rule
@@ -0,0 +1,1467 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/usr/diag/prdf/common/plat/explorer/explorer_ocmb.rule $
+#
+# OpenPOWER HostBoot Project
+#
+# Contributors Listed Below - COPYRIGHT 2018
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+
+chip explorer_ocmb
+{
+    name        "EXPLORER OCMB target";
+    targettype  TYPE_OCMB_CHIP;
+    sigoff      0x9000;
+    dump        DUMP_CONTENT_HW;
+    scomlen     64;
+
+ #############################################################################
+ #                                                                           #
+ #  ######                                                                   #
+ #  #     #  ######   ####     ###    ####    #####  ######  #####    ####   #
+ #  #     #  #       #    #     #    #          #    #       #    #  #       #
+ #  ######   #####   #          #     ####      #    #####   #    #   ####   #
+ #  #   #    #       #  ###     #         #     #    #       #####        #  #
+ #  #    #   #       #    #     #    #    #     #    #       #   #   #    #  #
+ #  #     #  ######   ####     ###    ####      #    ######  #    #   ####   #
+ #                                                                           #
+ #############################################################################
+
+    ############################################################################
+    # MB Chiplet FIR
+    ############################################################################
+
+    register MB_CHIPLET_CS_FIR
+    {
+        name        "MB Chiplet Checkstop FIR";
+        scomaddr    0x08040000;
+        capture     group default;
+    };
+
+    register MB_CHIPLET_RE_FIR
+    {
+        name        "MB Chiplet Recoverable FIR";
+        scomaddr    0x08040001;
+        capture     group default;
+    };
+
+    register MB_CHIPLET_FIR_MASK
+    {
+        name        "MB Chiplet FIR MASK";
+        scomaddr    0x08040002;
+        capture     group default;
+    };
+
+    ############################################################################
+    # MB Chiplet Special Attention FIR
+    ############################################################################
+
+    register MB_CHIPLET_SPA_FIR
+    {
+        name        "MB Chiplet Special Attention FIR";
+        scomaddr    0x08040004;
+        capture     group default;
+    };
+
+    register MB_CHIPLET_SPA_FIR_MASK
+    {
+        name        "MB Chiplet Special Attention FIR MASK";
+        scomaddr    0x08040007;
+        capture     group default;
+    };
+
+    ############################################################################
+    # Explorer chip MB_LFIR
+    ############################################################################
+
+    register MB_LFIR
+    {
+        name        "Explorer chip MB_LFIR";
+        scomaddr    0x0804000a;
+        reset       (&, 0x0804000b);
+        mask        (|, 0x0804000f);
+        capture     group default;
+    };
+
+    register MB_LFIR_MASK
+    {
+        name        "Explorer chip MB_LFIR MASK";
+        scomaddr    0x0804000d;
+        capture     group default;
+    };
+
+    register MB_LFIR_ACT0
+    {
+        name        "Explorer chip MB_LFIR ACT0";
+        scomaddr    0x08040010;
+        capture     group default;
+        capture     req nonzero("MB_LFIR");
+    };
+
+    register MB_LFIR_ACT1
+    {
+        name        "Explorer chip MB_LFIR ACT1";
+        scomaddr    0x08040011;
+        capture     group default;
+        capture     req nonzero("MB_LFIR");
+    };
+
+    ############################################################################
+    # Explorer chip MMIOFIR
+    ############################################################################
+
+    register MMIOFIR
+    {
+        name        "Explorer chip MMIOFIR";
+        scomaddr    0x08010870;
+        reset       (&, 0x08010871);
+        mask        (|, 0x08010875);
+        capture     group default;
+    };
+
+    register MMIOFIR_MASK
+    {
+        name        "Explorer chip MMIOFIR MASK";
+        scomaddr    0x08010873;
+        capture     group default;
+    };
+
+    register MMIOFIR_ACT0
+    {
+        name        "Explorer chip MMIOFIR ACT0";
+        scomaddr    0x08010876;
+        capture     group default;
+        capture     req nonzero("MMIOFIR");
+    };
+
+    register MMIOFIR_ACT1
+    {
+        name        "Explorer chip MMIOFIR ACT1";
+        scomaddr    0x08010877;
+        capture     group default;
+        capture     req nonzero("MMIOFIR");
+    };
+
+    ############################################################################
+    # Explorer chip SRQFIR
+    ############################################################################
+
+    register SRQFIR
+    {
+        name        "Explorer chip SRQFIR";
+        scomaddr    0x08011400;
+        reset       (&, 0x08011401);
+        mask        (|, 0x08011405);
+        capture     group default;
+    };
+
+    register SRQFIR_MASK
+    {
+        name        "Explorer chip SRQFIR MASK";
+        scomaddr    0x08011403;
+        capture     group default;
+    };
+
+    register SRQFIR_ACT0
+    {
+        name        "Explorer chip SRQFIR ACT0";
+        scomaddr    0x08011406;
+        capture     group default;
+        capture     req nonzero("SRQFIR");
+    };
+
+    register SRQFIR_ACT1
+    {
+        name        "Explorer chip SRQFIR ACT1";
+        scomaddr    0x08011407;
+        capture     group default;
+        capture     req nonzero("SRQFIR");
+    };
+
+    ############################################################################
+    # Explorer chip MCBISTFIR
+    ############################################################################
+
+    register MCBISTFIR
+    {
+        name        "Explorer chip MCBISTFIR";
+        scomaddr    0x08011800;
+        reset       (&, 0x08011801);
+        mask        (|, 0x08011805);
+        capture     group default;
+    };
+
+    register MCBISTFIR_MASK
+    {
+        name        "Explorer chip MCBISTFIR MASK";
+        scomaddr    0x08011803;
+        capture     group default;
+    };
+
+    register MCBISTFIR_ACT0
+    {
+        name        "Explorer chip MCBISTFIR ACT0";
+        scomaddr    0x08011806;
+        capture     group default;
+        capture     req nonzero("MCBISTFIR");
+    };
+
+    register MCBISTFIR_ACT1
+    {
+        name        "Explorer chip MCBISTFIR ACT1";
+        scomaddr    0x08011807;
+        capture     group default;
+        capture     req nonzero("MCBISTFIR");
+    };
+
+    ############################################################################
+    # Explorer chip RDFFIR
+    ############################################################################
+
+    register RDFFIR
+    {
+        name        "Explorer chip RDFFIR";
+        scomaddr    0x08011c00;
+        reset       (&, 0x08011c01);
+        mask        (|, 0x08011c05);
+        capture     group default;
+    };
+
+    register RDFFIR_MASK
+    {
+        name        "Explorer chip RDFFIR MASK";
+        scomaddr    0x08011c03;
+        capture     group default;
+    };
+
+    register RDFFIR_ACT0
+    {
+        name        "Explorer chip RDFFIR ACT0";
+        scomaddr    0x08011c06;
+        capture     group default;
+        capture     req nonzero("RDFFIR");
+    };
+
+    register RDFFIR_ACT1
+    {
+        name        "Explorer chip RDFFIR ACT1";
+        scomaddr    0x08011c07;
+        capture     group default;
+        capture     req nonzero("RDFFIR");
+    };
+
+    ############################################################################
+    # Explorer chip TLXFIR
+    ############################################################################
+
+    register TLXFIR
+    {
+        name        "Explorer chip TLXFIR";
+        scomaddr    0x08012400;
+        reset       (&, 0x08012401);
+        mask        (|, 0x08012405);
+        capture     group default;
+    };
+
+    register TLXFIR_MASK
+    {
+        name        "Explorer chip TLXFIR MASK";
+        scomaddr    0x08012403;
+        capture     group default;
+    };
+
+    register TLXFIR_ACT0
+    {
+        name        "Explorer chip TLXFIR ACT0";
+        scomaddr    0x08012406;
+        capture     group default;
+        capture     req nonzero("TLXFIR");
+    };
+
+    register TLXFIR_ACT1
+    {
+        name        "Explorer chip TLXFIR ACT1";
+        scomaddr    0x08012407;
+        capture     group default;
+        capture     req nonzero("TLXFIR");
+    };
+
+    ############################################################################
+    # Explorer chip OMIDLFIR
+    ############################################################################
+
+    register OMIDLFIR
+    {
+        name        "Explorer chip OMIDLFIR";
+        scomaddr    0x08012800;
+        reset       (&, 0x08012801);
+        mask        (|, 0x08012805);
+        capture     group default;
+    };
+
+    register OMIDLFIR_MASK
+    {
+        name        "Explorer chip OMIDLFIR MASK";
+        scomaddr    0x08012803;
+        capture     group default;
+    };
+
+    register OMIDLFIR_ACT0
+    {
+        name        "Explorer chip OMIDLFIR ACT0";
+        scomaddr    0x08012806;
+        capture     group default;
+        capture     req nonzero("OMIDLFIR");
+    };
+
+    register OMIDLFIR_ACT1
+    {
+        name        "Explorer chip OMIDLFIR ACT1";
+        scomaddr    0x08012807;
+        capture     group default;
+        capture     req nonzero("OMIDLFIR");
+    };
+
+# Include registers not defined by the xml
+.include "explorer_ocmb_regs.rule";
+
+};
+
+ ##############################################################################
+ #                                                                            #
+ # ####                                 #                                     #
+ # #   # #   # #    #####  ###      #  # #    ##  ##### ###  ###  #   #  ###  #
+ # #   # #   # #    #     #        #  #   #  #  #   #    #  #   # ##  # #     #
+ # ####  #   # #    ####   ###    #  ####### #      #    #  #   # # # #  ###  #
+ # #  #  #   # #    #         #  #   #     # #  #   #    #  #   # #  ##     # #
+ # #   #  ###  #### #####  ###  #    #     #  ##    #   ###  ###  #   #  ###  #
+ #                                                                            #
+ ##############################################################################
+
+################################################################################
+# MB Chiplet FIR
+################################################################################
+
+rule rMB_CHIPLET_FIR
+{
+  UNIT_CS:
+     MB_CHIPLET_CS_FIR       & ~MB_CHIPLET_FIR_MASK & `1fffffffffffffff`;
+  RECOVERABLE:
+    (MB_CHIPLET_RE_FIR >> 2) & ~MB_CHIPLET_FIR_MASK & `1fffffffffffffff`;
+};
+
+group gMB_CHIPLET_FIR attntype CHECK_STOP, RECOVERABLE
+    filter singlebit
+{
+    /** MB_CHIPLET_FIR[3]
+     *  Attention from MB_LFIR
+     */
+    (rMB_CHIPLET_FIR, bit(3)) ? analyzeMB_LFIR;
+
+    /** MB_CHIPLET_FIR[4]
+     *  Attention from MMIOFIR
+     */
+    (rMB_CHIPLET_FIR, bit(4)) ? analyzeMMIOFIR;
+
+    /** MB_CHIPLET_FIR[7]
+     *  Attention from SRQFIR
+     */
+    (rMB_CHIPLET_FIR, bit(7)) ? analyzeSRQFIR;
+
+    /** MB_CHIPLET_FIR[8]
+     *  Attention from MCBISTFIR
+     */
+    (rMB_CHIPLET_FIR, bit(8)) ? analyzeMCBISTFIR;
+
+    /** MB_CHIPLET_FIR[9]
+     *  Attention from RDFFIR
+     */
+    (rMB_CHIPLET_FIR, bit(9)) ? analyzeRDFFIR;
+
+    /** MB_CHIPLET_FIR[11]
+     *  Attention from TLXFIR
+     */
+    (rMB_CHIPLET_FIR, bit(11)) ? analyzeTLXFIR;
+
+    /** MB_CHIPLET_FIR[12]
+     *  Attention from OMIDLFIR
+     */
+    (rMB_CHIPLET_FIR, bit(12)) ? analyzeOMIDLFIR;
+
+};
+
+################################################################################
+# MB Chiplet Special Attention FIR
+################################################################################
+
+rule rMB_CHIPLET_SPA_FIR
+{
+  HOST_ATTN:
+    MB_CHIPLET_SPA_FIR & ~MB_CHIPLET_SPA_FIR_MASK;
+};
+
+group gMB_CHIPLET_SPA_FIR attntype HOST_ATTN
+    filter singlebit
+{
+    /** MB_CHIPLET_SPA_FIR[1]
+     *  Attention from MMIOFIR
+     */
+    (rMB_CHIPLET_SPA_FIR, bit(1)) ? analyzeMMIOFIR;
+
+    /** MB_CHIPLET_SPA_FIR[4]
+     *  Attention from SRQFIR
+     */
+    (rMB_CHIPLET_SPA_FIR, bit(4)) ? analyzeSRQFIR;
+
+    /** MB_CHIPLET_SPA_FIR[5]
+     *  Attention from MCBISTFIR
+     */
+    (rMB_CHIPLET_SPA_FIR, bit(5)) ? analyzeMCBISTFIR;
+
+    /** MB_CHIPLET_SPA_FIR[6]
+     *  Attention from RDFFIR
+     */
+    (rMB_CHIPLET_SPA_FIR, bit(6)) ? analyzeRDFFIR;
+
+    /** MB_CHIPLET_SPA_FIR[8]
+     *  Attention from TLXFIR
+     */
+    (rMB_CHIPLET_SPA_FIR, bit(8)) ? analyzeTLXFIR;
+
+    /** MB_CHIPLET_SPA_FIR[9]
+     *  Attention from OMIDLFIR
+     */
+    (rMB_CHIPLET_SPA_FIR, bit(9)) ? analyzeOMIDLFIR;
+
+};
+
+################################################################################
+# Explorer chip MB_LFIR
+################################################################################
+
+rule rMB_LFIR
+{
+  UNIT_CS:
+    MB_LFIR & ~MB_LFIR_MASK & ~MB_LFIR_ACT0 & ~MB_LFIR_ACT1;
+  RECOVERABLE:
+    MB_LFIR & ~MB_LFIR_MASK & ~MB_LFIR_ACT0 &  MB_LFIR_ACT1;
+  HOST_ATTN:
+    MB_LFIR & ~MB_LFIR_MASK &  MB_LFIR_ACT0 & ~MB_LFIR_ACT1;
+};
+
+group gMB_LFIR
+    filter singlebit,
+           cs_root_cause
+{
+    /** MB_LFIR[0]
+     *  CFIR access PCB error
+     */
+    (rMB_LFIR, bit(0)) ? defaultMaskedError;
+
+    /** MB_LFIR[1]
+     *  CFIR internal parity error
+     */
+    (rMB_LFIR, bit(1)) ? defaultMaskedError;
+
+    /** MB_LFIR[2]
+     *  LFIR internal parity error
+     */
+    (rMB_LFIR, bit(2)) ? defaultMaskedError;
+
+    /** MB_LFIR[3]
+     *  Debug scom satellite error
+     */
+    (rMB_LFIR, bit(3)) ? defaultMaskedError;
+
+    /** MB_LFIR[4]
+     *  PSCOM Logic: PCB Access Error
+     */
+    (rMB_LFIR, bit(4)) ? defaultMaskedError;
+
+    /** MB_LFIR[5]
+     *  PSCOM Logic: Summarized internal errors
+     */
+    (rMB_LFIR, bit(5)) ? defaultMaskedError;
+
+    /** MB_LFIR[6]
+     *  Trace Logic : Scom Satellite Error - Trace0
+     */
+    (rMB_LFIR, bit(6)) ? defaultMaskedError;
+
+    /** MB_LFIR[7]
+     *  Trace Logic : Scom Satellite Error - Trace1
+     */
+    (rMB_LFIR, bit(7)) ? defaultMaskedError;
+
+    /** MB_LFIR[8]
+     *  unused
+     */
+    (rMB_LFIR, bit(8)) ? defaultMaskedError;
+
+    /** MB_LFIR[9]
+     *  MSG access PCB error
+     */
+    (rMB_LFIR, bit(9)) ? defaultMaskedError;
+
+    /** MB_LFIR[10:62]
+     *  bits from the microsemi message register (0 to 52)
+     */
+    (rMB_LFIR, bit(10|11|12|13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40|41|42|43|44|45|46|47|48|49|50|51|52|53|54|55|56|57|58|59|60|61|62)) ? defaultMaskedError;
+
+};
+
+################################################################################
+# Explorer chip MMIOFIR
+################################################################################
+
+rule rMMIOFIR
+{
+  UNIT_CS:
+    MMIOFIR & ~MMIOFIR_MASK & ~MMIOFIR_ACT0 & ~MMIOFIR_ACT1;
+  RECOVERABLE:
+    MMIOFIR & ~MMIOFIR_MASK & ~MMIOFIR_ACT0 &  MMIOFIR_ACT1;
+  HOST_ATTN:
+    MMIOFIR & ~MMIOFIR_MASK &  MMIOFIR_ACT0 & ~MMIOFIR_ACT1;
+};
+
+group gMMIOFIR
+    filter singlebit,
+           cs_root_cause
+{
+    /** MMIOFIR[0]
+     *  AFU desc unimp
+     */
+    (rMMIOFIR, bit(0)) ? defaultMaskedError;
+
+    /** MMIOFIR[1]
+     *  MMIO err
+     */
+    (rMMIOFIR, bit(1)) ? defaultMaskedError;
+
+    /** MMIOFIR[2]
+     *  SCOM err
+     */
+    (rMMIOFIR, bit(2)) ? defaultMaskedError;
+
+    /** MMIOFIR[3]
+     *  FSM err
+     */
+    (rMMIOFIR, bit(3)) ? defaultMaskedError;
+
+    /** MMIOFIR[4]
+     *  FIFO overflow
+     */
+    (rMMIOFIR, bit(4)) ? defaultMaskedError;
+
+    /** MMIOFIR[5]
+     *  Ctl reg parity err
+     */
+    (rMMIOFIR, bit(5)) ? defaultMaskedError;
+
+    /** MMIOFIR[6]
+     *  Info reg parity error
+     */
+    (rMMIOFIR, bit(6)) ? defaultMaskedError;
+
+    /** MMIOFIR[7]
+     *  SNSC both starts err
+     */
+    (rMMIOFIR, bit(7)) ? defaultMaskedError;
+
+    /** MMIOFIR[8]
+     *  SNSC mult seq parity err
+     */
+    (rMMIOFIR, bit(8)) ? defaultMaskedError;
+
+    /** MMIOFIR[9]
+     *  SNSC FSM parity err
+     */
+    (rMMIOFIR, bit(9)) ? defaultMaskedError;
+
+    /** MMIOFIR[10]
+     *  SNSC reg parity err
+     */
+    (rMMIOFIR, bit(10)) ? defaultMaskedError;
+
+    /** MMIOFIR[11]
+     *  acTAG PASID cfg err
+     */
+    (rMMIOFIR, bit(11)) ? defaultMaskedError;
+
+};
+
+################################################################################
+# Explorer chip SRQFIR
+################################################################################
+
+rule rSRQFIR
+{
+  UNIT_CS:
+    SRQFIR & ~SRQFIR_MASK & ~SRQFIR_ACT0 & ~SRQFIR_ACT1;
+  RECOVERABLE:
+    SRQFIR & ~SRQFIR_MASK & ~SRQFIR_ACT0 &  SRQFIR_ACT1;
+  HOST_ATTN:
+    SRQFIR & ~SRQFIR_MASK &  SRQFIR_ACT0 & ~SRQFIR_ACT1;
+};
+
+group gSRQFIR
+    filter singlebit,
+           cs_root_cause
+{
+    /** SRQFIR[0]
+     *  SRQ recoverable error
+     */
+    (rSRQFIR, bit(0)) ? defaultMaskedError;
+
+    /** SRQFIR[1]
+     *  SRQ nonrecoverable error
+     */
+    (rSRQFIR, bit(1)) ? defaultMaskedError;
+
+    /** SRQFIR[2]
+     *  Refresh overrun
+     */
+    (rSRQFIR, bit(2)) ? defaultMaskedError;
+
+    /** SRQFIR[3]
+     *  WAT error
+     */
+    (rSRQFIR, bit(3)) ? defaultMaskedError;
+
+    /** SRQFIR[4]
+     *  RCD parity error
+     */
+    (rSRQFIR, bit(4)) ? defaultMaskedError;
+
+    /** SRQFIR[5]
+     *  MCB logic error
+     */
+    (rSRQFIR, bit(5)) ? defaultMaskedError;
+
+    /** SRQFIR[6]
+     *  Emergency throttle
+     */
+    (rSRQFIR, bit(6)) ? defaultMaskedError;
+
+    /** SRQFIR[7]
+     *  NCF MCB parity error
+     */
+    (rSRQFIR, bit(7)) ? defaultMaskedError;
+
+    /** SRQFIR[8]
+     *  DDR MBA event n
+     */
+    (rSRQFIR, bit(8)) ? defaultMaskedError;
+
+    /** SRQFIR[9]
+     *  WRQ RRQ hang err
+     */
+    (rSRQFIR, bit(9)) ? defaultMaskedError;
+
+    /** SRQFIR[10]
+     *  SM one hot error
+     */
+    (rSRQFIR, bit(10)) ? defaultMaskedError;
+
+    /** SRQFIR[11]
+     *  Reg parity error
+     */
+    (rSRQFIR, bit(11)) ? defaultMaskedError;
+
+    /** SRQFIR[12]
+     *  Cmd parity error
+     */
+    (rSRQFIR, bit(12)) ? defaultMaskedError;
+
+    /** SRQFIR[13]
+     *  Port fail
+     */
+    (rSRQFIR, bit(13)) ? defaultMaskedError;
+
+    /** SRQFIR[14]
+     *  Spare
+     */
+    (rSRQFIR, bit(14)) ? defaultMaskedError;
+
+    /** SRQFIR[15]
+     *  Debug parity error
+     */
+    (rSRQFIR, bit(15)) ? defaultMaskedError;
+
+    /** SRQFIR[16]
+     *  WDF unrecoverable mainline error
+     */
+    (rSRQFIR, bit(16)) ? defaultMaskedError;
+
+    /** SRQFIR[17]
+     *  WDF mmio error
+     */
+    (rSRQFIR, bit(17)) ? defaultMaskedError;
+
+    /** SRQFIR[18]
+     *  WDF array UE on mainline operations (SUE put in mem)
+     */
+    (rSRQFIR, bit(18)) ? defaultMaskedError;
+
+    /** SRQFIR[19]
+     *  WDF mainline dataflow error (SUE not reliably put in mem)
+     */
+    (rSRQFIR, bit(19)) ? defaultMaskedError;
+
+    /** SRQFIR[20]
+     *  WDF scom register parity err, affecting mainline config
+     */
+    (rSRQFIR, bit(20)) ? defaultMaskedError;
+
+    /** SRQFIR[21]
+     *  WDF scom register parity err, affecting scom ops only
+     */
+    (rSRQFIR, bit(21)) ? defaultMaskedError;
+
+    /** SRQFIR[22]
+     *  WDF SCOM fsm parity error
+     */
+    (rSRQFIR, bit(22)) ? defaultMaskedError;
+
+    /** SRQFIR[23]
+     *  WDF write buffer array CE
+     */
+    (rSRQFIR, bit(23)) ? defaultMaskedError;
+
+    /** SRQFIR[24]
+     *  NCF UE
+     */
+    (rSRQFIR, bit(24)) ? defaultMaskedError;
+
+    /** SRQFIR[25]
+     *  TBD
+     */
+    (rSRQFIR, bit(25)) ? defaultMaskedError;
+
+    /** SRQFIR[26]
+     *  NCF logic error
+     */
+    (rSRQFIR, bit(26)) ? defaultMaskedError;
+
+    /** SRQFIR[27]
+     *  NCF parity error
+     */
+    (rSRQFIR, bit(27)) ? defaultMaskedError;
+
+    /** SRQFIR[28]
+     *  NCF correctable error
+     */
+    (rSRQFIR, bit(28)) ? defaultMaskedError;
+
+    /** SRQFIR[29]
+     *  Internal scom error
+     */
+    (rSRQFIR, bit(29)) ? defaultMaskedError;
+
+    /** SRQFIR[30]
+     *  Internal scom error copy
+     */
+    (rSRQFIR, bit(30)) ? defaultMaskedError;
+
+};
+
+################################################################################
+# Explorer chip MCBISTFIR
+################################################################################
+
+rule rMCBISTFIR
+{
+  UNIT_CS:
+    MCBISTFIR & ~MCBISTFIR_MASK & ~MCBISTFIR_ACT0 & ~MCBISTFIR_ACT1;
+  RECOVERABLE:
+    MCBISTFIR & ~MCBISTFIR_MASK & ~MCBISTFIR_ACT0 &  MCBISTFIR_ACT1;
+  HOST_ATTN:
+    MCBISTFIR & ~MCBISTFIR_MASK &  MCBISTFIR_ACT0 & ~MCBISTFIR_ACT1;
+};
+
+group gMCBISTFIR
+    filter singlebit,
+           cs_root_cause
+{
+    /** MCBISTFIR[0]
+     *  Invalid maint address
+     */
+    (rMCBISTFIR, bit(0)) ? defaultMaskedError;
+
+    /** MCBISTFIR[1]
+     *  Command address timeout
+     */
+    (rMCBISTFIR, bit(1)) ? defaultMaskedError;
+
+    /** MCBISTFIR[2]
+     *  Internal FSM error
+     */
+    (rMCBISTFIR, bit(2)) ? defaultMaskedError;
+
+    /** MCBISTFIR[3]
+     *  MCBIST broadcast out of sync
+     */
+    (rMCBISTFIR, bit(3)) ? defaultMaskedError;
+
+    /** MCBISTFIR[4]
+     *  MCBIST data error
+     */
+    (rMCBISTFIR, bit(4)) ? defaultMaskedError;
+
+    /** MCBISTFIR[5]
+     *  Hard NCE ETE attn
+     */
+    (rMCBISTFIR, bit(5)) ? defaultMaskedError;
+
+    /** MCBISTFIR[6]
+     *  Soft NCE ETE attn
+     */
+    (rMCBISTFIR, bit(6)) ? defaultMaskedError;
+
+    /** MCBISTFIR[7]
+     *  Int NCE ETE attn
+     */
+    (rMCBISTFIR, bit(7)) ? defaultMaskedError;
+
+    /** MCBISTFIR[8]
+     *  RCE ETE attn
+     */
+    (rMCBISTFIR, bit(8)) ? defaultMaskedError;
+
+    /** MCBISTFIR[9]
+     *  ICE (IMPE) ETE attn
+     */
+    (rMCBISTFIR, bit(9)) ? defaultMaskedError;
+
+    /** MCBISTFIR[10]
+     *  MCBIST program complete
+     */
+    (rMCBISTFIR, bit(10)) ? defaultMaskedError;
+
+    /** MCBISTFIR[11]
+     *  MCBIST CCS subtest done
+     */
+    (rMCBISTFIR, bit(11)) ? defaultMaskedError;
+
+    /** MCBISTFIR[12]
+     *  WAT debug bus attn
+     */
+    (rMCBISTFIR, bit(12)) ? defaultMaskedError;
+
+    /** MCBISTFIR[13]
+     *  SCOM recoverable reg parity error
+     */
+    (rMCBISTFIR, bit(13)) ? defaultMaskedError;
+
+    /** MCBISTFIR[14]
+     *  SCOM fatal reg parity error
+     */
+    (rMCBISTFIR, bit(14)) ? defaultMaskedError;
+
+    /** MCBISTFIR[15]
+     *  SCOM WAT and debug reg parity error
+     */
+    (rMCBISTFIR, bit(15)) ? defaultMaskedError;
+
+    /** MCBISTFIR[16]
+     *  Reserved
+     */
+    (rMCBISTFIR, bit(16)) ? defaultMaskedError;
+
+    /** MCBISTFIR[17]
+     *  Reserved
+     */
+    (rMCBISTFIR, bit(17)) ? defaultMaskedError;
+
+    /** MCBISTFIR[18]
+     *  Internal SCOM error
+     */
+    (rMCBISTFIR, bit(18)) ? defaultMaskedError;
+
+    /** MCBISTFIR[19]
+     *  Internal SCOM error clone
+     */
+    (rMCBISTFIR, bit(19)) ? defaultMaskedError;
+
+};
+
+################################################################################
+# Explorer chip RDFFIR
+################################################################################
+
+rule rRDFFIR
+{
+  UNIT_CS:
+    RDFFIR & ~RDFFIR_MASK & ~RDFFIR_ACT0 & ~RDFFIR_ACT1;
+  RECOVERABLE:
+    RDFFIR & ~RDFFIR_MASK & ~RDFFIR_ACT0 &  RDFFIR_ACT1;
+  HOST_ATTN:
+    RDFFIR & ~RDFFIR_MASK &  RDFFIR_ACT0 & ~RDFFIR_ACT1;
+};
+
+group gRDFFIR
+    filter singlebit,
+           cs_root_cause
+{
+    /** RDFFIR[0]
+     *  Mainline read MPE on rank 0
+     */
+    (rRDFFIR, bit(0)) ? defaultMaskedError;
+
+    /** RDFFIR[1]
+     *  Mainline read MPE on rank 1
+     */
+    (rRDFFIR, bit(1)) ? defaultMaskedError;
+
+    /** RDFFIR[2]
+     *  Mainline read MPE on rank 2
+     */
+    (rRDFFIR, bit(2)) ? defaultMaskedError;
+
+    /** RDFFIR[3]
+     *  Maineline read MPE on rank 3
+     */
+    (rRDFFIR, bit(3)) ? defaultMaskedError;
+
+    /** RDFFIR[4]
+     *  Mainline read MPE on rank 4
+     */
+    (rRDFFIR, bit(4)) ? defaultMaskedError;
+
+    /** RDFFIR[5]
+     *  Mainline read MPE on rank 5
+     */
+    (rRDFFIR, bit(5)) ? defaultMaskedError;
+
+    /** RDFFIR[6]
+     *  Mainline read MPE on rank 6
+     */
+    (rRDFFIR, bit(6)) ? defaultMaskedError;
+
+    /** RDFFIR[7]
+     *  Mainline read MPE on rank 7
+     */
+    (rRDFFIR, bit(7)) ? defaultMaskedError;
+
+    /** RDFFIR[8]
+     *  Mainline read NCE
+     */
+    (rRDFFIR, bit(8)) ? defaultMaskedError;
+
+    /** RDFFIR[9]
+     *  Mainline read TCE
+     */
+    (rRDFFIR, bit(9)) ? defaultMaskedError;
+
+    /** RDFFIR[10]
+     *  Mainline read SCE
+     */
+    (rRDFFIR, bit(10)) ? defaultMaskedError;
+
+    /** RDFFIR[11]
+     *  Mainline read MCE
+     */
+    (rRDFFIR, bit(11)) ? defaultMaskedError;
+
+    /** RDFFIR[12]
+     *  Mainline read SUE
+     */
+    (rRDFFIR, bit(12)) ? defaultMaskedError;
+
+    /** RDFFIR[13]
+     *  Mainline read AUE
+     */
+    (rRDFFIR, bit(13)) ? defaultMaskedError;
+
+    /** RDFFIR[14]
+     *  Mainline read UE
+     */
+    (rRDFFIR, bit(14)) ? defaultMaskedError;
+
+    /** RDFFIR[15]
+     *  Mainline read RCD
+     */
+    (rRDFFIR, bit(15)) ? defaultMaskedError;
+
+    /** RDFFIR[16]
+     *  Mainline read IAUE
+     */
+    (rRDFFIR, bit(16)) ? defaultMaskedError;
+
+    /** RDFFIR[17]
+     *  Mainline read IUE
+     */
+    (rRDFFIR, bit(17)) ? defaultMaskedError;
+
+    /** RDFFIR[18]
+     *  Mainline read IRCD
+     */
+    (rRDFFIR, bit(18)) ? defaultMaskedError;
+
+    /** RDFFIR[19]
+     *  Mainline read IMPE
+     */
+    (rRDFFIR, bit(19)) ? defaultMaskedError;
+
+    /** RDFFIR[20:27]
+     *  Maintenance MPE
+     */
+    (rRDFFIR, bit(20|21|22|23|24|25|26|27)) ? defaultMaskedError;
+
+    /** RDFFIR[28]
+     *  Maintenance NCE
+     */
+    (rRDFFIR, bit(28)) ? defaultMaskedError;
+
+    /** RDFFIR[29]
+     *  Maintenance TCE
+     */
+    (rRDFFIR, bit(29)) ? defaultMaskedError;
+
+    /** RDFFIR[30]
+     *  Maintenance SCE
+     */
+    (rRDFFIR, bit(30)) ? defaultMaskedError;
+
+    /** RDFFIR[31]
+     *  Maintenance MCE
+     */
+    (rRDFFIR, bit(31)) ? defaultMaskedError;
+
+    /** RDFFIR[32]
+     *  Maintenance SUE
+     */
+    (rRDFFIR, bit(32)) ? defaultMaskedError;
+
+    /** RDFFIR[33]
+     *  Maintenance AUE
+     */
+    (rRDFFIR, bit(33)) ? defaultMaskedError;
+
+    /** RDFFIR[34]
+     *  Maintenance UE
+     */
+    (rRDFFIR, bit(34)) ? defaultMaskedError;
+
+    /** RDFFIR[35]
+     *  Maintenance RCD
+     */
+    (rRDFFIR, bit(35)) ? defaultMaskedError;
+
+    /** RDFFIR[36]
+     *  Maintenance IAUE
+     */
+    (rRDFFIR, bit(36)) ? defaultMaskedError;
+
+    /** RDFFIR[37]
+     *  Maintenance IUE
+     */
+    (rRDFFIR, bit(37)) ? defaultMaskedError;
+
+    /** RDFFIR[38]
+     *  Maintenance IRCD
+     */
+    (rRDFFIR, bit(38)) ? defaultMaskedError;
+
+    /** RDFFIR[39]
+     *  Maintenance IMPE
+     */
+    (rRDFFIR, bit(39)) ? defaultMaskedError;
+
+    /** RDFFIR[40]
+     *  RDDATA valid error
+     */
+    (rRDFFIR, bit(40)) ? defaultMaskedError;
+
+    /** RDFFIR[41]
+     *  SCOM status register parity error
+     */
+    (rRDFFIR, bit(41)) ? defaultMaskedError;
+
+    /** RDFFIR[42]
+     *  SCOM recoverable register parity error
+     */
+    (rRDFFIR, bit(42)) ? defaultMaskedError;
+
+    /** RDFFIR[43]
+     *  SCOM unrecoverable register parity error
+     */
+    (rRDFFIR, bit(43)) ? defaultMaskedError;
+
+    /** RDFFIR[44]
+     *  ECC corrector internal parity error
+     */
+    (rRDFFIR, bit(44)) ? defaultMaskedError;
+
+    /** RDFFIR[45]
+     *  Rd Buff ECC CHK Cor CE DW0 Detected
+     */
+    (rRDFFIR, bit(45)) ? defaultMaskedError;
+
+    /** RDFFIR[46]
+     *  Rd Buff ECC CHK Cor CE DW1 Detected
+     */
+    (rRDFFIR, bit(46)) ? defaultMaskedError;
+
+    /** RDFFIR[47]
+     *  Rd Buff ECC CHK Cor UE DW0 Detected
+     */
+    (rRDFFIR, bit(47)) ? defaultMaskedError;
+
+    /** RDFFIR[48]
+     *  Rd Buff ECC CHK Cor UE DW1 Detected
+     */
+    (rRDFFIR, bit(48)) ? defaultMaskedError;
+
+    /** RDFFIR[49:59]
+     *  Reserved
+     */
+    (rRDFFIR, bit(49|50|51|52|53|54|55|56|57|58|59)) ? defaultMaskedError;
+
+    /** RDFFIR[60]
+     *  SCOM register parity error for debug/wat control
+     */
+    (rRDFFIR, bit(60)) ? defaultMaskedError;
+
+    /** RDFFIR[61]
+     *  Reserved
+     */
+    (rRDFFIR, bit(61)) ? defaultMaskedError;
+
+    /** RDFFIR[62]
+     *  Internal SCOM error
+     */
+    (rRDFFIR, bit(62)) ? defaultMaskedError;
+
+    /** RDFFIR[63]
+     *  Internal SCOM error copy
+     */
+    (rRDFFIR, bit(63)) ? defaultMaskedError;
+
+};
+
+################################################################################
+# Explorer chip TLXFIR
+################################################################################
+
+rule rTLXFIR
+{
+  UNIT_CS:
+    TLXFIR & ~TLXFIR_MASK & ~TLXFIR_ACT0 & ~TLXFIR_ACT1;
+  RECOVERABLE:
+    TLXFIR & ~TLXFIR_MASK & ~TLXFIR_ACT0 &  TLXFIR_ACT1;
+  HOST_ATTN:
+    TLXFIR & ~TLXFIR_MASK &  TLXFIR_ACT0 & ~TLXFIR_ACT1;
+};
+
+group gTLXFIR
+    filter singlebit,
+           cs_root_cause
+{
+    /** TLXFIR[0]
+     *  Info reg parity error
+     */
+    (rTLXFIR, bit(0)) ? defaultMaskedError;
+
+    /** TLXFIR[1]
+     *  Ctrl reg parity error
+     */
+    (rTLXFIR, bit(1)) ? defaultMaskedError;
+
+    /** TLXFIR[2]
+     *  TLX VC0 return credit counter overflow
+     */
+    (rTLXFIR, bit(2)) ? defaultMaskedError;
+
+    /** TLXFIR[3]
+     *  TLX VC1 return credit counter overflow
+     */
+    (rTLXFIR, bit(3)) ? defaultMaskedError;
+
+    /** TLXFIR[4]
+     *  TLX dcp0 return credit counter overflow
+     */
+    (rTLXFIR, bit(4)) ? defaultMaskedError;
+
+    /** TLXFIR[5]
+     *  TLX dcp1 return credit counter overflow
+     */
+    (rTLXFIR, bit(5)) ? defaultMaskedError;
+
+    /** TLXFIR[6]
+     *  TLX credit management block error
+     */
+    (rTLXFIR, bit(6)) ? defaultMaskedError;
+
+    /** TLXFIR[7]
+     *  TLX credit management block parity error
+     */
+    (rTLXFIR, bit(7)) ? defaultMaskedError;
+
+    /** TLXFIR[8]
+     *  TLXT fatal parity error
+     */
+    (rTLXFIR, bit(8)) ? defaultMaskedError;
+
+    /** TLXFIR[9]
+     *  TLXT recoverable error
+     */
+    (rTLXFIR, bit(9)) ? defaultMaskedError;
+
+    /** TLXFIR[10]
+     *  TLXT configuration error
+     */
+    (rTLXFIR, bit(10)) ? defaultMaskedError;
+
+    /** TLXFIR[11]
+     *  TLXT informational parity error
+     */
+    (rTLXFIR, bit(11)) ? defaultMaskedError;
+
+    /** TLXFIR[12]
+     *  TLXT hard error
+     */
+    (rTLXFIR, bit(12)) ? defaultMaskedError;
+
+    /** TLXFIR[13:15]
+     *  Reserved
+     */
+    (rTLXFIR, bit(13|14|15)) ? defaultMaskedError;
+
+    /** TLXFIR[16]
+     *  Corrupted pad mem pattern
+     */
+    (rTLXFIR, bit(16)) ? defaultMaskedError;
+
+    /** TLXFIR[17]
+     *  Downstream OC parity error
+     */
+    (rTLXFIR, bit(17)) ? defaultMaskedError;
+
+    /** TLXFIR[18]
+     *  OC malformed
+     */
+    (rTLXFIR, bit(18)) ? defaultMaskedError;
+
+    /** TLXFIR[19]
+     *  OC protocol error
+     */
+    (rTLXFIR, bit(19)) ? defaultMaskedError;
+
+    /** TLXFIR[20]
+     *  Address translate error
+     */
+    (rTLXFIR, bit(20)) ? defaultMaskedError;
+
+    /** TLXFIR[21]
+     *  Metadata unc or data parity error
+     */
+    (rTLXFIR, bit(21)) ? defaultMaskedError;
+
+    /** TLXFIR[22]
+     *  OC unsupported group 2
+     */
+    (rTLXFIR, bit(22)) ? defaultMaskedError;
+
+    /** TLXFIR[23]
+     *  OC unsupported group 1
+     */
+    (rTLXFIR, bit(23)) ? defaultMaskedError;
+
+    /** TLXFIR[24]
+     *  Bit flip control error
+     */
+    (rTLXFIR, bit(24)) ? defaultMaskedError;
+
+    /** TLXFIR[25]
+     *  Control HW error
+     */
+    (rTLXFIR, bit(25)) ? defaultMaskedError;
+
+    /** TLXFIR[26]
+     *  ECC corrected and others
+     */
+    (rTLXFIR, bit(26)) ? defaultMaskedError;
+
+    /** TLXFIR[27]
+     *  Trace stop
+     */
+    (rTLXFIR, bit(27)) ? defaultMaskedError;
+
+    /** TLXFIR[28]
+     *  Internal SCOM error
+     */
+    (rTLXFIR, bit(28)) ? defaultMaskedError;
+
+    /** TLXFIR[29]
+     *  Internal SCOM error clone
+     */
+    (rTLXFIR, bit(29)) ? defaultMaskedError;
+
+};
+
+################################################################################
+# Explorer chip OMIDLFIR
+################################################################################
+
+rule rOMIDLFIR
+{
+  UNIT_CS:
+    OMIDLFIR & ~OMIDLFIR_MASK & ~OMIDLFIR_ACT0 & ~OMIDLFIR_ACT1;
+  RECOVERABLE:
+    OMIDLFIR & ~OMIDLFIR_MASK & ~OMIDLFIR_ACT0 &  OMIDLFIR_ACT1;
+  HOST_ATTN:
+    OMIDLFIR & ~OMIDLFIR_MASK &  OMIDLFIR_ACT0 & ~OMIDLFIR_ACT1;
+};
+
+group gOMIDLFIR
+    filter singlebit,
+           cs_root_cause
+{
+    /** OMIDLFIR[0]
+     *  DL0 fatal error
+     */
+    (rOMIDLFIR, bit(0)) ? defaultMaskedError;
+
+    /** OMIDLFIR[1]
+     *  Dl0 data UE
+     */
+    (rOMIDLFIR, bit(1)) ? defaultMaskedError;
+
+    /** OMIDLFIR[2]
+     *  Dl0 flit CE
+     */
+    (rOMIDLFIR, bit(2)) ? defaultMaskedError;
+
+    /** OMIDLFIR[3]
+     *  Dl0 CRC error
+     */
+    (rOMIDLFIR, bit(3)) ? defaultMaskedError;
+
+    /** OMIDLFIR[4]
+     *  DL0 nack
+     */
+    (rOMIDLFIR, bit(4)) ? defaultMaskedError;
+
+    /** OMIDLFIR[5]
+     *  DL0 X4 mode
+     */
+    (rOMIDLFIR, bit(5)) ? defaultMaskedError;
+
+    /** OMIDLFIR[6]
+     *  DL0 EDPL
+     */
+    (rOMIDLFIR, bit(6)) ? defaultMaskedError;
+
+    /** OMIDLFIR[7]
+     *  DL0 timeout
+     */
+    (rOMIDLFIR, bit(7)) ? defaultMaskedError;
+
+    /** OMIDLFIR[8]
+     *  DL0 remote retrain
+     */
+    (rOMIDLFIR, bit(8)) ? defaultMaskedError;
+
+    /** OMIDLFIR[9]
+     *  DL0 error retrain
+     */
+    (rOMIDLFIR, bit(9)) ? defaultMaskedError;
+
+    /** OMIDLFIR[10]
+     *  DL0 EDPL retrain
+     */
+    (rOMIDLFIR, bit(10)) ? defaultMaskedError;
+
+    /** OMIDLFIR[11]
+     *  DL0 trained
+     */
+    (rOMIDLFIR, bit(11)) ? defaultMaskedError;
+
+    /** OMIDLFIR[12]
+     *  DL0 endpoint bit 0
+     */
+    (rOMIDLFIR, bit(12)) ? defaultMaskedError;
+
+    /** OMIDLFIR[13]
+     *  DL0 endpoint bit 1
+     */
+    (rOMIDLFIR, bit(13)) ? defaultMaskedError;
+
+    /** OMIDLFIR[14]
+     *  DL0 endpoint bit 2
+     */
+    (rOMIDLFIR, bit(14)) ? defaultMaskedError;
+
+    /** OMIDLFIR[15]
+     *  DL0 endpoint bit 3
+     */
+    (rOMIDLFIR, bit(15)) ? defaultMaskedError;
+
+    /** OMIDLFIR[16]
+     *  DL0 endpoint bit 4
+     */
+    (rOMIDLFIR, bit(16)) ? defaultMaskedError;
+
+    /** OMIDLFIR[17]
+     *  DL0 endpoint bit 5
+     */
+    (rOMIDLFIR, bit(17)) ? defaultMaskedError;
+
+    /** OMIDLFIR[18]
+     *  DL0 endpoint bit 6
+     */
+    (rOMIDLFIR, bit(18)) ? defaultMaskedError;
+
+    /** OMIDLFIR[19]
+     *  DL0 endpoint bit 7
+     */
+    (rOMIDLFIR, bit(19)) ? defaultMaskedError;
+
+    /** OMIDLFIR[20:39]
+     *  DL1 reserved
+     */
+    (rOMIDLFIR, bit(20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? defaultMaskedError;
+
+    /** OMIDLFIR[40:59]
+     *  DL2 reserved
+     */
+    (rOMIDLFIR, bit(40|41|42|43|44|45|46|47|48|49|50|51|52|53|54|55|56|57|58|59)) ? defaultMaskedError;
+
+    /** OMIDLFIR[60]
+     *  Performance monitor wrapped
+     */
+    (rOMIDLFIR, bit(60)) ? defaultMaskedError;
+
+};
+
+ ##############################################################################
+ #                                                                            #
+ #    #                                  ###                                  #
+ #   # #    ##  ##### ###  ###  #   #   #   # #     #    ###   ###  ###  ###  #
+ #  #   #  #  #   #    #  #   # ##  #   #     #    # #  #     #     #   #     #
+ # ####### #      #    #  #   # # # #   #     #   #####  ###   ###  ##   ###  #
+ # #     # #  #   #    #  #   # #  ##   #   # #   #   #     #     # #       # #
+ # #     #  ##    #   ###  ###  #   #    ###  ### #   #  ###   ###  ###  ###  #
+ #                                                                            #
+ ##############################################################################
+
+# Include the actions defined for this target
+.include "explorer_ocmb_actions.rule";
+
diff --git a/src/usr/diag/prdf/common/plat/explorer/explorer_ocmb_actions.rule b/src/usr/diag/prdf/common/plat/explorer/explorer_ocmb_actions.rule
new file mode 100644
index 000000000..023821b0d
--- /dev/null
+++ b/src/usr/diag/prdf/common/plat/explorer/explorer_ocmb_actions.rule
@@ -0,0 +1,166 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/usr/diag/prdf/common/plat/explorer/explorer_ocmb_actions.rule $
+#
+# OpenPOWER HostBoot Project
+#
+# Contributors Listed Below - COPYRIGHT 2018
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+
+################################################################################
+#                                Thresholds                                    #
+################################################################################
+
+# Threshold syntax:
+#   threshold( field(<timebase>) [, mfg(<timebase>)|mfg_file(<mfg_theshold>)] );
+#
+# Timebase syntax:
+#   <threshold_count> [/ [timbase_count] <sec|min|hour|day>]
+#
+# Note that <mfg_theshold> can be found in prdfMfgThresholds.lst
+#
+# Examples:
+#   threshold( field( 1        ) );
+#   threshold( field(32 /   day) );
+#   threshold( field( 5 / 2 min) );
+#   threshold( field(32 / 1 day), mfg(2 / hour) );
+#   threshold( field( 2 /   min), mfg(1       ) );
+#   threshold( field(32 /   day), mfg_file(P8CHIP_OFFNODE_BUS_CES) );
+
+/** Threshold of 1 */
+actionclass threshold1
+{
+    threshold( field(1) );
+};
+
+/** Threshold of 32 per day */
+actionclass threshold32pday
+{
+    threshold( field(32 / day) );
+};
+
+################################################################################
+#                       Threshold and Mask policy
+################################################################################
+
+/**
+ * Threshold 32/day (field) and 1 (mnfg). Do not predictively callout on
+ * threshold in the field, instead just mask.
+ */
+actionclass threshold_and_mask
+{
+    threshold32pday;
+    funccall("ClearServiceCallFlag");
+};
+
+actionclass threshold_and_mask_self   { calloutSelfMed;   threshold_and_mask; };
+
+################################################################################
+#                               Special Flags                                  #
+################################################################################
+
+/** SUE source */
+actionclass SueSource { flag(UERE); };
+
+/** SUE originated from somewhere else */
+actionclass SueSeen { flag(SUE); };
+
+################################################################################
+#                               Simple Callouts                                #
+################################################################################
+
+# Callout self
+actionclass calloutSelfHigh { callout(MRU_HIGH); };
+actionclass calloutSelfMed  { callout(MRU_MED);  };
+actionclass calloutSelfMedA { callout(MRU_MEDA); };
+actionclass calloutSelfLow  { callout(MRU_LOW);  };
+
+# 2nd Level Support
+actionclass callout2ndLvlMed
+{ callout(procedure(LEVEL2_SUPPORT), MRU_MED); };
+
+/** Callout self with  low priority but don't gard it */
+actionclass calloutSelfLowNoGard
+{ callout(MRU_LOW, NO_GARD); };
+
+################################################################################
+#                           Callouts with thresholds                           #
+################################################################################
+
+actionclass self_th_1
+{
+    calloutSelfMed;
+    threshold1;
+};
+
+actionclass self_th_5perHour
+{
+    calloutSelfMed;
+    threshold5phour;
+};
+
+actionclass self_th_32perDay
+{
+    calloutSelfMed;
+    threshold32pday;
+};
+
+actionclass level2_th_1
+{
+    callout2ndLvlMed;
+    threshold1;
+};
+
+################################################################################
+#                           Callouts with flags                                #
+################################################################################
+
+actionclass self_th_1_UERE   { self_th_1;   SueSource; };
+actionclass level2_th_1_UERE { level2_th_1; SueSource; };
+
+################################################################################
+#                               Default callouts                               #
+################################################################################
+
+/** Default action for an unexpected unmasked bit */
+actionclass defaultMaskedError
+{
+    callout2ndLvlMed;
+    threshold1;
+};
+
+/** Default TBD action */
+actionclass TBDDefaultCallout
+{
+    callout2ndLvlMed;
+    threshold( field(32 / day), mfg(32 / day) );
+};
+
+################################################################################
+# Analyze groups
+################################################################################
+
+actionclass analyzeMB_LFIR   { analyze(gMB_LFIR);   };
+actionclass analyzeMMIOFIR   { analyze(gMMIOFIR);   };
+actionclass analyzeSRQFIR    { analyze(gSRQFIR);    };
+actionclass analyzeMCBISTFIR { analyze(gMCBISTFIR); };
+actionclass analyzeRDFFIR    { analyze(gRDFFIR);    };
+actionclass analyzeTLXFIR    { analyze(gTLXFIR);    };
+actionclass analyzeOMIDLFIR  { analyze(gOMIDLFIR);  };
+