PRD: Add default support for memory ECC errors

Change-Id: Idb7e894e8beedf561dba002e6f4c857cc7e6c0bc
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4929
Tested-by: Jenkins Server
Reviewed-by: Christopher T. Phan <cphan@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5022

2 files changed, 243 insertions, 37 deletions

diff --git a/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_NEST.rule b/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_NEST.rule
index db56173a3..f9ae06316 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_NEST.rule
+++ b/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_NEST.rule
@@ -812,16 +812,14 @@ rule Mba1_MbsEccFir
 group gMbsEccFir filter singlebit
 {
     /** MBA0_MBSECCFIR[0:7]
-     *  MBECCFIR_MEMORY_MPE_RANK_0_7
+     *  Memory MPE
      */
-    #TODO via RTC 22866 ( Chip Mark Verification )
-    (Mba0_MbsEccFir, bit(0|1|2|3|4|5|6|7)) ? TBDDefaultCallout;
+    (Mba0_MbsEccFir, bit(0|1|2|3|4|5|6|7)) ? analyzeFetchMpe0;
 
     /** MBA1_MBSECCFIR[0:7]
-     *  MBECCFIR_MEMORY_MPE_RANK_0_7
+     *  Memory MPE
      */
-    #TODO via RTC 22866 ( Chip Mark Verification )
-    (Mba1_MbsEccFir, bit(0|1|2|3|4|5|6|7)) ? TBDDefaultCallout;
+    (Mba1_MbsEccFir, bit(0|1|2|3|4|5|6|7)) ? analyzeFetchMpe1;
 
     /** MBA0_MBSECCFIR[8:15]
      *  Reserved
@@ -834,73 +832,64 @@ group gMbsEccFir filter singlebit
     (Mba1_MbsEccFir, bit(8|9|10|11|12|13|14|15)) ? defaultMaskedError;
 
     /** MBA0_MBSECCFIR[16]
-     *  MBECCFIR_MEMORY_NCE
+     *  Memory NCE
      */
-    #TODO via RTC 47289 ( CE/UE isolation )
-    (Mba0_MbsEccFir, bit(16)) ? TBDDefaultCallout;
+    (Mba0_MbsEccFir, bit(16)) ? analyzeFetchNce0;
 
     /** MBA1_MBSECCFIR[16]
-     *  MBECCFIR_MEMORY_NCE
+     *  Memory NCE
      */
-    #TODO via RTC 47289 ( CE/UE isolation )
-    (Mba1_MbsEccFir, bit(16)) ? TBDDefaultCallout;
+    (Mba1_MbsEccFir, bit(16)) ? analyzeFetchNce1;
 
     /** MBA0_MBSECCFIR[17]
-     *  MBECCFIR_MEMORY_RCE
+     *  Memory RCE
      */
-    # TODO via RTC 23125. How to do this. In RAS spreadsheet action is RCE
-    # In description, Threshold per rank 8/24 make a callout of DIMM pair
-    # Needs discussion
-    (Mba0_MbsEccFir, bit(17)) ? TBDDefaultCallout;
+    (Mba0_MbsEccFir, bit(17)) ? analyzeFetchRce0;
 
     /** MBA1_MBSECCFIR[17]
-     *  MBECCFIR_MEMORY_RCE
+     *  Memory RCE
      */
-    (Mba1_MbsEccFir, bit(17)) ? TBDDefaultCallout;
+    (Mba1_MbsEccFir, bit(17)) ? analyzeFetchRce1;
 
     /** MBA0_MBSECCFIR[18]
-     *  MBECCFIR_MEMORY_SUE
+     *  Memory SUE
      */
     (Mba0_MbsEccFir, bit(18)) ? defaultMaskedError;
 
     /** MBA1_MBSECCFIR[18]
-     *  MBECCFIR_MEMORY_SUE
+     *  Memory SUE
      */
     (Mba1_MbsEccFir, bit(18)) ? defaultMaskedError;
 
     /** MBA0_MBSECCFIR[19]
-     *  MBECCFIR_MEMORY_UE
+     *  Memory UE
      */
-    #TODO via RTC 47289 ( CE/UE isolation )
-    (Mba0_MbsEccFir, bit(19)) ? TBDDefaultCallout;
+    (Mba0_MbsEccFir, bit(19)) ? analyzeFetchUe0;
 
     /** MBA1_MBSECCFIR[19]
-     *  MBECCFIR_MEMORY_UE
+     *  Memory UE
      */
-    #TODO via RTC 47289 ( CE/UE isolation )
-    (Mba1_MbsEccFir, bit(19)) ? TBDDefaultCallout;
+    (Mba1_MbsEccFir, bit(19)) ? analyzeFetchUe1;
 
     /** MBA0_MBSECCFIR[20:27]
      *  MBECCFIR_MAINT_MPE_RANK_0_7
      */
-    #TODO via RTC 22866 ( Chip Mark Verification )
-    (Mba0_MbsEccFir, bit(20|21|22|23|24|25|26|27)) ? TBDDefaultCallout;
+    (Mba0_MbsEccFir, bit(20|21|22|23|24|25|26|27)) ? analyzeMaintMpe0;
 
     /** MBA1_MBSECCFIR[20:27]
      *  MBECCFIR_MAINT_MPE_RANK_0_7
      */
-    #TODO via RTC 22866 ( Chip Mark Verification )
-    (Mba1_MbsEccFir, bit(20|21|22|23|24|25|26|27)) ? TBDDefaultCallout;
+    (Mba1_MbsEccFir, bit(20|21|22|23|24|25|26|27)) ? analyzeMaintMpe1;
 
     /** MBA0_MBSECCFIR[28:35]
      *  Reserved
      */
-    (Mba0_MbsEccFir, bit(28|29|30|31|32|33|34|35)) ? TBDDefaultCallout;
+    (Mba0_MbsEccFir, bit(28|29|30|31|32|33|34|35)) ? defaultMaskedError;
 
     /** MBA1_MBSECCFIR[28:35]
      *  Reserved
      */
-    (Mba1_MbsEccFir, bit(28|29|30|31|32|33|34|35)) ? TBDDefaultCallout;
+    (Mba1_MbsEccFir, bit(28|29|30|31|32|33|34|35)) ? defaultMaskedError;
 
     /** MBA0_MBSECCFIR[36]
      *  MBECCFIR_MAINTENANCE_NCE
@@ -955,14 +944,12 @@ group gMbsEccFir filter singlebit
     /** MBA0_MBSECCFIR[41]
      *  MBECCFIR_MAINTENANCE_UE
      */
-    #TODO via RTC 47289 ( CE/UE isolation )
-    (Mba0_MbsEccFir, bit(41)) ? TBDDefaultCallout;
+    (Mba0_MbsEccFir, bit(41)) ? analyzeMaintUe0;
 
     /** MBA1_MBSECCFIR[41]
      *  MBECCFIR_MAINTENANCE_UE
      */
-    #TODO via RTC 47289 ( CE/UE isolation )
-    (Mba1_MbsEccFir, bit(41)) ? TBDDefaultCallout;
+    (Mba1_MbsEccFir, bit(41)) ? analyzeMaintUe1;
 
     /** MBA0_MBSECCFIR[42]
      *  MBECCFIR_MPE_DURING_USE_MAINTENANCE_MARK_MODE
@@ -1240,3 +1227,42 @@ actionclass analyzeSpareBitAndThr
     try( funccall("checkSpareBit"), calloutDmiBusTh2pday );
 };
 
+/** Analyze a fetch MPE on MBA0 */
+actionclass analyzeFetchMpe0 { funccall("AnalyzeFetchMpe0"); };
+
+/** Analyze a fetch MPE on MBA1 */
+actionclass analyzeFetchMpe1 { funccall("AnalyzeFetchMpe1"); };
+
+/** Analyze a fetch NCE on MBA0 */
+actionclass analyzeFetchNce0 { funccall("AnalyzeFetchNce0"); threshold32pday; };
+
+/** Analyze a fetch NCE on MBA1 */
+actionclass analyzeFetchNce1 { funccall("AnalyzeFetchNce1"); threshold32pday; };
+
+# TODO: RTC 23125 The RAS spreadsheet action is RCE is: "Threshold per rank 8/24
+#       make a callout of DIMM pair". Needs discussion.
+
+/** Analyze a fetch RCE on MBA0 */
+actionclass analyzeFetchRce0 { funccall("AnalyzeFetchRce0"); threshold32pday; };
+
+/** Analyze a fetch RCE on MBA1 */
+actionclass analyzeFetchRce1 { funccall("AnalyzeFetchRce1"); threshold32pday; };
+
+/** Analyze a fetch UE on MBA0 */
+actionclass analyzeFetchUe0 { funccall("AnalyzeFetchUe0"); threshold1; };
+
+/** Analyze a fetch UE on MBA1 */
+actionclass analyzeFetchUe1 { funccall("AnalyzeFetchUe1"); threshold1; };
+
+/** Analyze a maintenance MPE on MBA0 */
+actionclass analyzeMaintMpe0 { funccall("AnalyzeMaintMpe0"); };
+
+/** Analyze a maintenance MPE on MBA1 */
+actionclass analyzeMaintMpe1 { funccall("AnalyzeMaintMpe1"); };
+
+/** Analyze a maintenance UE on MBA0 */
+actionclass analyzeMaintUe0 { funccall("AnalyzeMaintUe0"); threshold1; };
+
+/** Analyze a maintenance UE on MBA1 */
+actionclass analyzeMaintUe1 { funccall("AnalyzeMaintUe1"); threshold1; };
+
diff --git a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule b/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule
index 39b086022..313174210 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule
+++ b/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule
@@ -604,6 +604,38 @@
     };
 
     ############################################################################
+    # NEST Chiplet memory maintenance error count registers
+    ############################################################################
+
+    register MBA0_MBSEC0
+    {
+        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSEC0Q";
+        scomaddr    0x02011653;
+        capture     group default;
+    };
+
+    register MBA0_MBSEC1
+    {
+        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSEC1Q";
+        scomaddr    0x02011654;
+        capture     group default;
+    };
+
+    register MBA1_MBSEC0
+    {
+        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSEC0Q";
+        scomaddr    0x02011753;
+        capture     group default;
+    };
+
+    register MBA1_MBSEC1
+    {
+        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSEC1Q";
+        scomaddr    0x02011754;
+        capture     group default;
+    };
+
+    ############################################################################
     # NEST Chiplet memory maintenance threshold control registers
     ############################################################################
 
@@ -621,3 +653,151 @@
         capture     group default;
     };
 
+    ############################################################################
+    # NEST Chiplet memory maintenance symbol error control registers
+    ############################################################################
+
+    register MBA0_MBSSYMEC0
+    {
+        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC0Q";
+        scomaddr    0x02011656;
+        capture     group default;
+    };
+
+    register MBA0_MBSSYMEC1
+    {
+        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC1Q";
+        scomaddr    0x02011657;
+        capture     group default;
+    };
+
+    register MBA0_MBSSYMEC2
+    {
+        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC2Q";
+        scomaddr    0x02011658;
+        capture     group default;
+    };
+
+    register MBA0_MBSSYMEC3
+    {
+        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC3Q";
+        scomaddr    0x02011659;
+        capture     group default;
+    };
+
+    register MBA0_MBSSYMEC4
+    {
+        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC4Q";
+        scomaddr    0x0201165a;
+        capture     group default;
+    };
+
+    register MBA0_MBSSYMEC5
+    {
+        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC5Q";
+        scomaddr    0x0201165b;
+        capture     group default;
+    };
+
+    register MBA0_MBSSYMEC6
+    {
+        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC6Q";
+        scomaddr    0x0201165c;
+        capture     group default;
+    };
+
+    register MBA0_MBSSYMEC7
+    {
+        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC7Q";
+        scomaddr    0x0201165d;
+        capture     group default;
+    };
+
+    register MBA0_MBSSYMEC8
+    {
+        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSSYMEC8Q";
+        scomaddr    0x0201165e;
+        capture     group default;
+    };
+
+    register MBA1_MBSSYMEC0
+    {
+        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC0Q";
+        scomaddr    0x02011756;
+        capture     group default;
+    };
+
+    register MBA1_MBSSYMEC1
+    {
+        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC1Q";
+        scomaddr    0x02011757;
+        capture     group default;
+    };
+
+    register MBA1_MBSSYMEC2
+    {
+        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC2Q";
+        scomaddr    0x02011758;
+        capture     group default;
+    };
+
+    register MBA1_MBSSYMEC3
+    {
+        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC3Q";
+        scomaddr    0x02011759;
+        capture     group default;
+    };
+
+    register MBA1_MBSSYMEC4
+    {
+        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC4Q";
+        scomaddr    0x0201175a;
+        capture     group default;
+    };
+
+    register MBA1_MBSSYMEC5
+    {
+        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC5Q";
+        scomaddr    0x0201175b;
+        capture     group default;
+    };
+
+    register MBA1_MBSSYMEC6
+    {
+        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC6Q";
+        scomaddr    0x0201175c;
+        capture     group default;
+    };
+
+    register MBA1_MBSSYMEC7
+    {
+        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC7Q";
+        scomaddr    0x0201175d;
+        capture     group default;
+    };
+
+    register MBA1_MBSSYMEC8
+    {
+        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSSYMEC8Q";
+        scomaddr    0x0201175e;
+        capture     group default;
+    };
+
+    ############################################################################
+    # NEST Chiplet memory fetch error vector registers
+    ############################################################################
+
+    register MBA0_MBSEVR
+    {
+        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSEVRQ";
+        scomaddr    0x0201165f;
+        capture     group default;
+    };
+
+    register MBA1_MBSEVR
+    {
+        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSEVRQ";
+        scomaddr    0x0201175f;
+        capture     group default;
+    };
+