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authorZane Shelley <zshelle@us.ibm.com>2014-09-22 12:51:02 -0500
committerA. Patrick Williams III <iawillia@us.ibm.com>2014-09-26 13:18:26 -0500
commita0a664cdf590c1007483f866a13c70120d44e350 (patch)
tree0c41ea1b2a2b2611a9103923d660db953f5b8ae6 /src/usr/diag/prdf/common/plat/pegasus
parent60e669b9771225da4b92ed978cc025d5762e7e06 (diff)
downloadtalos-hostboot-a0a664cdf590c1007483f866a13c70120d44e350.tar.gz
talos-hostboot-a0a664cdf590c1007483f866a13c70120d44e350.zip
PRD: DRAM init training workaround in DRAM repairs VPD
Change-Id: Iefae6fd38322c8f15bae6d176febc8ec91334958 CQ: SW275686 Backport: release-fips811 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/13523 Tested-by: Jenkins Server Reviewed-by: Christopher T. Phan <cphan@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com> Reviewed-by: Zane Shelley <zshelle@us.ibm.com> Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/13607
Diffstat (limited to 'src/usr/diag/prdf/common/plat/pegasus')
-rw-r--r--src/usr/diag/prdf/common/plat/pegasus/prdfCenDqBitmap.C16
1 files changed, 12 insertions, 4 deletions
diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfCenDqBitmap.C b/src/usr/diag/prdf/common/plat/pegasus/prdfCenDqBitmap.C
index 44cefd2ea..4eb7b6952 100644
--- a/src/usr/diag/prdf/common/plat/pegasus/prdfCenDqBitmap.C
+++ b/src/usr/diag/prdf/common/plat/pegasus/prdfCenDqBitmap.C
@@ -5,7 +5,9 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* COPYRIGHT International Business Machines Corp. 2013,2014 */
+/* Contributors Listed Below - COPYRIGHT 2013,2014 */
+/* [+] International Business Machines Corp. */
+/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
@@ -212,18 +214,24 @@ int32_t CenDqBitmap::isChipMark( const CenSymbol & i_symbol, bool & o_cm )
break;
}
- uint8_t pins = 0xff;
+ // When PRD marks a DRAM as 'bad', it will set all bits on the DRAM in
+ // VPD. Due to a bug in DRAM init training, the training procedure will
+ // change the VPD to 0xee (x8) or 0xe (x4). Therefore, PRD will need to
+ // compare against the value the procedure sets in order to confirm a
+ // chip mark has been verified on this DRAM.
+
+ uint8_t pinMsk = 0xee;
uint8_t cmData = iv_data[portSlct][byteIdx];
if ( iv_x4Dram )
{
- pins = 0xf; // limit to 4 bits
+ pinMsk = 0xe; // limit to 4 bits
uint32_t shift = (DQS_PER_BYTE-1) - bitIdx;
shift = (shift / DQS_PER_NIBBLE) * DQS_PER_NIBBLE; // 0,4
cmData = (cmData >> shift) & 0xf;
}
- o_cm = ( cmData == pins );
+ o_cm = ( (cmData & pinMsk) == pinMsk );
} while (0);
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