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| author | Zane Shelley <zshelle@us.ibm.com> | 2016-05-02 14:42:28 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-05-25 15:01:19 -0400 |
| commit | 7048f1fdd57c1cf4af6812d7492ad2182f1cfff7 (patch) | |
| tree | 61d58cf756f669c22d58e85b4b32ae59bbed113d /src/usr/diag/prdf/common/plat/p9/p9_mcs.rule | |
| parent | c1dae582e0f016a0e830f11819baf66de6e58cef (diff) | |
| download | talos-hostboot-7048f1fdd57c1cf4af6812d7492ad2182f1cfff7.tar.gz talos-hostboot-7048f1fdd57c1cf4af6812d7492ad2182f1cfff7.zip | |
PRD: add HOST_ATTN support in rule code
Change-Id: I6f22c807c47b741b078929624db672e3c2895138
RTC: 148637
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23962
Tested-by: Jenkins Server
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com>
Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24995
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr/diag/prdf/common/plat/p9/p9_mcs.rule')
| -rw-r--r-- | src/usr/diag/prdf/common/plat/p9/p9_mcs.rule | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/usr/diag/prdf/common/plat/p9/p9_mcs.rule b/src/usr/diag/prdf/common/plat/p9/p9_mcs.rule index 08e362e4d..0f16690b3 100644 --- a/src/usr/diag/prdf/common/plat/p9/p9_mcs.rule +++ b/src/usr/diag/prdf/common/plat/p9/p9_mcs.rule @@ -107,9 +107,12 @@ rule rMCS UNIT_CS: summary( 0, rMCFIR ); + HOST_ATTN: + summary( 0, rMCFIR ); + }; -group gMCS attntype CHECK_STOP, RECOVERABLE, UNIT_CS +group gMCS attntype CHECK_STOP, RECOVERABLE, UNIT_CS, HOST_ATTN { (rMCS, bit(0)) ? analyze(gMCFIR); }; @@ -124,6 +127,8 @@ rule rMCFIR MCFIR & ~MCFIR_MASK & ~MCFIR_ACT0 & ~MCFIR_ACT1; RECOVERABLE: MCFIR & ~MCFIR_MASK & ~MCFIR_ACT0 & MCFIR_ACT1; + HOST_ATTN: + MCFIR & ~MCFIR_MASK & MCFIR_ACT0 & ~MCFIR_ACT1; UNIT_CS: MCFIR & ~MCFIR_MASK & MCFIR_ACT0 & MCFIR_ACT1; }; |
