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author | Zane Shelley <zshelle@us.ibm.com> | 2018-04-24 11:26:06 -0500 |
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committer | Zane C. Shelley <zshelle@us.ibm.com> | 2018-04-27 21:29:49 -0400 |
commit | ed55b087c5b070c99bdd4cb379e1291282d89897 (patch) | |
tree | c0877310845d8fef26d9fe1229c0a45105966300 /src/usr/diag/prdf/common/plat/cen/cen_centaur.rule | |
parent | 06d556e9b03c86d451b3a383f12834cb88302ae1 (diff) | |
download | talos-hostboot-ed55b087c5b070c99bdd4cb379e1291282d89897.tar.gz talos-hostboot-ed55b087c5b070c99bdd4cb379e1291282d89897.zip |
PRD: single bit analysis support for MEMBUF target
Change-Id: I9203af796be7f832d1aac1ed674252cb2df29e66
RTC: 187481
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57750
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com>
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57884
CI-Ready: Zane C. Shelley <zshelle@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/usr/diag/prdf/common/plat/cen/cen_centaur.rule')
-rw-r--r-- | src/usr/diag/prdf/common/plat/cen/cen_centaur.rule | 100 |
1 files changed, 53 insertions, 47 deletions
diff --git a/src/usr/diag/prdf/common/plat/cen/cen_centaur.rule b/src/usr/diag/prdf/common/plat/cen/cen_centaur.rule index f75ff5791..240615c62 100644 --- a/src/usr/diag/prdf/common/plat/cen/cen_centaur.rule +++ b/src/usr/diag/prdf/common/plat/cen/cen_centaur.rule @@ -790,8 +790,12 @@ rule rNEST_CHIPLET_FIR (NEST_CHIPLET_RE_FIR >> 2) & ~NEST_CHIPLET_FIR_MASK & `1fffffffffffffff`; }; -group gNEST_CHIPLET_FIR filter singlebit +group gNEST_CHIPLET_FIR filter priority( 3, 6, 5, 7 ) { + # NOTE: The MBIFIR must be analyzed before the DMIFIR and both the MBIFIR + # and DMIFIR must be analyzed before the MBSFIR. All other FIRs will be + # analyzed in order. + /** NEST_CHIPLET_FIR[3] * Attention from NEST_LFIR */ @@ -947,7 +951,8 @@ rule rDMIFIR DMIFIR & ~DMIFIR_MASK & ~DMIFIR_ACT0 & DMIFIR_ACT1; }; -group gDMIFIR filter singlebit, cs_root_cause( 10 ) +group gDMIFIR filter priority( 10, 2, 11, 12, 9 ), + cs_root_cause( 10 ) { /** DMIFIR[0] * RX invalid state or parity error @@ -1043,7 +1048,8 @@ rule rMBIFIR MBIFIR & ~MBIFIR_MASK & ~MBIFIR_ACT0 & MBIFIR_ACT1; }; -group gMBIFIR filter singlebit, cs_root_cause( 0, 6, 8, 9 ) +group gMBIFIR filter priority( 8, 9, 19, 20, 6, 0, 16, 5, 10 ), + cs_root_cause( 0, 6, 8, 9, 19, 20 ) { /** MBIFIR[0] * Replay Timeout @@ -1078,7 +1084,7 @@ group gMBIFIR filter singlebit, cs_root_cause( 0, 6, 8, 9 ) /** MBIFIR[6] * Replay Buffer ECC UE */ - (rMBIFIR, bit(6)) ? self_th_1; + (rMBIFIR, bit(6)) ? self_th_1_UERE; /** MBIFIR[7] * MBI State Machine Timeout @@ -1088,12 +1094,12 @@ group gMBIFIR filter singlebit, cs_root_cause( 0, 6, 8, 9 ) /** MBIFIR[8] * MBI Internal Control Parity Error */ - (rMBIFIR, bit(8)) ? self_th_1; + (rMBIFIR, bit(8)) ? self_th_1_UERE; /** MBIFIR[9] * MBI Data Flow Parity Error */ - (rMBIFIR, bit(9)) ? self_th_1; + (rMBIFIR, bit(9)) ? self_th_1_UERE; /** MBIFIR[10] * CRC Performance Degradation @@ -1143,7 +1149,7 @@ group gMBIFIR filter singlebit, cs_root_cause( 0, 6, 8, 9 ) /** MBIFIR[19] * MBICFG parity error */ - (rMBIFIR, bit(19)) ? self_th_1; + (rMBIFIR, bit(19)) ? self_th_1_UERE; /** MBIFIR[20] * Replay Buffer Overrun @@ -1194,12 +1200,12 @@ group gMBSFIR filter singlebit, cs_root_cause( 0, 1, 2, 4, 6, 8, 10, 13, 16, 18, /** MBSFIR[1] * INT_PROTOCOL_ERROR */ - (rMBSFIR, bit(1)) ? self_th_1; + (rMBSFIR, bit(1)) ? self_th_1_UERE; /** MBSFIR[2] * INVALID_ADDRESS_ERROR */ - (rMBSFIR, bit(2)) ? level2_th_1; + (rMBSFIR, bit(2)) ? level2_th_1_UERE; /** MBSFIR[3] * EXTERNAL_TIMEOUT @@ -1219,7 +1225,7 @@ group gMBSFIR filter singlebit, cs_root_cause( 0, 1, 2, 4, 6, 8, 10, 13, 16, 18, /** MBSFIR[6] * INT_BUFFER_UE */ - (rMBSFIR, bit(6)) ? self_th_1; + (rMBSFIR, bit(6)) ? self_th_1_UERE; /** MBSFIR[7] * INT_BUFFER_SUE @@ -1229,7 +1235,7 @@ group gMBSFIR filter singlebit, cs_root_cause( 0, 1, 2, 4, 6, 8, 10, 13, 16, 18, /** MBSFIR[8] * INT_PARITY_ERROR */ - (rMBSFIR, bit(8)) ? self_th_1; + (rMBSFIR, bit(8)) ? self_th_1_UERE; /** MBSFIR[9] * CACHE_SRW_CE @@ -1264,12 +1270,12 @@ group gMBSFIR filter singlebit, cs_root_cause( 0, 1, 2, 4, 6, 8, 10, 13, 16, 18, /** MBSFIR[15] * DIR_CE */ - (rMBSFIR, bit(15)) ? TBDDefaultCallout; + (rMBSFIR, bit(15)) ? l4_th_32perDay; /** MBSFIR[16] * DIR_UE */ - (rMBSFIR, bit(16)) ? TBDDefaultCallout; + (rMBSFIR, bit(16)) ? l4_th_1_UERE; /** MBSFIR[17] * DIR_MEMBER_DELETED @@ -1279,17 +1285,17 @@ group gMBSFIR filter singlebit, cs_root_cause( 0, 1, 2, 4, 6, 8, 10, 13, 16, 18, /** MBSFIR[18] * DIR_ALL_MEMBERS_DELETED */ - (rMBSFIR, bit(18)) ? TBDDefaultCallout; + (rMBSFIR, bit(18)) ? l4_th_1_UERE; /** MBSFIR[19] * LRU_ERROR */ - (rMBSFIR, bit(19)) ? TBDDefaultCallout; + (rMBSFIR, bit(19)) ? l4_th_32perDay; /** MBSFIR[20] * EDRAM ERROR */ - (rMBSFIR, bit(20)) ? TBDDefaultCallout; + (rMBSFIR, bit(20)) ? l4_th_1_UERE; /** MBSFIR[21] * EMERGENCY_THROTTLE_SET @@ -1324,7 +1330,7 @@ group gMBSFIR filter singlebit, cs_root_cause( 0, 1, 2, 4, 6, 8, 10, 13, 16, 18, /** MBSFIR[27] * SRB_BUFFER_UE */ - (rMBSFIR, bit(27)) ? self_th_1; + (rMBSFIR, bit(27)) ? self_th_1_UERE; /** MBSFIR[28] * SRB_BUFFER_SUE @@ -1339,7 +1345,7 @@ group gMBSFIR filter singlebit, cs_root_cause( 0, 1, 2, 4, 6, 8, 10, 13, 16, 18, /** MBSFIR[30] * PROXIMAL_CE_UE */ - (rMBSFIR, bit(30)) ? TBDDefaultCallout; + (rMBSFIR, bit(30)) ? l4_th_1_UERE; /** MBSFIR[31:32] * Spare @@ -1414,7 +1420,7 @@ rule rMBSECCFIR_0 MBSECCFIR_0 & ~MBSECCFIR_0_MASK & ~MBSECCFIR_0_ACT0 & MBSECCFIR_0_ACT1; }; -group gMBSECCFIR_0 filter singlebit, cs_root_cause +group gMBSECCFIR_0 filter singlebit, cs_root_cause( 19, 44, 47, 49 ) { /** MBSECCFIR_0[0] * Memory chip mark on rank 0 @@ -1534,7 +1540,7 @@ group gMBSECCFIR_0 filter singlebit, cs_root_cause /** MBSECCFIR_0[44] * Memory RCD parity error */ - (rMBSECCFIR_0, bit(44)) ? self_th_1; # CUMULUS_10 + (rMBSECCFIR_0, bit(44)) ? self_th_1_UERE; # CUMULUS_10 /** MBSECCFIR_0[45] * Maintenance RCD parity error @@ -1544,32 +1550,32 @@ group gMBSECCFIR_0 filter singlebit, cs_root_cause /** MBSECCFIR_0[46] * Recoverable config reg PE */ - (rMBSECCFIR_0, bit(46)) ? TBDDefaultCallout; + (rMBSECCFIR_0, bit(46)) ? mba0_th_1; /** MBSECCFIR_0[47] * Unrecoverable config reg PE */ - (rMBSECCFIR_0, bit(47)) ? TBDDefaultCallout; + (rMBSECCFIR_0, bit(47)) ? mba0_th_1_UERE; /** MBSECCFIR_0[48] * Maskable config reg PE */ - (rMBSECCFIR_0, bit(48)) ? TBDDefaultCallout; + (rMBSECCFIR_0, bit(48)) ? threshold_and_mask_mba0; /** MBSECCFIR_0[49] * ECC datapath parity error */ - (rMBSECCFIR_0, bit(49)) ? TBDDefaultCallout; + (rMBSECCFIR_0, bit(49)) ? mba0_th_1_UERE; /** MBSECCFIR_0[50] * internal scom error */ - (rMBSECCFIR_0, bit(50)) ? TBDDefaultCallout; + (rMBSECCFIR_0, bit(50)) ? threshold_and_mask_mba0; /** MBSECCFIR_0[51] * internal scom error clone */ - (rMBSECCFIR_0, bit(51)) ? TBDDefaultCallout; + (rMBSECCFIR_0, bit(51)) ? threshold_and_mask_mba0; }; @@ -1585,7 +1591,7 @@ rule rMBSECCFIR_1 MBSECCFIR_1 & ~MBSECCFIR_1_MASK & ~MBSECCFIR_1_ACT0 & MBSECCFIR_1_ACT1; }; -group gMBSECCFIR_1 filter singlebit +group gMBSECCFIR_1 filter singlebit, cs_root_cause( 19, 44, 47, 49 ) { /** MBSECCFIR_1[0] * Memory chip mark on rank 0 @@ -1705,7 +1711,7 @@ group gMBSECCFIR_1 filter singlebit /** MBSECCFIR_1[44] * Memory RCD parity error */ - (rMBSECCFIR_1, bit(44)) ? self_th_1; # CUMULUS_10 + (rMBSECCFIR_1, bit(44)) ? self_th_1_UERE; # CUMULUS_10 /** MBSECCFIR_1[45] * Maintenance RCD parity error @@ -1715,32 +1721,32 @@ group gMBSECCFIR_1 filter singlebit /** MBSECCFIR_1[46] * Recoverable config reg PE */ - (rMBSECCFIR_1, bit(46)) ? TBDDefaultCallout; + (rMBSECCFIR_1, bit(46)) ? mba1_th_1; /** MBSECCFIR_1[47] * Unrecoverable config reg PE */ - (rMBSECCFIR_1, bit(47)) ? TBDDefaultCallout; + (rMBSECCFIR_1, bit(47)) ? mba1_th_1_UERE; /** MBSECCFIR_1[48] * Maskable config reg PE */ - (rMBSECCFIR_1, bit(48)) ? TBDDefaultCallout; + (rMBSECCFIR_1, bit(48)) ? threshold_and_mask_mba1; /** MBSECCFIR_1[49] * ECC datapath parity error */ - (rMBSECCFIR_1, bit(49)) ? TBDDefaultCallout; + (rMBSECCFIR_1, bit(49)) ? mba1_th_1_UERE; /** MBSECCFIR_1[50] * internal scom error */ - (rMBSECCFIR_1, bit(50)) ? TBDDefaultCallout; + (rMBSECCFIR_1, bit(50)) ? threshold_and_mask_mba1; /** MBSECCFIR_1[51] * internal scom error clone */ - (rMBSECCFIR_1, bit(51)) ? TBDDefaultCallout; + (rMBSECCFIR_1, bit(51)) ? threshold_and_mask_mba1; }; @@ -1756,7 +1762,7 @@ rule rSCACFIR SCACFIR & ~SCACFIR_MASK & ~SCACFIR_ACT0 & SCACFIR_ACT1; }; -group gSCACFIR filter singlebit, cs_root_cause +group gSCACFIR filter singlebit, cs_root_cause( 25, 26 ) { /** SCACFIR[0] * I2CM(0) Invalid Address @@ -1871,12 +1877,12 @@ group gSCACFIR filter singlebit, cs_root_cause /** SCACFIR[25] * Parity Error on Internal Register */ - (rSCACFIR, bit(25)) ? self_th_1; + (rSCACFIR, bit(25)) ? self_th_1_UERE; /** SCACFIR[26] * Parity Error on Pib Target Register */ - (rSCACFIR, bit(26)) ? self_th_1; + (rSCACFIR, bit(26)) ? self_th_1_UERE; /** SCACFIR[27:31] * Reserved @@ -1922,17 +1928,17 @@ rule rMCBISTFIR_0 MCBISTFIR_0 & ~MCBISTFIR_0_MASK & ~MCBISTFIR_0_ACT0 & MCBISTFIR_0_ACT1; }; -group gMCBISTFIR_0 filter singlebit, cs_root_cause +group gMCBISTFIR_0 filter singlebit, cs_root_cause( 0, 1 ) { /** MCBISTFIR_0[0] * SCOM Parity Errors */ - (rMCBISTFIR_0, bit(0)) ? TBDDefaultCallout; + (rMCBISTFIR_0, bit(0)) ? mba0_th_1_UERE; /** MCBISTFIR_0[1] * MBX parity errors */ - (rMCBISTFIR_0, bit(1)) ? TBDDefaultCallout; + (rMCBISTFIR_0, bit(1)) ? mba0_th_1_UERE; /** MCBISTFIR_0[2] * DRAM event 0 error @@ -1952,12 +1958,12 @@ group gMCBISTFIR_0 filter singlebit, cs_root_cause /** MCBISTFIR_0[15] * SCOM FIR error */ - (rMCBISTFIR_0, bit(15)) ? TBDDefaultCallout; + (rMCBISTFIR_0, bit(15)) ? threshold_and_mask_mba0; /** MCBISTFIR_0[16] * SCOM FIR error clone */ - (rMCBISTFIR_0, bit(16)) ? TBDDefaultCallout; + (rMCBISTFIR_0, bit(16)) ? threshold_and_mask_mba0; }; @@ -1973,17 +1979,17 @@ rule rMCBISTFIR_1 MCBISTFIR_1 & ~MCBISTFIR_1_MASK & ~MCBISTFIR_1_ACT0 & MCBISTFIR_1_ACT1; }; -group gMCBISTFIR_1 filter singlebit, cs_root_cause +group gMCBISTFIR_1 filter singlebit, cs_root_cause( 0, 1 ) { /** MCBISTFIR_1[0] * SCOM Parity Errors */ - (rMCBISTFIR_1, bit(0)) ? TBDDefaultCallout; + (rMCBISTFIR_1, bit(0)) ? mba1_th_1_UERE; /** MCBISTFIR_1[1] * MBX parity errors */ - (rMCBISTFIR_1, bit(1)) ? TBDDefaultCallout; + (rMCBISTFIR_1, bit(1)) ? mba1_th_1_UERE; /** MCBISTFIR_1[2] * DRAM event 0 error @@ -2003,12 +2009,12 @@ group gMCBISTFIR_1 filter singlebit, cs_root_cause /** MCBISTFIR_1[15] * SCOM FIR error */ - (rMCBISTFIR_1, bit(15)) ? TBDDefaultCallout; + (rMCBISTFIR_1, bit(15)) ? threshold_and_mask_mba1; /** MCBISTFIR_1[16] * SCOM FIR error clone */ - (rMCBISTFIR_1, bit(16)) ? TBDDefaultCallout; + (rMCBISTFIR_1, bit(16)) ? threshold_and_mask_mba1; }; |