ATTN: Clear Intr Reg on RECOV errors from Host Side

Change-Id: I6427f18fc6d50fc60a9de9d1a06ebc0850fa906b
RTC: 159844
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28753
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 3 insertions, 12 deletions

diff --git a/src/usr/diag/attn/common/attnbits.H b/src/usr/diag/attn/common/attnbits.H
index af34cb5b4..763f0c987 100644
--- a/src/usr/diag/attn/common/attnbits.H
+++ b/src/usr/diag/attn/common/attnbits.H
@@ -176,26 +176,17 @@ bool getCheckbits(
  */
 enum
 {
-    // Interrupt Type Mask Register
-    INTR_TYPE_MASK_OR_REG            = 0x000F002D,
-    INTR_TYPE_MASK_AND_REG           = 0x000F002E,
-
-    // Interrupt Type Config Register
-    // (contains MUX'ing bits now)
-    INTR_TYPE_CONFIG_AND_REG         = 0x000F0031,
-
     // This was for MCS usage, but not needed right now
     GP2_REG                          = 0x02000002,
 
+    // PIB interrupt register (spec/recov/chkstop)
+    PIB_INTR_TYPE_REG                = 0x000F001A,
+
     // IPOLL MASK register
     IPOLL_MASK_REG                   = 0x000F0033,
     // (IPOLL) Error status reg
     IPOLL_STATUS_REG                 = 0x000F0034,
 
-    // Interrupt Presentation Reg (IPR)
-    INTR_TYPE_LCL_ERR_STATUS_REG     = 0x000F0020,
-    INTR_TYPE_LCL_ERR_STATUS_OR_REG  = 0x000F0021,
-    INTR_TYPE_LCL_ERR_STATUS_AND_REG = 0x000F0022,
 };