Optimize PageTableManager and associated VMM.

    - Changed overall page table behavior to no longer use C bits
      in page table entries.  Instead, individual blocks mark
      pages as dirty based on stores during page faults.  Initially
      all writable pages are marked read-only until the first store
      to it.  At that time the block gets an exception and changes
      the permission on the page table entry to writable and marks
      its own SPTE to dirty.

    - Greatly reduced the number of tlbie's and page table accesses.
      Accomplished this by:
          * Skipping many of the page table manipulations, such as
	    LRU updates, when the PTE is invalid.
	  * Converting most of the previously general-case of
	    "Modifying a PTE" to specific cases such as "Resetting
	    the Reference Bit" and "Modifying the SW field".

    - Fixed the LRU-flush algorithm so that it is O(n) instead of
      O(n^2), where n = size of page table.

Change-Id: I2520fa88970fd7f656e6348bf6b34d5db82fd3db
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/892
Tested-by: Jenkins Server
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

1 files changed, 18 insertions, 3 deletions

diff --git a/src/kernel/exception.C b/src/kernel/exception.C
index 78f43d581..2759c71e4 100644
--- a/src/kernel/exception.C
+++ b/src/kernel/exception.C
@@ -58,8 +58,10 @@ void kernel_execute_prog_ex()
     }
 }
 
-const uint64_t EXCEPTION_DSISR_MASK	= 0x0000000040000000;
+const uint64_t EXCEPTION_DSISR_MASK	= 0x0000000048000000;
 const uint64_t EXCEPTION_DSISR_PTEMISS  = 0x0000000040000000;
+const uint64_t EXCEPTION_DSISR_PERMERR  = 0x0000000008000000;
+const uint64_t EXCEPTION_DSISR_STORE    = 0x0000000002000000;
 
 extern "C"
 void kernel_execute_data_storage()
@@ -71,8 +73,21 @@ void kernel_execute_data_storage()
     switch(exception)
     {
 	case EXCEPTION_DSISR_PTEMISS:
-	    handled = VmmManager::pteMiss(t, getDAR());
+        {
+            uint64_t is_store = getDSISR() & EXCEPTION_DSISR_STORE;
+            handled = VmmManager::pteMiss(t, getDAR(), 0 != is_store);
+            break;
+        }
+
+        case EXCEPTION_DSISR_PERMERR:
+        {
+            uint64_t is_store = getDSISR() & EXCEPTION_DSISR_STORE;
+            if (is_store)
+            {
+	        handled = VmmManager::pteMiss(t, getDAR(), true);
+            }
 	    break;
+        }
     }
     if (!handled)
     {
@@ -103,7 +118,7 @@ void kernel_execute_inst_storage()
     switch (exception)
     {
         case EXCEPTION_SRR1_INSTR_PTEMISS:
-            handled = VmmManager::pteMiss(t, getSRR0());
+            handled = VmmManager::pteMiss(t, getSRR0(), false);
             break;
     }
     if (!handled)