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| author | Ilya Smirnov <ismirno@us.ibm.com> | 2017-07-28 10:55:14 -0500 |
|---|---|---|
| committer | William G. Hoffa <wghoffa@us.ibm.com> | 2017-08-23 14:28:43 -0400 |
| commit | e5790aed63a53234a4ae733b5b351feae9e81670 (patch) | |
| tree | c191b191a43cd3cb191aa7a1e8e46ad86ef1ca75 /src/include | |
| parent | a8cbc4f396c1c3555e133aebded97ee03398925d (diff) | |
| download | talos-hostboot-e5790aed63a53234a4ae733b5b351feae9e81670.tar.gz talos-hostboot-e5790aed63a53234a4ae733b5b351feae9e81670.zip | |
IPL Time Checkstop Analysis Part 2: Start OCC
Created a function that calls the necessary HWPs to start OCC
Change-Id: Id94820dc1f8105bb183a25ddef88ab32bda7db97
RTC:155065
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43863
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/usr/isteps/pm/occCheckstop.H | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/src/include/usr/isteps/pm/occCheckstop.H b/src/include/usr/isteps/pm/occCheckstop.H index 10efd4897..026c8db55 100644 --- a/src/include/usr/isteps/pm/occCheckstop.H +++ b/src/include/usr/isteps/pm/occCheckstop.H @@ -53,16 +53,20 @@ namespace HBOCC OCC_GPE1_SRAM_ADDRESS = 0xFFF10000, // SRAM Address and length for FIR HOMER data - OCC_SRAM_FIR_DATA = 0xFFFBA000, - OCC_SRAM_FIR_LENGTH = 0x3000, + OCC_SRAM_FIR_DATA = 0xFFFBD000, + OCC_SRAM_FIR_LENGTH = 0x1000, // offsets for OCC loading during IPL OCC_OFFSET_LENGTH = 0x48, OCC_OFFSET_GPE0_LENGTH = 0x64, OCC_OFFSET_GPE1_LENGTH = 0x68, + OCC_OFFSET_MAIN_EP = 0x6C, OCC_OFFSET_IPL_FLAG = 0x92, OCC_OFFSET_FREQ = 0x94, + OCC_BRANCH_INSTR = 0x4B00000200000000, + BRANCH_ADDR_MASK = 0x00FFFFFC, + }; enum occAction_t @@ -97,6 +101,17 @@ namespace HBOCC #endif #ifdef CONFIG_IPLTIME_CHECKSTOP_ANALYSIS + + /** + * @brief Starts OCC that has been loaded to SRAM (used during IPL time + * checkstop analysis. + * + * @param[in] i_target: the proc we're operating on (should be masterproc) + * + * @return errlHndl_t Error log if start fails + */ + errlHndl_t startOCCFromSRAM(TARGETING::Target* i_proc); + /** * @brief Loads the OCC image from PNOR to SRAM * |
